1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_usart.c
4 * @author MCD Application Team
5 * @brief USART LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_usart.h"
22 #include "stm32f3xx_ll_rcc.h"
23 #include "stm32f3xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
35
36 /** @addtogroup USART_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup USART_LL_Private_Constants
44 * @{
45 */
46
47 /* Definition of default baudrate value used for USART initialisation */
48 #define USART_DEFAULT_BAUDRATE (9600U)
49
50 /**
51 * @}
52 */
53
54 /* Private macros ------------------------------------------------------------*/
55 /** @addtogroup USART_LL_Private_Macros
56 * @{
57 */
58
59 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
60 * divided by the smallest oversampling used on the USART (i.e. 8) */
61 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
62
63 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
64 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
65
66 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
67 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
68 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
69 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
70
71 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
72 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
73 || ((__VALUE__) == LL_USART_PARITY_ODD))
74
75 #if defined(USART_7BITS_SUPPORT)
76 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
77 || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
78 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
79 #else
80 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
81 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
82 #endif /* USART_7BITS_SUPPORT */
83
84 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
85 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
86
87 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
88 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
89
90 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
91 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
92
93 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
94 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
95
96 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
97 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
98
99 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
100 || ((__VALUE__) == LL_USART_STOPBITS_1) \
101 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
102 || ((__VALUE__) == LL_USART_STOPBITS_2))
103
104 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
105 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
106 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
107 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
108
109 /**
110 * @}
111 */
112
113 /* Private function prototypes -----------------------------------------------*/
114
115 /* Exported functions --------------------------------------------------------*/
116 /** @addtogroup USART_LL_Exported_Functions
117 * @{
118 */
119
120 /** @addtogroup USART_LL_EF_Init
121 * @{
122 */
123
124 /**
125 * @brief De-initialize USART registers (Registers restored to their default values).
126 * @param USARTx USART Instance
127 * @retval An ErrorStatus enumeration value:
128 * - SUCCESS: USART registers are de-initialized
129 * - ERROR: USART registers are not de-initialized
130 */
LL_USART_DeInit(const USART_TypeDef * USARTx)131 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
132 {
133 ErrorStatus status = SUCCESS;
134
135 /* Check the parameters */
136 assert_param(IS_UART_INSTANCE(USARTx));
137
138 if (USARTx == USART1)
139 {
140 /* Force reset of USART clock */
141 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
142
143 /* Release reset of USART clock */
144 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
145 }
146 else if (USARTx == USART2)
147 {
148 /* Force reset of USART clock */
149 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
150
151 /* Release reset of USART clock */
152 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
153 }
154 else if (USARTx == USART3)
155 {
156 /* Force reset of USART clock */
157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
158
159 /* Release reset of USART clock */
160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
161 }
162 #if defined(UART4)
163 else if (USARTx == UART4)
164 {
165 /* Force reset of UART clock */
166 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
167
168 /* Release reset of UART clock */
169 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
170 }
171 #endif /* UART4 */
172 #if defined(UART5)
173 else if (USARTx == UART5)
174 {
175 /* Force reset of UART clock */
176 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
177
178 /* Release reset of UART clock */
179 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
180 }
181 #endif /* UART5 */
182 else
183 {
184 status = ERROR;
185 }
186
187 return (status);
188 }
189
190 /**
191 * @brief Initialize USART registers according to the specified
192 * parameters in USART_InitStruct.
193 * @note As some bits in USART configuration registers can only be written when
194 * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
195 * this function. Otherwise, ERROR result will be returned.
196 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
197 * @param USARTx USART Instance
198 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
199 * that contains the configuration information for the specified USART peripheral.
200 * @retval An ErrorStatus enumeration value:
201 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
202 * - ERROR: Problem occurred during USART Registers initialization
203 */
LL_USART_Init(USART_TypeDef * USARTx,const LL_USART_InitTypeDef * USART_InitStruct)204 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
205 {
206 ErrorStatus status = ERROR;
207 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
208 #if (!defined(RCC_CFGR3_USART2SW)||!defined (RCC_CFGR3_USART3SW))
209 LL_RCC_ClocksTypeDef RCC_Clocks;
210 #endif /* USART clock selection flags */
211
212 /* Check the parameters */
213 assert_param(IS_UART_INSTANCE(USARTx));
214 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
215 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
216 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
217 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
218 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
219 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
220 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
221
222 /* USART needs to be in disabled state, in order to be able to configure some bits in
223 CRx registers */
224 if (LL_USART_IsEnabled(USARTx) == 0U)
225 {
226 /*---------------------------- USART CR1 Configuration ---------------------
227 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
228 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
229 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
230 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
231 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
232 */
233 MODIFY_REG(USARTx->CR1,
234 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
235 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
236 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
237 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
238
239 /*---------------------------- USART CR2 Configuration ---------------------
240 * Configure USARTx CR2 (Stop bits) with parameters:
241 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
242 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
243 */
244 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
245
246 /*---------------------------- USART CR3 Configuration ---------------------
247 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
248 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
249 * USART_InitStruct->HardwareFlowControl value.
250 */
251 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
252
253 /*---------------------------- USART BRR Configuration ---------------------
254 * Retrieve Clock frequency used for USART Peripheral
255 */
256 if (USARTx == USART1)
257 {
258 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
259 }
260 else if (USARTx == USART2)
261 {
262 #if defined(RCC_CFGR3_USART2SW)
263 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
264 #else
265 /* USART2 clock is PCLK */
266 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
267 periphclk = RCC_Clocks.PCLK1_Frequency;
268 #endif /* USART2 Clock selector flag */
269 }
270 else if (USARTx == USART3)
271 {
272 #if defined(RCC_CFGR3_USART3SW)
273 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
274 #else
275 /* USART3 clock is PCLK */
276 LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
277 periphclk = RCC_Clocks.PCLK1_Frequency;
278 #endif /* USART3 Clock selector flag */
279 }
280 #if defined(UART4)
281 else if (USARTx == UART4)
282 {
283 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
284 }
285 #endif /* UART4 */
286 #if defined(UART5)
287 else if (USARTx == UART5)
288 {
289 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
290 }
291 #endif /* UART5 */
292 else
293 {
294 /* Nothing to do, as error code is already assigned to ERROR value */
295 }
296
297 /* Configure the USART Baud Rate :
298 - valid baud rate value (different from 0) is required
299 - Peripheral clock as returned by RCC service, should be valid (different from 0).
300 */
301 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
302 && (USART_InitStruct->BaudRate != 0U))
303 {
304 status = SUCCESS;
305 LL_USART_SetBaudRate(USARTx,
306 periphclk,
307 USART_InitStruct->OverSampling,
308 USART_InitStruct->BaudRate);
309
310 /* Check BRR is greater than or equal to 16d */
311 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
312 }
313 }
314 /* Endif (=> USART not in Disabled state => return ERROR) */
315
316 return (status);
317 }
318
319 /**
320 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
321 * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
322 * whose fields will be set to default values.
323 * @retval None
324 */
325
LL_USART_StructInit(LL_USART_InitTypeDef * USART_InitStruct)326 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
327 {
328 /* Set USART_InitStruct fields to default values */
329 USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE;
330 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
331 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
332 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
333 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
334 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
335 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
336 }
337
338 /**
339 * @brief Initialize USART Clock related settings according to the
340 * specified parameters in the USART_ClockInitStruct.
341 * @note As some bits in USART configuration registers can only be written when
342 * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
343 * this function. Otherwise, ERROR result will be returned.
344 * @param USARTx USART Instance
345 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
346 * that contains the Clock configuration information for the specified USART peripheral.
347 * @retval An ErrorStatus enumeration value:
348 * - SUCCESS: USART registers related to Clock settings are initialized according
349 * to USART_ClockInitStruct content
350 * - ERROR: Problem occurred during USART Registers initialization
351 */
LL_USART_ClockInit(USART_TypeDef * USARTx,const LL_USART_ClockInitTypeDef * USART_ClockInitStruct)352 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
353 {
354 ErrorStatus status = SUCCESS;
355
356 /* Check USART Instance and Clock signal output parameters */
357 assert_param(IS_UART_INSTANCE(USARTx));
358 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
359
360 /* USART needs to be in disabled state, in order to be able to configure some bits in
361 CRx registers */
362 if (LL_USART_IsEnabled(USARTx) == 0U)
363 {
364 /* If USART Clock signal is disabled */
365 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
366 {
367 /* Deactivate Clock signal delivery :
368 * - Disable Clock Output: USART_CR2_CLKEN cleared
369 */
370 LL_USART_DisableSCLKOutput(USARTx);
371 }
372 else
373 {
374 /* Ensure USART instance is USART capable */
375 assert_param(IS_USART_INSTANCE(USARTx));
376
377 /* Check clock related parameters */
378 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
379 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
380 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
381
382 /*---------------------------- USART CR2 Configuration -----------------------
383 * Configure USARTx CR2 (Clock signal related bits) with parameters:
384 * - Enable Clock Output: USART_CR2_CLKEN set
385 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
386 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
387 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
388 */
389 MODIFY_REG(USARTx->CR2,
390 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
391 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
392 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
393 }
394 }
395 /* Else (USART not in Disabled state => return ERROR */
396 else
397 {
398 status = ERROR;
399 }
400
401 return (status);
402 }
403
404 /**
405 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
406 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
407 * whose fields will be set to default values.
408 * @retval None
409 */
LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef * USART_ClockInitStruct)410 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
411 {
412 /* Set LL_USART_ClockInitStruct fields with default values */
413 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
414 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
415 LL_USART_CLOCK_DISABLE */
416 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
417 LL_USART_CLOCK_DISABLE */
418 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
419 LL_USART_CLOCK_DISABLE */
420 }
421
422 /**
423 * @}
424 */
425
426 /**
427 * @}
428 */
429
430 /**
431 * @}
432 */
433
434 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
435
436 /**
437 * @}
438 */
439
440 #endif /* USE_FULL_LL_DRIVER */
441
442
443
