1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_spi.h"
22 #include "stm32f3xx_ll_bus.h"
23 #include "stm32f3xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F3xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164 #if defined(SPI3)
165 if (SPIx == SPI3)
166 {
167 /* Force reset of SPI clock */
168 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
169
170 /* Release reset of SPI clock */
171 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
172
173 status = SUCCESS;
174 }
175 #endif /* SPI3 */
176 #if defined(SPI4)
177 if (SPIx == SPI4)
178 {
179 /* Force reset of SPI clock */
180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
181
182 /* Release reset of SPI clock */
183 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
184
185 status = SUCCESS;
186 }
187 #endif /* SPI4 */
188
189 return status;
190 }
191
192 /**
193 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
194 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
195 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
196 * @param SPIx SPI Instance
197 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
198 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
199 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)200 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
201 {
202 ErrorStatus status = ERROR;
203
204 /* Check the SPI Instance SPIx*/
205 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
206
207 /* Check the SPI parameters from SPI_InitStruct*/
208 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
209 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
210 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
211 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
212 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
213 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
214 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
215 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
216 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
217
218 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
219 {
220 /*---------------------------- SPIx CR1 Configuration ------------------------
221 * Configure SPIx CR1 with parameters:
222 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
223 * - Master/Slave Mode: SPI_CR1_MSTR bit
224 * - ClockPolarity: SPI_CR1_CPOL bit
225 * - ClockPhase: SPI_CR1_CPHA bit
226 * - NSS management: SPI_CR1_SSM bit
227 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
228 * - BitOrder: SPI_CR1_LSBFIRST bit
229 * - CRCCalculation: SPI_CR1_CRCEN bit
230 */
231 MODIFY_REG(SPIx->CR1,
232 SPI_CR1_CLEAR_MASK,
233 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
234 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
235 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
236 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
237
238 /*---------------------------- SPIx CR2 Configuration ------------------------
239 * Configure SPIx CR2 with parameters:
240 * - DataWidth: DS[3:0] bits
241 * - NSS management: SSOE bit
242 */
243 MODIFY_REG(SPIx->CR2,
244 SPI_CR2_DS | SPI_CR2_SSOE,
245 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
246
247 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
248 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
249 {
250 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
251 }
252
253 /*---------------------------- SPIx CRCPR Configuration ----------------------
254 * Configure SPIx CRCPR with parameters:
255 * - CRCPoly: CRCPOLY[15:0] bits
256 */
257 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
258 {
259 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
260 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
261 }
262 status = SUCCESS;
263 }
264
265 #if defined (SPI_I2S_SUPPORT)
266 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
267 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
268 #endif /* SPI_I2S_SUPPORT */
269 return status;
270 }
271
272 /**
273 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
274 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
275 * whose fields will be set to default values.
276 * @retval None
277 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)278 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
279 {
280 /* Set SPI_InitStruct fields to default values */
281 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
282 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
283 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
284 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
285 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
286 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
287 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
288 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
289 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
290 SPI_InitStruct->CRCPoly = 7U;
291 }
292
293 /**
294 * @}
295 */
296
297 /**
298 * @}
299 */
300
301 /**
302 * @}
303 */
304
305 #if defined(SPI_I2S_SUPPORT)
306 /** @addtogroup I2S_LL
307 * @{
308 */
309
310 /* Private types -------------------------------------------------------------*/
311 /* Private variables ---------------------------------------------------------*/
312 /* Private constants ---------------------------------------------------------*/
313 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
314 * @{
315 */
316 /* I2S registers Masks */
317 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
318 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
319 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
320
321 #define I2S_I2SPR_CLEAR_MASK 0x0002U
322 /**
323 * @}
324 */
325 /* Private macros ------------------------------------------------------------*/
326 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
327 * @{
328 */
329
330 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
331 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
332 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
333 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
334
335 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
336 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
337
338 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
339 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
340 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
341 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
342 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
343
344 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
345 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
346 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
347 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
348
349 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
350 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
351
352 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
353 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
354 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
355
356 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
357
358 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
359 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
360 /**
361 * @}
362 */
363
364 /* Private function prototypes -----------------------------------------------*/
365
366 /* Exported functions --------------------------------------------------------*/
367 /** @addtogroup I2S_LL_Exported_Functions
368 * @{
369 */
370
371 /** @addtogroup I2S_LL_EF_Init
372 * @{
373 */
374
375 /**
376 * @brief De-initialize the SPI/I2S registers to their default reset values.
377 * @param SPIx SPI Instance
378 * @retval An ErrorStatus enumeration value:
379 * - SUCCESS: SPI registers are de-initialized
380 * - ERROR: SPI registers are not de-initialized
381 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)382 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
383 {
384 return LL_SPI_DeInit(SPIx);
385 }
386
387 /**
388 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
389 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
390 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
391 * @param SPIx SPI Instance
392 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: SPI registers are Initialized
395 * - ERROR: SPI registers are not Initialized
396 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)397 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
398 {
399 uint32_t i2sdiv = 2U;
400 uint32_t i2sodd = 0U;
401 uint32_t packetlength = 1U;
402 uint32_t tmp;
403 #if !defined (SPI_I2S_FULLDUPLEX_SUPPORT)
404 LL_RCC_ClocksTypeDef rcc_clocks;
405 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
406 uint32_t sourceclock;
407 ErrorStatus status = ERROR;
408
409 /* Check the I2S parameters */
410 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
411 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
412 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
413 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
414 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
415 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
416 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
417
418 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
419 {
420 /*---------------------------- SPIx I2SCFGR Configuration --------------------
421 * Configure SPIx I2SCFGR with parameters:
422 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
423 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
424 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
425 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
426 */
427
428 /* Write to SPIx I2SCFGR */
429 MODIFY_REG(SPIx->I2SCFGR,
430 I2S_I2SCFGR_CLEAR_MASK,
431 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
432 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
433 SPI_I2SCFGR_I2SMOD);
434
435 /*---------------------------- SPIx I2SPR Configuration ----------------------
436 * Configure SPIx I2SPR with parameters:
437 * - MCLKOutput: SPI_I2SPR_MCKOE bit
438 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
439 */
440
441 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
442 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
443 */
444 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
445 {
446 /* Check the frame length (For the Prescaler computing)
447 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
448 */
449 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
450 {
451 /* Packet length is 32 bits */
452 packetlength = 2U;
453 }
454
455 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
456 /* If an external I2S clock has to be used, the specific define should be set
457 in the project configuration or in the stm32f3xx_ll_rcc.h file */
458 /* Get the I2S source clock value */
459 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
460 #else /* Case for STM32F373xC and STM32F378xx series */
461 /* I2S Clock source is System clock: Get System Clock frequency */
462 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
463 if (SPIx == SPI1)
464 {
465 sourceclock = rcc_clocks.PCLK2_Frequency;
466 }
467 else /* SPI2 or SPI3 */
468 {
469 sourceclock = rcc_clocks.PCLK1_Frequency;
470 }
471
472 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
473
474 /* Compute the Real divider depending on the MCLK output state with a floating point */
475 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
476 {
477 /* MCLK output is enabled */
478 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
479 }
480 else
481 {
482 /* MCLK output is disabled */
483 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
484 }
485
486 /* Remove the floating point */
487 tmp = tmp / 10U;
488
489 /* Check the parity of the divider */
490 i2sodd = (tmp & (uint16_t)0x0001U);
491
492 /* Compute the i2sdiv prescaler */
493 i2sdiv = ((tmp - i2sodd) / 2U);
494
495 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
496 i2sodd = (i2sodd << 8U);
497 }
498
499 /* Test if the divider is 1 or 0 or greater than 0xFF */
500 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
501 {
502 /* Set the default values */
503 i2sdiv = 2U;
504 i2sodd = 0U;
505 }
506
507 /* Write to SPIx I2SPR register the computed value */
508 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
509
510 status = SUCCESS;
511 }
512 return status;
513 }
514
515 /**
516 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
517 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
518 * whose fields will be set to default values.
519 * @retval None
520 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)521 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
522 {
523 /*--------------- Reset I2S init structure parameters values -----------------*/
524 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
525 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
526 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
527 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
528 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
529 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
530 }
531
532 /**
533 * @brief Set linear and parity prescaler.
534 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
535 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
536 * @param SPIx SPI Instance
537 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
538 * @param PrescalerParity This parameter can be one of the following values:
539 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
540 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
541 * @retval None
542 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)543 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
544 {
545 /* Check the I2S parameters */
546 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
547 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
548 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
549
550 /* Write to SPIx I2SPR */
551 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
552 }
553
554 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
555 /**
556 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
557 * I2Sxext according to the specified parameters in the I2S_InitStruct.
558 * @note The structure pointed by I2S_InitStruct parameter should be the same
559 * used for the master I2S peripheral. In this case, if the master is
560 * configured as transmitter, the slave will be receiver and vice versa.
561 * Or you can force a different mode by modifying the field I2S_Mode to the
562 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
563 * @param I2Sxext SPI Instance
564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
565 * @retval An ErrorStatus enumeration value:
566 * - SUCCESS: I2Sxext registers are Initialized
567 * - ERROR: I2Sxext registers are not Initialized
568 */
LL_I2S_InitFullDuplex(SPI_TypeDef * I2Sxext,LL_I2S_InitTypeDef * I2S_InitStruct)569 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
570 {
571 uint32_t mode = 0U;
572 ErrorStatus status = ERROR;
573
574 /* Check the I2S parameters */
575 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
576 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
577 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
578 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
579 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
580
581 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
582 {
583 /*---------------------------- SPIx I2SCFGR Configuration --------------------
584 * Configure SPIx I2SCFGR with parameters:
585 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
586 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
587 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
588 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
589 */
590
591 /* Reset I2SPR registers */
592 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
593
594 /* Get the mode to be configured for the extended I2S */
595 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
596 {
597 mode = LL_I2S_MODE_SLAVE_RX;
598 }
599 else
600 {
601 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
602 {
603 mode = LL_I2S_MODE_SLAVE_TX;
604 }
605 }
606
607 /* Write to SPIx I2SCFGR */
608 MODIFY_REG(I2Sxext->I2SCFGR,
609 I2S_I2SCFGR_CLEAR_MASK,
610 I2S_InitStruct->Standard |
611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
612 SPI_I2SCFGR_I2SMOD | mode);
613
614 status = SUCCESS;
615 }
616 return status;
617 }
618 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
619
620 /**
621 * @}
622 */
623
624 /**
625 * @}
626 */
627
628 /**
629 * @}
630 */
631 #endif /* SPI_I2S_SUPPORT */
632
633 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
634
635 /**
636 * @}
637 */
638
639 #endif /* USE_FULL_LL_DRIVER */
640
641
