1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f3xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif /* USE_FULL_ASSERT */
26 /** @addtogroup STM32F3xx_LL_Driver
27 * @{
28 */
29
30 #if defined(RCC)
31
32 /** @defgroup RCC_LL RCC
33 * @{
34 */
35
36 /* Private types -------------------------------------------------------------*/
37 /* Private variables ---------------------------------------------------------*/
38 /** @addtogroup RCC_LL_Private_Variables
39 * @{
40 */
41 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
42 static const uint16_t aADCPrescTable[16U] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
43 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
44 #if defined(RCC_CFGR_SDPRE)
45 static const uint8_t aSDADCPrescTable[16U] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
46 #endif /* RCC_CFGR_SDPRE */
47 /**
48 * @}
49 */
50
51
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 /** @addtogroup RCC_LL_Private_Macros
55 * @{
56 */
57 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
58 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
60 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
61 #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
62 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
64 #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
65 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
67 #else
68 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
69 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
70
71 #if defined(UART4) && defined(UART5)
72 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
73 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
74 #elif defined(UART4)
75 #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
76 #elif defined(UART5)
77 #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
78 #endif /* UART4 && UART5*/
79
80 #if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
81 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
82 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
83 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
84
85 #elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
86 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
87 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
88
89 #elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
90 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
91 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
92
93 #else
94 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
95 #endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
96
97 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
98
99 #if defined(USB)
100 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
101 #endif /* USB */
102
103 #if defined(RCC_CFGR_ADCPRE)
104 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
105 #else
106 #if defined(RCC_CFGR2_ADC1PRES)
107 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
108 #elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
109 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
110 || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
111 #else /* RCC_CFGR2_ADCPRE12 */
112 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
113 #endif /* RCC_CFGR2_ADC1PRES */
114 #endif /* RCC_CFGR_ADCPRE */
115
116 #if defined(RCC_CFGR_SDPRE)
117 #define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
118 #endif /* RCC_CFGR_SDPRE */
119
120 #if defined(CEC)
121 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
122 #endif /* CEC */
123
124 #if defined(RCC_CFGR3_TIMSW)
125 #if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
126 && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
127 && defined(RCC_CFGR3_TIM34SW)
128
129 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
130 || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
131 || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
132 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
133 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
134 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
135 || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
136 || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
137
138 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
139 && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
140 && defined(RCC_CFGR3_TIM34SW)
141
142 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
143 || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
144 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
145 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
146 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
147 || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
148
149 #elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
150 && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
151 && !defined(RCC_CFGR3_TIM34SW)
152
153 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
154 || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
155
156 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
157 && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
158 && !defined(RCC_CFGR3_TIM34SW)
159
160 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
161 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
162 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
163 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
164
165 #elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
166 && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
167 && !defined(RCC_CFGR3_TIM34SW)
168
169 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
170
171 #else
172 #error "Miss macro"
173 #endif /* RCC_CFGR3_TIMxSW */
174 #endif /* RCC_CFGR3_TIMSW */
175
176 #if defined(HRTIM1)
177 #define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
178 #endif /* HRTIM1 */
179
180 /**
181 * @}
182 */
183
184 /* Private function prototypes -----------------------------------------------*/
185 /** @defgroup RCC_LL_Private_Functions RCC Private functions
186 * @{
187 */
188 uint32_t RCC_GetSystemClockFreq(void);
189 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
190 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
191 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
192 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
193 /**
194 * @}
195 */
196
197
198 /* Exported functions --------------------------------------------------------*/
199 /** @addtogroup RCC_LL_Exported_Functions
200 * @{
201 */
202
203 /** @addtogroup RCC_LL_EF_Init
204 * @{
205 */
206
207 /**
208 * @brief Reset the RCC clock configuration to the default reset state.
209 * @note The default reset state of the clock configuration is given below:
210 * - HSI ON and used as system clock source
211 * - HSE and PLL OFF
212 * - AHB, APB1 and APB2 prescaler set to 1.
213 * - CSS, MCO OFF
214 * - All interrupts disabled
215 * @note This function doesn't modify the configuration of the
216 * - Peripheral clocks
217 * - LSI, LSE and RTC clocks
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: RCC registers are de-initialized
220 * - ERROR: not applicable
221 */
LL_RCC_DeInit(void)222 ErrorStatus LL_RCC_DeInit(void)
223 {
224 __IO uint32_t vl_mask;
225
226 /* Set HSION bit */
227 LL_RCC_HSI_Enable();
228
229 /* Wait for HSI READY bit */
230 while(LL_RCC_HSI_IsReady() != 1U)
231 {}
232
233 /* Set HSITRIM bits to the reset value*/
234 LL_RCC_HSI_SetCalibTrimming(0x10U);
235
236 /* Reset SW, HPRE, PPRE and MCOSEL bits */
237 vl_mask = 0xFFFFFFFFU;
238 CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 |\
239 RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
240
241 /* Write new value in CFGR register */
242 LL_RCC_WriteReg(CFGR, vl_mask);
243
244 /* Wait till system clock source is ready */
245 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
246 {}
247
248 /* Read CR register */
249 vl_mask = LL_RCC_ReadReg(CR);
250
251 /* Reset HSEON, CSSON, PLLON bits */
252 CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
253
254 /* Write new value in CR register */
255 LL_RCC_WriteReg(CR, vl_mask);
256
257 /* Wait for PLL READY bit to be reset */
258 while(LL_RCC_PLL_IsReady() != 0U)
259 {}
260
261 /* Reset HSEBYP bit */
262 LL_RCC_HSE_DisableBypass();
263
264 /* Reset CFGR register */
265 LL_RCC_WriteReg(CFGR, 0x00000000U);
266
267 /* Reset CFGR2 register */
268 LL_RCC_WriteReg(CFGR2, 0x00000000U);
269
270 /* Reset CFGR3 register */
271 LL_RCC_WriteReg(CFGR3, 0x00000000U);
272
273 /* Clear pending flags */
274 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC |\
275 LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
276
277 /* Write new value in CIR register */
278 LL_RCC_WriteReg(CIR, vl_mask);
279
280 /* Disable all interrupts */
281 LL_RCC_WriteReg(CIR, 0x00000000U);
282
283 /* Clear reset flags */
284 LL_RCC_ClearResetFlags();
285
286 return SUCCESS;
287 }
288
289 /**
290 * @}
291 */
292
293 /** @addtogroup RCC_LL_EF_Get_Freq
294 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
295 * and different peripheral clocks available on the device.
296 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
297 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
298 * @note If SYSCLK source is PLL, function returns values based on
299 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
300 * @note (**) HSI_VALUE is a defined constant but the real value may vary
301 * depending on the variations in voltage and temperature.
302 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
303 * HSE_VALUE is same as the real frequency of the crystal used.
304 * Otherwise, this function may have wrong result.
305 * @note The result of this function could be incorrect when using fractional
306 * value for HSE crystal.
307 * @note This function can be used by the user application to compute the
308 * baud-rate for the communication peripherals or configure other parameters.
309 * @{
310 */
311
312 /**
313 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
314 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
315 * must be called to update structure fields. Otherwise, any
316 * configuration based on this function will be incorrect.
317 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
318 * @retval None
319 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)320 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
321 {
322 /* Get SYSCLK frequency */
323 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
324
325 /* HCLK clock frequency */
326 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
327
328 /* PCLK1 clock frequency */
329 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
330
331 /* PCLK2 clock frequency */
332 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
333 }
334
335 /**
336 * @brief Return USARTx clock frequency
337 * @param USARTxSource This parameter can be one of the following values:
338 * @arg @ref LL_RCC_USART1_CLKSOURCE
339 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
340 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
341 *
342 * (*) value not defined in all devices.
343 * @retval USART clock frequency (in Hz)
344 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
345 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)346 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
347 {
348 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
349
350 /* Check parameter */
351 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
352 #if defined(RCC_CFGR3_USART1SW)
353 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
354 {
355 /* USART1CLK clock frequency */
356 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
357 {
358 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
359 usart_frequency = RCC_GetSystemClockFreq();
360 break;
361
362 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
363 if (LL_RCC_HSI_IsReady())
364 {
365 usart_frequency = HSI_VALUE;
366 }
367 break;
368
369 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
370 if (LL_RCC_LSE_IsReady())
371 {
372 usart_frequency = LSE_VALUE;
373 }
374 break;
375
376 #if defined(RCC_CFGR3_USART1SW_PCLK1)
377 case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
378 default:
379 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
380 #else
381 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
382 default:
383 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
384 #endif /* RCC_CFGR3_USART1SW_PCLK1 */
385 break;
386 }
387 }
388 #endif /* RCC_CFGR3_USART1SW */
389
390 #if defined(RCC_CFGR3_USART2SW)
391 if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
392 {
393 /* USART2CLK clock frequency */
394 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
395 {
396 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
397 usart_frequency = RCC_GetSystemClockFreq();
398 break;
399
400 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
401 if (LL_RCC_HSI_IsReady())
402 {
403 usart_frequency = HSI_VALUE;
404 }
405 break;
406
407 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
408 if (LL_RCC_LSE_IsReady())
409 {
410 usart_frequency = LSE_VALUE;
411 }
412 break;
413
414 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
415 default:
416 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
417 break;
418 }
419 }
420 #endif /* RCC_CFGR3_USART2SW */
421
422 #if defined(RCC_CFGR3_USART3SW)
423 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
424 {
425 /* USART3CLK clock frequency */
426 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
427 {
428 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
429 usart_frequency = RCC_GetSystemClockFreq();
430 break;
431
432 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
433 if (LL_RCC_HSI_IsReady())
434 {
435 usart_frequency = HSI_VALUE;
436 }
437 break;
438
439 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
440 if (LL_RCC_LSE_IsReady())
441 {
442 usart_frequency = LSE_VALUE;
443 }
444 break;
445
446 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
447 default:
448 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
449 break;
450 }
451 }
452
453 #endif /* RCC_CFGR3_USART3SW */
454 return usart_frequency;
455 }
456
457 #if defined(UART4) || defined(UART5)
458 /**
459 * @brief Return UARTx clock frequency
460 * @param UARTxSource This parameter can be one of the following values:
461 * @arg @ref LL_RCC_UART4_CLKSOURCE
462 * @arg @ref LL_RCC_UART5_CLKSOURCE
463 * @retval UART clock frequency (in Hz)
464 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
465 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)466 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
467 {
468 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
469
470 /* Check parameter */
471 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
472
473 #if defined(UART4)
474 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
475 {
476 /* UART4CLK clock frequency */
477 switch (LL_RCC_GetUARTClockSource(UARTxSource))
478 {
479 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
480 uart_frequency = RCC_GetSystemClockFreq();
481 break;
482
483 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
484 if (LL_RCC_HSI_IsReady())
485 {
486 uart_frequency = HSI_VALUE;
487 }
488 break;
489
490 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
491 if (LL_RCC_LSE_IsReady())
492 {
493 uart_frequency = LSE_VALUE;
494 }
495 break;
496
497 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
498 default:
499 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
500 break;
501 }
502 }
503 #endif /* UART4 */
504
505 #if defined(UART5)
506 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
507 {
508 /* UART5CLK clock frequency */
509 switch (LL_RCC_GetUARTClockSource(UARTxSource))
510 {
511 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
512 uart_frequency = RCC_GetSystemClockFreq();
513 break;
514
515 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
516 if (LL_RCC_HSI_IsReady())
517 {
518 uart_frequency = HSI_VALUE;
519 }
520 break;
521
522 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
523 if (LL_RCC_LSE_IsReady())
524 {
525 uart_frequency = LSE_VALUE;
526 }
527 break;
528
529 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
530 default:
531 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
532 break;
533 }
534 }
535 #endif /* UART5 */
536
537 return uart_frequency;
538 }
539 #endif /* UART4 || UART5 */
540
541 /**
542 * @brief Return I2Cx clock frequency
543 * @param I2CxSource This parameter can be one of the following values:
544 * @arg @ref LL_RCC_I2C1_CLKSOURCE
545 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
546 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
547 *
548 * (*) value not defined in all devices
549 * @retval I2C clock frequency (in Hz)
550 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
551 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)552 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
553 {
554 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
555
556 /* Check parameter */
557 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
558
559 /* I2C1 CLK clock frequency */
560 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
561 {
562 switch (LL_RCC_GetI2CClockSource(I2CxSource))
563 {
564 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
565 i2c_frequency = RCC_GetSystemClockFreq();
566 break;
567
568 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
569 default:
570 if (LL_RCC_HSI_IsReady())
571 {
572 i2c_frequency = HSI_VALUE;
573 }
574 break;
575 }
576 }
577
578 #if defined(RCC_CFGR3_I2C2SW)
579 /* I2C2 CLK clock frequency */
580 if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
581 {
582 switch (LL_RCC_GetI2CClockSource(I2CxSource))
583 {
584 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
585 i2c_frequency = RCC_GetSystemClockFreq();
586 break;
587
588 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
589 default:
590 if (LL_RCC_HSI_IsReady())
591 {
592 i2c_frequency = HSI_VALUE;
593 }
594 break;
595 }
596 }
597 #endif /*RCC_CFGR3_I2C2SW*/
598
599 #if defined(RCC_CFGR3_I2C3SW)
600 /* I2C3 CLK clock frequency */
601 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
602 {
603 switch (LL_RCC_GetI2CClockSource(I2CxSource))
604 {
605 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
606 i2c_frequency = RCC_GetSystemClockFreq();
607 break;
608
609 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
610 default:
611 if (LL_RCC_HSI_IsReady())
612 {
613 i2c_frequency = HSI_VALUE;
614 }
615 break;
616 }
617 }
618 #endif /*RCC_CFGR3_I2C3SW*/
619
620 return i2c_frequency;
621 }
622
623 #if defined(RCC_CFGR_I2SSRC)
624 /**
625 * @brief Return I2Sx clock frequency
626 * @param I2SxSource This parameter can be one of the following values:
627 * @arg @ref LL_RCC_I2S_CLKSOURCE
628 * @retval I2S clock frequency (in Hz)
629 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)630 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
631 {
632 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
633
634 /* Check parameter */
635 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
636
637 /* I2S1CLK clock frequency */
638 switch (LL_RCC_GetI2SClockSource(I2SxSource))
639 {
640 case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
641 i2s_frequency = RCC_GetSystemClockFreq();
642 break;
643
644 /* If an external I2S clock has to be used, LL_RCC_SetI2SClockSource(LL_RCC_I2S_CLKSOURCE_PIN)
645 have to be called in the main after calling SystemClock_Config() */
646 case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
647 i2s_frequency = EXTERNAL_CLOCK_VALUE;
648 break;
649 default:
650 i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
651 break;
652 }
653
654 return i2s_frequency;
655 }
656 #endif /* RCC_CFGR_I2SSRC */
657 #if defined(USB)
658 /**
659 * @brief Return USBx clock frequency
660 * @param USBxSource This parameter can be one of the following values:
661 * @arg @ref LL_RCC_USB_CLKSOURCE
662 * @retval USB clock frequency (in Hz)
663 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
664 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
665 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)666 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
667 {
668 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
669
670 /* Check parameter */
671 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
672
673 /* USBCLK clock frequency */
674 switch (LL_RCC_GetUSBClockSource(USBxSource))
675 {
676 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
677 if (LL_RCC_PLL_IsReady())
678 {
679 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
680 }
681 break;
682
683 case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
684 default:
685 if (LL_RCC_PLL_IsReady())
686 {
687 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
688 }
689 break;
690 }
691
692 return usb_frequency;
693 }
694 #endif /* USB */
695
696 #if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
697 /**
698 * @brief Return ADCx clock frequency
699 * @param ADCxSource This parameter can be one of the following values:
700 * @arg @ref LL_RCC_ADC_CLKSOURCE (*)
701 * @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
702 * @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
703 * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
704 *
705 * (*) value not defined in all devices
706 * @retval ADC clock frequency (in Hz)
707 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)708 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
709 {
710 uint32_t adc_prescaler = 0U;
711 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
712
713 /* Check parameter */
714 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
715
716 /* Get ADC prescaler */
717 adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
718
719 #if defined(RCC_CFGR_ADCPRE)
720 /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
721 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
722 / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
723 #else
724 if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
725 {
726 /* ADC frequency = HCLK frequency */
727 adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
728 }
729 else
730 {
731 /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
732 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
733 / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
734 }
735 #endif /* RCC_CFGR_ADCPRE */
736
737 return adc_frequency;
738 }
739 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
740
741 #if defined(RCC_CFGR_SDPRE)
742 /**
743 * @brief Return SDADCx clock frequency
744 * @param SDADCxSource This parameter can be one of the following values:
745 * @arg @ref LL_RCC_SDADC_CLKSOURCE
746 * @retval SDADC clock frequency (in Hz)
747 */
LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)748 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
749 {
750 uint32_t sdadc_prescaler = 0U;
751 uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
752
753 /* Check parameter */
754 assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
755
756 /* Get SDADC prescaler */
757 sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
758
759 /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
760 sdadc_frequency = RCC_GetSystemClockFreq()
761 / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
762
763 return sdadc_frequency;
764 }
765 #endif /*RCC_CFGR_SDPRE */
766
767 #if defined(CEC)
768 /**
769 * @brief Return CECx clock frequency
770 * @param CECxSource This parameter can be one of the following values:
771 * @arg @ref LL_RCC_CEC_CLKSOURCE
772 * @retval CEC clock frequency (in Hz)
773 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
774 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)775 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
776 {
777 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
778
779 /* Check parameter */
780 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
781
782 /* CECCLK clock frequency */
783 switch (LL_RCC_GetCECClockSource(CECxSource))
784 {
785 case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
786 if (LL_RCC_HSI_IsReady())
787 {
788 cec_frequency = HSI_VALUE / 244U;
789 }
790 break;
791
792 case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
793 default:
794 if (LL_RCC_LSE_IsReady())
795 {
796 cec_frequency = LSE_VALUE;
797 }
798 break;
799 }
800
801 return cec_frequency;
802 }
803 #endif /* CEC */
804
805 #if defined(RCC_CFGR3_TIMSW)
806 /**
807 * @brief Return TIMx clock frequency
808 * @param TIMxSource This parameter can be one of the following values:
809 * @arg @ref LL_RCC_TIM1_CLKSOURCE
810 * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
811 * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
812 * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
813 * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
814 * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
815 * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
816 * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
817 *
818 * (*) value not defined in all devices
819 * @retval TIM clock frequency (in Hz)
820 */
LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)821 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
822 {
823 uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
824
825 /* Check parameter */
826 assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
827
828 if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
829 {
830 /* TIM1CLK clock frequency */
831 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
832 {
833 /* PCLK2 used as TIM1 clock source */
834 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
835 }
836 else /* LL_RCC_TIM1_CLKSOURCE_PLL */
837 {
838 /* PLL clock used as TIM1 clock source */
839 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
840 }
841 }
842
843 #if defined(RCC_CFGR3_TIM8SW)
844 if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
845 {
846 /* TIM8CLK clock frequency */
847 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
848 {
849 /* PCLK2 used as TIM8 clock source */
850 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
851 }
852 else /* LL_RCC_TIM8_CLKSOURCE_PLL */
853 {
854 /* PLL clock used as TIM8 clock source */
855 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
856 }
857 }
858 #endif /*RCC_CFGR3_TIM8SW*/
859
860 #if defined(RCC_CFGR3_TIM15SW)
861 if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
862 {
863 /* TIM15CLK clock frequency */
864 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
865 {
866 /* PCLK2 used as TIM15 clock source */
867 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
868 }
869 else /* LL_RCC_TIM15_CLKSOURCE_PLL */
870 {
871 /* PLL clock used as TIM15 clock source */
872 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
873 }
874 }
875 #endif /*RCC_CFGR3_TIM15SW*/
876
877 #if defined(RCC_CFGR3_TIM16SW)
878 if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
879 {
880 /* TIM16CLK clock frequency */
881 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
882 {
883 /* PCLK2 used as TIM16 clock source */
884 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
885 }
886 else /* LL_RCC_TIM16_CLKSOURCE_PLL */
887 {
888 /* PLL clock used as TIM16 clock source */
889 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
890 }
891 }
892 #endif /*RCC_CFGR3_TIM16SW*/
893
894 #if defined(RCC_CFGR3_TIM17SW)
895 if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
896 {
897 /* TIM17CLK clock frequency */
898 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
899 {
900 /* PCLK2 used as TIM17 clock source */
901 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
902 }
903 else /* LL_RCC_TIM17_CLKSOURCE_PLL */
904 {
905 /* PLL clock used as TIM17 clock source */
906 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
907 }
908 }
909 #endif /*RCC_CFGR3_TIM17SW*/
910
911 #if defined(RCC_CFGR3_TIM20SW)
912 if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
913 {
914 /* TIM20CLK clock frequency */
915 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
916 {
917 /* PCLK2 used as TIM20 clock source */
918 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
919 }
920 else /* LL_RCC_TIM20_CLKSOURCE_PLL */
921 {
922 /* PLL clock used as TIM20 clock source */
923 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
924 }
925 }
926 #endif /*RCC_CFGR3_TIM20SW*/
927
928 #if defined(RCC_CFGR3_TIM2SW)
929 if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
930 {
931 /* TIM2CLK clock frequency */
932 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
933 {
934 /* PCLK1 used as TIM2 clock source */
935 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
936 }
937 else /* LL_RCC_TIM2_CLKSOURCE_PLL */
938 {
939 /* PLL clock used as TIM2 clock source */
940 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
941 }
942 }
943 #endif /*RCC_CFGR3_TIM2SW*/
944
945 #if defined(RCC_CFGR3_TIM34SW)
946 if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
947 {
948 /* TIM3/4 CLK clock frequency */
949 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
950 {
951 /* PCLK1 used as TIM3/4 clock source */
952 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
953 }
954 else /* LL_RCC_TIM34_CLKSOURCE_PLL */
955 {
956 /* PLL clock used as TIM3/4 clock source */
957 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
958 }
959 }
960 #endif /*RCC_CFGR3_TIM34SW*/
961
962 return tim_frequency;
963 }
964 #endif /*RCC_CFGR3_TIMSW*/
965
966 #if defined(HRTIM1)
967 /**
968 * @brief Return HRTIMx clock frequency
969 * @param HRTIMxSource This parameter can be one of the following values:
970 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
971 * @retval HRTIM clock frequency (in Hz)
972 */
LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)973 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
974 {
975 uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
976
977 /* Check parameter */
978 assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
979
980 /* HRTIM1CLK clock frequency */
981 if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
982 {
983 /* PCLK2 used as HRTIM1 clock source */
984 hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
985 }
986 else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
987 {
988 /* PLL clock used as HRTIM1 clock source */
989 hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
990 }
991
992 return hrtim_frequency;
993 }
994 #endif /* HRTIM1 */
995
996 /**
997 * @}
998 */
999
1000 /**
1001 * @}
1002 */
1003
1004 /** @addtogroup RCC_LL_Private_Functions
1005 * @{
1006 */
1007
1008 /**
1009 * @brief Return SYSTEM clock frequency
1010 * @retval SYSTEM clock frequency (in Hz)
1011 */
RCC_GetSystemClockFreq(void)1012 uint32_t RCC_GetSystemClockFreq(void)
1013 {
1014 uint32_t frequency = 0U;
1015
1016 /* Get SYSCLK source -------------------------------------------------------*/
1017 switch (LL_RCC_GetSysClkSource())
1018 {
1019 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1020 frequency = HSI_VALUE;
1021 break;
1022
1023 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1024 frequency = HSE_VALUE;
1025 break;
1026
1027 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1028 frequency = RCC_PLL_GetFreqDomain_SYS();
1029 break;
1030
1031 default:
1032 frequency = HSI_VALUE;
1033 break;
1034 }
1035
1036 return frequency;
1037 }
1038
1039 /**
1040 * @brief Return HCLK clock frequency
1041 * @param SYSCLK_Frequency SYSCLK clock frequency
1042 * @retval HCLK clock frequency (in Hz)
1043 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1044 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1045 {
1046 /* HCLK clock frequency */
1047 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1048 }
1049
1050 /**
1051 * @brief Return PCLK1 clock frequency
1052 * @param HCLK_Frequency HCLK clock frequency
1053 * @retval PCLK1 clock frequency (in Hz)
1054 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1055 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1056 {
1057 /* PCLK1 clock frequency */
1058 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1059 }
1060
1061 /**
1062 * @brief Return PCLK2 clock frequency
1063 * @param HCLK_Frequency HCLK clock frequency
1064 * @retval PCLK2 clock frequency (in Hz)
1065 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1066 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1067 {
1068 /* PCLK2 clock frequency */
1069 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1070 }
1071
1072 /**
1073 * @brief Return PLL clock frequency used for system domain
1074 * @retval PLL clock frequency (in Hz)
1075 */
RCC_PLL_GetFreqDomain_SYS(void)1076 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1077 {
1078 uint32_t pllinputfreq = 0U, pllsource = 0U;
1079
1080 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
1081
1082 /* Get PLL source */
1083 pllsource = LL_RCC_PLL_GetMainSource();
1084
1085 switch (pllsource)
1086 {
1087 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1088 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1089 pllinputfreq = HSI_VALUE;
1090 #else
1091 case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
1092 pllinputfreq = HSI_VALUE / 2U;
1093 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1094 break;
1095
1096 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1097 pllinputfreq = HSE_VALUE;
1098 break;
1099
1100 default:
1101 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1102 pllinputfreq = HSI_VALUE;
1103 #else
1104 pllinputfreq = HSI_VALUE / 2U;
1105 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1106 break;
1107 }
1108 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1109 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
1110 #else
1111 return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
1112 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1113 }
1114 /**
1115 * @}
1116 */
1117
1118 /**
1119 * @}
1120 */
1121
1122 #endif /* defined(RCC) */
1123
1124 /**
1125 * @}
1126 */
1127
1128 #endif /* USE_FULL_LL_DRIVER */
1129
1130
