1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_dma.h"
22 #include "stm32f3xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28
29 /** @addtogroup STM32F3xx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
52
53 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
55
56 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
57 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
58
59 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
60 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
62
63 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
64 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
66
67 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
68
69
70 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
71 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
72 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
74
75 #if defined (DMA2)
76 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
77 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
78 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
79 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
84 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
85 (((INSTANCE) == DMA2) && \
86 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
87 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
88 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
89 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
90 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
91 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
92 ((CHANNEL) == LL_DMA_CHANNEL_7))))
93 #else
94 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
95 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
96 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
97 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
98 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
99 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
100 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
101 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
102 (((INSTANCE) == DMA2) && \
103 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
104 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
105 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
106 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
107 ((CHANNEL) == LL_DMA_CHANNEL_5))))
108 #endif
109 #else
110 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
111 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
112 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
113 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
114 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
115 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
116 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
117 ((CHANNEL) == LL_DMA_CHANNEL_7))))
118 #endif
119 /**
120 * @}
121 */
122
123 /* Private function prototypes -----------------------------------------------*/
124
125 /* Exported functions --------------------------------------------------------*/
126 /** @addtogroup DMA_LL_Exported_Functions
127 * @{
128 */
129
130 /** @addtogroup DMA_LL_EF_Init
131 * @{
132 */
133
134 /**
135 * @brief De-initialize the DMA registers to their default reset values.
136 * @param DMAx DMAx Instance
137 * @param Channel This parameter can be one of the following values:
138 * @arg @ref LL_DMA_CHANNEL_1
139 * @arg @ref LL_DMA_CHANNEL_2
140 * @arg @ref LL_DMA_CHANNEL_3
141 * @arg @ref LL_DMA_CHANNEL_4
142 * @arg @ref LL_DMA_CHANNEL_5
143 * @arg @ref LL_DMA_CHANNEL_6
144 * @arg @ref LL_DMA_CHANNEL_7
145 * @retval An ErrorStatus enumeration value:
146 * - SUCCESS: DMA registers are de-initialized
147 * - ERROR: DMA registers are not de-initialized
148 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)149 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
150 {
151 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
152 ErrorStatus status = SUCCESS;
153
154 /* Check the DMA Instance DMAx and Channel parameters*/
155 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
156
157 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
158
159 /* Disable the selected DMAx_Channely */
160 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
161
162 /* Reset DMAx_Channely control register */
163 LL_DMA_WriteReg(tmp, CCR, 0U);
164
165 /* Reset DMAx_Channely remaining bytes register */
166 LL_DMA_WriteReg(tmp, CNDTR, 0U);
167
168 /* Reset DMAx_Channely peripheral address register */
169 LL_DMA_WriteReg(tmp, CPAR, 0U);
170
171 /* Reset DMAx_Channely memory address register */
172 LL_DMA_WriteReg(tmp, CMAR, 0U);
173
174
175 if (Channel == LL_DMA_CHANNEL_1)
176 {
177 /* Reset interrupt pending bits for DMAx Channel1 */
178 LL_DMA_ClearFlag_GI1(DMAx);
179 }
180 else if (Channel == LL_DMA_CHANNEL_2)
181 {
182 /* Reset interrupt pending bits for DMAx Channel2 */
183 LL_DMA_ClearFlag_GI2(DMAx);
184 }
185 else if (Channel == LL_DMA_CHANNEL_3)
186 {
187 /* Reset interrupt pending bits for DMAx Channel3 */
188 LL_DMA_ClearFlag_GI3(DMAx);
189 }
190 else if (Channel == LL_DMA_CHANNEL_4)
191 {
192 /* Reset interrupt pending bits for DMAx Channel4 */
193 LL_DMA_ClearFlag_GI4(DMAx);
194 }
195 else if (Channel == LL_DMA_CHANNEL_5)
196 {
197 /* Reset interrupt pending bits for DMAx Channel5 */
198 LL_DMA_ClearFlag_GI5(DMAx);
199 }
200
201 else if (Channel == LL_DMA_CHANNEL_6)
202 {
203 /* Reset interrupt pending bits for DMAx Channel6 */
204 LL_DMA_ClearFlag_GI6(DMAx);
205 }
206 else if (Channel == LL_DMA_CHANNEL_7)
207 {
208 /* Reset interrupt pending bits for DMAx Channel7 */
209 LL_DMA_ClearFlag_GI7(DMAx);
210 }
211 else
212 {
213 status = ERROR;
214 }
215
216 return status;
217 }
218
219 /**
220 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
221 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
222 * @arg @ref __LL_DMA_GET_INSTANCE
223 * @arg @ref __LL_DMA_GET_CHANNEL
224 * @param DMAx DMAx Instance
225 * @param Channel This parameter can be one of the following values:
226 * @arg @ref LL_DMA_CHANNEL_1
227 * @arg @ref LL_DMA_CHANNEL_2
228 * @arg @ref LL_DMA_CHANNEL_3
229 * @arg @ref LL_DMA_CHANNEL_4
230 * @arg @ref LL_DMA_CHANNEL_5
231 * @arg @ref LL_DMA_CHANNEL_6
232 * @arg @ref LL_DMA_CHANNEL_7
233 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
234 * @retval An ErrorStatus enumeration value:
235 * - SUCCESS: DMA registers are initialized
236 * - ERROR: Not applicable
237 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)238 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
239 {
240 /* Check the DMA Instance DMAx and Channel parameters*/
241 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
242
243 /* Check the DMA parameters from DMA_InitStruct */
244 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
245 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
246 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
247 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
248 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
249 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
250 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
251 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
252
253 /*---------------------------- DMAx CCR Configuration ------------------------
254 * Configure DMAx_Channely: data transfer direction, data transfer mode,
255 * peripheral and memory increment mode,
256 * data size alignment and priority level with parameters :
257 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
258 * - Mode: DMA_CCR_CIRC bit
259 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
260 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
261 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
262 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
263 * - Priority: DMA_CCR_PL[1:0] bits
264 */
265 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
266 DMA_InitStruct->Mode | \
267 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
268 DMA_InitStruct->MemoryOrM2MDstIncMode | \
269 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
270 DMA_InitStruct->MemoryOrM2MDstDataSize | \
271 DMA_InitStruct->Priority);
272
273 /*-------------------------- DMAx CMAR Configuration -------------------------
274 * Configure the memory or destination base address with parameter :
275 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
276 */
277 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
278
279 /*-------------------------- DMAx CPAR Configuration -------------------------
280 * Configure the peripheral or source base address with parameter :
281 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
282 */
283 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
284
285 /*--------------------------- DMAx CNDTR Configuration -----------------------
286 * Configure the peripheral base address with parameter :
287 * - NbData: DMA_CNDTR_NDT[15:0] bits
288 */
289 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
290
291
292 return SUCCESS;
293 }
294
295 /**
296 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
297 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
298 * @retval None
299 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)300 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
301 {
302 /* Set DMA_InitStruct fields to default values */
303 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
304 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
305 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
306 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
307 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
308 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
309 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
310 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
311 DMA_InitStruct->NbData = 0x00000000U;
312 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
313 }
314
315 /**
316 * @}
317 */
318
319 /**
320 * @}
321 */
322
323 /**
324 * @}
325 */
326
327 #endif /* DMA1 || DMA2 */
328
329 /**
330 * @}
331 */
332
333 #endif /* USE_FULL_LL_DRIVER */
334
335
