1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2016 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file in
17 * the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 ******************************************************************************
20 */
21
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f3xx_hal.h"
24
25 /** @addtogroup STM32F3xx_HAL_Driver
26 * @{
27 */
28
29 #ifdef HAL_RCC_MODULE_ENABLED
30
31 /** @defgroup RCCEx RCCEx
32 * @brief RCC Extension HAL module driver.
33 * @{
34 */
35
36 /* Private typedef -----------------------------------------------------------*/
37 /* Private define ------------------------------------------------------------*/
38 /* Private macro -------------------------------------------------------------*/
39 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
40 * @{
41 */
42 /**
43 * @}
44 */
45
46 /* Private variables ---------------------------------------------------------*/
47 /* Private function prototypes -----------------------------------------------*/
48 /* Private functions ---------------------------------------------------------*/
49 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
50 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
51 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
52 || defined(RCC_CFGR3_HRTIM1SW)
53 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
54 * @{
55 */
56 static uint32_t RCC_GetPLLCLKFreq(void);
57
58 /**
59 * @}
60 */
61 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
62
63 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
64 * @{
65 */
66
67 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
68 * @brief Extended Peripheral Control functions
69 *
70 @verbatim
71 ===============================================================================
72 ##### Extended Peripheral Control functions #####
73 ===============================================================================
74 [..]
75 This subsection provides a set of functions allowing to control the RCC Clocks
76 frequencies.
77 [..]
78 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
79 select the RTC clock source; in this case the Backup domain will be reset in
80 order to modify the RTC Clock source, as consequence RTC registers (including
81 the backup registers) are set to their reset values.
82
83 @endverbatim
84 * @{
85 */
86
87 /**
88 * @brief Initializes the RCC extended peripherals clocks according to the specified
89 * parameters in the RCC_PeriphCLKInitTypeDef.
90 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
91 * contains the configuration information for the Extended Peripherals clocks
92 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
93 *
94 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
95 * the RTC clock source; in this case the Backup domain will be reset in
96 * order to modify the RTC Clock source, as consequence RTC registers (including
97 * the backup registers) and RCC_BDCR register are set to their reset values.
98 *
99 * @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or
100 * APB clock x 2 depending on the APB prescaler.
101 * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
102 *
103 * @retval HAL status
104 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)105 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
106 {
107 uint32_t tickstart = 0U;
108 uint32_t temp_reg = 0U;
109 FlagStatus pwrclkchanged = RESET;
110
111 /* Check the parameters */
112 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
113
114 /*---------------------------- RTC configuration -------------------------------*/
115 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
116 {
117 /* check for RTC Parameters used to output RTCCLK */
118 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
119
120
121 /* As soon as function is called to change RTC clock source, activation of the
122 power domain is done. */
123 /* Requires to enable write access to Backup Domain of necessary */
124 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
125 {
126 __HAL_RCC_PWR_CLK_ENABLE();
127 pwrclkchanged = SET;
128 }
129
130 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
131 {
132 /* Enable write access to Backup domain */
133 SET_BIT(PWR->CR, PWR_CR_DBP);
134
135 /* Wait for Backup domain Write protection disable */
136 tickstart = HAL_GetTick();
137
138 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
139 {
140 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
141 {
142 return HAL_TIMEOUT;
143 }
144 }
145 }
146
147 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
148 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
149 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
150 {
151 /* Store the content of BDCR register before the reset of Backup Domain */
152 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
153 /* RTC Clock selection can be changed only if the Backup Domain is reset */
154 __HAL_RCC_BACKUPRESET_FORCE();
155 __HAL_RCC_BACKUPRESET_RELEASE();
156 /* Restore the Content of BDCR register */
157 RCC->BDCR = temp_reg;
158
159 /* Wait for LSERDY if LSE was enabled */
160 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
161 {
162 /* Get Start Tick */
163 tickstart = HAL_GetTick();
164
165 /* Wait till LSE is ready */
166 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
167 {
168 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
169 {
170 return HAL_TIMEOUT;
171 }
172 }
173 }
174 }
175 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
176
177 /* Require to disable power clock if necessary */
178 if(pwrclkchanged == SET)
179 {
180 __HAL_RCC_PWR_CLK_DISABLE();
181 }
182 }
183
184 /*------------------------------- USART1 Configuration ------------------------*/
185 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
186 {
187 /* Check the parameters */
188 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
189
190 /* Configure the USART1 clock source */
191 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
192 }
193
194 #if defined(RCC_CFGR3_USART2SW)
195 /*----------------------------- USART2 Configuration --------------------------*/
196 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
197 {
198 /* Check the parameters */
199 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
200
201 /* Configure the USART2 clock source */
202 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
203 }
204 #endif /* RCC_CFGR3_USART2SW */
205
206 #if defined(RCC_CFGR3_USART3SW)
207 /*------------------------------ USART3 Configuration ------------------------*/
208 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
209 {
210 /* Check the parameters */
211 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
212
213 /* Configure the USART3 clock source */
214 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
215 }
216 #endif /* RCC_CFGR3_USART3SW */
217
218 /*------------------------------ I2C1 Configuration ------------------------*/
219 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
220 {
221 /* Check the parameters */
222 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
223
224 /* Configure the I2C1 clock source */
225 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
226 }
227
228 #if defined(STM32F302xE) || defined(STM32F303xE)\
229 || defined(STM32F302xC) || defined(STM32F303xC)\
230 || defined(STM32F302x8) \
231 || defined(STM32F373xC)
232 /*------------------------------ USB Configuration ------------------------*/
233 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
234 {
235 /* Check the parameters */
236 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
237
238 /* Configure the USB clock source */
239 __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
240 }
241
242 #endif /* STM32F302xE || STM32F303xE || */
243 /* STM32F302xC || STM32F303xC || */
244 /* STM32F302x8 || */
245 /* STM32F373xC */
246
247 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
248 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
249 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
250 || defined(STM32F373xC) || defined(STM32F378xx)
251
252 /*------------------------------ I2C2 Configuration ------------------------*/
253 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
254 {
255 /* Check the parameters */
256 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
257
258 /* Configure the I2C2 clock source */
259 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
260 }
261
262 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
263 /* STM32F302xC || STM32F303xC || STM32F358xx || */
264 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
265 /* STM32F373xC || STM32F378xx */
266
267 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
268 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
269
270 /*------------------------------ I2C3 Configuration ------------------------*/
271 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
272 {
273 /* Check the parameters */
274 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
275
276 /* Configure the I2C3 clock source */
277 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
278 }
279 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
280 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
281
282 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
283 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
284
285 /*------------------------------ UART4 Configuration ------------------------*/
286 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
287 {
288 /* Check the parameters */
289 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
290
291 /* Configure the UART4 clock source */
292 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
293 }
294
295 /*------------------------------ UART5 Configuration ------------------------*/
296 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
297 {
298 /* Check the parameters */
299 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
300
301 /* Configure the UART5 clock source */
302 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
303 }
304
305 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
306 /* STM32F302xC || STM32F303xC || STM32F358xx */
307
308 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
309 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
310 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
311 /*------------------------------ I2S Configuration ------------------------*/
312 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
313 {
314 /* Check the parameters */
315 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
316
317 /* Configure the I2S clock source */
318 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
319 }
320
321 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
322 /* STM32F302xC || STM32F303xC || STM32F358xx || */
323 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
324
325 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
326
327 /*------------------------------ ADC1 clock Configuration ------------------*/
328 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
329 {
330 /* Check the parameters */
331 assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
332
333 /* Configure the ADC1 clock source */
334 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
335 }
336
337 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
338
339 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
340 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
341 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
342
343 /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
344 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
345 {
346 /* Check the parameters */
347 assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
348
349 /* Configure the ADC12 clock source */
350 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
351 }
352
353 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
354 /* STM32F302xC || STM32F303xC || STM32F358xx || */
355 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
356
357 #if defined(STM32F303xE) || defined(STM32F398xx)\
358 || defined(STM32F303xC) || defined(STM32F358xx)
359
360 /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
361 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
362 {
363 /* Check the parameters */
364 assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
365
366 /* Configure the ADC34 clock source */
367 __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
368 }
369
370 #endif /* STM32F303xE || STM32F398xx || */
371 /* STM32F303xC || STM32F358xx */
372
373 #if defined(STM32F373xC) || defined(STM32F378xx)
374
375 /*------------------------------ ADC1 clock Configuration ------------------*/
376 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
377 {
378 /* Check the parameters */
379 assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
380
381 /* Configure the ADC1 clock source */
382 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
383 }
384
385 #endif /* STM32F373xC || STM32F378xx */
386
387 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
388 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
389 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
390 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
391
392 /*------------------------------ TIM1 clock Configuration ----------------*/
393 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
394 {
395 /* Check the parameters */
396 assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
397
398 /* Configure the TIM1 clock source */
399 __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
400 }
401
402 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
403 /* STM32F302xC || STM32F303xC || STM32F358xx || */
404 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
405 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
406
407 #if defined(STM32F303xE) || defined(STM32F398xx)\
408 || defined(STM32F303xC) || defined(STM32F358xx)
409
410 /*------------------------------ TIM8 clock Configuration ----------------*/
411 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
412 {
413 /* Check the parameters */
414 assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
415
416 /* Configure the TIM8 clock source */
417 __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
418 }
419
420 #endif /* STM32F303xE || STM32F398xx || */
421 /* STM32F303xC || STM32F358xx */
422
423 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
424
425 /*------------------------------ TIM15 clock Configuration ----------------*/
426 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
427 {
428 /* Check the parameters */
429 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
430
431 /* Configure the TIM15 clock source */
432 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
433 }
434
435 /*------------------------------ TIM16 clock Configuration ----------------*/
436 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
437 {
438 /* Check the parameters */
439 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
440
441 /* Configure the TIM16 clock source */
442 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
443 }
444
445 /*------------------------------ TIM17 clock Configuration ----------------*/
446 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
447 {
448 /* Check the parameters */
449 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
450
451 /* Configure the TIM17 clock source */
452 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
453 }
454
455 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
456
457 #if defined(STM32F334x8)
458
459 /*------------------------------ HRTIM1 clock Configuration ----------------*/
460 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
461 {
462 /* Check the parameters */
463 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
464
465 /* Configure the HRTIM1 clock source */
466 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
467 }
468
469 #endif /* STM32F334x8 */
470
471 #if defined(STM32F373xC) || defined(STM32F378xx)
472
473 /*------------------------------ SDADC clock Configuration -------------------*/
474 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
475 {
476 /* Check the parameters */
477 assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
478
479 /* Configure the SDADC clock prescaler */
480 __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
481 }
482
483 /*------------------------------ CEC clock Configuration -------------------*/
484 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
485 {
486 /* Check the parameters */
487 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
488
489 /* Configure the CEC clock source */
490 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
491 }
492
493 #endif /* STM32F373xC || STM32F378xx */
494
495 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
496
497 /*------------------------------ TIM2 clock Configuration -------------------*/
498 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
499 {
500 /* Check the parameters */
501 assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
502
503 /* Configure the CEC clock source */
504 __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
505 }
506
507 /*------------------------------ TIM3 clock Configuration -------------------*/
508 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
509 {
510 /* Check the parameters */
511 assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
512
513 /* Configure the CEC clock source */
514 __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
515 }
516
517 /*------------------------------ TIM15 clock Configuration ------------------*/
518 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
519 {
520 /* Check the parameters */
521 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
522
523 /* Configure the CEC clock source */
524 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
525 }
526
527 /*------------------------------ TIM16 clock Configuration ------------------*/
528 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
529 {
530 /* Check the parameters */
531 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
532
533 /* Configure the CEC clock source */
534 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
535 }
536
537 /*------------------------------ TIM17 clock Configuration ------------------*/
538 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
539 {
540 /* Check the parameters */
541 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
542
543 /* Configure the CEC clock source */
544 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
545 }
546
547 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
548
549 #if defined(STM32F303xE) || defined(STM32F398xx)
550 /*------------------------------ TIM20 clock Configuration ------------------*/
551 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
552 {
553 /* Check the parameters */
554 assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
555
556 /* Configure the CEC clock source */
557 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
558 }
559 #endif /* STM32F303xE || STM32F398xx */
560
561
562 return HAL_OK;
563 }
564
565 /**
566 * @brief Get the RCC_ClkInitStruct according to the internal
567 * RCC configuration registers.
568 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
569 * returns the configuration information for the Extended Peripherals clocks
570 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
571 * @retval None
572 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)573 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
574 {
575 /* Set all possible values for the extended clock type parameter------------*/
576 /* Common part first */
577 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
578 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
579 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
580 #else
581 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
582 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
583 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
584
585 /* Get the RTC configuration --------------------------------------------*/
586 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
587 /* Get the USART1 clock configuration --------------------------------------------*/
588 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
589 #if defined(RCC_CFGR3_USART2SW)
590 /* Get the USART2 clock configuration -----------------------------------------*/
591 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
592 #endif /* RCC_CFGR3_USART2SW */
593 #if defined(RCC_CFGR3_USART3SW)
594 /* Get the USART3 clock configuration -----------------------------------------*/
595 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
596 #endif /* RCC_CFGR3_USART3SW */
597 /* Get the I2C1 clock configuration -----------------------------------------*/
598 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
599
600 #if defined(STM32F302xE) || defined(STM32F303xE)\
601 || defined(STM32F302xC) || defined(STM32F303xC)\
602 || defined(STM32F302x8) \
603 || defined(STM32F373xC)
604
605 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
606 /* Get the USB clock configuration -----------------------------------------*/
607 PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
608
609 #endif /* STM32F302xE || STM32F303xE || */
610 /* STM32F302xC || STM32F303xC || */
611 /* STM32F302x8 || */
612 /* STM32F373xC */
613
614 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
615 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
616 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
617 || defined(STM32F373xC) || defined(STM32F378xx)
618
619 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
620 /* Get the I2C2 clock configuration -----------------------------------------*/
621 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
622
623 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
624 /* STM32F302xC || STM32F303xC || STM32F358xx || */
625 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
626 /* STM32F373xC || STM32F378xx */
627
628 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
629 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
630
631 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
632 /* Get the I2C3 clock configuration -----------------------------------------*/
633 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
634
635 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
636 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
637
638 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
639 || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
640
641 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
642 /* Get the UART4 clock configuration -----------------------------------------*/
643 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
644 /* Get the UART5 clock configuration -----------------------------------------*/
645 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
646
647 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
648 /* STM32F302xC || STM32F303xC || STM32F358xx */
649
650 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
651 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
652 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
653
654 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
655 /* Get the I2S clock configuration -----------------------------------------*/
656 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
657
658 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
659 /* STM32F302xC || STM32F303xC || STM32F358xx || */
660 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
661
662 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
663 || defined(STM32F373xC) || defined(STM32F378xx)
664
665 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
666 /* Get the ADC1 clock configuration -----------------------------------------*/
667 PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
668
669 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
670 /* STM32F373xC || STM32F378xx */
671
672 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
673 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
674 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
675
676 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
677 /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
678 PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
679
680 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
681 /* STM32F302xC || STM32F303xC || STM32F358xx || */
682 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
683
684 #if defined(STM32F303xE) || defined(STM32F398xx)\
685 || defined(STM32F303xC) || defined(STM32F358xx)
686
687 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
688 /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
689 PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
690
691 #endif /* STM32F303xE || STM32F398xx || */
692 /* STM32F303xC || STM32F358xx */
693
694 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
695 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
696 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
697 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
698
699 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
700 /* Get the TIM1 clock configuration -----------------------------------------*/
701 PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
702
703 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
704 /* STM32F302xC || STM32F303xC || STM32F358xx || */
705 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
706 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
707
708 #if defined(STM32F303xE) || defined(STM32F398xx)\
709 || defined(STM32F303xC) || defined(STM32F358xx)
710
711 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
712 /* Get the TIM8 clock configuration -----------------------------------------*/
713 PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
714
715 #endif /* STM32F303xE || STM32F398xx || */
716 /* STM32F303xC || STM32F358xx */
717
718 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
719
720 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
721 /* Get the TIM15 clock configuration -----------------------------------------*/
722 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
723 /* Get the TIM16 clock configuration -----------------------------------------*/
724 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
725 /* Get the TIM17 clock configuration -----------------------------------------*/
726 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
727
728 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
729
730 #if defined(STM32F334x8)
731
732 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
733 /* Get the HRTIM1 clock configuration -----------------------------------------*/
734 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
735
736 #endif /* STM32F334x8 */
737
738 #if defined(STM32F373xC) || defined(STM32F378xx)
739
740 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
741 /* Get the SDADC clock configuration -----------------------------------------*/
742 PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
743
744 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
745 /* Get the CEC clock configuration -----------------------------------------*/
746 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
747
748 #endif /* STM32F373xC || STM32F378xx */
749
750 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
751
752 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
753 /* Get the TIM2 clock configuration -----------------------------------------*/
754 PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
755
756 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
757 /* Get the TIM3 clock configuration -----------------------------------------*/
758 PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
759
760 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
761 /* Get the TIM15 clock configuration -----------------------------------------*/
762 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
763
764 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
765 /* Get the TIM16 clock configuration -----------------------------------------*/
766 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
767
768 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
769 /* Get the TIM17 clock configuration -----------------------------------------*/
770 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
771
772 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
773
774 #if defined (STM32F303xE) || defined(STM32F398xx)
775 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
776 /* Get the TIM20 clock configuration -----------------------------------------*/
777 PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
778 #endif /* STM32F303xE || STM32F398xx */
779 }
780
781 /**
782 * @brief Returns the peripheral clock frequency
783 * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
784 * @param PeriphClk Peripheral clock identifier
785 * This parameter can be one of the following values:
786 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
787 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
788 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
789 @if STM32F301x8
790 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
791 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
792 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
793 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
794 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
795 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
796 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
797 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
798 @endif
799 @if STM32F302x8
800 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
801 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
802 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
803 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
804 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
805 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
806 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
807 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
808 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
809 @endif
810 @if STM32F302xC
811 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
812 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
813 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
814 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
815 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
816 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
817 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
818 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
819 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
820 @endif
821 @if STM32F302xE
822 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
823 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
824 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
825 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
826 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
827 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
828 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
829 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
830 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
831 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
832 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
833 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
834 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
835 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
836 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
837 @endif
838 @if STM32F303x8
839 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
840 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
841 @endif
842 @if STM32F303xC
843 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
844 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
845 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
846 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
847 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
848 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
849 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
850 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
851 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
852 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
853 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
854 @endif
855 @if STM32F303xE
856 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
857 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
858 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
859 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
860 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
861 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
862 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
863 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
864 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
865 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
866 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
867 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
868 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
869 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
870 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
871 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
872 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
873 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
874 @endif
875 @if STM32F318xx
876 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
877 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
878 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
879 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
880 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
881 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
882 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
883 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
884 @endif
885 @if STM32F328xx
886 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
887 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
888 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
889 @endif
890 @if STM32F334x8
891 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
892 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
893 * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
894 @endif
895 @if STM32F358xx
896 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
897 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
898 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
899 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
900 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
901 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
902 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
903 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
904 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
905 @endif
906 @if STM32F373xC
907 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
908 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
909 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
910 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
911 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
912 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
913 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
914 @endif
915 @if STM32F378xx
916 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
917 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
918 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
919 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
920 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
921 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
922 @endif
923 @if STM32F398xx
924 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
925 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
926 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
927 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
928 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
929 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
930 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
931 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
932 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
933 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
934 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
935 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
936 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
937 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
938 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
939 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
940 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
941 @endif
942 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
943 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)944 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
945 {
946 /* frequency == 0 : means that no available frequency for the peripheral */
947 uint32_t frequency = 0U;
948
949 uint32_t srcclk = 0U;
950 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
951 static const uint16_t adc_pll_prediv_table[16U] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
952 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
953 #if defined(RCC_CFGR_SDPRE)
954 static const uint8_t sdadc_prescaler_table[16U] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
955 #endif /* RCC_CFGR_SDPRE */
956
957 /* Check the parameters */
958 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
959
960 switch (PeriphClk)
961 {
962 case RCC_PERIPHCLK_RTC:
963 {
964 /* Get the current RTC source */
965 srcclk = __HAL_RCC_GET_RTC_SOURCE();
966
967 /* Check if LSE is ready and if RTC clock selection is LSE */
968 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
969 {
970 frequency = LSE_VALUE;
971 }
972 /* Check if LSI is ready and if RTC clock selection is LSI */
973 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
974 {
975 frequency = LSI_VALUE;
976 }
977 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
978 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
979 {
980 frequency = HSE_VALUE / 32U;
981 }
982 break;
983 }
984 case RCC_PERIPHCLK_USART1:
985 {
986 /* Get the current USART1 source */
987 srcclk = __HAL_RCC_GET_USART1_SOURCE();
988
989 /* Check if USART1 clock selection is PCLK1 */
990 #if defined(RCC_USART1CLKSOURCE_PCLK2)
991 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
992 {
993 frequency = HAL_RCC_GetPCLK2Freq();
994 }
995 #else
996 if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
997 {
998 frequency = HAL_RCC_GetPCLK1Freq();
999 }
1000 #endif /* RCC_USART1CLKSOURCE_PCLK2 */
1001 /* Check if HSI is ready and if USART1 clock selection is HSI */
1002 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1003 {
1004 frequency = HSI_VALUE;
1005 }
1006 /* Check if USART1 clock selection is SYSCLK */
1007 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
1008 {
1009 frequency = HAL_RCC_GetSysClockFreq();
1010 }
1011 /* Check if LSE is ready and if USART1 clock selection is LSE */
1012 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1013 {
1014 frequency = LSE_VALUE;
1015 }
1016 break;
1017 }
1018 #if defined(RCC_CFGR3_USART2SW)
1019 case RCC_PERIPHCLK_USART2:
1020 {
1021 /* Get the current USART2 source */
1022 srcclk = __HAL_RCC_GET_USART2_SOURCE();
1023
1024 /* Check if USART2 clock selection is PCLK1 */
1025 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
1026 {
1027 frequency = HAL_RCC_GetPCLK1Freq();
1028 }
1029 /* Check if HSI is ready and if USART2 clock selection is HSI */
1030 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1031 {
1032 frequency = HSI_VALUE;
1033 }
1034 /* Check if USART2 clock selection is SYSCLK */
1035 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
1036 {
1037 frequency = HAL_RCC_GetSysClockFreq();
1038 }
1039 /* Check if LSE is ready and if USART2 clock selection is LSE */
1040 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1041 {
1042 frequency = LSE_VALUE;
1043 }
1044 break;
1045 }
1046 #endif /* RCC_CFGR3_USART2SW */
1047 #if defined(RCC_CFGR3_USART3SW)
1048 case RCC_PERIPHCLK_USART3:
1049 {
1050 /* Get the current USART3 source */
1051 srcclk = __HAL_RCC_GET_USART3_SOURCE();
1052
1053 /* Check if USART3 clock selection is PCLK1 */
1054 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
1055 {
1056 frequency = HAL_RCC_GetPCLK1Freq();
1057 }
1058 /* Check if HSI is ready and if USART3 clock selection is HSI */
1059 else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1060 {
1061 frequency = HSI_VALUE;
1062 }
1063 /* Check if USART3 clock selection is SYSCLK */
1064 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
1065 {
1066 frequency = HAL_RCC_GetSysClockFreq();
1067 }
1068 /* Check if LSE is ready and if USART3 clock selection is LSE */
1069 else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1070 {
1071 frequency = LSE_VALUE;
1072 }
1073 break;
1074 }
1075 #endif /* RCC_CFGR3_USART3SW */
1076 #if defined(RCC_CFGR3_UART4SW)
1077 case RCC_PERIPHCLK_UART4:
1078 {
1079 /* Get the current UART4 source */
1080 srcclk = __HAL_RCC_GET_UART4_SOURCE();
1081
1082 /* Check if UART4 clock selection is PCLK1 */
1083 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
1084 {
1085 frequency = HAL_RCC_GetPCLK1Freq();
1086 }
1087 /* Check if HSI is ready and if UART4 clock selection is HSI */
1088 else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1089 {
1090 frequency = HSI_VALUE;
1091 }
1092 /* Check if UART4 clock selection is SYSCLK */
1093 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
1094 {
1095 frequency = HAL_RCC_GetSysClockFreq();
1096 }
1097 /* Check if LSE is ready and if UART4 clock selection is LSE */
1098 else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1099 {
1100 frequency = LSE_VALUE;
1101 }
1102 break;
1103 }
1104 #endif /* RCC_CFGR3_UART4SW */
1105 #if defined(RCC_CFGR3_UART5SW)
1106 case RCC_PERIPHCLK_UART5:
1107 {
1108 /* Get the current UART5 source */
1109 srcclk = __HAL_RCC_GET_UART5_SOURCE();
1110
1111 /* Check if UART5 clock selection is PCLK1 */
1112 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
1113 {
1114 frequency = HAL_RCC_GetPCLK1Freq();
1115 }
1116 /* Check if HSI is ready and if UART5 clock selection is HSI */
1117 else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1118 {
1119 frequency = HSI_VALUE;
1120 }
1121 /* Check if UART5 clock selection is SYSCLK */
1122 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
1123 {
1124 frequency = HAL_RCC_GetSysClockFreq();
1125 }
1126 /* Check if LSE is ready and if UART5 clock selection is LSE */
1127 else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1128 {
1129 frequency = LSE_VALUE;
1130 }
1131 break;
1132 }
1133 #endif /* RCC_CFGR3_UART5SW */
1134 case RCC_PERIPHCLK_I2C1:
1135 {
1136 /* Get the current I2C1 source */
1137 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
1138
1139 /* Check if HSI is ready and if I2C1 clock selection is HSI */
1140 if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1141 {
1142 frequency = HSI_VALUE;
1143 }
1144 /* Check if I2C1 clock selection is SYSCLK */
1145 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
1146 {
1147 frequency = HAL_RCC_GetSysClockFreq();
1148 }
1149 break;
1150 }
1151 #if defined(RCC_CFGR3_I2C2SW)
1152 case RCC_PERIPHCLK_I2C2:
1153 {
1154 /* Get the current I2C2 source */
1155 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
1156
1157 /* Check if HSI is ready and if I2C2 clock selection is HSI */
1158 if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1159 {
1160 frequency = HSI_VALUE;
1161 }
1162 /* Check if I2C2 clock selection is SYSCLK */
1163 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
1164 {
1165 frequency = HAL_RCC_GetSysClockFreq();
1166 }
1167 break;
1168 }
1169 #endif /* RCC_CFGR3_I2C2SW */
1170 #if defined(RCC_CFGR3_I2C3SW)
1171 case RCC_PERIPHCLK_I2C3:
1172 {
1173 /* Get the current I2C3 source */
1174 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
1175
1176 /* Check if HSI is ready and if I2C3 clock selection is HSI */
1177 if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1178 {
1179 frequency = HSI_VALUE;
1180 }
1181 /* Check if I2C3 clock selection is SYSCLK */
1182 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
1183 {
1184 frequency = HAL_RCC_GetSysClockFreq();
1185 }
1186 break;
1187 }
1188 #endif /* RCC_CFGR3_I2C3SW */
1189 #if defined(RCC_CFGR_I2SSRC)
1190 case RCC_PERIPHCLK_I2S:
1191 {
1192 /* Get the current I2S source */
1193 srcclk = __HAL_RCC_GET_I2S_SOURCE();
1194
1195 /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
1196 if (srcclk == RCC_I2SCLKSOURCE_EXT)
1197 {
1198 /* External clock used. Frequency cannot be returned.*/
1199 frequency = 0xDEADDEADU;
1200 }
1201 /* Check if I2S clock selection is SYSCLK */
1202 else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
1203 {
1204 frequency = HAL_RCC_GetSysClockFreq();
1205 }
1206 break;
1207 }
1208 #endif /* RCC_CFGR_I2SSRC */
1209 #if defined(RCC_CFGR_USBPRE)
1210 case RCC_PERIPHCLK_USB:
1211 {
1212 /* Check if PLL is ready */
1213 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1214 {
1215 /* Get the current USB source */
1216 srcclk = __HAL_RCC_GET_USB_SOURCE();
1217
1218 /* Check if USB clock selection is not divided */
1219 if (srcclk == RCC_USBCLKSOURCE_PLL)
1220 {
1221 frequency = RCC_GetPLLCLKFreq();
1222 }
1223 /* Check if USB clock selection is divided by 1.5 */
1224 else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
1225 {
1226 frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
1227 }
1228 }
1229 break;
1230 }
1231 #endif /* RCC_CFGR_USBPRE */
1232 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
1233 case RCC_PERIPHCLK_ADC1:
1234 {
1235 /* Get the current ADC1 source */
1236 srcclk = __HAL_RCC_GET_ADC1_SOURCE();
1237 #if defined(RCC_CFGR2_ADC1PRES)
1238 /* Check if ADC1 clock selection is AHB */
1239 if (srcclk == RCC_ADC1PLLCLK_OFF)
1240 {
1241 frequency = SystemCoreClock;
1242 }
1243 /* PLL clock has been selected */
1244 else
1245 {
1246 /* Check if PLL is ready */
1247 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1248 {
1249 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
1250 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
1251 }
1252 }
1253 #else /* RCC_CFGR_ADCPRE */
1254 /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
1255 frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
1256 #endif /* RCC_CFGR2_ADC1PRES */
1257 break;
1258 }
1259 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
1260 #if defined(RCC_CFGR2_ADCPRE12)
1261 case RCC_PERIPHCLK_ADC12:
1262 {
1263 /* Get the current ADC12 source */
1264 srcclk = __HAL_RCC_GET_ADC12_SOURCE();
1265 /* Check if ADC12 clock selection is AHB */
1266 if (srcclk == RCC_ADC12PLLCLK_OFF)
1267 {
1268 frequency = SystemCoreClock;
1269 }
1270 /* PLL clock has been selected */
1271 else
1272 {
1273 /* Check if PLL is ready */
1274 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1275 {
1276 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
1277 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
1278 }
1279 }
1280 break;
1281 }
1282 #endif /* RCC_CFGR2_ADCPRE12 */
1283 #if defined(RCC_CFGR2_ADCPRE34)
1284 case RCC_PERIPHCLK_ADC34:
1285 {
1286 /* Get the current ADC34 source */
1287 srcclk = __HAL_RCC_GET_ADC34_SOURCE();
1288 /* Check if ADC34 clock selection is AHB */
1289 if (srcclk == RCC_ADC34PLLCLK_OFF)
1290 {
1291 frequency = SystemCoreClock;
1292 }
1293 /* PLL clock has been selected */
1294 else
1295 {
1296 /* Check if PLL is ready */
1297 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1298 {
1299 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
1300 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
1301 }
1302 }
1303 break;
1304 }
1305 #endif /* RCC_CFGR2_ADCPRE34 */
1306 #if defined(RCC_CFGR3_TIM1SW)
1307 case RCC_PERIPHCLK_TIM1:
1308 {
1309 /* Get the current TIM1 source */
1310 srcclk = __HAL_RCC_GET_TIM1_SOURCE();
1311
1312 /* Check if PLL is ready and if TIM1 clock selection is PLL */
1313 if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1314 {
1315 frequency = RCC_GetPLLCLKFreq();
1316 }
1317 /* Check if TIM1 clock selection is SYSCLK */
1318 else if (srcclk == RCC_TIM1CLK_HCLK)
1319 {
1320 frequency = SystemCoreClock;
1321 }
1322 break;
1323 }
1324 #endif /* RCC_CFGR3_TIM1SW */
1325 #if defined(RCC_CFGR3_TIM2SW)
1326 case RCC_PERIPHCLK_TIM2:
1327 {
1328 /* Get the current TIM2 source */
1329 srcclk = __HAL_RCC_GET_TIM2_SOURCE();
1330
1331 /* Check if PLL is ready and if TIM2 clock selection is PLL */
1332 if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1333 {
1334 frequency = RCC_GetPLLCLKFreq();
1335 }
1336 /* Check if TIM2 clock selection is SYSCLK */
1337 else if (srcclk == RCC_TIM2CLK_HCLK)
1338 {
1339 frequency = SystemCoreClock;
1340 }
1341 break;
1342 }
1343 #endif /* RCC_CFGR3_TIM2SW */
1344 #if defined(RCC_CFGR3_TIM8SW)
1345 case RCC_PERIPHCLK_TIM8:
1346 {
1347 /* Get the current TIM8 source */
1348 srcclk = __HAL_RCC_GET_TIM8_SOURCE();
1349
1350 /* Check if PLL is ready and if TIM8 clock selection is PLL */
1351 if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1352 {
1353 frequency = RCC_GetPLLCLKFreq();
1354 }
1355 /* Check if TIM8 clock selection is SYSCLK */
1356 else if (srcclk == RCC_TIM8CLK_HCLK)
1357 {
1358 frequency = SystemCoreClock;
1359 }
1360 break;
1361 }
1362 #endif /* RCC_CFGR3_TIM8SW */
1363 #if defined(RCC_CFGR3_TIM15SW)
1364 case RCC_PERIPHCLK_TIM15:
1365 {
1366 /* Get the current TIM15 source */
1367 srcclk = __HAL_RCC_GET_TIM15_SOURCE();
1368
1369 /* Check if PLL is ready and if TIM15 clock selection is PLL */
1370 if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1371 {
1372 frequency = RCC_GetPLLCLKFreq();
1373 }
1374 /* Check if TIM15 clock selection is SYSCLK */
1375 else if (srcclk == RCC_TIM15CLK_HCLK)
1376 {
1377 frequency = SystemCoreClock;
1378 }
1379 break;
1380 }
1381 #endif /* RCC_CFGR3_TIM15SW */
1382 #if defined(RCC_CFGR3_TIM16SW)
1383 case RCC_PERIPHCLK_TIM16:
1384 {
1385 /* Get the current TIM16 source */
1386 srcclk = __HAL_RCC_GET_TIM16_SOURCE();
1387
1388 /* Check if PLL is ready and if TIM16 clock selection is PLL */
1389 if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1390 {
1391 frequency = RCC_GetPLLCLKFreq();
1392 }
1393 /* Check if TIM16 clock selection is SYSCLK */
1394 else if (srcclk == RCC_TIM16CLK_HCLK)
1395 {
1396 frequency = SystemCoreClock;
1397 }
1398 break;
1399 }
1400 #endif /* RCC_CFGR3_TIM16SW */
1401 #if defined(RCC_CFGR3_TIM17SW)
1402 case RCC_PERIPHCLK_TIM17:
1403 {
1404 /* Get the current TIM17 source */
1405 srcclk = __HAL_RCC_GET_TIM17_SOURCE();
1406
1407 /* Check if PLL is ready and if TIM17 clock selection is PLL */
1408 if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1409 {
1410 frequency = RCC_GetPLLCLKFreq();
1411 }
1412 /* Check if TIM17 clock selection is SYSCLK */
1413 else if (srcclk == RCC_TIM17CLK_HCLK)
1414 {
1415 frequency = SystemCoreClock;
1416 }
1417 break;
1418 }
1419 #endif /* RCC_CFGR3_TIM17SW */
1420 #if defined(RCC_CFGR3_TIM20SW)
1421 case RCC_PERIPHCLK_TIM20:
1422 {
1423 /* Get the current TIM20 source */
1424 srcclk = __HAL_RCC_GET_TIM20_SOURCE();
1425
1426 /* Check if PLL is ready and if TIM20 clock selection is PLL */
1427 if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1428 {
1429 frequency = RCC_GetPLLCLKFreq();
1430 }
1431 /* Check if TIM20 clock selection is SYSCLK */
1432 else if (srcclk == RCC_TIM20CLK_HCLK)
1433 {
1434 frequency = SystemCoreClock;
1435 }
1436 break;
1437 }
1438 #endif /* RCC_CFGR3_TIM20SW */
1439 #if defined(RCC_CFGR3_TIM34SW)
1440 case RCC_PERIPHCLK_TIM34:
1441 {
1442 /* Get the current TIM34 source */
1443 srcclk = __HAL_RCC_GET_TIM34_SOURCE();
1444
1445 /* Check if PLL is ready and if TIM34 clock selection is PLL */
1446 if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1447 {
1448 frequency = RCC_GetPLLCLKFreq();
1449 }
1450 /* Check if TIM34 clock selection is SYSCLK */
1451 else if (srcclk == RCC_TIM34CLK_HCLK)
1452 {
1453 frequency = SystemCoreClock;
1454 }
1455 break;
1456 }
1457 #endif /* RCC_CFGR3_TIM34SW */
1458 #if defined(RCC_CFGR3_HRTIM1SW)
1459 case RCC_PERIPHCLK_HRTIM1:
1460 {
1461 /* Get the current HRTIM1 source */
1462 srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
1463
1464 /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
1465 if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
1466 {
1467 frequency = RCC_GetPLLCLKFreq();
1468 }
1469 /* Check if HRTIM1 clock selection is SYSCLK */
1470 else if (srcclk == RCC_HRTIM1CLK_HCLK)
1471 {
1472 frequency = SystemCoreClock;
1473 }
1474 break;
1475 }
1476 #endif /* RCC_CFGR3_HRTIM1SW */
1477 #if defined(RCC_CFGR_SDPRE)
1478 case RCC_PERIPHCLK_SDADC:
1479 {
1480 /* Get the current SDADC source */
1481 srcclk = __HAL_RCC_GET_SDADC_SOURCE();
1482 /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
1483 frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
1484 break;
1485 }
1486 #endif /* RCC_CFGR_SDPRE */
1487 #if defined(RCC_CFGR3_CECSW)
1488 case RCC_PERIPHCLK_CEC:
1489 {
1490 /* Get the current CEC source */
1491 srcclk = __HAL_RCC_GET_CEC_SOURCE();
1492
1493 /* Check if HSI is ready and if CEC clock selection is HSI */
1494 if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
1495 {
1496 frequency = HSI_VALUE;
1497 }
1498 /* Check if LSE is ready and if CEC clock selection is LSE */
1499 else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
1500 {
1501 frequency = LSE_VALUE;
1502 }
1503 break;
1504 }
1505 #endif /* RCC_CFGR3_CECSW */
1506 default:
1507 {
1508 break;
1509 }
1510 }
1511 return(frequency);
1512 }
1513
1514 /**
1515 * @}
1516 */
1517
1518 /**
1519 * @}
1520 */
1521
1522
1523 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
1524 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
1525 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
1526 || defined(RCC_CFGR3_HRTIM1SW)
1527
1528 /** @addtogroup RCCEx_Private_Functions
1529 * @{
1530 */
RCC_GetPLLCLKFreq(void)1531 static uint32_t RCC_GetPLLCLKFreq(void)
1532 {
1533 uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
1534
1535 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
1536 pllmul = ( pllmul >> 18U) + 2U;
1537 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
1538 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
1539 if (pllsource != RCC_PLLSOURCE_HSI)
1540 {
1541 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
1542 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
1543 pllclk = (HSE_VALUE/prediv) * pllmul;
1544 }
1545 else
1546 {
1547 /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
1548 pllclk = (HSI_VALUE >> 1U) * pllmul;
1549 }
1550 #else
1551 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
1552 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
1553 {
1554 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
1555 pllclk = (HSE_VALUE/prediv) * pllmul;
1556 }
1557 else
1558 {
1559 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
1560 pllclk = (HSI_VALUE/prediv) * pllmul;
1561 }
1562 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
1563
1564 return pllclk;
1565 }
1566 /**
1567 * @}
1568 */
1569
1570 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
1571
1572 /**
1573 * @}
1574 */
1575
1576 #endif /* HAL_RCC_MODULE_ENABLED */
1577
1578 /**
1579 * @}
1580 */
1581
1582
