1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2016 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32f3xx_hal.h"
26
27 /** @addtogroup STM32F3xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40 /* Private macro -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private function prototypes -----------------------------------------------*/
43 /* Private functions ---------------------------------------------------------*/
44
45 /** @defgroup PWR_Exported_Functions PWR Exported Functions
46 * @{
47 */
48
49 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
50 * @brief Initialization and de-initialization functions
51 *
52 @verbatim
53 ===============================================================================
54 ##### Initialization and de-initialization functions #####
55 ===============================================================================
56 [..]
57 After reset, the backup domain (RTC registers, RTC backup data
58 registers and backup SRAM) is protected against possible unwanted
59 write accesses.
60 To enable access to the RTC Domain and RTC registers, proceed as follows:
61 (+) Enable the Power Controller (PWR) APB1 interface clock using the
62 __HAL_RCC_PWR_CLK_ENABLE() macro.
63 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
64
65 @endverbatim
66 * @{
67 */
68
69 /**
70 * @brief Deinitializes the PWR peripheral registers to their default reset values.
71 * @retval None
72 */
HAL_PWR_DeInit(void)73 void HAL_PWR_DeInit(void)
74 {
75 __HAL_RCC_PWR_FORCE_RESET();
76 __HAL_RCC_PWR_RELEASE_RESET();
77 }
78
79 /**
80 * @brief Enables access to the backup domain (RTC registers, RTC
81 * backup data registers and backup SRAM).
82 * @note If the HSE divided by 32 is used as the RTC clock, the
83 * Backup Domain Access should be kept enabled.
84 * @retval None
85 */
HAL_PWR_EnableBkUpAccess(void)86 void HAL_PWR_EnableBkUpAccess(void)
87 {
88 SET_BIT(PWR->CR, PWR_CR_DBP);
89 }
90
91 /**
92 * @brief Disables access to the backup domain (RTC registers, RTC
93 * backup data registers and backup SRAM).
94 * @note If the HSE divided by 32 is used as the RTC clock, the
95 * Backup Domain Access should be kept enabled.
96 * @retval None
97 */
HAL_PWR_DisableBkUpAccess(void)98 void HAL_PWR_DisableBkUpAccess(void)
99 {
100 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
101 }
102
103 /**
104 * @}
105 */
106
107 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
108 * @brief Low Power modes configuration functions
109 *
110 @verbatim
111
112 ===============================================================================
113 ##### Peripheral Control functions #####
114 ===============================================================================
115
116 *** WakeUp pin configuration ***
117 ================================
118 [..]
119 (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
120 forced in input pull down configuration and is active on rising edges.
121 (+) There are up to three WakeUp pins:
122 (++)WakeUp Pin 1 on PA.00.
123 (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
124 (++)WakeUp Pin 3 on PE.06.
125
126 *** Main and Backup Regulators configuration ***
127 ================================================
128 [..]
129 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
130 the backup SRAM is powered from VDD which replaces the VBAT power supply to
131 save battery life.
132
133 (+) The backup SRAM is not mass erased by a tamper event. It is read
134 protected to prevent confidential data, such as cryptographic private
135 key, from being accessed. The backup SRAM can be erased only through
136 the Flash interface when a protection level change from level 1 to
137 level 0 is requested.
138 -@- Refer to the description of Read protection (RDP) in the Flash
139 programming manual.
140
141 Refer to the datasheets for more details.
142
143 *** Low Power modes configuration ***
144 =====================================
145 [..]
146 The devices feature 3 low-power modes:
147 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
148 (+) Stop mode: all clocks are stopped, regulator running, regulator
149 in low power mode
150 (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
151
152 *** Sleep mode ***
153 ==================
154 [..]
155 (+) Entry:
156 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
157 functions with
158 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
159 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
160
161 (+) Exit:
162 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
163 controller (NVIC) can wake up the device from Sleep mode.
164
165 *** Stop mode ***
166 =================
167 [..]
168 In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
169 and the HSE RC oscillators are disabled. Internal SRAM and register contents
170 are preserved.
171 The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
172
173 (+) Entry:
174 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
175 function with:
176 (++) Main regulator ON or
177 (++) Low Power regulator ON.
178 (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
179 (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
180 (+) Exit:
181 (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
182 (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
183 when programmed in wakeup mode (the peripheral must be
184 programmed in wakeup mode and the corresponding interrupt vector
185 must be enabled in the NVIC).
186
187 *** Standby mode ***
188 ====================
189 [..]
190 The Standby mode allows to achieve the lowest power consumption. It is based
191 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
192 The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
193 the HSE oscillator are also switched off. SRAM and register contents are lost
194 except for the RTC registers, RTC backup registers, backup SRAM and Standby
195 circuitry.
196 The voltage regulator is OFF.
197
198 (+) Entry:
199 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
200 (+) Exit:
201 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
202 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
203
204 *** Auto-wakeup (AWU) from low-power mode ***
205 =============================================
206 [..]
207 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
208 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
209 without depending on an external interrupt (Auto-wakeup mode).
210
211 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
212
213 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
214 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
215
216 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
217 is necessary to configure the RTC to detect the tamper or time stamp event using the
218 HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
219
220 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
221 configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
222
223 (+) Comparator auto-wakeup (AWU) from the Stop mode
224
225 (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
226 (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
227 to be sensitive to to the selected edges (falling, rising or falling
228 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
229 (+++) Configure the comparator to generate the event.
230 @endverbatim
231 * @{
232 */
233
234 /**
235 * @brief Enables the WakeUp PINx functionality.
236 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
237 * This parameter can be value of :
238 * @ref PWR_WakeUp_Pins
239 * @retval None
240 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)241 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
242 {
243 /* Check the parameters */
244 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
245 /* Enable the EWUPx pin */
246 SET_BIT(PWR->CSR, WakeUpPinx);
247 }
248
249 /**
250 * @brief Disables the WakeUp PINx functionality.
251 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
252 * This parameter can be values of :
253 * @ref PWR_WakeUp_Pins
254 * @retval None
255 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)256 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
257 {
258 /* Check the parameters */
259 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
260 /* Disable the EWUPx pin */
261 CLEAR_BIT(PWR->CSR, WakeUpPinx);
262 }
263
264 /**
265 * @brief Enters Sleep mode.
266 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
267 * @param Regulator Specifies the regulator state in SLEEP mode.
268 * This parameter can be one of the following values:
269 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
270 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
271 * @note This parameter has no effect in F3 family and is just maintained to
272 * offer full portability of other STM32 families software.
273 * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
274 * When WFI entry is used, tick interrupt have to be disabled if not desired as
275 * the interrupt wake up source.
276 * This parameter can be one of the following values:
277 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
278 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
279 * @retval None
280 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)281 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
282 {
283 /* Check the parameters */
284 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
285
286 /* Clear SLEEPDEEP bit of Cortex System Control Register */
287 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
288
289 /* Select SLEEP mode entry -------------------------------------------------*/
290 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
291 {
292 /* Request Wait For Interrupt */
293 __WFI();
294 }
295 else
296 {
297 /* Request Wait For Event */
298 __SEV();
299 __WFE();
300 __WFE();
301 }
302 }
303
304 /**
305 * @brief Enters STOP mode.
306 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
307 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
308 * the HSI RC oscillator is selected as system clock.
309 * @note When the voltage regulator operates in low power mode, an additional
310 * startup delay is incurred when waking up from Stop mode.
311 * By keeping the internal regulator ON during Stop mode, the consumption
312 * is higher although the startup time is reduced.
313 * @param Regulator Specifies the regulator state in STOP mode.
314 * This parameter can be one of the following values:
315 * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
316 * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
317 * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
318 * This parameter can be one of the following values:
319 * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
320 * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
321 * @retval None
322 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)323 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
324 {
325 uint32_t tmpreg = 0U;
326
327 /* Check the parameters */
328 assert_param(IS_PWR_REGULATOR(Regulator));
329 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
330
331 /* Select the regulator state in STOP mode ---------------------------------*/
332 tmpreg = PWR->CR;
333
334 /* Clear PDDS and LPDS bits */
335 tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
336
337 /* Set LPDS bit according to Regulator value */
338 tmpreg |= Regulator;
339
340 /* Store the new value */
341 PWR->CR = tmpreg;
342
343 /* Set SLEEPDEEP bit of Cortex System Control Register */
344 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
345
346 /* Select STOP mode entry --------------------------------------------------*/
347 if(STOPEntry == PWR_STOPENTRY_WFI)
348 {
349 /* Request Wait For Interrupt */
350 __WFI();
351 }
352 else
353 {
354 /* Request Wait For Event */
355 __SEV();
356 __WFE();
357 __WFE();
358 }
359
360 /* Reset SLEEPDEEP bit of Cortex System Control Register */
361 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
362 }
363
364 /**
365 * @brief Enters STANDBY mode.
366 * @note In Standby mode, all I/O pins are high impedance except for:
367 * - Reset pad (still available),
368 * - RTC alternate function pins if configured for tamper, time-stamp, RTC
369 * Alarm out, or RTC clock calibration out,
370 * - WKUP pins if enabled.
371 * @retval None
372 */
HAL_PWR_EnterSTANDBYMode(void)373 void HAL_PWR_EnterSTANDBYMode(void)
374 {
375 /* Select STANDBY mode */
376 PWR->CR |= PWR_CR_PDDS;
377
378 /* Set SLEEPDEEP bit of Cortex System Control Register */
379 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
380
381 /* This option is used to ensure that store operations are completed */
382 #if defined ( __CC_ARM)
383 __force_stores();
384 #endif
385 /* Request Wait For Interrupt */
386 __WFI();
387 }
388
389 /**
390 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
391 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
392 * re-enters SLEEP mode when an interruption handling is over.
393 * Setting this bit is useful when the processor is expected to run only on
394 * interruptions handling.
395 * @retval None
396 */
HAL_PWR_EnableSleepOnExit(void)397 void HAL_PWR_EnableSleepOnExit(void)
398 {
399 /* Set SLEEPONEXIT bit of Cortex System Control Register */
400 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
401 }
402
403
404 /**
405 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
406 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
407 * re-enters SLEEP mode when an interruption handling is over.
408 * @retval None
409 */
HAL_PWR_DisableSleepOnExit(void)410 void HAL_PWR_DisableSleepOnExit(void)
411 {
412 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
413 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
414 }
415
416
417
418 /**
419 * @brief Enables CORTEX M4 SEVONPEND bit.
420 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
421 * WFE to wake up when an interrupt moves from inactive to pended.
422 * @retval None
423 */
HAL_PWR_EnableSEVOnPend(void)424 void HAL_PWR_EnableSEVOnPend(void)
425 {
426 /* Set SEVONPEND bit of Cortex System Control Register */
427 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
428 }
429
430
431 /**
432 * @brief Disables CORTEX M4 SEVONPEND bit.
433 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
434 * WFE to wake up when an interrupt moves from inactive to pended.
435 * @retval None
436 */
HAL_PWR_DisableSEVOnPend(void)437 void HAL_PWR_DisableSEVOnPend(void)
438 {
439 /* Clear SEVONPEND bit of Cortex System Control Register */
440 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
441 }
442 /**
443 * @}
444 */
445
446 /**
447 * @}
448 */
449
450 #endif /* HAL_PWR_MODULE_ENABLED */
451 /**
452 * @}
453 */
454
455 /**
456 * @}
457 */
458
