1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 *
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2016 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file
61 * in the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 *
64 ******************************************************************************
65 @verbatim
66 ==============================================================================
67 ##### Simple mode v.s. waveform mode #####
68 ==============================================================================
69 [..] The HRTIM HAL API is split into 2 categories:
70 (#)Simple functions: these functions allow for using a HRTIM timer as a
71 general purpose timer with high resolution capabilities.
72 HRTIM simple modes are managed through the set of functions named
73 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
74 to the one defined for the TIM peripheral. When a HRTIM timer operates in
75 simple mode, only a very limited set of HRTIM features are used.
76 Following simple modes are proposed:
77 (++)Output compare mode,
78 (++)PWM output mode,
79 (++)Input capture mode,
80 (++)One pulse mode.
81 (#)Waveform functions: These functions allow taking advantage of the HRTIM
82 flexibility to produce numerous types of control signal. When a HRTIM timer
83 operates in waveform mode, all the HRTIM features are accessible without
84 any restriction. HRTIM waveform modes are managed through the set of
85 functions named HAL_HRTIM_Waveform<Function>
86
87 ==============================================================================
88 ##### How to use this driver #####
89 ==============================================================================
90 [..]
91 (#)Initialize the HRTIM low level resources by implementing the
92 HAL_HRTIM_MspInit() function:
93 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
94 (##)Connect HRTIM pins to MCU I/Os
95 (+++) Enable the clock for the HRTIM GPIOs using the following
96 function: __HAL_RCC_GPIOx_CLK_ENABLE()
97 (+++) Configure these GPIO pins in Alternate Function mode using
98 HAL_GPIO_Init()
99 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
100 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
101 (+++)Initialize the DMA handle
102 (+++)Associate the initialized DMA handle to the appropriate DMA
103 handle of the HRTIM handle using __HAL_LINKDMA()
104 (+++)Initialize the DMA channel using HAL_DMA_Init()
105 (+++)Configure the priority and enable the NVIC for the transfer
106 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
107 and HAL_NVIC_EnableIRQ()
108 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
109 (+++)Configure the priority and enable the NVIC for the concerned
110 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
111
112 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
113 structure (field of the HRTIM handle) specifies which global interrupt of
114 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
115 It also contains the HRTIM external synchronization configuration. HRTIM
116 can act as a master (generating a synchronization signal) or as a slave
117 (waiting for a trigger to be synchronized).
118
119 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
120 calibration is executed periodically and compensate for potential voltage
121 and temperature drifts. DLL calibration period is specified by the
122 CalibrationRate argument.
123
124 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
125 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
126 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
127 is still going on when timeout given as argument expires. DLL calibration
128 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
129 In that case an interrupt is generated when the DLL calibration is completed.
130 Note that as DLL calibration is executed on a periodic basis an interrupt
131 will be generated at the end of every DLL calibration operation
132 (worst case: one interrupt every 14 micro seconds !).
133
134 (#) Configure HRTIM resources shared by all HRTIM timers
135 (##)Burst Mode Controller:
136 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
137 controller: operating mode (continuous or one-shot mode), clock
138 (source, prescaler) , trigger(s), period, idle duration.
139 (##)External Events Conditioning:
140 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
141 external event channel: source, polarity, edge-sensitivity.
142 External event can be used as triggers (timer reset, input
143 capture, burst mode, ADC triggers, delayed protection)
144 They can also be used to set or reset timer outputs. Up to
145 10 event channels are available.
146 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
147 event sampling clock (used for digital filtering).
148 (##)Fault Conditioning:
149 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
150 fault channel: source, polarity, edge-sensitivity. Fault
151 channels are used to disable the outputs in case of an
152 abnormal operation. Up to 5 fault channels are available.
153 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
154 sampling clock (used for digital filtering).
155 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
156 circuitry. By default all fault inputs are disabled.
157 (##)ADC trigger:
158 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
159 the update of the ADC trigger register and the ADC trigger.
160 4 independent triggers are available to start both the regular
161 and the injected sequencers of the 2 ADCs
162
163 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
164 function must be called whatever the HRTIM timer operating mode is
165 (simple v.s. waveform). It configures mainly:
166 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
167 (##)The HRTIM timer clock prescaler
168 (##)The HRTIM timer period
169 (##)The HRTIM timer repetition counter
170
171 *** If the HRTIM timer operates in simple mode ***
172 ===================================================
173 [..]
174 (#) Start or Stop simple timers
175 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
176 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
177 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
178 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
179 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
180 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
181 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
182 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
183 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
184 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
185 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
186 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
187 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
188 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
189 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
190 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
191 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
192 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
193
194 *** If the HRTIM timer operates in waveform mode ***
195 ====================================================
196 [..]
197 (#) Completes waveform timer configuration
198 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
199 operating in wave form mode mainly consists in:
200 (+++)Enabling the HRTIM timer interrupts and DMA requests.
201 (+++)Enabling the half mode for the HRTIM timer.
202 (+++)Defining how the HRTIM timer reacts to external synchronization input.
203 (+++)Enabling the push-pull mode for the HRTIM timer.
204 (+++)Enabling the fault channels for the HRTIM timer.
205 (+++)Enabling the dead-time insertion for the HRTIM timer.
206 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
207 on which the delayed protection are applied).
208 (+++)Specifying the HRTIM timer update and reset triggers.
209 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
210 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
211 event blanking and windowing circuitry of a HRTIM timer:
212 (+++)Blanking: to mask external events during a defined time period a defined time period
213 (+++)Windowing, to enable external events only during a defined time period
214 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
215 unit for a HRTIM timer. Allows to generate a couple of
216 complementary signals from a single reference waveform,
217 with programmable delays between active state.
218 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
219 the high-frequency carrier signal added on top of the timing
220 unit output. Chopper mode can be enabled or disabled for each
221 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
222 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
223 controller. Allows having multiple HRTIM registers updated
224 with a single DMA request. The burst DMA operation is started
225 by calling HAL_HRTIM_BurstDMATransfer().
226 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
227 of a HRTIM timer. This operation consists in setting the
228 compare value and possibly specifying the auto delayed mode
229 for compare units 2 and 4 (allows to have compare events
230 generated relatively to capture events). Note that when auto
231 delayed mode is needed, the capture unit associated to the
232 compare unit must be configured separately.
233 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
234 of a HRTIM timer. This operation consists in specifying the
235 source(s) triggering the capture (timer register update event,
236 external event, timer output set/reset event, other HRTIM
237 timer related events).
238 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
239 output mainly consists in:
240 (+++)Setting the output polarity (active high or active low),
241 (+++)Defining the set/reset crossbar for the output,
242 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
243
244 (#) Set waveform timer output(s) level
245 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
246 active or inactive level. For example, when deadtime insertion
247 is enabled it is necessary to force the output level by software
248 to have the outputs in a complementary state as soon as the RUN mode is entered.
249
250 (#) Enable or Disable waveform timer output(s)
251 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
252
253 (#) Start or Stop waveform HRTIM timer(s).
254 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
255 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
256 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
257 (#) Burst mode controller enabling:
258 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
259 burst mode controller.
260
261 (#) Some HRTIM operations can be triggered by software:
262 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
263 trigs the burst operation.
264 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
265 capture of the HRTIM timer counter.
266 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
267 update of the pre-loadable registers of the HRTIM timer
268 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
269 HRTIM timer counter.
270
271 (#) Some functions can be used any time to retrieve HRTIM timer related
272 information
273 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
274 capture register of the designated capture unit.
275 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
276 (ACTIVE/INACTIVE) of the designated timer output.
277 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
278 (IDLE/RUN/FAULT) of the designated timer output.
279 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
280 (ACTIVE/INACTIVE) of the designated output when the delayed
281 protection was triggered.
282 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
283 (ACTIVE/INACTIVE) of the burst mode controller.
284 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
285 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
286 the push-pull status indicates on which output the signal is currently
287 active (e.g signal applied on output 1 and output 2 forced
288 inactive or vice versa).
289 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
290 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
291 the idle push-pull status indicates during which period the
292 delayed protection request occurred (e.g. protection occurred
293 when the output 1 was active and output 2 forced inactive or
294 vice versa).
295
296 (#) Some functions can be used any time to retrieve actual HRTIM status
297 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
298
299 *** Callback registration ***
300 =============================
301 [..]
302 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
303 allows the user to configure dynamically the driver callbacks.
304 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
305 to register an interrupt callback.
306
307 [..]
308 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
309 (+) Fault1Callback : Fault 1 interrupt callback function
310 (+) Fault2Callback : Fault 2 interrupt callback function
311 (+) Fault3Callback : Fault 3 interrupt callback function
312 (+) Fault4Callback : Fault 4 interrupt callback function
313 (+) Fault5Callback : Fault 5 interrupt callback function
314 (+) SystemFaultCallback : System fault interrupt callback function
315 (+) DLLCalibrationReadyCallback : DLL Ready interrupt callback function
316 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
317 (+) SynchronizationEventCallback : Sync Input interrupt callback function
318 (+) ErrorCallback : DMA error callback function
319 (+) MspInitCallback : HRTIM MspInit callback function
320 (+) MspDeInitCallback : HRTIM MspInit callback function
321
322 [..]
323 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
324 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
325 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
326 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
327 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
328 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
329 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
330 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
331 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
332 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
333 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
334 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
335 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
336 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
337 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
338 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
339
340 [..]
341 Both functions take as parameters the HAL peripheral handle, the Callback ID
342 and a pointer to the user callback function.
343
344 [..]
345 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
346 to reset a callback to the default weak function. Both functions take as parameters
347 the HAL peripheral handle and the Callback ID.
348
349 [..]
350 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
351 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
352 Exception done for MspInit and MspDeInit functions that are reset to the legacy
353 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
354 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
355 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
356 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
357
358 [..]
359 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
360 Exception done MspInit/MspDeInit functions that can be registered/unregistered
361 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
362 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
363 Then, the user first registers the MspInit/MspDeInit user callbacks
364 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
365 or HAL_HRTIM_Init() function.
366
367 [..]
368 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
369 not defined, the callback registration feature is not available and all
370 callbacks are set to the corresponding weak functions.
371
372 @endverbatim
373 ******************************************************************************
374 */
375
376 /* Includes ------------------------------------------------------------------*/
377 #include "stm32f3xx_hal.h"
378
379 /** @addtogroup STM32F3xx_HAL_Driver
380 * @{
381 */
382
383 #ifdef HAL_HRTIM_MODULE_ENABLED
384
385 #if defined(HRTIM1)
386
387 /** @defgroup HRTIM HRTIM
388 * @brief HRTIM HAL module driver
389 * @{
390 */
391
392 /* Private typedef -----------------------------------------------------------*/
393 /* Private define ------------------------------------------------------------*/
394 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
395 * @{
396 */
397 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
398 HRTIM_FLTR_FLT2EN |\
399 HRTIM_FLTR_FLT3EN |\
400 HRTIM_FLTR_FLT4EN | \
401 HRTIM_FLTR_FLT5EN)
402
403 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
404 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
405 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
406 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
407 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
408 HRTIM_TIMUPDATETRIGGER_TIMER_E)
409
410 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
411 (HRTIM_FAULTLOCK_READONLY << 8U) | \
412 (HRTIM_FAULTLOCK_READONLY << 16U) | \
413 (HRTIM_FAULTLOCK_READONLY << 24U))
414
415 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
416 (HRTIM_FAULTLOCK_READONLY << 8U))
417 /**
418 * @}
419 */
420
421 /* Private macro -------------------------------------------------------------*/
422 /* Private variables ---------------------------------------------------------*/
423 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
424 * @{
425 */
426 static uint32_t TimerIdxToTimerId[] =
427 {
428 HRTIM_TIMERID_TIMER_A,
429 HRTIM_TIMERID_TIMER_B,
430 HRTIM_TIMERID_TIMER_C,
431 HRTIM_TIMERID_TIMER_D,
432 HRTIM_TIMERID_TIMER_E,
433 HRTIM_TIMERID_MASTER,
434 };
435 /**
436 * @}
437 */
438
439 /* Private function prototypes -----------------------------------------------*/
440 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
441 * @{
442 */
443 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
444 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
445
446 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
447 uint32_t TimerIdx,
448 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
449
450 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
451 const HRTIM_TimerCfgTypeDef * pTimerCfg);
452
453 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
454 uint32_t TimerIdx,
455 const HRTIM_TimerCfgTypeDef * pTimerCfg);
456
457
458 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
459 uint32_t TimerIdx,
460 uint32_t CaptureUnit,
461 uint32_t Event);
462
463 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
464 uint32_t TimerIdx,
465 uint32_t Output,
466 const HRTIM_OutputCfgTypeDef * pOutputCfg);
467
468 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
469 uint32_t Event,
470 const HRTIM_EventCfgTypeDef * pEventCfg);
471
472 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
473 uint32_t TimerIdx,
474 uint32_t Event);
475
476 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
477 uint32_t TimerIdx,
478 uint32_t OCChannel);
479
480 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
481 uint32_t TimerIdx,
482 uint32_t OCChannel);
483
484 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
485 uint32_t TimerIdx);
486
487 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
488 const DMA_HandleTypeDef * hdma);
489
490 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
491 uint32_t TimerIdx);
492
493 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
494
495 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
496
497 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
498 uint32_t TimerIdx);
499
500 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
501
502 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
503
504 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
505
506 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
507 /**
508 * @}
509 */
510
511 /* Exported functions ---------------------------------------------------------*/
512 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
513 * @{
514 */
515
516 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
517 * @brief Initialization and Configuration functions
518 @verbatim
519 ===============================================================================
520 ##### Initialization and Time Base Configuration functions #####
521 ===============================================================================
522 [..] This section provides functions allowing to:
523 (+) Initialize a HRTIM instance
524 (+) De-initialize a HRTIM instance
525 (+) Initialize the HRTIM MSP
526 (+) De-initialize the HRTIM MSP
527 (+) Start the high-resolution unit (start DLL calibration)
528 (+) Check that the high resolution unit is ready (DLL calibration done)
529 (+) Configure the time base unit of a HRTIM timer
530
531 @endverbatim
532 * @{
533 */
534
535 /**
536 * @brief Initialize a HRTIM instance
537 * @param hhrtim pointer to HAL HRTIM handle
538 * @retval HAL status
539 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)540 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
541 {
542 uint8_t timer_idx;
543 uint32_t hrtim_mcr;
544
545 /* Check the HRTIM handle allocation */
546 if(hhrtim == NULL)
547 {
548 return HAL_ERROR;
549 }
550
551 /* Check the parameters */
552 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
553 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
554
555 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
556 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
557 {
558 /* Initialize callback function pointers to their default values */
559 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
560 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
561 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
562 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
563 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
564 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
565 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
566 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
567 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
568 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
569 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
570 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
571 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
572 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
573 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
574 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
575 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
576 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
577 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
578 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
579 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
580 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
581 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
582 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
583 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
584
585 if (hhrtim->MspInitCallback == NULL)
586 {
587 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
588 }
589 }
590 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
591
592 /* Set the HRTIM state */
593 hhrtim->State = HAL_HRTIM_STATE_BUSY;
594
595 /* Initialize the DMA handles */
596 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
597 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
598 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
599 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
600 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
601 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
602
603 /* HRTIM output synchronization configuration (if required) */
604 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
605 {
606 /* Check parameters */
607 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
608 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
609
610 /* The synchronization output initialization procedure must be done prior
611 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
612 */
613 if (hhrtim->Instance == HRTIM1)
614 {
615 /* Enable the HRTIM peripheral clock */
616 __HAL_RCC_HRTIM1_CLK_ENABLE();
617 }
618
619 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
620
621 /* Set the event to be sent on the synchronization output */
622 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
623 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
624
625 /* Set the polarity of the synchronization output */
626 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
627 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
628
629 /* Update the HRTIM registers */
630 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
631 }
632
633 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
634 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
635 hhrtim->MspInitCallback(hhrtim);
636 #else
637 HAL_HRTIM_MspInit(hhrtim);
638 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
639
640 /* HRTIM input synchronization configuration (if required) */
641 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
642 {
643 /* Check parameters */
644 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
645
646 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
647
648 /* Set the synchronization input source */
649 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
650 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
651
652 /* Update the HRTIM registers */
653 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
654 }
655
656 /* Initialize the HRTIM state*/
657 hhrtim->State = HAL_HRTIM_STATE_READY;
658
659 /* Initialize the lock status of the HRTIM HAL API */
660 __HAL_UNLOCK(hhrtim);
661
662 /* Initialize timer related parameters */
663 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
664 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
665 timer_idx++)
666 {
667 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
668 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
669 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
670 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
671 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
672 hhrtim->TimerParam[timer_idx].DMASize = 0U;
673 }
674
675 return HAL_OK;
676 }
677
678 /**
679 * @brief De-initialize a HRTIM instance
680 * @param hhrtim pointer to HAL HRTIM handle
681 * @retval HAL status
682 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)683 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
684 {
685 /* Check the HRTIM handle allocation */
686 if(hhrtim == NULL)
687 {
688 return HAL_ERROR;
689 }
690
691 /* Check the parameters */
692 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
693
694 /* Set the HRTIM state */
695 hhrtim->State = HAL_HRTIM_STATE_BUSY;
696
697 /* DeInit the low level hardware */
698 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
699 if (hhrtim->MspDeInitCallback == NULL)
700 {
701 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
702 }
703
704 hhrtim->MspDeInitCallback(hhrtim);
705 #else
706 HAL_HRTIM_MspDeInit(hhrtim);
707 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
708
709 hhrtim->State = HAL_HRTIM_STATE_READY;
710
711 return HAL_OK;
712 }
713
714 /**
715 * @brief MSP initialization for a HRTIM instance
716 * @param hhrtim pointer to HAL HRTIM handle
717 * @retval None
718 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)719 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
720 {
721 /* Prevent unused argument(s) compilation warning */
722 UNUSED(hhrtim);
723
724 /* NOTE: This function should not be modified, when the callback is needed,
725 the HAL_HRTIM_MspInit could be implemented in the user file
726 */
727 }
728
729 /**
730 * @brief MSP de-initialization of a HRTIM instance
731 * @param hhrtim pointer to HAL HRTIM handle
732 * @retval None
733 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)734 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
735 {
736 /* Prevent unused argument(s) compilation warning */
737 UNUSED(hhrtim);
738
739 /* NOTE: This function should not be modified, when the callback is needed,
740 the HAL_HRTIM_MspDeInit could be implemented in the user file
741 */
742 }
743
744 /**
745 * @brief Start the DLL calibration
746 * @param hhrtim pointer to HAL HRTIM handle
747 * @param CalibrationRate DLL calibration period
748 * This parameter can be one of the following values:
749 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
750 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.300 ms
751 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=0.910 ms
752 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=0.114 ms
753 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=0.014 ms
754 * @retval HAL status
755 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
756 * within the HAL_HRTIM_PollForDLLCalibration function, just before
757 * exiting the function.
758 */
HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)759 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
760 uint32_t CalibrationRate)
761 {
762 /* Check the parameters */
763 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
764
765 /* Process Locked */
766 __HAL_LOCK(hhrtim);
767
768 hhrtim->State = HAL_HRTIM_STATE_BUSY;
769
770 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
771 {
772 /* One shot DLL calibration */
773 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
774 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
775 }
776 else
777 {
778 /* Periodic DLL calibration */
779 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
780 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
781 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
782 }
783
784 /* Set HRTIM state */
785 hhrtim->State = HAL_HRTIM_STATE_READY;
786
787 return HAL_OK;
788 }
789
790 /**
791 * @brief Start the DLL calibration.
792 * DLL ready interrupt is enabled
793 * @param hhrtim pointer to HAL HRTIM handle
794 * @param CalibrationRate DLL calibration period
795 * This parameter can be one of the following values:
796 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
797 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.300 ms
798 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=0.910 ms
799 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=0.114 ms
800 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=0.014 ms
801 * @retval HAL status
802 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
803 * within the IRQ processing function when processing the DLL ready
804 * interrupt.
805 * @note If this function is called for periodic calibration, the DLLRDY
806 * interrupt is generated every time the calibration completes which
807 * will significantly increases the overall interrupt rate.
808 */
HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)809 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
810 uint32_t CalibrationRate)
811 {
812 /* Check the parameters */
813 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
814
815 /* Process Locked */
816 __HAL_LOCK(hhrtim);
817
818 hhrtim->State = HAL_HRTIM_STATE_BUSY;
819
820 /* Enable DLL Ready interrupt flag */
821 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
822
823 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
824 {
825 /* One shot DLL calibration */
826 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
827 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
828 }
829 else
830 {
831 /* Periodic DLL calibration */
832 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
833 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
834 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
835 }
836
837 /* Set HRTIM state */
838 hhrtim->State = HAL_HRTIM_STATE_READY;
839
840 return HAL_OK;
841 }
842
843 /**
844 * @brief Poll the DLL calibration ready flag and returns when the flag is
845 * set (DLL calibration completed) or upon timeout expiration.
846 * @param hhrtim pointer to HAL HRTIM handle
847 * @param Timeout Timeout duration in millisecond
848 * @retval HAL status
849 */
HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,uint32_t Timeout)850 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
851 uint32_t Timeout)
852 {
853 uint32_t tickstart;
854
855 tickstart = HAL_GetTick();
856
857 /* Check End of conversion flag */
858 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
859 {
860 if (Timeout != HAL_MAX_DELAY)
861 {
862 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
863 {
864 hhrtim->State = HAL_HRTIM_STATE_ERROR;
865 return HAL_TIMEOUT;
866 }
867 }
868 }
869
870 /* Set HRTIM State */
871 hhrtim->State = HAL_HRTIM_STATE_READY;
872
873 /* Process unlocked */
874 __HAL_UNLOCK(hhrtim);
875
876 return HAL_OK;
877 }
878
879 /**
880 * @brief Configure the time base unit of a timer
881 * @param hhrtim pointer to HAL HRTIM handle
882 * @param TimerIdx Timer index
883 * This parameter can be one of the following values:
884 * @arg HRTIM_TIMERINDEX_MASTER for master timer
885 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
886 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
887 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
888 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
889 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
890 * @param pTimeBaseCfg pointer to the time base configuration structure
891 * @note This function must be called prior starting the timer
892 * @note The time-base unit initialization parameters specify:
893 * The timer counter operating mode (continuous, one shot),
894 * The timer clock prescaler,
895 * The timer period,
896 * The timer repetition counter.
897 * @retval HAL status
898 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)899 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
900 uint32_t TimerIdx,
901 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
902 {
903 /* Check the parameters */
904 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
905 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
906 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
907
908 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
909 {
910 return HAL_BUSY;
911 }
912
913 /* Set the HRTIM state */
914 hhrtim->State = HAL_HRTIM_STATE_BUSY;
915
916 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
917 {
918 /* Configure master timer time base unit */
919 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
920 }
921 else
922 {
923 /* Configure timing unit time base unit */
924 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
925 }
926
927 /* Set HRTIM state */
928 hhrtim->State = HAL_HRTIM_STATE_READY;
929
930 return HAL_OK;
931 }
932
933 /**
934 * @}
935 */
936
937 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
938 * @brief Simple time base mode functions.
939 @verbatim
940 ===============================================================================
941 ##### Simple time base mode functions #####
942 ===============================================================================
943 [..] This section provides functions allowing to:
944 (+) Start simple time base
945 (+) Stop simple time base
946 (+) Start simple time base and enable interrupt
947 (+) Stop simple time base and disable interrupt
948 (+) Start simple time base and enable DMA transfer
949 (+) Stop simple time base and disable DMA transfer
950 -@- When a HRTIM timer operates in simple time base mode, the timer
951 counter counts from 0 to the period value.
952
953 @endverbatim
954 * @{
955 */
956
957 /**
958 * @brief Start the counter of a timer operating in simple time base mode.
959 * @param hhrtim pointer to HAL HRTIM handle
960 * @param TimerIdx Timer index.
961 * This parameter can be one of the following values:
962 * @arg HRTIM_TIMERINDEX_MASTER for master timer
963 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
964 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
965 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
966 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
967 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
968 * @retval HAL status
969 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)970 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
971 uint32_t TimerIdx)
972 {
973 /* Check the parameters */
974 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
975
976 /* Process Locked */
977 __HAL_LOCK(hhrtim);
978
979 hhrtim->State = HAL_HRTIM_STATE_BUSY;
980
981 /* Enable the timer counter */
982 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
983
984 hhrtim->State = HAL_HRTIM_STATE_READY;
985
986 /* Process Unlocked */
987 __HAL_UNLOCK(hhrtim);
988
989 return HAL_OK;
990 }
991
992 /**
993 * @brief Stop the counter of a timer operating in simple time base mode.
994 * @param hhrtim pointer to HAL HRTIM handle
995 * @param TimerIdx Timer index.
996 * This parameter can be one of the following values:
997 * @arg HRTIM_TIMERINDEX_MASTER for master timer
998 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
999 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1000 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1001 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1002 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1003 * @retval HAL status
1004 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1005 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
1006 uint32_t TimerIdx)
1007 {
1008 /* Check the parameters */
1009 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1010
1011 /* Process Locked */
1012 __HAL_LOCK(hhrtim);
1013
1014 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1015
1016 /* Disable the timer counter */
1017 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1018
1019 hhrtim->State = HAL_HRTIM_STATE_READY;
1020
1021 /* Process Unlocked */
1022 __HAL_UNLOCK(hhrtim);
1023
1024 return HAL_OK;
1025 }
1026
1027 /**
1028 * @brief Start the counter of a timer operating in simple time base mode
1029 * (Timer repetition interrupt is enabled).
1030 * @param hhrtim pointer to HAL HRTIM handle
1031 * @param TimerIdx Timer index.
1032 * This parameter can be one of the following values:
1033 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1034 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1035 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1036 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1037 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1038 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1039 * @retval HAL status
1040 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1041 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
1042 uint32_t TimerIdx)
1043 {
1044 /* Check the parameters */
1045 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1046
1047 /* Process Locked */
1048 __HAL_LOCK(hhrtim);
1049
1050 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1051
1052 /* Enable the repetition interrupt */
1053 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1054 {
1055 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1056 }
1057 else
1058 {
1059 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1060 }
1061
1062 /* Enable the timer counter */
1063 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1064
1065 hhrtim->State = HAL_HRTIM_STATE_READY;
1066
1067 /* Process Unlocked */
1068 __HAL_UNLOCK(hhrtim);
1069
1070 return HAL_OK;
1071 }
1072
1073 /**
1074 * @brief Stop the counter of a timer operating in simple time base mode
1075 * (Timer repetition interrupt is disabled).
1076 * @param hhrtim pointer to HAL HRTIM handle
1077 * @param TimerIdx Timer index.
1078 * This parameter can be one of the following values:
1079 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1080 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1081 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1082 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1083 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1084 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1085 * @retval HAL status
1086 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1087 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
1088 uint32_t TimerIdx)
1089 {
1090 /* Check the parameters */
1091 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1092
1093 /* Process Locked */
1094 __HAL_LOCK(hhrtim);
1095
1096 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1097
1098 /* Disable the repetition interrupt */
1099 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1100 {
1101 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1102 }
1103 else
1104 {
1105 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1106 }
1107
1108 /* Disable the timer counter */
1109 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1110
1111 hhrtim->State = HAL_HRTIM_STATE_READY;
1112
1113 /* Process Unlocked */
1114 __HAL_UNLOCK(hhrtim);
1115
1116 return HAL_OK;
1117 }
1118
1119 /**
1120 * @brief Start the counter of a timer operating in simple time base mode
1121 * (Timer repetition DMA request is enabled).
1122 * @param hhrtim pointer to HAL HRTIM handle
1123 * @param TimerIdx Timer index.
1124 * This parameter can be one of the following values:
1125 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1126 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1127 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1128 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1129 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1130 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1131 * @param SrcAddr DMA transfer source address
1132 * @param DestAddr DMA transfer destination address
1133 * @param Length The length of data items (data size) to be transferred
1134 * from source to destination
1135 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1136 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1137 uint32_t TimerIdx,
1138 uint32_t SrcAddr,
1139 uint32_t DestAddr,
1140 uint32_t Length)
1141 {
1142 DMA_HandleTypeDef * hdma;
1143
1144 /* Check the parameters */
1145 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1146
1147 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1148 {
1149 return HAL_BUSY;
1150 }
1151 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1152 {
1153 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1154 {
1155 return HAL_ERROR;
1156 }
1157 else
1158 {
1159 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1160 }
1161 }
1162
1163 /* Process Locked */
1164 __HAL_LOCK(hhrtim);
1165
1166 /* Get the timer DMA handler */
1167 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1168
1169 if (hdma == NULL)
1170 {
1171 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1172
1173 /* Process Unlocked */
1174 __HAL_UNLOCK(hhrtim);
1175
1176 return HAL_ERROR;
1177 }
1178
1179 /* Set the DMA transfer completed callback */
1180 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1181 {
1182 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1183 }
1184 else
1185 {
1186 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1187 }
1188
1189 /* Set the DMA error callback */
1190 hdma->XferErrorCallback = HRTIM_DMAError ;
1191
1192 /* Enable the DMA channel */
1193 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1194 {
1195 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1196
1197 /* Process Unlocked */
1198 __HAL_UNLOCK(hhrtim);
1199
1200 return HAL_ERROR;
1201 }
1202
1203 /* Enable the timer repetition DMA request */
1204 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1205 {
1206 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1207 }
1208 else
1209 {
1210 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1211 }
1212
1213 /* Enable the timer counter */
1214 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1215
1216 hhrtim->State = HAL_HRTIM_STATE_READY;
1217
1218 /* Process Unlocked */
1219 __HAL_UNLOCK(hhrtim);
1220
1221 return HAL_OK;
1222 }
1223
1224 /**
1225 * @brief Stop the counter of a timer operating in simple time base mode
1226 * (Timer repetition DMA request is disabled).
1227 * @param hhrtim pointer to HAL HRTIM handle
1228 * @param TimerIdx Timer index.
1229 * This parameter can be one of the following values:
1230 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1231 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1232 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1233 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1234 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1235 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1236 * @retval HAL status
1237 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1238 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1239 uint32_t TimerIdx)
1240 {
1241 DMA_HandleTypeDef * hdma;
1242
1243 /* Check the parameters */
1244 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1245
1246 /* Process Locked */
1247 __HAL_LOCK(hhrtim);
1248
1249 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1250 {
1251 hhrtim->State = HAL_HRTIM_STATE_READY;
1252
1253 /* Disable the DMA */
1254 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1255 {
1256 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1257 }
1258 /* Disable the timer repetition DMA request */
1259 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1260 }
1261 else
1262 {
1263 /* Get the timer DMA handler */
1264 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1265
1266 if (hdma == NULL)
1267 {
1268 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1269 }
1270 else
1271 {
1272 hhrtim->State = HAL_HRTIM_STATE_READY;
1273
1274 /* Disable the DMA */
1275 if (HAL_DMA_Abort(hdma) != HAL_OK)
1276 {
1277 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1278 }
1279
1280 /* Disable the timer repetition DMA request */
1281 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1282 }
1283 }
1284
1285 /* Disable the timer counter */
1286 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1287
1288 /* Process Unlocked */
1289 __HAL_UNLOCK(hhrtim);
1290
1291 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1292 {
1293 return HAL_ERROR;
1294 }
1295 else
1296 {
1297 return HAL_OK;
1298 }
1299 }
1300
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1306 * @brief Simple output compare functions
1307 @verbatim
1308 ===============================================================================
1309 ##### Simple output compare functions #####
1310 ===============================================================================
1311 [..] This section provides functions allowing to:
1312 (+) Configure simple output channel
1313 (+) Start simple output compare
1314 (+) Stop simple output compare
1315 (+) Start simple output compare and enable interrupt
1316 (+) Stop simple output compare and disable interrupt
1317 (+) Start simple output compare and enable DMA transfer
1318 (+) Stop simple output compare and disable DMA transfer
1319 -@- When a HRTIM timer operates in simple output compare mode
1320 the output level is set to a programmable value when a match
1321 is found between the compare register and the counter.
1322 Compare unit 1 is automatically associated to output 1
1323 Compare unit 2 is automatically associated to output 2
1324 @endverbatim
1325 * @{
1326 */
1327
1328 /**
1329 * @brief Configure an output in simple output compare mode
1330 * @param hhrtim pointer to HAL HRTIM handle
1331 * @param TimerIdx Timer index
1332 * This parameter can be one of the following values:
1333 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1334 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1335 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1336 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1337 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1338 * @param OCChannel Timer output
1339 * This parameter can be one of the following values:
1340 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1341 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1342 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1343 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1344 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1345 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1346 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1347 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1348 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1349 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1350 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1351 * @note When the timer operates in simple output compare mode:
1352 * Output 1 is implicitly controlled by the compare unit 1
1353 * Output 2 is implicitly controlled by the compare unit 2
1354 * Output Set/Reset crossbar is set according to the selected output compare mode:
1355 * Toggle: SETxyR = RSTxyR = CMPy
1356 * Active: SETxyR = CMPy, RSTxyR = 0
1357 * Inactive: SETxy =0, RSTxy = CMPy
1358 * @retval HAL status
1359 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,const HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1360 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1361 uint32_t TimerIdx,
1362 uint32_t OCChannel,
1363 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1364 {
1365 uint32_t CompareUnit = (uint32_t)RESET;
1366 HRTIM_OutputCfgTypeDef OutputCfg;
1367
1368 /* Check parameters */
1369 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1370 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1371 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1372 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1373 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1374
1375 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1376 {
1377 return HAL_BUSY;
1378 }
1379
1380 /* Process Locked */
1381 __HAL_LOCK(hhrtim);
1382
1383 /* Set HRTIM state */
1384 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1385
1386 /* Configure timer compare unit */
1387 switch (OCChannel)
1388 {
1389 case HRTIM_OUTPUT_TA1:
1390 case HRTIM_OUTPUT_TB1:
1391 case HRTIM_OUTPUT_TC1:
1392 case HRTIM_OUTPUT_TD1:
1393 case HRTIM_OUTPUT_TE1:
1394 {
1395 CompareUnit = HRTIM_COMPAREUNIT_1;
1396 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1397 break;
1398 }
1399 case HRTIM_OUTPUT_TA2:
1400 case HRTIM_OUTPUT_TB2:
1401 case HRTIM_OUTPUT_TC2:
1402 case HRTIM_OUTPUT_TD2:
1403 case HRTIM_OUTPUT_TE2:
1404 {
1405 CompareUnit = HRTIM_COMPAREUNIT_2;
1406 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1407 break;
1408 }
1409 default:
1410 {
1411 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1412
1413 /* Process Unlocked */
1414 __HAL_UNLOCK(hhrtim);
1415
1416 break;
1417 }
1418 }
1419
1420 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1421 {
1422 return HAL_ERROR;
1423 }
1424
1425 /* Configure timer output */
1426 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1427 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1428 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1429 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1430 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1431 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1432
1433 switch (pSimpleOCChannelCfg->Mode)
1434 {
1435 case HRTIM_BASICOCMODE_TOGGLE:
1436 {
1437 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1438 {
1439 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1440 }
1441 else
1442 {
1443 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1444 }
1445 OutputCfg.ResetSource = OutputCfg.SetSource;
1446 break;
1447 }
1448
1449 case HRTIM_BASICOCMODE_ACTIVE:
1450 {
1451 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1452 {
1453 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1454 }
1455 else
1456 {
1457 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1458 }
1459 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1460 break;
1461 }
1462
1463 case HRTIM_BASICOCMODE_INACTIVE:
1464 {
1465 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1466 {
1467 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1468 }
1469 else
1470 {
1471 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1472 }
1473 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1474 break;
1475 }
1476
1477 default:
1478 {
1479 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1480 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1481
1482 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1483
1484 /* Process Unlocked */
1485 __HAL_UNLOCK(hhrtim);
1486
1487 break;
1488 }
1489 }
1490
1491 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1492 {
1493 return HAL_ERROR;
1494 }
1495
1496 HRTIM_OutputConfig(hhrtim,
1497 TimerIdx,
1498 OCChannel,
1499 &OutputCfg);
1500
1501 /* Set HRTIM state */
1502 hhrtim->State = HAL_HRTIM_STATE_READY;
1503
1504 /* Process Unlocked */
1505 __HAL_UNLOCK(hhrtim);
1506
1507 return HAL_OK;
1508 }
1509
1510 /**
1511 * @brief Start the output compare signal generation on the designed timer output
1512 * @param hhrtim pointer to HAL HRTIM handle
1513 * @param TimerIdx Timer index
1514 * This parameter can be one of the following values:
1515 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1516 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1517 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1518 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1519 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1520 * @param OCChannel Timer output
1521 * This parameter can be one of the following values:
1522 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1523 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1524 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1525 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1526 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1527 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1528 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1529 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1530 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1531 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1532 * @retval HAL status
1533 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1534 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1535 uint32_t TimerIdx,
1536 uint32_t OCChannel)
1537 {
1538 /* Check the parameters */
1539 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1540
1541 /* Process Locked */
1542 __HAL_LOCK(hhrtim);
1543
1544 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1545
1546 /* Enable the timer output */
1547 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1548
1549 /* Enable the timer counter */
1550 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1551
1552 hhrtim->State = HAL_HRTIM_STATE_READY;
1553
1554 /* Process Unlocked */
1555 __HAL_UNLOCK(hhrtim);
1556
1557 return HAL_OK;
1558 }
1559
1560 /**
1561 * @brief Stop the output compare signal generation on the designed timer output
1562 * @param hhrtim pointer to HAL HRTIM handle
1563 * @param TimerIdx Timer index
1564 * This parameter can be one of the following values:
1565 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1566 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1567 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1568 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1569 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1570 * @param OCChannel Timer output
1571 * This parameter can be one of the following values:
1572 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1573 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1574 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1575 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1576 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1577 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1578 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1579 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1580 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1581 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1582 * @retval HAL status
1583 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1584 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1585 uint32_t TimerIdx,
1586 uint32_t OCChannel)
1587 {
1588 /* Check the parameters */
1589 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1590
1591 /* Process Locked */
1592 __HAL_LOCK(hhrtim);
1593
1594 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1595
1596 /* Disable the timer output */
1597 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1598
1599 /* Disable the timer counter */
1600 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1601
1602 hhrtim->State = HAL_HRTIM_STATE_READY;
1603
1604 /* Process Unlocked */
1605 __HAL_UNLOCK(hhrtim);
1606
1607 return HAL_OK;
1608 }
1609
1610 /**
1611 * @brief Start the output compare signal generation on the designed timer output
1612 * (Interrupt is enabled (see note note below)).
1613 * @param hhrtim pointer to HAL HRTIM handle
1614 * @param TimerIdx Timer index
1615 * This parameter can be one of the following values:
1616 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1617 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1618 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1619 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1620 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1621 * @param OCChannel Timer output
1622 * This parameter can be one of the following values:
1623 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1624 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1625 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1626 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1627 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1628 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1629 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1630 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1631 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1632 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1633 * @note Interrupt enabling depends on the chosen output compare mode
1634 * Output toggle: compare match interrupt is enabled
1635 * Output set active: output set interrupt is enabled
1636 * Output set inactive: output reset interrupt is enabled
1637 * @retval HAL status
1638 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1639 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1640 uint32_t TimerIdx,
1641 uint32_t OCChannel)
1642 {
1643 uint32_t interrupt;
1644
1645 /* Check the parameters */
1646 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1647
1648 /* Process Locked */
1649 __HAL_LOCK(hhrtim);
1650
1651 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1652
1653 /* Get the interrupt to enable (depends on the output compare mode) */
1654 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1655
1656 /* Enable the timer output */
1657 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1658
1659 /* Enable the timer interrupt (depends on the output compare mode) */
1660 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1661
1662 /* Enable the timer counter */
1663 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1664
1665 hhrtim->State = HAL_HRTIM_STATE_READY;
1666
1667 /* Process Unlocked */
1668 __HAL_UNLOCK(hhrtim);
1669
1670 return HAL_OK;
1671 }
1672
1673 /**
1674 * @brief Stop the output compare signal generation on the designed timer output
1675 * (Interrupt is disabled).
1676 * @param hhrtim pointer to HAL HRTIM handle
1677 * @param TimerIdx Timer index
1678 * This parameter can be one of the following values:
1679 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1680 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1681 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1682 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1683 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1684 * @param OCChannel Timer output
1685 * This parameter can be one of the following values:
1686 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1687 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1688 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1689 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1690 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1691 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1692 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1693 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1694 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1695 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1696 * @retval HAL status
1697 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1698 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1699 uint32_t TimerIdx,
1700 uint32_t OCChannel)
1701 {
1702 uint32_t interrupt;
1703
1704 /* Check the parameters */
1705 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1706
1707 /* Process Locked */
1708 __HAL_LOCK(hhrtim);
1709
1710 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1711
1712 /* Disable the timer output */
1713 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1714
1715 /* Get the interrupt to disable (depends on the output compare mode) */
1716 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1717
1718 /* Disable the timer interrupt */
1719 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1720
1721 /* Disable the timer counter */
1722 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1723
1724 hhrtim->State = HAL_HRTIM_STATE_READY;
1725
1726 /* Process Unlocked */
1727 __HAL_UNLOCK(hhrtim);
1728
1729 return HAL_OK;
1730 }
1731
1732 /**
1733 * @brief Start the output compare signal generation on the designed timer output
1734 * (DMA request is enabled (see note below)).
1735 * @param hhrtim pointer to HAL HRTIM handle
1736 * @param TimerIdx Timer index
1737 * This parameter can be one of the following values:
1738 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1739 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1740 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1741 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1742 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1743 * @param OCChannel Timer output
1744 * This parameter can be one of the following values:
1745 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1746 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1747 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1748 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1749 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1750 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1751 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1752 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1753 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1754 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1755 * @param SrcAddr DMA transfer source address
1756 * @param DestAddr DMA transfer destination address
1757 * @param Length The length of data items (data size) to be transferred
1758 * from source to destination
1759 * @note DMA request enabling depends on the chosen output compare mode
1760 * Output toggle: compare match DMA request is enabled
1761 * Output set active: output set DMA request is enabled
1762 * Output set inactive: output reset DMA request is enabled
1763 * @retval HAL status
1764 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1765 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1766 uint32_t TimerIdx,
1767 uint32_t OCChannel,
1768 uint32_t SrcAddr,
1769 uint32_t DestAddr,
1770 uint32_t Length)
1771 {
1772 DMA_HandleTypeDef * hdma;
1773 uint32_t dma_request;
1774
1775 /* Check the parameters */
1776 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1777
1778 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1779 {
1780 return HAL_BUSY;
1781 }
1782 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1783 {
1784 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1785 {
1786 return HAL_ERROR;
1787 }
1788 else
1789 {
1790 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1791 }
1792 }
1793
1794 /* Process Locked */
1795 __HAL_LOCK(hhrtim);
1796
1797 /* Enable the timer output */
1798 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1799
1800 /* Get the DMA request to enable */
1801 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1802
1803 /* Get the timer DMA handler */
1804 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1805
1806 if (hdma == NULL)
1807 {
1808 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1809
1810 /* Process Unlocked */
1811 __HAL_UNLOCK(hhrtim);
1812
1813 return HAL_ERROR;
1814 }
1815
1816 /* Set the DMA error callback */
1817 hdma->XferErrorCallback = HRTIM_DMAError ;
1818
1819 /* Set the DMA transfer completed callback */
1820 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1821
1822 /* Enable the DMA channel */
1823 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1824 {
1825 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1826
1827 /* Process Unlocked */
1828 __HAL_UNLOCK(hhrtim);
1829
1830 return HAL_ERROR;
1831 }
1832
1833 /* Enable the timer DMA request */
1834 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1835
1836 /* Enable the timer counter */
1837 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1838
1839 hhrtim->State = HAL_HRTIM_STATE_READY;
1840
1841 /* Process Unlocked */
1842 __HAL_UNLOCK(hhrtim);
1843
1844 return HAL_OK;
1845 }
1846
1847 /**
1848 * @brief Stop the output compare signal generation on the designed timer output
1849 * (DMA request is disabled).
1850 * @param hhrtim pointer to HAL HRTIM handle
1851 * @param TimerIdx Timer index
1852 * This parameter can be one of the following values:
1853 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1854 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1855 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1856 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1857 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1858 * @param OCChannel Timer output
1859 * This parameter can be one of the following values:
1860 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1861 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1862 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1863 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1864 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1865 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1866 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1867 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1868 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1869 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1870 * @retval HAL status
1871 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1872 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1873 uint32_t TimerIdx,
1874 uint32_t OCChannel)
1875 {
1876 uint32_t dma_request;
1877
1878 /* Check the parameters */
1879 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1880
1881 /* Process Locked */
1882 __HAL_LOCK(hhrtim);
1883
1884 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1885
1886 /* Disable the timer output */
1887 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1888
1889 /* Get the timer DMA handler */
1890 /* Disable the DMA */
1891 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1892 {
1893 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1894
1895 /* Process Unlocked */
1896 __HAL_UNLOCK(hhrtim);
1897
1898 return HAL_ERROR;
1899 }
1900
1901 /* Get the DMA request to disable */
1902 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1903
1904 /* Disable the timer DMA request */
1905 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1906
1907 /* Disable the timer counter */
1908 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1909
1910 hhrtim->State = HAL_HRTIM_STATE_READY;
1911
1912 /* Process Unlocked */
1913 __HAL_UNLOCK(hhrtim);
1914
1915 return HAL_OK;
1916 }
1917
1918 /**
1919 * @}
1920 */
1921
1922 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1923 * @brief Simple PWM output functions
1924 @verbatim
1925 ===============================================================================
1926 ##### Simple PWM output functions #####
1927 ===============================================================================
1928 [..] This section provides functions allowing to:
1929 (+) Configure simple PWM output channel
1930 (+) Start simple PWM output
1931 (+) Stop simple PWM output
1932 (+) Start simple PWM output and enable interrupt
1933 (+) Stop simple PWM output and disable interrupt
1934 (+) Start simple PWM output and enable DMA transfer
1935 (+) Stop simple PWM output and disable DMA transfer
1936 -@- When a HRTIM timer operates in simple PWM output mode
1937 the output level is set to a programmable value when a match is
1938 found between the compare register and the counter and reset when
1939 the timer period is reached. Duty cycle is determined by the
1940 comparison value.
1941 Compare unit 1 is automatically associated to output 1
1942 Compare unit 2 is automatically associated to output 2
1943 @endverbatim
1944 * @{
1945 */
1946
1947 /**
1948 * @brief Configure an output in simple PWM mode
1949 * @param hhrtim pointer to HAL HRTIM handle
1950 * @param TimerIdx Timer index
1951 * This parameter can be one of the following values:
1952 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1953 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1954 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1955 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1956 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1957 * @param PWMChannel Timer output
1958 * This parameter can be one of the following values:
1959 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1960 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1961 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1962 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1963 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1964 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1965 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1966 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1967 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1968 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1969 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1970 * @note When the timer operates in simple PWM output mode:
1971 * Output 1 is implicitly controlled by the compare unit 1
1972 * Output 2 is implicitly controlled by the compare unit 2
1973 * Output Set/Reset crossbar is set as follows:
1974 * Output 1: SETx1R = CMP1, RSTx1R = PER
1975 * Output 2: SETx2R = CMP2, RST2R = PER
1976 * @note When Simple PWM mode is used the registers preload mechanism is
1977 * enabled (otherwise the behavior is not guaranteed).
1978 * @retval HAL status
1979 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,const HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)1980 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1981 uint32_t TimerIdx,
1982 uint32_t PWMChannel,
1983 const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1984 {
1985 HRTIM_OutputCfgTypeDef OutputCfg;
1986 uint32_t hrtim_timcr;
1987
1988 /* Check parameters */
1989 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1990 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1991 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1992 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1993
1994 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1995 {
1996 return HAL_BUSY;
1997 }
1998
1999 /* Process Locked */
2000 __HAL_LOCK(hhrtim);
2001
2002 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2003
2004 /* Configure timer compare unit */
2005 switch (PWMChannel)
2006 {
2007 case HRTIM_OUTPUT_TA1:
2008 case HRTIM_OUTPUT_TB1:
2009 case HRTIM_OUTPUT_TC1:
2010 case HRTIM_OUTPUT_TD1:
2011 case HRTIM_OUTPUT_TE1:
2012 {
2013 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
2014 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2015 break;
2016 }
2017
2018 case HRTIM_OUTPUT_TA2:
2019 case HRTIM_OUTPUT_TB2:
2020 case HRTIM_OUTPUT_TC2:
2021 case HRTIM_OUTPUT_TD2:
2022 case HRTIM_OUTPUT_TE2:
2023 {
2024 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
2025 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2026 break;
2027 }
2028 default:
2029 {
2030 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
2031 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
2032
2033 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2034
2035 /* Process Unlocked */
2036 __HAL_UNLOCK(hhrtim);
2037
2038 break;
2039 }
2040 }
2041
2042 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2043 {
2044 return HAL_ERROR;
2045 }
2046
2047 /* Configure timer output */
2048 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
2049 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
2050 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2051 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2052 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2053 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2054 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
2055
2056 HRTIM_OutputConfig(hhrtim,
2057 TimerIdx,
2058 PWMChannel,
2059 &OutputCfg);
2060
2061 /* Enable the registers preload mechanism */
2062 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
2063 hrtim_timcr |= HRTIM_TIMCR_PREEN;
2064 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
2065
2066 hhrtim->State = HAL_HRTIM_STATE_READY;
2067
2068 /* Process Unlocked */
2069 __HAL_UNLOCK(hhrtim);
2070
2071 return HAL_OK;
2072 }
2073
2074 /**
2075 * @brief Start the PWM output signal generation on the designed timer output
2076 * @param hhrtim pointer to HAL HRTIM handle
2077 * @param TimerIdx Timer index
2078 * This parameter can be one of the following values:
2079 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2080 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2081 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2082 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2083 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2084 * @param PWMChannel Timer output
2085 * This parameter can be one of the following values:
2086 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2087 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2088 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2089 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2090 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2091 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2092 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2093 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2094 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2095 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2096 * @retval HAL status
2097 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2098 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
2099 uint32_t TimerIdx,
2100 uint32_t PWMChannel)
2101 {
2102 /* Check the parameters */
2103 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2104
2105 /* Process Locked */
2106 __HAL_LOCK(hhrtim);
2107
2108 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2109
2110 /* Enable the timer output */
2111 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2112
2113 /* Enable the timer counter */
2114 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2115
2116 hhrtim->State = HAL_HRTIM_STATE_READY;
2117
2118 /* Process Unlocked */
2119 __HAL_UNLOCK(hhrtim);
2120
2121 return HAL_OK;
2122 }
2123
2124 /**
2125 * @brief Stop the PWM output signal generation on the designed timer output
2126 * @param hhrtim pointer to HAL HRTIM handle
2127 * @param TimerIdx Timer index
2128 * This parameter can be one of the following values:
2129 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2130 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2131 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2132 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2133 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2134 * @param PWMChannel Timer output
2135 * This parameter can be one of the following values:
2136 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2137 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2138 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2139 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2140 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2141 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2142 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2143 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2144 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2145 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2146 * @retval HAL status
2147 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2148 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
2149 uint32_t TimerIdx,
2150 uint32_t PWMChannel)
2151 {
2152 /* Check the parameters */
2153 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2154
2155 /* Process Locked */
2156 __HAL_LOCK(hhrtim);
2157
2158 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2159
2160 /* Disable the timer output */
2161 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2162
2163 /* Disable the timer counter */
2164 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2165
2166 hhrtim->State = HAL_HRTIM_STATE_READY;
2167
2168 /* Process Unlocked */
2169 __HAL_UNLOCK(hhrtim);
2170
2171 return HAL_OK;
2172 }
2173
2174 /**
2175 * @brief Start the PWM output signal generation on the designed timer output
2176 * (The compare interrupt is enabled).
2177 * @param hhrtim pointer to HAL HRTIM handle
2178 * @param TimerIdx Timer index
2179 * This parameter can be one of the following values:
2180 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2181 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2182 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2183 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2184 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2185 * @param PWMChannel Timer output
2186 * This parameter can be one of the following values:
2187 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2188 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2189 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2190 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2191 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2192 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2193 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2194 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2195 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2196 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2197 * @retval HAL status
2198 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2199 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2200 uint32_t TimerIdx,
2201 uint32_t PWMChannel)
2202 {
2203 /* Check the parameters */
2204 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2205
2206 /* Process Locked */
2207 __HAL_LOCK(hhrtim);
2208
2209 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2210
2211 /* Enable the timer output */
2212 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2213
2214 /* Enable the timer interrupt (depends on the PWM output) */
2215 switch (PWMChannel)
2216 {
2217 case HRTIM_OUTPUT_TA1:
2218 case HRTIM_OUTPUT_TB1:
2219 case HRTIM_OUTPUT_TC1:
2220 case HRTIM_OUTPUT_TD1:
2221 case HRTIM_OUTPUT_TE1:
2222 {
2223 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2224 break;
2225 }
2226
2227 case HRTIM_OUTPUT_TA2:
2228 case HRTIM_OUTPUT_TB2:
2229 case HRTIM_OUTPUT_TC2:
2230 case HRTIM_OUTPUT_TD2:
2231 case HRTIM_OUTPUT_TE2:
2232 {
2233 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2234 break;
2235 }
2236
2237 default:
2238 {
2239 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2240
2241 /* Process Unlocked */
2242 __HAL_UNLOCK(hhrtim);
2243
2244 break;
2245 }
2246 }
2247
2248 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2249 {
2250 return HAL_ERROR;
2251 }
2252
2253 /* Enable the timer counter */
2254 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2255
2256 hhrtim->State = HAL_HRTIM_STATE_READY;
2257
2258 /* Process Unlocked */
2259 __HAL_UNLOCK(hhrtim);
2260
2261 return HAL_OK;
2262 }
2263
2264 /**
2265 * @brief Stop the PWM output signal generation on the designed timer output
2266 * (The compare interrupt is disabled).
2267 * @param hhrtim pointer to HAL HRTIM handle
2268 * @param TimerIdx Timer index
2269 * This parameter can be one of the following values:
2270 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2271 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2272 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2273 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2274 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2275 * @param PWMChannel Timer output
2276 * This parameter can be one of the following values:
2277 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2278 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2279 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2280 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2281 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2282 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2283 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2284 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2285 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2286 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2287 * @retval HAL status
2288 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2289 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2290 uint32_t TimerIdx,
2291 uint32_t PWMChannel)
2292 {
2293 /* Check the parameters */
2294 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2295
2296 /* Process Locked */
2297 __HAL_LOCK(hhrtim);
2298
2299 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2300
2301 /* Disable the timer output */
2302 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2303
2304 /* Disable the timer interrupt (depends on the PWM output) */
2305 switch (PWMChannel)
2306 {
2307 case HRTIM_OUTPUT_TA1:
2308 case HRTIM_OUTPUT_TB1:
2309 case HRTIM_OUTPUT_TC1:
2310 case HRTIM_OUTPUT_TD1:
2311 case HRTIM_OUTPUT_TE1:
2312 {
2313 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2314 break;
2315 }
2316
2317 case HRTIM_OUTPUT_TA2:
2318 case HRTIM_OUTPUT_TB2:
2319 case HRTIM_OUTPUT_TC2:
2320 case HRTIM_OUTPUT_TD2:
2321 case HRTIM_OUTPUT_TE2:
2322 {
2323 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2324 break;
2325 }
2326
2327 default:
2328 {
2329 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2330
2331 /* Process Unlocked */
2332 __HAL_UNLOCK(hhrtim);
2333
2334 break;
2335 }
2336 }
2337
2338 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2339 {
2340 return HAL_ERROR;
2341 }
2342
2343 /* Disable the timer counter */
2344 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2345
2346 hhrtim->State = HAL_HRTIM_STATE_READY;
2347
2348 /* Process Unlocked */
2349 __HAL_UNLOCK(hhrtim);
2350
2351 return HAL_OK;
2352 }
2353
2354 /**
2355 * @brief Start the PWM output signal generation on the designed timer output
2356 * (The compare DMA request is enabled).
2357 * @param hhrtim pointer to HAL HRTIM handle
2358 * @param TimerIdx Timer index
2359 * This parameter can be one of the following values:
2360 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2361 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2362 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2363 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2364 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2365 * @param PWMChannel Timer output
2366 * This parameter can be one of the following values:
2367 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2368 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2369 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2370 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2371 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2372 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2373 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2374 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2375 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2376 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2377 * @param SrcAddr DMA transfer source address
2378 * @param DestAddr DMA transfer destination address
2379 * @param Length The length of data items (data size) to be transferred
2380 * from source to destination
2381 * @retval HAL status
2382 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2383 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2384 uint32_t TimerIdx,
2385 uint32_t PWMChannel,
2386 uint32_t SrcAddr,
2387 uint32_t DestAddr,
2388 uint32_t Length)
2389 {
2390 DMA_HandleTypeDef * hdma;
2391
2392 /* Check the parameters */
2393 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2394
2395 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2396 {
2397 return HAL_BUSY;
2398 }
2399 if(hhrtim->State == HAL_HRTIM_STATE_READY)
2400 {
2401 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2402 {
2403 return HAL_ERROR;
2404 }
2405 else
2406 {
2407 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2408 }
2409 }
2410
2411 /* Process Locked */
2412 __HAL_LOCK(hhrtim);
2413
2414 /* Enable the timer output */
2415 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2416
2417 /* Get the timer DMA handler */
2418 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2419
2420 if (hdma == NULL)
2421 {
2422 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2423
2424 /* Process Unlocked */
2425 __HAL_UNLOCK(hhrtim);
2426
2427 return HAL_ERROR;
2428 }
2429
2430 /* Set the DMA error callback */
2431 hdma->XferErrorCallback = HRTIM_DMAError ;
2432
2433 /* Set the DMA transfer completed callback */
2434 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2435
2436 /* Enable the DMA channel */
2437 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2438 {
2439 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2440
2441 /* Process Unlocked */
2442 __HAL_UNLOCK(hhrtim);
2443
2444 return HAL_ERROR;
2445 }
2446
2447 /* Enable the timer DMA request */
2448 switch (PWMChannel)
2449 {
2450 case HRTIM_OUTPUT_TA1:
2451 case HRTIM_OUTPUT_TB1:
2452 case HRTIM_OUTPUT_TC1:
2453 case HRTIM_OUTPUT_TD1:
2454 case HRTIM_OUTPUT_TE1:
2455 {
2456 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2457 break;
2458 }
2459
2460 case HRTIM_OUTPUT_TA2:
2461 case HRTIM_OUTPUT_TB2:
2462 case HRTIM_OUTPUT_TC2:
2463 case HRTIM_OUTPUT_TD2:
2464 case HRTIM_OUTPUT_TE2:
2465 {
2466 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2467 break;
2468 }
2469
2470 default:
2471 {
2472 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2473
2474 /* Process Unlocked */
2475 __HAL_UNLOCK(hhrtim);
2476
2477 break;
2478 }
2479 }
2480
2481 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2482 {
2483 return HAL_ERROR;
2484 }
2485
2486 /* Enable the timer counter */
2487 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2488
2489 hhrtim->State = HAL_HRTIM_STATE_READY;
2490
2491 /* Process Unlocked */
2492 __HAL_UNLOCK(hhrtim);
2493
2494 return HAL_OK;
2495 }
2496
2497 /**
2498 * @brief Stop the PWM output signal generation on the designed timer output
2499 * (The compare DMA request is disabled).
2500 * @param hhrtim pointer to HAL HRTIM handle
2501 * @param TimerIdx Timer index
2502 * This parameter can be one of the following values:
2503 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2504 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2505 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2506 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2507 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2508 * @param PWMChannel Timer output
2509 * This parameter can be one of the following values:
2510 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2511 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2512 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2513 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2514 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2515 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2516 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2517 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2518 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2519 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2520 * @retval HAL status
2521 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2522 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2523 uint32_t TimerIdx,
2524 uint32_t PWMChannel)
2525 {
2526 /* Check the parameters */
2527 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2528
2529 /* Process Locked */
2530 __HAL_LOCK(hhrtim);
2531
2532 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2533
2534 /* Disable the timer output */
2535 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2536
2537 /* Get the timer DMA handler */
2538 /* Disable the DMA */
2539 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2540 {
2541 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2542
2543 /* Process Unlocked */
2544 __HAL_UNLOCK(hhrtim);
2545
2546 return HAL_ERROR;
2547 }
2548
2549 /* Disable the timer DMA request */
2550 switch (PWMChannel)
2551 {
2552 case HRTIM_OUTPUT_TA1:
2553 case HRTIM_OUTPUT_TB1:
2554 case HRTIM_OUTPUT_TC1:
2555 case HRTIM_OUTPUT_TD1:
2556 case HRTIM_OUTPUT_TE1:
2557 {
2558 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2559 break;
2560 }
2561
2562 case HRTIM_OUTPUT_TA2:
2563 case HRTIM_OUTPUT_TB2:
2564 case HRTIM_OUTPUT_TC2:
2565 case HRTIM_OUTPUT_TD2:
2566 case HRTIM_OUTPUT_TE2:
2567 {
2568 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2569 break;
2570 }
2571
2572 default:
2573 {
2574 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2575
2576 /* Process Unlocked */
2577 __HAL_UNLOCK(hhrtim);
2578
2579 break;
2580 }
2581 }
2582
2583 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2584 {
2585 return HAL_ERROR;
2586 }
2587
2588 /* Disable the timer counter */
2589 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2590
2591 hhrtim->State = HAL_HRTIM_STATE_READY;
2592
2593 /* Process Unlocked */
2594 __HAL_UNLOCK(hhrtim);
2595
2596 return HAL_OK;
2597 }
2598
2599 /**
2600 * @}
2601 */
2602
2603 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2604 * @brief Simple input capture functions
2605 @verbatim
2606 ===============================================================================
2607 ##### Simple input capture functions #####
2608 ===============================================================================
2609 [..] This section provides functions allowing to:
2610 (+) Configure simple input capture channel
2611 (+) Start simple input capture
2612 (+) Stop simple input capture
2613 (+) Start simple input capture and enable interrupt
2614 (+) Stop simple input capture and disable interrupt
2615 (+) Start simple input capture and enable DMA transfer
2616 (+) Stop simple input capture and disable DMA transfer
2617 -@- When a HRTIM timer operates in simple input capture mode
2618 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2619 value of the timer counter counter after a transition detected
2620 on a given external event input.
2621 @endverbatim
2622 * @{
2623 */
2624
2625 /**
2626 * @brief Configure a simple capture
2627 * @param hhrtim pointer to HAL HRTIM handle
2628 * @param TimerIdx Timer index
2629 * This parameter can be one of the following values:
2630 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2631 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2632 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2633 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2634 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2635 * @param CaptureChannel Capture unit
2636 * This parameter can be one of the following values:
2637 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2638 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2639 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2640 * @note When the timer operates in simple capture mode the capture is triggered
2641 * by the designated external event and GPIO input is implicitly used as event source.
2642 * The cature can be triggered by a rising edge, a falling edge or both
2643 * edges on event channel.
2644 * @retval HAL status
2645 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,const HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2646 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2647 uint32_t TimerIdx,
2648 uint32_t CaptureChannel,
2649 const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2650 {
2651 HRTIM_EventCfgTypeDef EventCfg;
2652
2653 /* Check parameters */
2654 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2655 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2656 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2657 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2658 pSimpleCaptureChannelCfg->EventPolarity));
2659 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2660 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2661 pSimpleCaptureChannelCfg->EventFilter));
2662
2663 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2664 {
2665 return HAL_BUSY;
2666 }
2667
2668 /* Process Locked */
2669 __HAL_LOCK(hhrtim);
2670
2671 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2672
2673 /* Configure external event channel */
2674 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2675 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2676 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2677 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2678 EventCfg.Source = HRTIM_EVENTSRC_1;
2679
2680 HRTIM_EventConfig(hhrtim,
2681 pSimpleCaptureChannelCfg->Event,
2682 &EventCfg);
2683
2684 /* Memorize capture trigger (will be configured when the capture is started */
2685 HRTIM_CaptureUnitConfig(hhrtim,
2686 TimerIdx,
2687 CaptureChannel,
2688 pSimpleCaptureChannelCfg->Event);
2689
2690 hhrtim->State = HAL_HRTIM_STATE_READY;
2691
2692 /* Process Unlocked */
2693 __HAL_UNLOCK(hhrtim);
2694
2695 return HAL_OK;
2696 }
2697
2698 /**
2699 * @brief Enable a simple capture on the designed capture unit
2700 * @param hhrtim pointer to HAL HRTIM handle
2701 * @param TimerIdx Timer index
2702 * This parameter can be one of the following values:
2703 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2704 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2705 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2706 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2707 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2708 * @param CaptureChannel Timer output
2709 * This parameter can be one of the following values:
2710 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2711 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2712 * @retval HAL status
2713 * @note The external event triggering the capture is available for all timing
2714 * units. It can be used directly and is active as soon as the timing
2715 * unit counter is enabled.
2716 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2717 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2718 uint32_t TimerIdx,
2719 uint32_t CaptureChannel)
2720 {
2721 /* Check the parameters */
2722 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2723 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2724
2725 /* Process Locked */
2726 __HAL_LOCK(hhrtim);
2727
2728 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2729
2730 /* Set the capture unit trigger */
2731 switch (CaptureChannel)
2732 {
2733 case HRTIM_CAPTUREUNIT_1:
2734 {
2735 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2736 break;
2737 }
2738
2739 case HRTIM_CAPTUREUNIT_2:
2740 {
2741 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2742 break;
2743 }
2744
2745 default:
2746 {
2747 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2748
2749 /* Process Unlocked */
2750 __HAL_UNLOCK(hhrtim);
2751
2752 break;
2753 }
2754 }
2755
2756 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2757 {
2758 return HAL_ERROR;
2759 }
2760
2761 /* Enable the timer counter */
2762 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2763
2764 hhrtim->State = HAL_HRTIM_STATE_READY;
2765
2766 /* Process Unlocked */
2767 __HAL_UNLOCK(hhrtim);
2768
2769 return HAL_OK;
2770 }
2771
2772 /**
2773 * @brief Disable a simple capture on the designed capture unit
2774 * @param hhrtim pointer to HAL HRTIM handle
2775 * @param TimerIdx Timer index
2776 * This parameter can be one of the following values:
2777 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2778 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2779 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2780 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2781 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2782 * @param CaptureChannel Timer output
2783 * This parameter can be one of the following values:
2784 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2785 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2786 * @retval HAL status
2787 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2788 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2789 uint32_t TimerIdx,
2790 uint32_t CaptureChannel)
2791 {
2792 uint32_t hrtim_cpt1cr;
2793 uint32_t hrtim_cpt2cr;
2794
2795 /* Check the parameters */
2796 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2797 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2798
2799 /* Process Locked */
2800 __HAL_LOCK(hhrtim);
2801
2802 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2803
2804 /* Set the capture unit trigger */
2805 switch (CaptureChannel)
2806 {
2807 case HRTIM_CAPTUREUNIT_1:
2808 {
2809 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2810 break;
2811 }
2812
2813 case HRTIM_CAPTUREUNIT_2:
2814 {
2815 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2816 break;
2817 }
2818
2819 default:
2820 {
2821 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2822
2823 /* Process Unlocked */
2824 __HAL_UNLOCK(hhrtim);
2825
2826 break;
2827 }
2828 }
2829
2830 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2831 {
2832 return HAL_ERROR;
2833 }
2834
2835 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2836 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2837
2838 /* Disable the timer counter */
2839 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2840 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2841 {
2842 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2843 }
2844
2845 hhrtim->State = HAL_HRTIM_STATE_READY;
2846
2847 /* Process Unlocked */
2848 __HAL_UNLOCK(hhrtim);
2849
2850 return HAL_OK;
2851 }
2852
2853 /**
2854 * @brief Enable a simple capture on the designed capture unit
2855 * (Capture interrupt is enabled).
2856 * @param hhrtim pointer to HAL HRTIM handle
2857 * @param TimerIdx Timer index
2858 * This parameter can be one of the following values:
2859 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2860 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2861 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2862 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2863 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2864 * @param CaptureChannel Timer output
2865 * This parameter can be one of the following values:
2866 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2867 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2868 * @retval HAL status
2869 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2870 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2871 uint32_t TimerIdx,
2872 uint32_t CaptureChannel)
2873 {
2874 /* Check the parameters */
2875 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2876 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2877
2878 /* Process Locked */
2879 __HAL_LOCK(hhrtim);
2880
2881 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2882
2883 /* Set the capture unit trigger */
2884 switch (CaptureChannel)
2885 {
2886 case HRTIM_CAPTUREUNIT_1:
2887 {
2888 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2889
2890 /* Enable the capture unit 1 interrupt */
2891 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2892 break;
2893 }
2894
2895 case HRTIM_CAPTUREUNIT_2:
2896 {
2897 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2898
2899 /* Enable the capture unit 2 interrupt */
2900 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2901 break;
2902 }
2903
2904 default:
2905 {
2906 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2907
2908 /* Process Unlocked */
2909 __HAL_UNLOCK(hhrtim);
2910
2911 break;
2912 }
2913 }
2914
2915 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2916 {
2917 return HAL_ERROR;
2918 }
2919
2920 /* Enable the timer counter */
2921 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2922
2923 hhrtim->State = HAL_HRTIM_STATE_READY;
2924
2925 /* Process Unlocked */
2926 __HAL_UNLOCK(hhrtim);
2927
2928 return HAL_OK;
2929 }
2930
2931 /**
2932 * @brief Disable a simple capture on the designed capture unit
2933 * (Capture interrupt is disabled).
2934 * @param hhrtim pointer to HAL HRTIM handle
2935 * @param TimerIdx Timer index
2936 * This parameter can be one of the following values:
2937 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2938 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2939 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2940 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2941 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2942 * @param CaptureChannel Timer output
2943 * This parameter can be one of the following values:
2944 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2945 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2946 * @retval HAL status
2947 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2948 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2949 uint32_t TimerIdx,
2950 uint32_t CaptureChannel)
2951 {
2952
2953 uint32_t hrtim_cpt1cr;
2954 uint32_t hrtim_cpt2cr;
2955
2956 /* Check the parameters */
2957 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2958 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2959
2960 /* Process Locked */
2961 __HAL_LOCK(hhrtim);
2962
2963 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2964
2965 /* Set the capture unit trigger */
2966 switch (CaptureChannel)
2967 {
2968 case HRTIM_CAPTUREUNIT_1:
2969 {
2970 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2971
2972 /* Disable the capture unit 1 interrupt */
2973 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2974 break;
2975 }
2976
2977 case HRTIM_CAPTUREUNIT_2:
2978 {
2979 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2980
2981 /* Disable the capture unit 2 interrupt */
2982 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2983 break;
2984 }
2985
2986 default:
2987 {
2988 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2989
2990 /* Process Unlocked */
2991 __HAL_UNLOCK(hhrtim);
2992
2993 break;
2994 }
2995 }
2996
2997 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2998 {
2999 return HAL_ERROR;
3000 }
3001
3002 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3003 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3004
3005 /* Disable the timer counter */
3006 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3007 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3008 {
3009 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3010 }
3011
3012 hhrtim->State = HAL_HRTIM_STATE_READY;
3013
3014 /* Process Unlocked */
3015 __HAL_UNLOCK(hhrtim);
3016
3017 return HAL_OK;
3018 }
3019
3020 /**
3021 * @brief Enable a simple capture on the designed capture unit
3022 * (Capture DMA request is enabled).
3023 * @param hhrtim pointer to HAL HRTIM handle
3024 * @param TimerIdx Timer index
3025 * This parameter can be one of the following values:
3026 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3027 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3028 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3029 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3030 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3031 * @param CaptureChannel Timer output
3032 * This parameter can be one of the following values:
3033 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3034 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3035 * @param SrcAddr DMA transfer source address
3036 * @param DestAddr DMA transfer destination address
3037 * @param Length The length of data items (data size) to be transferred
3038 * from source to destination
3039 * @retval HAL status
3040 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)3041 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
3042 uint32_t TimerIdx,
3043 uint32_t CaptureChannel,
3044 uint32_t SrcAddr,
3045 uint32_t DestAddr,
3046 uint32_t Length)
3047 {
3048 DMA_HandleTypeDef * hdma;
3049
3050 /* Check the parameters */
3051 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3052 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3053
3054 /* Process Locked */
3055 __HAL_LOCK(hhrtim);
3056
3057 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3058
3059 /* Get the timer DMA handler */
3060 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
3061
3062 if (hdma == NULL)
3063 {
3064 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3065
3066 /* Process Unlocked */
3067 __HAL_UNLOCK(hhrtim);
3068
3069 return HAL_ERROR;
3070 }
3071
3072 /* Set the DMA error callback */
3073 hdma->XferErrorCallback = HRTIM_DMAError ;
3074
3075 /* Set the DMA transfer completed callback */
3076 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
3077
3078 /* Enable the DMA channel */
3079 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
3080 {
3081 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3082
3083 /* Process Unlocked */
3084 __HAL_UNLOCK(hhrtim);
3085
3086 return HAL_ERROR;
3087 }
3088
3089 switch (CaptureChannel)
3090 {
3091 case HRTIM_CAPTUREUNIT_1:
3092 {
3093 /* Set the capture unit trigger */
3094 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
3095
3096 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3097 break;
3098 }
3099
3100 case HRTIM_CAPTUREUNIT_2:
3101 {
3102 /* Set the capture unit trigger */
3103 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
3104
3105 /* Enable the timer DMA request */
3106 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3107 break;
3108 }
3109
3110 default:
3111 {
3112 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3113
3114 /* Process Unlocked */
3115 __HAL_UNLOCK(hhrtim);
3116
3117 break;
3118 }
3119 }
3120
3121 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3122 {
3123 return HAL_ERROR;
3124 }
3125
3126 /* Enable the timer counter */
3127 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3128
3129 hhrtim->State = HAL_HRTIM_STATE_READY;
3130
3131 /* Process Unlocked */
3132 __HAL_UNLOCK(hhrtim);
3133
3134 return HAL_OK;
3135 }
3136
3137 /**
3138 * @brief Disable a simple capture on the designed capture unit
3139 * (Capture DMA request is disabled).
3140 * @param hhrtim pointer to HAL HRTIM handle
3141 * @param TimerIdx Timer index
3142 * This parameter can be one of the following values:
3143 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3144 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3145 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3146 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3147 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3148 * @param CaptureChannel Timer output
3149 * This parameter can be one of the following values:
3150 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3151 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3152 * @retval HAL status
3153 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3154 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3155 uint32_t TimerIdx,
3156 uint32_t CaptureChannel)
3157 {
3158
3159 uint32_t hrtim_cpt1cr;
3160 uint32_t hrtim_cpt2cr;
3161
3162 /* Check the parameters */
3163 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3164 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3165
3166 /* Process Locked */
3167 __HAL_LOCK(hhrtim);
3168
3169 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3170
3171 /* Get the timer DMA handler */
3172 /* Disable the DMA */
3173 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3174 {
3175 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3176
3177 /* Process Unlocked */
3178 __HAL_UNLOCK(hhrtim);
3179
3180 return HAL_ERROR;
3181 }
3182
3183 switch (CaptureChannel)
3184 {
3185 case HRTIM_CAPTUREUNIT_1:
3186 {
3187 /* Reset the capture unit trigger */
3188 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3189
3190 /* Disable the capture unit 1 DMA request */
3191 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3192 break;
3193 }
3194
3195 case HRTIM_CAPTUREUNIT_2:
3196 {
3197 /* Reset the capture unit trigger */
3198 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3199
3200 /* Disable the capture unit 2 DMA request */
3201 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3202 break;
3203 }
3204
3205 default:
3206 {
3207 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3208
3209 /* Process Unlocked */
3210 __HAL_UNLOCK(hhrtim);
3211
3212 break;
3213 }
3214 }
3215
3216 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3217 {
3218 return HAL_ERROR;
3219 }
3220
3221 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3222 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3223
3224 /* Disable the timer counter */
3225 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3226 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3227 {
3228 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3229 }
3230
3231 hhrtim->State = HAL_HRTIM_STATE_READY;
3232
3233 /* Process Unlocked */
3234 __HAL_UNLOCK(hhrtim);
3235
3236 return HAL_OK;
3237 }
3238
3239 /**
3240 * @}
3241 */
3242
3243 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3244 * @brief Simple one pulse functions
3245 @verbatim
3246 ===============================================================================
3247 ##### Simple one pulse functions #####
3248 ===============================================================================
3249 [..] This section provides functions allowing to:
3250 (+) Configure one pulse channel
3251 (+) Start one pulse generation
3252 (+) Stop one pulse generation
3253 (+) Start one pulse generation and enable interrupt
3254 (+) Stop one pulse generation and disable interrupt
3255 -@- When a HRTIM timer operates in simple one pulse mode
3256 the timer counter is started in response to transition detected
3257 on a given external event input to generate a pulse with a
3258 programmable length after a programmable delay.
3259 @endverbatim
3260 * @{
3261 */
3262
3263 /**
3264 * @brief Configure an output simple one pulse mode
3265 * @param hhrtim pointer to HAL HRTIM handle
3266 * @param TimerIdx Timer index
3267 * This parameter can be one of the following values:
3268 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3269 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3270 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3271 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3272 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3273 * @param OnePulseChannel Timer output
3274 * This parameter can be one of the following values:
3275 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3276 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3277 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3278 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3279 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3280 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3281 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3282 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3283 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3284 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3285 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3286 * @note When the timer operates in simple one pulse mode:
3287 * the timer counter is implicitly started by the reset event,
3288 * the reset of the timer counter is triggered by the designated external event
3289 * GPIO input is implicitly used as event source,
3290 * Output 1 is implicitly controlled by the compare unit 1,
3291 * Output 2 is implicitly controlled by the compare unit 2.
3292 * Output Set/Reset crossbar is set as follows:
3293 * Output 1: SETx1R = CMP1, RSTx1R = PER
3294 * Output 2: SETx2R = CMP2, RST2R = PER
3295 * @retval HAL status
3296 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3297 * outputs, the reset event related configuration data provided in the
3298 * second call will override the reset event related configuration data
3299 * provided in the first call.
3300 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,const HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3301 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3302 uint32_t TimerIdx,
3303 uint32_t OnePulseChannel,
3304 const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3305 {
3306 HRTIM_OutputCfgTypeDef OutputCfg;
3307 HRTIM_EventCfgTypeDef EventCfg;
3308
3309 /* Check parameters */
3310 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3311 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3312 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3313 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3314 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3315 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3316 pSimpleOnePulseChannelCfg->EventPolarity));
3317 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3318 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3319 pSimpleOnePulseChannelCfg->EventFilter));
3320
3321 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3322 {
3323 return HAL_BUSY;
3324 }
3325
3326 /* Process Locked */
3327 __HAL_LOCK(hhrtim);
3328
3329 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3330
3331 /* Configure timer compare unit */
3332 switch (OnePulseChannel)
3333 {
3334 case HRTIM_OUTPUT_TA1:
3335 case HRTIM_OUTPUT_TB1:
3336 case HRTIM_OUTPUT_TC1:
3337 case HRTIM_OUTPUT_TD1:
3338 case HRTIM_OUTPUT_TE1:
3339 {
3340 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3341 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3342 break;
3343 }
3344
3345 case HRTIM_OUTPUT_TA2:
3346 case HRTIM_OUTPUT_TB2:
3347 case HRTIM_OUTPUT_TC2:
3348 case HRTIM_OUTPUT_TD2:
3349 case HRTIM_OUTPUT_TE2:
3350 {
3351 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3352 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3353 break;
3354 }
3355
3356 default:
3357 {
3358 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3359 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3360
3361 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3362
3363 /* Process Unlocked */
3364 __HAL_UNLOCK(hhrtim);
3365
3366 break;
3367 }
3368 }
3369
3370 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3371 {
3372 return HAL_ERROR;
3373 }
3374
3375 /* Configure timer output */
3376 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3377 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3378 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3379 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3380 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3381 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3382 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3383
3384 HRTIM_OutputConfig(hhrtim,
3385 TimerIdx,
3386 OnePulseChannel,
3387 &OutputCfg);
3388
3389 /* Configure external event channel */
3390 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3391 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3392 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3393 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3394 EventCfg.Source = HRTIM_EVENTSRC_1;
3395
3396 HRTIM_EventConfig(hhrtim,
3397 pSimpleOnePulseChannelCfg->Event,
3398 &EventCfg);
3399
3400 /* Configure the timer reset register */
3401 HRTIM_TIM_ResetConfig(hhrtim,
3402 TimerIdx,
3403 pSimpleOnePulseChannelCfg->Event);
3404
3405 hhrtim->State = HAL_HRTIM_STATE_READY;
3406
3407 /* Process Unlocked */
3408 __HAL_UNLOCK(hhrtim);
3409
3410 return HAL_OK;
3411 }
3412
3413 /**
3414 * @brief Enable the simple one pulse signal generation on the designed output
3415 * @param hhrtim pointer to HAL HRTIM handle
3416 * @param TimerIdx Timer index
3417 * This parameter can be one of the following values:
3418 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3419 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3420 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3421 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3422 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3423 * @param OnePulseChannel Timer output
3424 * This parameter can be one of the following values:
3425 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3426 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3427 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3428 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3429 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3430 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3431 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3432 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3433 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3434 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3435 * @retval HAL status
3436 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3437 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3438 uint32_t TimerIdx,
3439 uint32_t OnePulseChannel)
3440 {
3441 /* Check the parameters */
3442 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3443
3444 /* Process Locked */
3445 __HAL_LOCK(hhrtim);
3446
3447 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3448
3449 /* Enable the timer output */
3450 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3451
3452 /* Enable the timer counter */
3453 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3454
3455 hhrtim->State = HAL_HRTIM_STATE_READY;
3456
3457 /* Process Unlocked */
3458 __HAL_UNLOCK(hhrtim);
3459
3460 return HAL_OK;
3461 }
3462
3463 /**
3464 * @brief Disable the simple one pulse signal generation on the designed output
3465 * @param hhrtim pointer to HAL HRTIM handle
3466 * @param TimerIdx Timer index
3467 * This parameter can be one of the following values:
3468 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3469 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3470 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3471 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3472 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3473 * @param OnePulseChannel Timer output
3474 * This parameter can be one of the following values:
3475 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3476 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3477 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3478 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3479 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3480 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3481 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3482 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3483 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3484 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3485 * @retval HAL status
3486 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3487 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3488 uint32_t TimerIdx,
3489 uint32_t OnePulseChannel)
3490 {
3491 /* Check the parameters */
3492 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3493
3494 /* Process Locked */
3495 __HAL_LOCK(hhrtim);
3496
3497 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3498
3499 /* Disable the timer output */
3500 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3501
3502 /* Disable the timer counter */
3503 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3504
3505 hhrtim->State = HAL_HRTIM_STATE_READY;
3506
3507 /* Process Unlocked */
3508 __HAL_UNLOCK(hhrtim);
3509
3510 return HAL_OK;
3511 }
3512
3513 /**
3514 * @brief Enable the simple one pulse signal generation on the designed output
3515 * (The compare interrupt is enabled (pulse start)).
3516 * @param hhrtim pointer to HAL HRTIM handle
3517 * @param TimerIdx Timer index
3518 * This parameter can be one of the following values:
3519 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3520 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3521 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3522 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3523 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3524 * @param OnePulseChannel Timer output
3525 * This parameter can be one of the following values:
3526 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3527 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3528 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3529 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3530 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3531 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3532 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3533 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3534 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3535 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3536 * @retval HAL status
3537 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3538 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3539 uint32_t TimerIdx,
3540 uint32_t OnePulseChannel)
3541 {
3542 /* Check the parameters */
3543 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3544
3545 /* Process Locked */
3546 __HAL_LOCK(hhrtim);
3547
3548 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3549
3550 /* Enable the timer output */
3551 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3552
3553 /* Enable the timer interrupt (depends on the OnePulse output) */
3554 switch (OnePulseChannel)
3555 {
3556 case HRTIM_OUTPUT_TA1:
3557 case HRTIM_OUTPUT_TB1:
3558 case HRTIM_OUTPUT_TC1:
3559 case HRTIM_OUTPUT_TD1:
3560 case HRTIM_OUTPUT_TE1:
3561 {
3562 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3563 break;
3564 }
3565
3566 case HRTIM_OUTPUT_TA2:
3567 case HRTIM_OUTPUT_TB2:
3568 case HRTIM_OUTPUT_TC2:
3569 case HRTIM_OUTPUT_TD2:
3570 case HRTIM_OUTPUT_TE2:
3571 {
3572 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3573 break;
3574 }
3575
3576 default:
3577 {
3578 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3579
3580 /* Process Unlocked */
3581 __HAL_UNLOCK(hhrtim);
3582
3583 break;
3584 }
3585 }
3586
3587 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3588 {
3589 return HAL_ERROR;
3590 }
3591
3592 /* Enable the timer counter */
3593 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3594
3595 hhrtim->State = HAL_HRTIM_STATE_READY;
3596
3597 /* Process Unlocked */
3598 __HAL_UNLOCK(hhrtim);
3599
3600 return HAL_OK;
3601 }
3602
3603 /**
3604 * @brief Disable the simple one pulse signal generation on the designed output
3605 * (The compare interrupt is disabled).
3606 * @param hhrtim pointer to HAL HRTIM handle
3607 * @param TimerIdx Timer index
3608 * This parameter can be one of the following values:
3609 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3610 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3611 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3612 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3613 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3614 * @param OnePulseChannel Timer output
3615 * This parameter can be one of the following values:
3616 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3617 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3618 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3619 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3620 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3621 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3622 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3623 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3624 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3625 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3626 * @retval HAL status
3627 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3628 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3629 uint32_t TimerIdx,
3630 uint32_t OnePulseChannel)
3631 {
3632 /* Check the parameters */
3633 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3634
3635 /* Process Locked */
3636 __HAL_LOCK(hhrtim);
3637
3638 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3639
3640 /* Disable the timer output */
3641 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3642
3643 /* Disable the timer interrupt (depends on the OnePulse output) */
3644 switch (OnePulseChannel)
3645 {
3646 case HRTIM_OUTPUT_TA1:
3647 case HRTIM_OUTPUT_TB1:
3648 case HRTIM_OUTPUT_TC1:
3649 case HRTIM_OUTPUT_TD1:
3650 case HRTIM_OUTPUT_TE1:
3651 {
3652 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3653 break;
3654 }
3655
3656 case HRTIM_OUTPUT_TA2:
3657 case HRTIM_OUTPUT_TB2:
3658 case HRTIM_OUTPUT_TC2:
3659 case HRTIM_OUTPUT_TD2:
3660 case HRTIM_OUTPUT_TE2:
3661 {
3662 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3663 break;
3664 }
3665
3666 default:
3667 {
3668 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3669
3670 /* Process Unlocked */
3671 __HAL_UNLOCK(hhrtim);
3672
3673 break;
3674 }
3675 }
3676
3677 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3678 {
3679 return HAL_ERROR;
3680 }
3681
3682 /* Disable the timer counter */
3683 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3684
3685 hhrtim->State = HAL_HRTIM_STATE_READY;
3686
3687 /* Process Unlocked */
3688 __HAL_UNLOCK(hhrtim);
3689
3690 return HAL_OK;
3691 }
3692
3693 /**
3694 * @}
3695 */
3696
3697 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3698 * @brief HRTIM configuration functions
3699 @verbatim
3700 ===============================================================================
3701 ##### HRTIM configuration functions #####
3702 ===============================================================================
3703 [..] This section provides functions allowing to configure the HRTIM
3704 resources shared by all the HRTIM timers operating in waveform mode:
3705 (+) Configure the burst mode controller
3706 (+) Configure an external event conditioning
3707 (+) Configure the external events sampling clock
3708 (+) Configure a fault conditioning
3709 (+) Enable or disable fault inputs
3710 (+) Configure the faults sampling clock
3711 (+) Configure an ADC trigger
3712
3713 @endverbatim
3714 * @{
3715 */
3716
3717 /**
3718 * @brief Configure the burst mode feature of the HRTIM
3719 * @param hhrtim pointer to HAL HRTIM handle
3720 * @param pBurstModeCfg pointer to the burst mode configuration structure
3721 * @retval HAL status
3722 * @note This function must be called before starting the burst mode
3723 * controller
3724 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,const HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3725 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3726 const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3727 {
3728 uint32_t hrtim_bmcr;
3729
3730 /* Check parameters */
3731 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3732 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3733 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3734 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3735 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3736
3737 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3738 {
3739 return HAL_BUSY;
3740 }
3741
3742 /* Process Locked */
3743 __HAL_LOCK(hhrtim);
3744
3745 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3746
3747 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3748
3749 /* Set the burst mode operating mode */
3750 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3751 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3752
3753 /* Set the burst mode clock source */
3754 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3755 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3756
3757 /* Set the burst mode prescaler */
3758 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3759 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3760
3761 /* Enable/disable burst mode registers preload */
3762 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3763 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3764
3765 /* Set the burst mode trigger */
3766 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3767
3768 /* Set the burst mode compare value */
3769 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3770
3771 /* Set the burst mode period */
3772 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3773
3774 /* Update the HRTIM registers */
3775 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3776
3777 hhrtim->State = HAL_HRTIM_STATE_READY;
3778
3779 /* Process Unlocked */
3780 __HAL_UNLOCK(hhrtim);
3781
3782 return HAL_OK;
3783 }
3784
3785 /**
3786 * @brief Configure the conditioning of an external event
3787 * @param hhrtim pointer to HAL HRTIM handle
3788 * @param Event external event to configure
3789 * This parameter can be one of the following values:
3790 * @arg HRTIM_EVENT_NONE: no external Event
3791 * @arg HRTIM_EVENT_1: External event 1
3792 * @arg HRTIM_EVENT_2: External event 2
3793 * @arg HRTIM_EVENT_3: External event 3
3794 * @arg HRTIM_EVENT_4: External event 4
3795 * @arg HRTIM_EVENT_5: External event 5
3796 * @arg HRTIM_EVENT_6: External event 6
3797 * @arg HRTIM_EVENT_7: External event 7
3798 * @arg HRTIM_EVENT_8: External event 8
3799 * @arg HRTIM_EVENT_9: External event 9
3800 * @arg HRTIM_EVENT_10: External event 10
3801 * @param pEventCfg pointer to the event conditioning configuration structure
3802 * @note This function must be called before starting the timer
3803 * @retval HAL status
3804 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)3805 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3806 uint32_t Event,
3807 const HRTIM_EventCfgTypeDef* pEventCfg)
3808 {
3809 /* Check parameters */
3810 assert_param(IS_HRTIM_EVENT(Event));
3811 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3812 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3813 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3814 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3815 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3816
3817 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3818 {
3819 return HAL_BUSY;
3820 }
3821
3822 /* Process Locked */
3823 __HAL_LOCK(hhrtim);
3824
3825 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3826
3827 /* Configure the event channel */
3828 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3829
3830 hhrtim->State = HAL_HRTIM_STATE_READY;
3831
3832 /* Process Unlocked */
3833 __HAL_UNLOCK(hhrtim);
3834
3835 return HAL_OK;
3836 }
3837
3838 /**
3839 * @brief Configure the external event conditioning block prescaler
3840 * @param hhrtim pointer to HAL HRTIM handle
3841 * @param Prescaler Prescaler value
3842 * This parameter can be one of the following values:
3843 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3844 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3845 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3846 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3847 * @note This function must be called before starting the timer
3848 * @retval HAL status
3849 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3850 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3851 uint32_t Prescaler)
3852 {
3853 /* Check parameters */
3854 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3855
3856 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3857 {
3858 return HAL_BUSY;
3859 }
3860
3861 /* Process Locked */
3862 __HAL_LOCK(hhrtim);
3863
3864 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3865
3866 /* Set the external event prescaler */
3867 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3868
3869 hhrtim->State = HAL_HRTIM_STATE_READY;
3870
3871 /* Process Unlocked */
3872 __HAL_UNLOCK(hhrtim);
3873
3874 return HAL_OK;
3875 }
3876
3877 /**
3878 * @brief Configure the conditioning of fault input
3879 * @param hhrtim pointer to HAL HRTIM handle
3880 * @param Fault fault input to configure
3881 * This parameter can be one of the following values:
3882 * @arg HRTIM_FAULT_1: Fault input 1
3883 * @arg HRTIM_FAULT_2: Fault input 2
3884 * @arg HRTIM_FAULT_3: Fault input 3
3885 * @arg HRTIM_FAULT_4: Fault input 4
3886 * @arg HRTIM_FAULT_5: Fault input 5
3887 * @param pFaultCfg pointer to the fault conditioning configuration structure
3888 * @note This function must be called before starting the timer and before
3889 * enabling faults inputs
3890 * @retval HAL status
3891 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultCfgTypeDef * pFaultCfg)3892 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3893 uint32_t Fault,
3894 const HRTIM_FaultCfgTypeDef* pFaultCfg)
3895 {
3896 uint32_t hrtim_fltinr1;
3897 uint32_t hrtim_fltinr2;
3898
3899 /* Check parameters */
3900 assert_param(IS_HRTIM_FAULT(Fault));
3901 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3902 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3903 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3904 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3905
3906 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3907 {
3908 return HAL_BUSY;
3909 }
3910
3911 /* Process Locked */
3912 __HAL_LOCK(hhrtim);
3913
3914 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3915
3916 /* Configure fault channel */
3917 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3918 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3919
3920 switch (Fault)
3921 {
3922 case HRTIM_FAULT_1:
3923 {
3924 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3925 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3926 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3927 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3928 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3929 break;
3930 }
3931
3932 case HRTIM_FAULT_2:
3933 {
3934 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3935 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3936 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3937 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3938 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3939 break;
3940 }
3941
3942 case HRTIM_FAULT_3:
3943 {
3944 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3945 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3946 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3947 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3948 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3949 break;
3950 }
3951
3952 case HRTIM_FAULT_4:
3953 {
3954 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3955 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3956 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3957 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3958 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3959 break;
3960 }
3961
3962 case HRTIM_FAULT_5:
3963 {
3964 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3965 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3966 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3967 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3968 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3969 break;
3970 }
3971
3972 default:
3973 {
3974 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3975
3976 /* Process Unlocked */
3977 __HAL_UNLOCK(hhrtim);
3978
3979 break;
3980 }
3981 }
3982
3983 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3984 {
3985 return HAL_ERROR;
3986 }
3987
3988 /* Update the HRTIM registers except LOCK bit */
3989 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3990 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3991
3992 /* Update the HRTIM registers LOCK bit */
3993 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3994 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3995
3996 hhrtim->State = HAL_HRTIM_STATE_READY;
3997
3998 /* Process Unlocked */
3999 __HAL_UNLOCK(hhrtim);
4000
4001 return HAL_OK;
4002 }
4003
4004 /**
4005 * @brief Configure the fault conditioning block prescaler
4006 * @param hhrtim pointer to HAL HRTIM handle
4007 * @param Prescaler Prescaler value
4008 * This parameter can be one of the following values:
4009 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
4010 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
4011 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
4012 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
4013 * @retval HAL status
4014 * @note This function must be called before starting the timer and before
4015 * enabling faults inputs
4016 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)4017 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
4018 uint32_t Prescaler)
4019 {
4020 /* Check parameters */
4021 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
4022
4023 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4024 {
4025 return HAL_BUSY;
4026 }
4027
4028 /* Process Locked */
4029 __HAL_LOCK(hhrtim);
4030
4031 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4032
4033 /* Set the external event prescaler */
4034 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
4035
4036 hhrtim->State = HAL_HRTIM_STATE_READY;
4037
4038 /* Process Unlocked */
4039 __HAL_UNLOCK(hhrtim);
4040
4041 return HAL_OK;
4042 }
4043
4044 /**
4045 * @brief Enable or disables the HRTIMx Fault mode.
4046 * @param hhrtim pointer to HAL HRTIM handle
4047 * @param Faults fault input(s) to enable or disable
4048 * This parameter can be any combination of the following values:
4049 * @arg HRTIM_FAULT_1: Fault input 1
4050 * @arg HRTIM_FAULT_2: Fault input 2
4051 * @arg HRTIM_FAULT_3: Fault input 3
4052 * @arg HRTIM_FAULT_4: Fault input 4
4053 * @arg HRTIM_FAULT_5: Fault input 5
4054 * @param Enable Fault(s) enabling
4055 * This parameter can be one of the following values:
4056 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
4057 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
4058 * @retval None
4059 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)4060 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
4061 uint32_t Faults,
4062 uint32_t Enable)
4063 {
4064 /* Check parameters */
4065 assert_param(IS_HRTIM_FAULT(Faults));
4066 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
4067
4068 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
4069 {
4070 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
4071 }
4072 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
4073 {
4074 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
4075 }
4076 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
4077 {
4078 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
4079 }
4080 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
4081 {
4082 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
4083 }
4084 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
4085 {
4086 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
4087 }
4088 }
4089
4090 /**
4091 * @brief Configure both the ADC trigger register update source and the ADC
4092 * trigger source.
4093 * @param hhrtim pointer to HAL HRTIM handle
4094 * @param ADCTrigger ADC trigger to configure
4095 * This parameter can be one of the following values:
4096 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4097 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4098 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4099 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4100 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
4101 * @retval HAL status
4102 * @note This function must be called before starting the timer
4103 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,const HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)4104 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
4105 uint32_t ADCTrigger,
4106 const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
4107 {
4108 uint32_t hrtim_cr1;
4109
4110 /* Check parameters */
4111 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4112 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
4113
4114 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4115 {
4116 return HAL_BUSY;
4117 }
4118
4119 /* Process Locked */
4120 __HAL_LOCK(hhrtim);
4121
4122 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4123
4124 /* Set the ADC trigger update source */
4125 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
4126
4127 switch (ADCTrigger)
4128 {
4129 case HRTIM_ADCTRIGGER_1:
4130 {
4131 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
4132 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
4133
4134 /* Set the ADC trigger 1 source */
4135 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
4136 break;
4137 }
4138
4139 case HRTIM_ADCTRIGGER_2:
4140 {
4141 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
4142 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4143
4144 /* Set the ADC trigger 2 source */
4145 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4146 break;
4147 }
4148
4149 case HRTIM_ADCTRIGGER_3:
4150 {
4151 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4152 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4153
4154 /* Set the ADC trigger 3 source */
4155 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4156 break;
4157 }
4158
4159 case HRTIM_ADCTRIGGER_4:
4160 {
4161 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4162 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4163
4164 /* Set the ADC trigger 4 source */
4165 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4166 break;
4167 }
4168
4169 default:
4170 {
4171 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4172
4173 /* Process Unlocked */
4174 __HAL_UNLOCK(hhrtim);
4175
4176 break;
4177 }
4178 }
4179
4180 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4181 {
4182 return HAL_ERROR;
4183 }
4184
4185 /* Update the HRTIM registers */
4186 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4187
4188 hhrtim->State = HAL_HRTIM_STATE_READY;
4189
4190 /* Process Unlocked */
4191 __HAL_UNLOCK(hhrtim);
4192
4193 return HAL_OK;
4194 }
4195
4196
4197 /**
4198 * @}
4199 */
4200
4201 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4202 * @brief HRTIM timer configuration and control functions
4203 @verbatim
4204 ===============================================================================
4205 ##### HRTIM timer configuration and control functions #####
4206 ===============================================================================
4207 [..] This section provides functions used to configure and control a
4208 HRTIM timer operating in waveform mode:
4209 (+) Configure HRTIM timer general behavior
4210 (+) Configure HRTIM timer event filtering
4211 (+) Configure HRTIM timer deadtime insertion
4212 (+) Configure HRTIM timer chopper mode
4213 (+) Configure HRTIM timer burst DMA
4214 (+) Configure HRTIM timer compare unit
4215 (+) Configure HRTIM timer capture unit
4216 (+) Configure HRTIM timer output
4217 (+) Set HRTIM timer output level
4218 (+) Enable HRTIM timer output
4219 (+) Disable HRTIM timer output
4220 (+) Start HRTIM timer
4221 (+) Stop HRTIM timer
4222 (+) Start HRTIM timer and enable interrupt
4223 (+) Stop HRTIM timer and disable interrupt
4224 (+) Start HRTIM timer and enable DMA transfer
4225 (+) Stop HRTIM timer and disable DMA transfer
4226 (+) Enable or disable the burst mode controller
4227 (+) Start the burst mode controller (by software)
4228 (+) Trigger a Capture (by software)
4229 (+) Update the HRTIM timer preloadable registers (by software)
4230 (+) Reset the HRTIM timer counter (by software)
4231 (+) Start a burst DMA transfer
4232 (+) Enable timer register update
4233 (+) Disable timer register update
4234
4235 @endverbatim
4236 * @{
4237 */
4238
4239 /**
4240 * @brief Configure the general behavior of a timer operating in waveform mode
4241 * @param hhrtim pointer to HAL HRTIM handle
4242 * @param TimerIdx Timer index
4243 * This parameter can be one of the following values:
4244 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4245 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4246 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4247 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4248 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4249 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4250 * @param pTimerCfg pointer to the timer configuration structure
4251 * @note When the timer operates in waveform mode, all the features supported by
4252 * the HRTIM are available without any limitation.
4253 * @retval HAL status
4254 * @note This function must be called before starting the timer
4255 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)4256 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4257 uint32_t TimerIdx,
4258 const HRTIM_TimerCfgTypeDef * pTimerCfg)
4259 {
4260 /* Check parameters */
4261 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4262
4263 /* Relevant for all HRTIM timers, including the master */
4264 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4265 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4266 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4267 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4268 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4269 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4270 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4271
4272 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4273 {
4274 return HAL_BUSY;
4275 }
4276
4277 /* Process Locked */
4278 __HAL_LOCK(hhrtim);
4279
4280 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4281
4282 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4283 {
4284 /* Check parameters */
4285 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4286 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4287 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4288
4289 /* Configure master timer */
4290 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4291 }
4292 else
4293 {
4294 /* Check parameters */
4295 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4296 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4297 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4298 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4299 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4300 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4301 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4302 pTimerCfg->DeadTimeInsertion));
4303 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4304 pTimerCfg->DelayedProtectionMode));
4305 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4306 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4307 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4308
4309 /* Configure timing unit */
4310 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4311 }
4312
4313 /* Update timer parameters */
4314 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4315 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4316 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4317 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4318 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4319
4320 /* Force a software update */
4321 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4322
4323 hhrtim->State = HAL_HRTIM_STATE_READY;
4324
4325 /* Process Unlocked */
4326 __HAL_UNLOCK(hhrtim);
4327
4328 return HAL_OK;
4329 }
4330
4331 /**
4332 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
4333 * @param hhrtim pointer to HAL HRTIM handle
4334 * @param TimerIdx Timer index
4335 * This parameter can be one of the following values:
4336 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4337 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4338 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4339 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4340 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4341 * @param Event external event for which timer event filtering must be configured
4342 * This parameter can be one of the following values:
4343 * @arg HRTIM_EVENT_1: External event 1
4344 * @arg HRTIM_EVENT_2: External event 2
4345 * @arg HRTIM_EVENT_3: External event 3
4346 * @arg HRTIM_EVENT_4: External event 4
4347 * @arg HRTIM_EVENT_5: External event 5
4348 * @arg HRTIM_EVENT_6: External event 6
4349 * @arg HRTIM_EVENT_7: External event 7
4350 * @arg HRTIM_EVENT_8: External event 8
4351 * @arg HRTIM_EVENT_9: External event 9
4352 * @arg HRTIM_EVENT_10: External event 10
4353 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
4354 * @note This function must be called before starting the timer
4355 * @retval HAL status
4356 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)4357 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
4358 uint32_t TimerIdx,
4359 uint32_t Event,
4360 const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4361 {
4362 /* Check parameters */
4363 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4364 assert_param(IS_HRTIM_EVENT(Event));
4365 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4366
4367 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4368
4369 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4370 {
4371 return HAL_BUSY;
4372 }
4373
4374 /* Process Locked */
4375 __HAL_LOCK(hhrtim);
4376
4377 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4378
4379 /* Configure timer event filtering capabilities */
4380 switch (Event)
4381 {
4382 case HRTIM_EVENT_NONE:
4383 {
4384 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4385 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4386 break;
4387 }
4388
4389 case HRTIM_EVENT_1:
4390 {
4391 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4392 break;
4393 }
4394
4395 case HRTIM_EVENT_2:
4396 {
4397 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4398 break;
4399 }
4400
4401 case HRTIM_EVENT_3:
4402 {
4403 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4404 break;
4405 }
4406
4407 case HRTIM_EVENT_4:
4408 {
4409 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4410 break;
4411 }
4412
4413 case HRTIM_EVENT_5:
4414 {
4415 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4416 break;
4417 }
4418
4419 case HRTIM_EVENT_6:
4420 {
4421 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
4422 break;
4423 }
4424
4425 case HRTIM_EVENT_7:
4426 {
4427 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
4428 break;
4429 }
4430
4431 case HRTIM_EVENT_8:
4432 {
4433 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
4434 break;
4435 }
4436
4437 case HRTIM_EVENT_9:
4438 {
4439 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
4440 break;
4441 }
4442
4443 case HRTIM_EVENT_10:
4444 {
4445 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
4446 break;
4447 }
4448
4449 default:
4450 {
4451 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4452
4453 /* Process Unlocked */
4454 __HAL_UNLOCK(hhrtim);
4455
4456 break;
4457 }
4458 }
4459
4460 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4461 {
4462 return HAL_ERROR;
4463 }
4464
4465 hhrtim->State = HAL_HRTIM_STATE_READY;
4466
4467 /* Process Unlocked */
4468 __HAL_UNLOCK(hhrtim);
4469
4470 return HAL_OK;
4471 }
4472
4473 /**
4474 * @brief Configure the dead-time insertion feature for a timer
4475 * @param hhrtim pointer to HAL HRTIM handle
4476 * @param TimerIdx Timer index
4477 * This parameter can be one of the following values:
4478 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4479 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4480 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4481 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4482 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4483 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4484 * @retval HAL status
4485 * @note This function must be called before starting the timer
4486 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)4487 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4488 uint32_t TimerIdx,
4489 const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4490 {
4491 uint32_t hrtim_dtr;
4492
4493 /* Check parameters */
4494 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4495 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4496 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4497 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4498 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4499 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4500 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4501 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4502
4503 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4504 {
4505 return HAL_BUSY;
4506 }
4507
4508 /* Process Locked */
4509 __HAL_LOCK(hhrtim);
4510
4511 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4512
4513 /* Set timer deadtime configuration */
4514 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4515 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4516 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4517 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4518 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4519 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4520 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4521 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4522 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4523
4524 /* Update the HRTIM registers */
4525 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4526 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4527 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4528 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4529
4530 hhrtim->State = HAL_HRTIM_STATE_READY;
4531
4532 /* Process Unlocked */
4533 __HAL_UNLOCK(hhrtim);
4534
4535 return HAL_OK;
4536 }
4537
4538 /**
4539 * @brief Configure the chopper mode feature for a timer
4540 * @param hhrtim pointer to HAL HRTIM handle
4541 * @param TimerIdx Timer index
4542 * This parameter can be one of the following values:
4543 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4544 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4545 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4546 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4547 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4548 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4549 * @retval HAL status
4550 * @note This function must be called before configuring the timer output(s)
4551 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)4552 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4553 uint32_t TimerIdx,
4554 const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4555 {
4556 uint32_t hrtim_chpr;
4557
4558 /* Check parameters */
4559 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4560 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4561 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4562 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4563
4564 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4565 {
4566 return HAL_BUSY;
4567 }
4568
4569 /* Process Locked */
4570 __HAL_LOCK(hhrtim);
4571
4572 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4573
4574 /* Set timer choppe mode configuration */
4575 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4576 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4577 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4578
4579 /* Update the HRTIM registers */
4580 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
4581 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
4582 hrtim_chpr);
4583
4584 hhrtim->State = HAL_HRTIM_STATE_READY;
4585
4586 /* Process Unlocked */
4587 __HAL_UNLOCK(hhrtim);
4588
4589 return HAL_OK;
4590 }
4591
4592 /**
4593 * @brief Configure the burst DMA controller for a timer
4594 * @param hhrtim pointer to HAL HRTIM handle
4595 * @param TimerIdx Timer index
4596 * This parameter can be one of the following values:
4597 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4598 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4599 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4600 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4601 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4602 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4603 * @param RegistersToUpdate registers to be written by DMA
4604 * This parameter can be any combination of the following values:
4605 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4606 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4607 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4608 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4609 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4610 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4611 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4612 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4613 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4614 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4615 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4616 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4617 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4618 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4619 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4620 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4621 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4622 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4623 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4624 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4625 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4626 * @retval HAL status
4627 * @note This function must be called before starting the timer
4628 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)4629 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4630 uint32_t TimerIdx,
4631 uint32_t RegistersToUpdate)
4632 {
4633 /* Check parameters */
4634 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4635
4636 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4637 {
4638 return HAL_BUSY;
4639 }
4640
4641 /* Process Locked */
4642 __HAL_LOCK(hhrtim);
4643
4644 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4645
4646 /* Set the burst DMA timer update register */
4647 switch (TimerIdx)
4648 {
4649 case HRTIM_TIMERINDEX_TIMER_A:
4650 {
4651 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4652 break;
4653 }
4654
4655 case HRTIM_TIMERINDEX_TIMER_B:
4656 {
4657 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4658 break;
4659 }
4660
4661 case HRTIM_TIMERINDEX_TIMER_C:
4662 {
4663 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4664 break;
4665 }
4666
4667 case HRTIM_TIMERINDEX_TIMER_D:
4668 {
4669 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4670 break;
4671 }
4672
4673 case HRTIM_TIMERINDEX_TIMER_E:
4674 {
4675 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4676 break;
4677 }
4678
4679 case HRTIM_TIMERINDEX_MASTER:
4680 {
4681 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4682 break;
4683 }
4684
4685 default:
4686 {
4687 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4688
4689 /* Process Unlocked */
4690 __HAL_UNLOCK(hhrtim);
4691
4692 break;
4693 }
4694 }
4695
4696 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4697 {
4698 return HAL_ERROR;
4699 }
4700
4701 hhrtim->State = HAL_HRTIM_STATE_READY;
4702
4703 /* Process Unlocked */
4704 __HAL_UNLOCK(hhrtim);
4705
4706 return HAL_OK;
4707 }
4708
4709 /**
4710 * @brief Configure the compare unit of a timer operating in waveform mode
4711 * @param hhrtim pointer to HAL HRTIM handle
4712 * @param TimerIdx Timer index
4713 * This parameter can be one of the following values:
4714 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4715 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4716 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4717 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4718 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4719 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4720 * @param CompareUnit Compare unit to configure
4721 * This parameter can be one of the following values:
4722 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4723 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4724 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4725 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4726 * @param pCompareCfg pointer to the compare unit configuration structure
4727 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4728 * application has to configure separately the capture unit. Capture unit
4729 * to configure in that case depends on the compare unit auto delayed mode
4730 * is applied to (see below):
4731 * Auto delayed on output compare 2: capture unit 1 must be configured
4732 * Auto delayed on output compare 4: capture unit 2 must be configured
4733 * @retval HAL status
4734 * @note This function must be called before starting the timer
4735 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,const HRTIM_CompareCfgTypeDef * pCompareCfg)4736 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4737 uint32_t TimerIdx,
4738 uint32_t CompareUnit,
4739 const HRTIM_CompareCfgTypeDef* pCompareCfg)
4740 {
4741 /* Check parameters */
4742 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4743
4744 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4745 {
4746 return HAL_BUSY;
4747 }
4748
4749 /* Process Locked */
4750 __HAL_LOCK(hhrtim);
4751
4752 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4753
4754 /* Configure the compare unit */
4755 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4756 {
4757 switch (CompareUnit)
4758 {
4759 case HRTIM_COMPAREUNIT_1:
4760 {
4761 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4762 break;
4763 }
4764
4765 case HRTIM_COMPAREUNIT_2:
4766 {
4767 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4768 break;
4769 }
4770
4771 case HRTIM_COMPAREUNIT_3:
4772 {
4773 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4774 break;
4775 }
4776
4777 case HRTIM_COMPAREUNIT_4:
4778 {
4779 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4780 break;
4781 }
4782
4783 default:
4784 {
4785 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4786
4787 /* Process Unlocked */
4788 __HAL_UNLOCK(hhrtim);
4789
4790 break;
4791 }
4792 }
4793
4794 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4795 {
4796 return HAL_ERROR;
4797 }
4798
4799 }
4800 else
4801 {
4802 switch (CompareUnit)
4803 {
4804 case HRTIM_COMPAREUNIT_1:
4805 {
4806 /* Set the compare value */
4807 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4808 break;
4809 }
4810
4811 case HRTIM_COMPAREUNIT_2:
4812 {
4813 /* Check parameters */
4814 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4815
4816 /* Set the compare value */
4817 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4818
4819 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4820 {
4821 /* Configure auto-delayed mode */
4822 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4823 /* to the other to reinitialize properly the auto-delayed mechanism */
4824 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4825 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4826
4827 /* Set the compare value for timeout compare unit (if any) */
4828 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4829 {
4830 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4831 }
4832 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4833 {
4834 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4835 }
4836 else
4837 {
4838 /* nothing to do */
4839 }
4840 }
4841 else
4842 {
4843 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
4844 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4845 }
4846 break;
4847 }
4848
4849 case HRTIM_COMPAREUNIT_3:
4850 {
4851 /* Set the compare value */
4852 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4853 break;
4854 }
4855
4856 case HRTIM_COMPAREUNIT_4:
4857 {
4858 /* Check parameters */
4859 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4860
4861 /* Set the compare value */
4862 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4863
4864 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4865 {
4866 /* Configure auto-delayed mode */
4867 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4868 /* to the other to reinitialize properly the auto-delayed mechanism */
4869 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4870 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4871
4872 /* Set the compare value for timeout compare unit (if any) */
4873 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4874 {
4875 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4876 }
4877 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4878 {
4879 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4880 }
4881 else
4882 {
4883 /* nothing to do */
4884 }
4885 }
4886 else
4887 {
4888 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
4889 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4890 }
4891 break;
4892 }
4893
4894 default:
4895 {
4896 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4897
4898 /* Process Unlocked */
4899 __HAL_UNLOCK(hhrtim);
4900
4901 break;
4902 }
4903 }
4904
4905 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4906 {
4907 return HAL_ERROR;
4908 }
4909
4910 }
4911 hhrtim->State = HAL_HRTIM_STATE_READY;
4912
4913 /* Process Unlocked */
4914 __HAL_UNLOCK(hhrtim);
4915
4916 return HAL_OK;
4917 }
4918
4919 /**
4920 * @brief Configure the capture unit of a timer operating in waveform mode
4921 * @param hhrtim pointer to HAL HRTIM handle
4922 * @param TimerIdx Timer index
4923 * This parameter can be one of the following values:
4924 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4925 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4926 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4927 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4928 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4929 * @param CaptureUnit Capture unit to configure
4930 * This parameter can be one of the following values:
4931 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4932 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4933 * @param pCaptureCfg pointer to the compare unit configuration structure
4934 * @retval HAL status
4935 * @note This function must be called before starting the timer
4936 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,const HRTIM_CaptureCfgTypeDef * pCaptureCfg)4937 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4938 uint32_t TimerIdx,
4939 uint32_t CaptureUnit,
4940 const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4941 {
4942 /* Check parameters */
4943 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4944
4945
4946 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4947 {
4948 return HAL_BUSY;
4949 }
4950
4951 /* Process Locked */
4952 __HAL_LOCK(hhrtim);
4953
4954 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4955
4956 /* Configure the capture unit */
4957 switch (CaptureUnit)
4958 {
4959 case HRTIM_CAPTUREUNIT_1:
4960 {
4961 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4962 break;
4963 }
4964
4965 case HRTIM_CAPTUREUNIT_2:
4966 {
4967 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4968 break;
4969 }
4970
4971 default:
4972 {
4973 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4974
4975 /* Process Unlocked */
4976 __HAL_UNLOCK(hhrtim);
4977
4978 break;
4979 }
4980 }
4981
4982 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4983 {
4984 return HAL_ERROR;
4985 }
4986
4987
4988 hhrtim->State = HAL_HRTIM_STATE_READY;
4989
4990 /* Process Unlocked */
4991 __HAL_UNLOCK(hhrtim);
4992
4993 return HAL_OK;
4994 }
4995
4996 /**
4997 * @brief Configure the output of a timer operating in waveform mode
4998 * @param hhrtim pointer to HAL HRTIM handle
4999 * @param TimerIdx Timer index
5000 * This parameter can be one of the following values:
5001 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5002 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5003 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5004 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5005 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5006 * @param Output Timer output
5007 * This parameter can be one of the following values:
5008 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5009 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5010 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5011 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5012 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5013 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5014 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5015 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5016 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5017 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5018 * @param pOutputCfg pointer to the timer output configuration structure
5019 * @retval HAL status
5020 * @note This function must be called before configuring the timer and after
5021 * configuring the deadtime insertion feature (if required).
5022 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)5023 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
5024 uint32_t TimerIdx,
5025 uint32_t Output,
5026 const HRTIM_OutputCfgTypeDef * pOutputCfg)
5027 {
5028 /* Check parameters */
5029 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5030 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
5031 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
5032 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
5033 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
5034 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
5035 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
5036
5037 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5038 {
5039 return HAL_BUSY;
5040 }
5041
5042 /* Process Locked */
5043 __HAL_LOCK(hhrtim);
5044
5045 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5046
5047 /* Configure the timer output */
5048 HRTIM_OutputConfig(hhrtim,
5049 TimerIdx,
5050 Output,
5051 pOutputCfg);
5052
5053 hhrtim->State = HAL_HRTIM_STATE_READY;
5054
5055 /* Process Unlocked */
5056 __HAL_UNLOCK(hhrtim);
5057
5058 return HAL_OK;
5059 }
5060
5061 /**
5062 * @brief Force the timer output to its active or inactive state
5063 * @param hhrtim pointer to HAL HRTIM handle
5064 * @param TimerIdx Timer index
5065 * This parameter can be one of the following values:
5066 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5067 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5068 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5069 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5070 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5071 * @param Output Timer output
5072 * This parameter can be one of the following values:
5073 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5074 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5075 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5076 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5077 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5078 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5079 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5080 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5081 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5082 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5083 * @param OutputLevel indicates whether the output is forced to its active or inactive level
5084 * This parameter can be one of the following values:
5085 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
5086 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
5087 * @retval HAL status
5088 * @note The 'software set/reset trigger' bit in the output set/reset registers
5089 * is automatically reset by hardware
5090 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)5091 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
5092 uint32_t TimerIdx,
5093 uint32_t Output,
5094 uint32_t OutputLevel)
5095 {
5096 /* Check parameters */
5097 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5098 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
5099
5100 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5101 {
5102 return HAL_BUSY;
5103 }
5104
5105 /* Process Locked */
5106 __HAL_LOCK(hhrtim);
5107
5108 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5109
5110 /* Force timer output level */
5111 switch (Output)
5112 {
5113 case HRTIM_OUTPUT_TA1:
5114 case HRTIM_OUTPUT_TB1:
5115 case HRTIM_OUTPUT_TC1:
5116 case HRTIM_OUTPUT_TD1:
5117 case HRTIM_OUTPUT_TE1:
5118 {
5119 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
5120 {
5121 /* Force output to its active state */
5122 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
5123 }
5124 else
5125 {
5126 /* Force output to its inactive state */
5127 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
5128 }
5129 break;
5130 }
5131
5132 case HRTIM_OUTPUT_TA2:
5133 case HRTIM_OUTPUT_TB2:
5134 case HRTIM_OUTPUT_TC2:
5135 case HRTIM_OUTPUT_TD2:
5136 case HRTIM_OUTPUT_TE2:
5137 {
5138 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
5139 {
5140 /* Force output to its active state */
5141 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
5142 }
5143 else
5144 {
5145 /* Force output to its inactive state */
5146 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
5147 }
5148 break;
5149 }
5150
5151 default:
5152 {
5153 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5154
5155 /* Process Unlocked */
5156 __HAL_UNLOCK(hhrtim);
5157
5158 break;
5159 }
5160 }
5161
5162 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5163 {
5164 return HAL_ERROR;
5165 }
5166
5167 hhrtim->State = HAL_HRTIM_STATE_READY;
5168
5169 /* Process Unlocked */
5170 __HAL_UNLOCK(hhrtim);
5171
5172 return HAL_OK;
5173 }
5174
5175 /**
5176 * @brief Enable the generation of the waveform signal on the designated output(s)
5177 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
5178 * @param hhrtim pointer to HAL HRTIM handle
5179 * @param OutputsToStart Timer output(s) to enable
5180 * This parameter can be any combination of the following values:
5181 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5182 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5183 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5184 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5185 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5186 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5187 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5188 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5189 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5190 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5191 * @retval HAL status
5192 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)5193 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
5194 uint32_t OutputsToStart)
5195 {
5196 /* Check the parameters */
5197 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5198
5199 /* Process Locked */
5200 __HAL_LOCK(hhrtim);
5201
5202 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5203
5204 /* Enable the HRTIM outputs */
5205 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5206
5207 hhrtim->State = HAL_HRTIM_STATE_READY;
5208
5209 /* Process Unlocked */
5210 __HAL_UNLOCK(hhrtim);
5211
5212 return HAL_OK;
5213 }
5214
5215 /**
5216 * @brief Disable the generation of the waveform signal on the designated output(s)
5217 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
5218 * @param hhrtim pointer to HAL HRTIM handle
5219 * @param OutputsToStop Timer output(s) to disable
5220 * This parameter can be any combination of the following values:
5221 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5222 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5223 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5224 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5225 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5226 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5227 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5228 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5229 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5230 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5231 * @retval HAL status
5232 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)5233 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
5234 uint32_t OutputsToStop)
5235 {
5236 /* Check the parameters */
5237 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5238
5239 /* Process Locked */
5240 __HAL_LOCK(hhrtim);
5241
5242 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5243
5244 /* Enable the HRTIM outputs */
5245 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5246
5247 hhrtim->State = HAL_HRTIM_STATE_READY;
5248
5249 /* Process Unlocked */
5250 __HAL_UNLOCK(hhrtim);
5251
5252 return HAL_OK;
5253 }
5254
5255 /**
5256 * @brief Start the counter of the designated timer(s) operating in waveform mode
5257 * Timers can be combined (ORed) to allow for simultaneous counter start.
5258 * @param hhrtim pointer to HAL HRTIM handle
5259 * @param Timers Timer counter(s) to start
5260 * This parameter can be any combination of the following values:
5261 * @arg HRTIM_TIMERID_MASTER
5262 * @arg HRTIM_TIMERID_TIMER_A
5263 * @arg HRTIM_TIMERID_TIMER_B
5264 * @arg HRTIM_TIMERID_TIMER_C
5265 * @arg HRTIM_TIMERID_TIMER_D
5266 * @arg HRTIM_TIMERID_TIMER_E
5267 * @retval HAL status
5268 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5269 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
5270 uint32_t Timers)
5271 {
5272 /* Check the parameters */
5273 assert_param(IS_HRTIM_TIMERID(Timers));
5274
5275 /* Process Locked */
5276 __HAL_LOCK(hhrtim);
5277
5278 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5279
5280 /* Enable timer(s) counter */
5281 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5282
5283 hhrtim->State = HAL_HRTIM_STATE_READY;
5284
5285 /* Process Unlocked */
5286 __HAL_UNLOCK(hhrtim);
5287
5288 return HAL_OK;
5289 }
5290
5291 /**
5292 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5293 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5294 * @param hhrtim pointer to HAL HRTIM handle
5295 * @param Timers Timer counter(s) to stop
5296 * This parameter can be any combination of the following values:
5297 * @arg HRTIM_TIMERID_MASTER
5298 * @arg HRTIM_TIMERID_TIMER_A
5299 * @arg HRTIM_TIMERID_TIMER_B
5300 * @arg HRTIM_TIMERID_TIMER_C
5301 * @arg HRTIM_TIMERID_TIMER_D
5302 * @arg HRTIM_TIMERID_TIMER_E
5303 * @retval HAL status
5304 * @note The counter of a timer is stopped only if all timer outputs are disabled
5305 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5306 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
5307 uint32_t Timers)
5308 {
5309 /* Check the parameters */
5310 assert_param(IS_HRTIM_TIMERID(Timers));
5311
5312 /* Process Locked */
5313 __HAL_LOCK(hhrtim);
5314
5315 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5316
5317 /* Disable timer(s) counter */
5318 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5319
5320 hhrtim->State = HAL_HRTIM_STATE_READY;
5321
5322 /* Process Unlocked */
5323 __HAL_UNLOCK(hhrtim);
5324
5325 return HAL_OK;
5326 }
5327
5328 /**
5329 * @brief Start the counter of the designated timer(s) operating in waveform mode
5330 * Timers can be combined (ORed) to allow for simultaneous counter start.
5331 * @param hhrtim pointer to HAL HRTIM handle
5332 * @param Timers Timer counter(s) to start
5333 * This parameter can be any combination of the following values:
5334 * @arg HRTIM_TIMERID_MASTER
5335 * @arg HRTIM_TIMERID_TIMER_A
5336 * @arg HRTIM_TIMERID_TIMER_B
5337 * @arg HRTIM_TIMERID_TIMER_C
5338 * @arg HRTIM_TIMERID_TIMER_D
5339 * @arg HRTIM_TIMERID_TIMER_E
5340 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
5341 * to the timers to start are enabled within this function.
5342 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
5343 * function.
5344 * @retval HAL status
5345 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5346 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
5347 uint32_t Timers)
5348 {
5349 uint8_t timer_idx;
5350
5351 /* Check the parameters */
5352 assert_param(IS_HRTIM_TIMERID(Timers));
5353
5354 /* Process Locked */
5355 __HAL_LOCK(hhrtim);
5356
5357 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5358
5359 /* Enable HRTIM interrupts (if required) */
5360 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5361
5362 /* Enable master timer related interrupts (if required) */
5363 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5364 {
5365 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5366 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5367 }
5368
5369 /* Enable timing unit related interrupts (if required) */
5370 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5371 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5372 timer_idx++)
5373 {
5374 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5375 {
5376 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5377 timer_idx,
5378 hhrtim->TimerParam[timer_idx].InterruptRequests);
5379 }
5380 }
5381
5382 /* Enable timer(s) counter */
5383 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5384
5385 hhrtim->State = HAL_HRTIM_STATE_READY;
5386
5387 /* Process Unlocked */
5388 __HAL_UNLOCK(hhrtim);
5389
5390 return HAL_OK;}
5391
5392 /**
5393 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5394 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5395 * @param hhrtim pointer to HAL HRTIM handle
5396 * @param Timers Timer counter(s) to stop
5397 * This parameter can be any combination of the following values:
5398 * @arg HRTIM_TIMERID_MASTER
5399 * @arg HRTIM_TIMERID_TIMER_A
5400 * @arg HRTIM_TIMERID_TIMER_B
5401 * @arg HRTIM_TIMERID_TIMER_C
5402 * @arg HRTIM_TIMERID_TIMER_D
5403 * @arg HRTIM_TIMERID_TIMER_E
5404 * @retval HAL status
5405 * @note The counter of a timer is stopped only if all timer outputs are disabled
5406 * @note All enabled timer related interrupts are disabled.
5407 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5408 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
5409 uint32_t Timers)
5410 {
5411 /* ++ WA */
5412 __IO uint32_t delai = (uint32_t)(0x17FU);
5413 /* -- WA */
5414
5415 uint8_t timer_idx;
5416
5417 /* Check the parameters */
5418 assert_param(IS_HRTIM_TIMERID(Timers));
5419
5420 /* Process Locked */
5421 __HAL_LOCK(hhrtim);
5422
5423 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5424
5425 /* Disable HRTIM interrupts (if required) */
5426 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
5427
5428 /* Disable master timer related interrupts (if required) */
5429 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5430 {
5431 /* Interrupts enable flag must be cleared one by one */
5432 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5433 }
5434
5435 /* Disable timing unit related interrupts (if required) */
5436 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5437 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5438 timer_idx++)
5439 {
5440 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5441 {
5442 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5443 }
5444 }
5445
5446 /* ++ WA */
5447 do { delai--; } while (delai != 0U);
5448 /* -- WA */
5449
5450 /* Disable timer(s) counter */
5451 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5452
5453 hhrtim->State = HAL_HRTIM_STATE_READY;
5454
5455 /* Process Unlocked */
5456 __HAL_UNLOCK(hhrtim);
5457
5458 return HAL_OK;
5459 }
5460
5461 /**
5462 * @brief Start the counter of the designated timer(s) operating in waveform mode
5463 * Timers can be combined (ORed) to allow for simultaneous counter start.
5464 * @param hhrtim pointer to HAL HRTIM handle
5465 * @param Timers Timer counter(s) to start
5466 * This parameter can be any combination of the following values:
5467 * @arg HRTIM_TIMERID_MASTER
5468 * @arg HRTIM_TIMERID_TIMER_A
5469 * @arg HRTIM_TIMERID_TIMER_B
5470 * @arg HRTIM_TIMERID_TIMER_C
5471 * @arg HRTIM_TIMERID_TIMER_D
5472 * @arg HRTIM_TIMERID_TIMER_E
5473 * @retval HAL status
5474 * @note This function enables the dma request(s) mentioned in the timer
5475 * configuration data structure for every timers to start.
5476 * @note The source memory address, the destination memory address and the
5477 * size of each DMA transfer are specified at timer configuration time
5478 * (see HAL_HRTIM_WaveformTimerConfig)
5479 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5480 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5481 uint32_t Timers)
5482 {
5483 uint8_t timer_idx;
5484 DMA_HandleTypeDef * hdma;
5485
5486 /* Check the parameters */
5487 assert_param(IS_HRTIM_TIMERID(Timers));
5488
5489 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5490 {
5491 return HAL_BUSY;
5492 }
5493
5494 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5495
5496 /* Process Locked */
5497 __HAL_LOCK(hhrtim);
5498
5499 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5500 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5501 {
5502 /* Set the DMA error callback */
5503 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5504
5505 /* Set the DMA transfer completed callback */
5506 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5507
5508 /* Enable the DMA channel */
5509 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5510 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5511 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5512 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5513 {
5514 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5515
5516 /* Process Unlocked */
5517 __HAL_UNLOCK(hhrtim);
5518
5519 return HAL_ERROR;
5520 }
5521
5522 /* Enable the timer DMA request */
5523 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5524 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5525 }
5526
5527 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5528 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5529 timer_idx++)
5530 {
5531 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5532 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5533 {
5534 /* Get the timer DMA handler */
5535 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5536
5537 if (hdma == NULL)
5538 {
5539 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5540
5541 /* Process Unlocked */
5542 __HAL_UNLOCK(hhrtim);
5543
5544 return HAL_ERROR;
5545 }
5546
5547 /* Set the DMA error callback */
5548 hdma->XferErrorCallback = HRTIM_DMAError ;
5549
5550 /* Set the DMA transfer completed callback */
5551 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5552
5553 /* Enable the DMA channel */
5554 if (HAL_DMA_Start_IT(hdma,
5555 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5556 hhrtim->TimerParam[timer_idx].DMADstAddress,
5557 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5558 {
5559 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5560
5561 /* Process Unlocked */
5562 __HAL_UNLOCK(hhrtim);
5563
5564 return HAL_ERROR;
5565 }
5566
5567 /* Enable the timer DMA request */
5568 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5569 timer_idx,
5570 hhrtim->TimerParam[timer_idx].DMARequests);
5571 }
5572 }
5573
5574 /* Enable the timer counter */
5575 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5576
5577 hhrtim->State = HAL_HRTIM_STATE_READY;
5578
5579 /* Process Unlocked */
5580 __HAL_UNLOCK(hhrtim);
5581
5582 return HAL_OK;
5583 }
5584
5585 /**
5586 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5587 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5588 * @param hhrtim pointer to HAL HRTIM handle
5589 * @param Timers Timer counter(s) to stop
5590 * This parameter can be any combination of the following values:
5591 * @arg HRTIM_TIMERID_MASTER
5592 * @arg HRTIM_TIMERID_TIMER_A
5593 * @arg HRTIM_TIMERID_TIMER_B
5594 * @arg HRTIM_TIMERID_TIMER_C
5595 * @arg HRTIM_TIMERID_TIMER_D
5596 * @arg HRTIM_TIMERID_TIMER_E
5597 * @retval HAL status
5598 * @note The counter of a timer is stopped only if all timer outputs are disabled
5599 * @note All enabled timer related DMA requests are disabled.
5600 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5601 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5602 uint32_t Timers)
5603 {
5604 uint8_t timer_idx;
5605
5606 /* Check the parameters */
5607 assert_param(IS_HRTIM_TIMERID(Timers));
5608
5609 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5610
5611 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5612 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5613 {
5614 /* Disable the DMA */
5615 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5616 {
5617 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5618 }
5619 else
5620 {
5621 hhrtim->State = HAL_HRTIM_STATE_READY;
5622 /* Disable the DMA request(s) */
5623 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5624 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5625 }
5626 }
5627
5628 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5629 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5630 timer_idx++)
5631 {
5632 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5633 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5634 {
5635 /* Get the timer DMA handler */
5636 /* Disable the DMA */
5637 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5638 {
5639 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5640 }
5641 else
5642 {
5643 hhrtim->State = HAL_HRTIM_STATE_READY;
5644
5645 /* Disable the DMA request(s) */
5646 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5647 timer_idx,
5648 hhrtim->TimerParam[timer_idx].DMARequests);
5649 }
5650 }
5651 }
5652
5653 /* Disable the timer counter */
5654 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5655
5656 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5657 {
5658 return HAL_ERROR;
5659 }
5660 else
5661 {
5662 return HAL_OK;
5663 }
5664 }
5665
5666 /**
5667 * @brief Enable or disables the HRTIM burst mode controller.
5668 * @param hhrtim pointer to HAL HRTIM handle
5669 * @param Enable Burst mode controller enabling
5670 * This parameter can be one of the following values:
5671 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5672 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5673 * @retval HAL status
5674 * @note This function must be called after starting the timer(s)
5675 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)5676 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5677 uint32_t Enable)
5678 {
5679 /* Check parameters */
5680 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5681
5682 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5683 {
5684 return HAL_BUSY;
5685 }
5686
5687 /* Process Locked */
5688 __HAL_LOCK(hhrtim);
5689
5690 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5691
5692 /* Enable/Disable the burst mode controller */
5693 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5694
5695 hhrtim->State = HAL_HRTIM_STATE_READY;
5696
5697 /* Process Unlocked */
5698 __HAL_UNLOCK(hhrtim);
5699
5700 return HAL_OK;
5701 }
5702
5703 /**
5704 * @brief Trig the burst mode operation.
5705 * @param hhrtim pointer to HAL HRTIM handle
5706 * @retval HAL status
5707 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)5708 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5709 {
5710 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5711 {
5712 return HAL_BUSY;
5713 }
5714
5715 /* Process Locked */
5716 __HAL_LOCK(hhrtim);
5717
5718 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5719
5720 /* Software trigger of the burst mode controller */
5721 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5722
5723 hhrtim->State = HAL_HRTIM_STATE_READY;
5724
5725 /* Process Unlocked */
5726 __HAL_UNLOCK(hhrtim);
5727
5728 return HAL_OK;
5729 }
5730
5731 /**
5732 * @brief Trig a software capture on the designed capture unit
5733 * @param hhrtim pointer to HAL HRTIM handle
5734 * @param TimerIdx Timer index
5735 * This parameter can be one of the following values:
5736 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5737 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5738 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5739 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5740 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5741 * @param CaptureUnit Capture unit to trig
5742 * This parameter can be one of the following values:
5743 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5744 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5745 * @retval HAL status
5746 * @note The 'software capture' bit in the capure configuration register is
5747 * automatically reset by hardware
5748 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5749 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5750 uint32_t TimerIdx,
5751 uint32_t CaptureUnit)
5752 {
5753 /* Check parameters */
5754 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5755 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5756
5757 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5758 {
5759 return HAL_BUSY;
5760 }
5761
5762 /* Process Locked */
5763 __HAL_LOCK(hhrtim);
5764
5765 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5766
5767 /* Force a software capture on concerned capture unit */
5768 switch (CaptureUnit)
5769 {
5770 case HRTIM_CAPTUREUNIT_1:
5771 {
5772 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5773 break;
5774 }
5775
5776 case HRTIM_CAPTUREUNIT_2:
5777 {
5778 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5779 break;
5780 }
5781
5782 default:
5783 {
5784 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5785
5786 /* Process Unlocked */
5787 __HAL_UNLOCK(hhrtim);
5788
5789 break;
5790 }
5791 }
5792
5793 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5794 {
5795 return HAL_ERROR;
5796 }
5797
5798 hhrtim->State = HAL_HRTIM_STATE_READY;
5799
5800 /* Process Unlocked */
5801 __HAL_UNLOCK(hhrtim);
5802
5803 return HAL_OK;
5804 }
5805
5806 /**
5807 * @brief Trig the update of the registers of one or several timers
5808 * @param hhrtim pointer to HAL HRTIM handle
5809 * @param Timers timers concerned with the software register update
5810 * This parameter can be any combination of the following values:
5811 * @arg HRTIM_TIMERUPDATE_MASTER
5812 * @arg HRTIM_TIMERUPDATE_A
5813 * @arg HRTIM_TIMERUPDATE_B
5814 * @arg HRTIM_TIMERUPDATE_C
5815 * @arg HRTIM_TIMERUPDATE_D
5816 * @arg HRTIM_TIMERUPDATE_E
5817 * @retval HAL status
5818 * @note The 'software update' bits in the HRTIM control register 2 register are
5819 * automatically reset by hardware
5820 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5821 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5822 uint32_t Timers)
5823 {
5824 /* Check parameters */
5825 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5826
5827 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5828 {
5829 return HAL_BUSY;
5830 }
5831
5832 /* Process Locked */
5833 __HAL_LOCK(hhrtim);
5834
5835 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5836
5837 /* Force timer(s) registers update */
5838 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5839
5840 hhrtim->State = HAL_HRTIM_STATE_READY;
5841
5842 /* Process Unlocked */
5843 __HAL_UNLOCK(hhrtim);
5844
5845 return HAL_OK;
5846 }
5847
5848 /**
5849 * @brief Trig the reset of one or several timers
5850 * @param hhrtim pointer to HAL HRTIM handle
5851 * @param Timers timers concerned with the software counter reset
5852 * This parameter can be any combination of the following values:
5853 * @arg HRTIM_TIMERRESET_MASTER
5854 * @arg HRTIM_TIMERRESET_TIMER_A
5855 * @arg HRTIM_TIMERRESET_TIMER_B
5856 * @arg HRTIM_TIMERRESET_TIMER_C
5857 * @arg HRTIM_TIMERRESET_TIMER_D
5858 * @arg HRTIM_TIMERRESET_TIMER_E
5859 * @retval HAL status
5860 * @note The 'software reset' bits in the HRTIM control register 2 are
5861 * automatically reset by hardware
5862 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5863 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5864 uint32_t Timers)
5865 {
5866 /* Check parameters */
5867 assert_param(IS_HRTIM_TIMERRESET(Timers));
5868
5869 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5870 {
5871 return HAL_BUSY;
5872 }
5873
5874 /* Process Locked */
5875 __HAL_LOCK(hhrtim);
5876
5877 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5878
5879 /* Force timer(s) registers reset */
5880 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5881
5882 hhrtim->State = HAL_HRTIM_STATE_READY;
5883
5884 /* Process Unlocked */
5885 __HAL_UNLOCK(hhrtim);
5886
5887 return HAL_OK;
5888 }
5889
5890 /**
5891 * @brief Start a burst DMA operation to update HRTIM control registers content
5892 * @param hhrtim pointer to HAL HRTIM handle
5893 * @param TimerIdx Timer index
5894 * This parameter can be one of the following values:
5895 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5896 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5897 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5898 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5899 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5900 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5901 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5902 * content will be updated from.
5903 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5904 * @retval HAL status
5905 * @note The TimerIdx parameter determines the dma channel to be used by the
5906 * DMA burst controller (see below)
5907 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5908 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5909 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5910 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5911 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5912 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5913 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)5914 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5915 uint32_t TimerIdx,
5916 uint32_t BurstBufferAddress,
5917 uint32_t BurstBufferLength)
5918 {
5919 DMA_HandleTypeDef * hdma;
5920
5921 /* Check the parameters */
5922 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5923
5924 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5925 {
5926 return HAL_BUSY;
5927 }
5928 if(hhrtim->State == HAL_HRTIM_STATE_READY)
5929 {
5930 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5931 {
5932 return HAL_ERROR;
5933 }
5934 else
5935 {
5936 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5937 }
5938 }
5939
5940 /* Process Locked */
5941 __HAL_LOCK(hhrtim);
5942
5943 /* Get the timer DMA handler */
5944 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5945
5946 if (hdma == NULL)
5947 {
5948 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5949
5950 /* Process Unlocked */
5951 __HAL_UNLOCK(hhrtim);
5952
5953 return HAL_ERROR;
5954 }
5955
5956 /* Set the DMA transfer completed callback */
5957 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5958
5959 /* Set the DMA error callback */
5960 hdma->XferErrorCallback = HRTIM_DMAError ;
5961
5962 /* Enable the DMA channel */
5963 if (HAL_DMA_Start_IT(hdma,
5964 BurstBufferAddress,
5965 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5966 BurstBufferLength) != HAL_OK)
5967 {
5968 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5969
5970 /* Process Unlocked */
5971 __HAL_UNLOCK(hhrtim);
5972
5973 return HAL_ERROR;
5974 }
5975
5976 hhrtim->State = HAL_HRTIM_STATE_READY;
5977
5978 /* Process Unlocked */
5979 __HAL_UNLOCK(hhrtim);
5980
5981 return HAL_OK;
5982 }
5983
5984 /**
5985 * @brief Enable the transfer from preload to active registers for one
5986 * or several timing units (including master timer).
5987 * @param hhrtim pointer to HAL HRTIM handle
5988 * @param Timers Timer(s) concerned by the register preload enabling command
5989 * This parameter can be any combination of the following values:
5990 * @arg HRTIM_TIMERUPDATE_MASTER
5991 * @arg HRTIM_TIMERUPDATE_A
5992 * @arg HRTIM_TIMERUPDATE_B
5993 * @arg HRTIM_TIMERUPDATE_C
5994 * @arg HRTIM_TIMERUPDATE_D
5995 * @arg HRTIM_TIMERUPDATE_E
5996 * @retval HAL status
5997 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5998 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5999 uint32_t Timers)
6000 {
6001 /* Check the parameters */
6002 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6003
6004 /* Process Locked */
6005 __HAL_LOCK(hhrtim);
6006
6007 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6008
6009 /* Enable timer(s) registers update */
6010 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
6011
6012 hhrtim->State = HAL_HRTIM_STATE_READY;
6013
6014 /* Process Unlocked */
6015 __HAL_UNLOCK(hhrtim);
6016
6017 return HAL_OK;
6018 }
6019
6020 /**
6021 * @brief Disable the transfer from preload to active registers for one
6022 * or several timing units (including master timer).
6023 * @param hhrtim pointer to HAL HRTIM handle
6024 * @param Timers Timer(s) concerned by the register preload disabling command
6025 * This parameter can be any combination of the following values:
6026 * @arg HRTIM_TIMERUPDATE_MASTER
6027 * @arg HRTIM_TIMERUPDATE_A
6028 * @arg HRTIM_TIMERUPDATE_B
6029 * @arg HRTIM_TIMERUPDATE_C
6030 * @arg HRTIM_TIMERUPDATE_D
6031 * @arg HRTIM_TIMERUPDATE_E
6032 * @retval HAL status
6033 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6034 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
6035 uint32_t Timers)
6036 {
6037 /* Check the parameters */
6038 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6039
6040 /* Process Locked */
6041 __HAL_LOCK(hhrtim);
6042
6043 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6044
6045 /* Enable timer(s) registers update */
6046 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
6047
6048 hhrtim->State = HAL_HRTIM_STATE_READY;
6049
6050 /* Process Unlocked */
6051 __HAL_UNLOCK(hhrtim);
6052
6053 return HAL_OK;
6054 }
6055
6056 /**
6057 * @}
6058 */
6059
6060 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
6061 * @brief Peripheral State functions
6062 @verbatim
6063 ===============================================================================
6064 ##### Peripheral State functions #####
6065 ===============================================================================
6066 [..] This section provides functions used to get HRTIM or HRTIM timer
6067 specific information:
6068 (+) Get HRTIM HAL state
6069 (+) Get captured value
6070 (+) Get HRTIM timer output level
6071 (+) Get HRTIM timer output state
6072 (+) Get delayed protection status
6073 (+) Get burst status
6074 (+) Get current push-pull status
6075 (+) Get idle push-pull status
6076
6077 @endverbatim
6078 * @{
6079 */
6080
6081 /**
6082 * @brief Return the HRTIM HAL state
6083 * @param hhrtim pointer to HAL HRTIM handle
6084 * @retval HAL state
6085 */
HAL_HRTIM_GetState(const HRTIM_HandleTypeDef * hhrtim)6086 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
6087 {
6088 /* Return HRTIM state */
6089 return hhrtim->State;
6090 }
6091
6092 /**
6093 * @brief Return actual value of the capture register of the designated capture unit
6094 * @param hhrtim pointer to HAL HRTIM handle
6095 * @param TimerIdx Timer index
6096 * This parameter can be one of the following values:
6097 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6098 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6099 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6100 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6101 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6102 * @param CaptureUnit Capture unit to trig
6103 * This parameter can be one of the following values:
6104 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6105 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6106 * @retval Captured value
6107 */
HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)6108 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
6109 uint32_t TimerIdx,
6110 uint32_t CaptureUnit)
6111 {
6112 uint32_t captured_value;
6113
6114 /* Check parameters */
6115 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6116 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
6117
6118 /* Read captured value */
6119 switch (CaptureUnit)
6120 {
6121 case HRTIM_CAPTUREUNIT_1:
6122 {
6123 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
6124 break;
6125 }
6126
6127 case HRTIM_CAPTUREUNIT_2:
6128 {
6129 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
6130 break;
6131 }
6132
6133 default:
6134 {
6135 captured_value = 0xFFFFFFFFUL;
6136 break;
6137 }
6138
6139 }
6140
6141 return captured_value;
6142 }
6143
6144
6145 /**
6146 * @brief Return actual level (active or inactive) of the designated output
6147 * @param hhrtim pointer to HAL HRTIM handle
6148 * @param TimerIdx Timer index
6149 * This parameter can be one of the following values:
6150 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6151 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6152 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6153 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6154 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6155 * @param Output Timer output
6156 * This parameter can be one of the following values:
6157 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6158 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6159 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6160 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6161 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6162 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6163 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6164 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6165 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6166 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6167 * @retval Output level
6168 * @note Returned output level is taken before the output stage (chopper,
6169 * polarity).
6170 */
HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6171 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
6172 uint32_t TimerIdx,
6173 uint32_t Output)
6174 {
6175 uint32_t output_level;
6176
6177 /* Check parameters */
6178 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6179
6180 /* Read the output level */
6181 switch (Output)
6182 {
6183 case HRTIM_OUTPUT_TA1:
6184 case HRTIM_OUTPUT_TB1:
6185 case HRTIM_OUTPUT_TC1:
6186 case HRTIM_OUTPUT_TD1:
6187 case HRTIM_OUTPUT_TE1:
6188 {
6189 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6190 {
6191 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6192 }
6193 else
6194 {
6195 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6196 }
6197 break;
6198 }
6199
6200 case HRTIM_OUTPUT_TA2:
6201 case HRTIM_OUTPUT_TB2:
6202 case HRTIM_OUTPUT_TC2:
6203 case HRTIM_OUTPUT_TD2:
6204 case HRTIM_OUTPUT_TE2:
6205 {
6206 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6207 {
6208 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6209 }
6210 else
6211 {
6212 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6213 }
6214 break;
6215 }
6216
6217 default:
6218 {
6219 output_level = 0xFFFFFFFFUL;
6220 break;
6221 }
6222 }
6223
6224 return output_level;
6225 }
6226
6227 /**
6228 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
6229 * @param hhrtim pointer to HAL HRTIM handle
6230 * @param TimerIdx Timer index
6231 * This parameter can be one of the following values:
6232 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6233 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6234 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6235 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6236 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6237 * @param Output Timer output
6238 * This parameter can be one of the following values:
6239 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6240 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6241 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6242 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6243 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6244 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6245 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6246 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6247 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6248 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6249 * @retval Output state
6250 */
HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6251 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
6252 uint32_t TimerIdx,
6253 uint32_t Output)
6254 {
6255 uint32_t output_bit;
6256 uint32_t output_state;
6257
6258 /* Check parameters */
6259 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6260
6261 /* Prevent unused argument(s) compilation warning */
6262 UNUSED(TimerIdx);
6263
6264 /* Set output state according to output control status and output disable status */
6265 switch (Output)
6266 {
6267 case HRTIM_OUTPUT_TA1:
6268 {
6269 output_bit = HRTIM_OENR_TA1OEN;
6270 break;
6271 }
6272
6273 case HRTIM_OUTPUT_TA2:
6274 {
6275 output_bit = HRTIM_OENR_TA2OEN;
6276 break;
6277 }
6278
6279 case HRTIM_OUTPUT_TB1:
6280 {
6281 output_bit = HRTIM_OENR_TB1OEN;
6282 break;
6283 }
6284
6285 case HRTIM_OUTPUT_TB2:
6286 {
6287 output_bit = HRTIM_OENR_TB2OEN;
6288 break;
6289 }
6290
6291 case HRTIM_OUTPUT_TC1:
6292 {
6293 output_bit = HRTIM_OENR_TC1OEN;
6294 break;
6295 }
6296
6297 case HRTIM_OUTPUT_TC2:
6298 {
6299 output_bit = HRTIM_OENR_TC2OEN;
6300 break;
6301 }
6302
6303 case HRTIM_OUTPUT_TD1:
6304 {
6305 output_bit = HRTIM_OENR_TD1OEN;
6306 break;
6307 }
6308
6309 case HRTIM_OUTPUT_TD2:
6310 {
6311 output_bit = HRTIM_OENR_TD2OEN;
6312 break;
6313 }
6314
6315 case HRTIM_OUTPUT_TE1:
6316 {
6317 output_bit = HRTIM_OENR_TE1OEN;
6318 break;
6319 }
6320
6321 case HRTIM_OUTPUT_TE2:
6322 {
6323 output_bit = HRTIM_OENR_TE2OEN;
6324 break;
6325 }
6326
6327 default:
6328 {
6329 output_bit = 0UL;
6330 break;
6331 }
6332 }
6333
6334 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6335 {
6336 /* Output is enabled: output in RUN state (whatever output disable status is)*/
6337 output_state = HRTIM_OUTPUTSTATE_RUN;
6338 }
6339 else
6340 {
6341 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6342 {
6343 /* Output is disabled: output in FAULT state */
6344 output_state = HRTIM_OUTPUTSTATE_FAULT;
6345 }
6346 else
6347 {
6348 /* Output is disabled: output in IDLE state */
6349 output_state = HRTIM_OUTPUTSTATE_IDLE;
6350 }
6351 }
6352
6353 return(output_state);
6354 }
6355
6356 /**
6357 * @brief Return the level (active or inactive) of the designated output
6358 * when the delayed protection was triggered.
6359 * @param hhrtim pointer to HAL HRTIM handle
6360 * @param TimerIdx Timer index
6361 * This parameter can be one of the following values:
6362 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6363 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6364 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6365 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6366 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6367 * @param Output Timer output
6368 * This parameter can be one of the following values:
6369 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6370 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6371 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6372 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6373 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6374 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6375 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6376 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6377 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6378 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6379 * @retval Delayed protection status
6380 */
HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6381 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
6382 uint32_t TimerIdx,
6383 uint32_t Output)
6384 {
6385 uint32_t delayed_protection_status;
6386
6387 /* Check parameters */
6388 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6389
6390 /* Read the delayed protection status */
6391 switch (Output)
6392 {
6393 case HRTIM_OUTPUT_TA1:
6394 case HRTIM_OUTPUT_TB1:
6395 case HRTIM_OUTPUT_TC1:
6396 case HRTIM_OUTPUT_TD1:
6397 case HRTIM_OUTPUT_TE1:
6398 {
6399 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6400 {
6401 /* Output 1 was active when the delayed idle protection was triggered */
6402 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6403 }
6404 else
6405 {
6406 /* Output 1 was inactive when the delayed idle protection was triggered */
6407 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6408 }
6409 break;
6410 }
6411
6412 case HRTIM_OUTPUT_TA2:
6413 case HRTIM_OUTPUT_TB2:
6414 case HRTIM_OUTPUT_TC2:
6415 case HRTIM_OUTPUT_TD2:
6416 case HRTIM_OUTPUT_TE2:
6417 {
6418 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6419 {
6420 /* Output 2 was active when the delayed idle protection was triggered */
6421 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6422 }
6423 else
6424 {
6425 /* Output 2 was inactive when the delayed idle protection was triggered */
6426 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6427 }
6428 break;
6429 }
6430
6431 default:
6432 {
6433 delayed_protection_status = 0xFFFFFFFFUL;
6434 break;
6435 }
6436 }
6437
6438 return delayed_protection_status;
6439 }
6440
6441 /**
6442 * @brief Return the actual status (active or inactive) of the burst mode controller
6443 * @param hhrtim pointer to HAL HRTIM handle
6444 * @retval Burst mode controller status
6445 */
HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)6446 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
6447 {
6448 uint32_t burst_mode_status;
6449
6450 /* Read burst mode status */
6451 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6452
6453 return burst_mode_status;
6454 }
6455
6456 /**
6457 * @brief Indicate on which output the signal is currently active (when the
6458 * push pull mode is enabled).
6459 * @param hhrtim pointer to HAL HRTIM handle
6460 * @param TimerIdx Timer index
6461 * This parameter can be one of the following values:
6462 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6463 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6464 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6465 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6466 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6467 * @retval Burst mode controller status
6468 */
HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6469 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6470 uint32_t TimerIdx)
6471 {
6472 uint32_t current_pushpull_status;
6473
6474 /* Check the parameters */
6475 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6476
6477 /* Read current push pull status */
6478 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6479
6480 return current_pushpull_status;
6481 }
6482
6483
6484 /**
6485 * @brief Indicate on which output the signal was applied, in push-pull mode,
6486 balanced fault mode or delayed idle mode, when the protection was triggered.
6487 * @param hhrtim pointer to HAL HRTIM handle
6488 * @param TimerIdx Timer index
6489 * This parameter can be one of the following values:
6490 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6491 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6492 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6493 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6494 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6495 * @retval Idle Push Pull Status
6496 */
HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6497 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
6498 uint32_t TimerIdx)
6499 {
6500 uint32_t idle_pushpull_status;
6501
6502 /* Check the parameters */
6503 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6504
6505 /* Read current push pull status */
6506 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6507
6508 return idle_pushpull_status;
6509 }
6510
6511 /**
6512 * @}
6513 */
6514
6515 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6516 * @brief Functions called when HRTIM generates an interrupt
6517 * 7 interrupts can be generated by the master timer:
6518 * - Master timer registers update
6519 * - Synchronization event received
6520 * - Master timer repetition event
6521 * - Master Compare 1 to 4 event
6522 * 14 interrupts can be generated by each timing unit:
6523 * - Delayed protection triggered
6524 * - Counter reset or roll-over event
6525 * - Output 1 and output 2 reset (transition active to inactive)
6526 * - Output 1 and output 2 set (transition inactive to active)
6527 * - Capture 1 and 2 events
6528 * - Timing unit registers update
6529 * - Repetition event
6530 * - Compare 1 to 4 event
6531 * 8 global interrupts are generated for the whole HRTIM:
6532 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6533 * - DLL calibration done
6534 * - Burst mode period completed
6535 @verbatim
6536 ===============================================================================
6537 ##### HRTIM interrupts handling #####
6538 ===============================================================================
6539 [..]
6540 This subsection provides a set of functions allowing to manage the HRTIM
6541 interrupts:
6542 (+) HRTIM interrupt handler
6543 (+) Callback function called when Fault1 interrupt occurs
6544 (+) Callback function called when Fault2 interrupt occurs
6545 (+) Callback function called when Fault3 interrupt occurs
6546 (+) Callback function called when Fault4 interrupt occurs
6547 (+) Callback function called when Fault5 interrupt occurs
6548 (+) Callback function called when system Fault interrupt occurs
6549 (+) Callback function called when DLL ready interrupt occurs
6550 (+) Callback function called when burst mode period interrupt occurs
6551 (+) Callback function called when synchronization input interrupt occurs
6552 (+) Callback function called when a timer register update interrupt occurs
6553 (+) Callback function called when a timer repetition interrupt occurs
6554 (+) Callback function called when a compare 1 match interrupt occurs
6555 (+) Callback function called when a compare 2 match interrupt occurs
6556 (+) Callback function called when a compare 3 match interrupt occurs
6557 (+) Callback function called when a compare 4 match interrupt occurs
6558 (+) Callback function called when a capture 1 interrupt occurs
6559 (+) Callback function called when a capture 2 interrupt occurs
6560 (+) Callback function called when a delayed protection interrupt occurs
6561 (+) Callback function called when a timer counter reset interrupt occurs
6562 (+) Callback function called when a timer output 1 set interrupt occurs
6563 (+) Callback function called when a timer output 1 reset interrupt occurs
6564 (+) Callback function called when a timer output 2 set interrupt occurs
6565 (+) Callback function called when a timer output 2 reset interrupt occurs
6566 (+) Callback function called when a timer output 2 reset interrupt occurs
6567 (+) Callback function called upon completion of a burst DMA transfer
6568 (+) HRTIM callback function registration
6569 (+) HRTIM callback function unregistration
6570 (+) HRTIM Timer x callback function registration
6571 (+) HRTIM Timer x callback function unregistration
6572
6573 @endverbatim
6574 * @{
6575 */
6576
6577 /**
6578 * @brief This function handles HRTIM interrupt request.
6579 * @param hhrtim pointer to HAL HRTIM handle
6580 * @param TimerIdx Timer index
6581 * This parameter can be any value of HRTIM_Timer_Index
6582 * @retval None
6583 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6584 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6585 uint32_t TimerIdx)
6586 {
6587 /* HRTIM interrupts handling */
6588 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6589 {
6590 HRTIM_HRTIM_ISR(hhrtim);
6591 }
6592 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6593 {
6594 /* Master related interrupts handling */
6595 HRTIM_Master_ISR(hhrtim);
6596 }
6597 else
6598 {
6599 /* Timing unit related interrupts handling */
6600 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6601 }
6602
6603 }
6604
6605 /**
6606 * @brief Callback function invoked when a fault 1 interrupt occurred
6607 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6608 * @retval None
6609 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)6610 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6611 {
6612 /* Prevent unused argument(s) compilation warning */
6613 UNUSED(hhrtim);
6614
6615 /* NOTE : This function should not be modified, when the callback is needed,
6616 the HAL_HRTIM_Fault1Callback could be implemented in the user file
6617 */
6618 }
6619
6620 /**
6621 * @brief Callback function invoked when a fault 2 interrupt occurred
6622 * @param hhrtim pointer to HAL HRTIM handle
6623 * @retval None
6624 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)6625 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6626 {
6627 /* Prevent unused argument(s) compilation warning */
6628 UNUSED(hhrtim);
6629
6630 /* NOTE : This function should not be modified, when the callback is needed,
6631 the HAL_HRTIM_Fault2Callback could be implemented in the user file
6632 */
6633 }
6634
6635 /**
6636 * @brief Callback function invoked when a fault 3 interrupt occurred
6637 * @param hhrtim pointer to HAL HRTIM handle
6638 * @retval None
6639 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)6640 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6641 {
6642 /* Prevent unused argument(s) compilation warning */
6643 UNUSED(hhrtim);
6644
6645 /* NOTE : This function should not be modified, when the callback is needed,
6646 the HAL_HRTIM_Fault3Callback could be implemented in the user file
6647 */
6648 }
6649
6650 /**
6651 * @brief Callback function invoked when a fault 4 interrupt occurred
6652 * @param hhrtim pointer to HAL HRTIM handle
6653 * @retval None
6654 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)6655 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6656 {
6657 /* Prevent unused argument(s) compilation warning */
6658 UNUSED(hhrtim);
6659
6660 /* NOTE : This function should not be modified, when the callback is needed,
6661 the HAL_HRTIM_Fault4Callback could be implemented in the user file
6662 */
6663 }
6664
6665 /**
6666 * @brief Callback function invoked when a fault 5 interrupt occurred
6667 * @param hhrtim pointer to HAL HRTIM handle
6668 * @retval None
6669 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)6670 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6671 {
6672 /* Prevent unused argument(s) compilation warning */
6673 UNUSED(hhrtim);
6674
6675 /* NOTE : This function should not be modified, when the callback is needed,
6676 the HAL_HRTIM_Fault5Callback could be implemented in the user file
6677 */
6678 }
6679
6680 /**
6681 * @brief Callback function invoked when a system fault interrupt occurred
6682 * @param hhrtim pointer to HAL HRTIM handle
6683 * @retval None
6684 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)6685 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6686 {
6687 /* Prevent unused argument(s) compilation warning */
6688 UNUSED(hhrtim);
6689
6690 /* NOTE : This function should not be modified, when the callback is needed,
6691 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
6692 */
6693 }
6694
6695 /**
6696 * @brief Callback function invoked when the DLL calibration is completed
6697 * @param hhrtim pointer to HAL HRTIM handle
6698 * @retval None
6699 */
HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)6700 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
6701 {
6702 /* Prevent unused argument(s) compilation warning */
6703 UNUSED(hhrtim);
6704
6705 /* NOTE : This function should not be modified, when the callback is needed,
6706 the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
6707 */
6708 }
6709
6710 /**
6711 * @brief Callback function invoked when the end of the burst mode period is reached
6712 * @param hhrtim pointer to HAL HRTIM handle
6713 * @retval None
6714 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)6715 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6716 {
6717 /* Prevent unused argument(s) compilation warning */
6718 UNUSED(hhrtim);
6719
6720 /* NOTE : This function should not be modified, when the callback is needed,
6721 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
6722 */
6723 }
6724
6725 /**
6726 * @brief Callback function invoked when a synchronization input event is received
6727 * @param hhrtim pointer to HAL HRTIM handle
6728 * @retval None
6729 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)6730 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6731 {
6732 /* Prevent unused argument(s) compilation warning */
6733 UNUSED(hhrtim);
6734
6735 /* NOTE : This function should not be modified, when the callback is needed,
6736 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
6737 */
6738 }
6739
6740 /**
6741 * @brief Callback function invoked when timer registers are updated
6742 * @param hhrtim pointer to HAL HRTIM handle
6743 * @param TimerIdx Timer index
6744 * This parameter can be one of the following values:
6745 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6746 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6747 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6748 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6749 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6750 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6751 * @retval None
6752 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6753 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6754 uint32_t TimerIdx)
6755 {
6756 /* Prevent unused argument(s) compilation warning */
6757 UNUSED(hhrtim);
6758 UNUSED(TimerIdx);
6759
6760 /* NOTE : This function should not be modified, when the callback is needed,
6761 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
6762 */
6763 }
6764
6765 /**
6766 * @brief Callback function invoked when timer repetition period has elapsed
6767 * @param hhrtim pointer to HAL HRTIM handle
6768 * @param TimerIdx Timer index
6769 * This parameter can be one of the following values:
6770 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6771 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6772 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6773 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6774 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6775 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6776 * @retval None
6777 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6778 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6779 uint32_t TimerIdx)
6780 {
6781 /* Prevent unused argument(s) compilation warning */
6782 UNUSED(hhrtim);
6783 UNUSED(TimerIdx);
6784
6785 /* NOTE : This function should not be modified, when the callback is needed,
6786 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
6787 */
6788 }
6789
6790 /**
6791 * @brief Callback function invoked when the timer counter matches the value
6792 * programmed in the compare 1 register
6793 * @param hhrtim pointer to HAL HRTIM handle
6794 * @param TimerIdx Timer index
6795 * This parameter can be one of the following values:
6796 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6797 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6798 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6799 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6800 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6801 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6802 * @retval None
6803 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6804 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6805 uint32_t TimerIdx)
6806 {
6807 /* Prevent unused argument(s) compilation warning */
6808 UNUSED(hhrtim);
6809 UNUSED(TimerIdx);
6810
6811 /* NOTE : This function should not be modified, when the callback is needed,
6812 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
6813 */
6814 }
6815
6816 /**
6817 * @brief Callback function invoked when the timer counter matches the value
6818 * programmed in the compare 2 register
6819 * @param hhrtim pointer to HAL HRTIM handle
6820 * @retval None
6821 * @param TimerIdx Timer index
6822 * This parameter can be one of the following values:
6823 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6824 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6825 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6826 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6827 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6828 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6829 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6830 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6831 uint32_t TimerIdx)
6832 {
6833 /* Prevent unused argument(s) compilation warning */
6834 UNUSED(hhrtim);
6835 UNUSED(TimerIdx);
6836
6837 /* NOTE : This function should not be modified, when the callback is needed,
6838 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
6839 */
6840 }
6841
6842 /**
6843 * @brief Callback function invoked when the timer counter matches the value
6844 * programmed in the compare 3 register
6845 * @param hhrtim pointer to HAL HRTIM handle
6846 * @param TimerIdx Timer index
6847 * This parameter can be one of the following values:
6848 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6849 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6850 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6851 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6852 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6853 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6854 * @retval None
6855 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6856 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6857 uint32_t TimerIdx)
6858 {
6859 /* Prevent unused argument(s) compilation warning */
6860 UNUSED(hhrtim);
6861 UNUSED(TimerIdx);
6862
6863 /* NOTE : This function should not be modified, when the callback is needed,
6864 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
6865 */
6866 }
6867
6868 /**
6869 * @brief Callback function invoked when the timer counter matches the value
6870 * programmed in the compare 4 register.
6871 * @param hhrtim pointer to HAL HRTIM handle
6872 * @param TimerIdx Timer index
6873 * This parameter can be one of the following values:
6874 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6875 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6876 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6877 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6878 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6879 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6880 * @retval None
6881 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6882 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6883 uint32_t TimerIdx)
6884 {
6885 /* Prevent unused argument(s) compilation warning */
6886 UNUSED(hhrtim);
6887 UNUSED(TimerIdx);
6888
6889 /* NOTE : This function should not be modified, when the callback is needed,
6890 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
6891 */
6892 }
6893
6894 /**
6895 * @brief Callback function invoked when the timer x capture 1 event occurs
6896 * @param hhrtim pointer to HAL HRTIM handle
6897 * @param TimerIdx Timer index
6898 * This parameter can be one of the following values:
6899 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6900 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6901 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6902 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6903 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6904 * @retval None
6905 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6906 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6907 uint32_t TimerIdx)
6908 {
6909 /* Prevent unused argument(s) compilation warning */
6910 UNUSED(hhrtim);
6911 UNUSED(TimerIdx);
6912
6913 /* NOTE : This function should not be modified, when the callback is needed,
6914 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
6915 */
6916 }
6917
6918 /**
6919 * @brief Callback function invoked when the timer x capture 2 event occurs
6920 * @param hhrtim pointer to HAL HRTIM handle
6921 * @param TimerIdx Timer index
6922 * This parameter can be one of the following values:
6923 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6924 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6925 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6926 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6927 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6928 * @retval None
6929 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6930 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6931 uint32_t TimerIdx)
6932 {
6933 /* Prevent unused argument(s) compilation warning */
6934 UNUSED(hhrtim);
6935 UNUSED(TimerIdx);
6936
6937 /* NOTE : This function should not be modified, when the callback is needed,
6938 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
6939 */
6940 }
6941
6942 /**
6943 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6944 * entered.
6945 * @param hhrtim pointer to HAL HRTIM handle
6946 * @param TimerIdx Timer index
6947 * This parameter can be one of the following values:
6948 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6949 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6950 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6951 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6952 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6953 * @retval None
6954 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6955 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6956 uint32_t TimerIdx)
6957 {
6958 /* Prevent unused argument(s) compilation warning */
6959 UNUSED(hhrtim);
6960 UNUSED(TimerIdx);
6961
6962 /* NOTE : This function should not be modified, when the callback is needed,
6963 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
6964 */
6965 }
6966
6967 /**
6968 * @brief Callback function invoked when the timer x counter reset/roll-over
6969 * event occurs.
6970 * @param hhrtim pointer to HAL HRTIM handle
6971 * @param TimerIdx Timer index
6972 * This parameter can be one of the following values:
6973 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6974 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6975 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6976 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6977 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6978 * @retval None
6979 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6980 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6981 uint32_t TimerIdx)
6982 {
6983 /* Prevent unused argument(s) compilation warning */
6984 UNUSED(hhrtim);
6985 UNUSED(TimerIdx);
6986
6987 /* NOTE : This function should not be modified, when the callback is needed,
6988 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
6989 */
6990 }
6991
6992 /**
6993 * @brief Callback function invoked when the timer x output 1 is set
6994 * @param hhrtim pointer to HAL HRTIM handle
6995 * @param TimerIdx Timer index
6996 * This parameter can be one of the following values:
6997 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6998 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6999 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7000 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7001 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7002 * @retval None
7003 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7004 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
7005 uint32_t TimerIdx)
7006 {
7007 /* Prevent unused argument(s) compilation warning */
7008 UNUSED(hhrtim);
7009 UNUSED(TimerIdx);
7010
7011 /* NOTE : This function should not be modified, when the callback is needed,
7012 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
7013 */
7014 }
7015
7016 /**
7017 * @brief Callback function invoked when the timer x output 1 is reset
7018 * @param hhrtim pointer to HAL HRTIM handle
7019 * @param TimerIdx Timer index
7020 * This parameter can be one of the following values:
7021 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7022 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7023 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7024 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7025 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7026 * @retval None
7027 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7028 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
7029 uint32_t TimerIdx)
7030 {
7031 /* Prevent unused argument(s) compilation warning */
7032 UNUSED(hhrtim);
7033 UNUSED(TimerIdx);
7034
7035 /* NOTE : This function should not be modified, when the callback is needed,
7036 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
7037 */
7038 }
7039
7040 /**
7041 * @brief Callback function invoked when the timer x output 2 is set
7042 * @param hhrtim pointer to HAL HRTIM handle
7043 * @param TimerIdx Timer index
7044 * This parameter can be one of the following values:
7045 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7046 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7047 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7048 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7049 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7050 * @retval None
7051 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7052 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
7053 uint32_t TimerIdx)
7054 {
7055 /* Prevent unused argument(s) compilation warning */
7056 UNUSED(hhrtim);
7057 UNUSED(TimerIdx);
7058
7059 /* NOTE : This function should not be modified, when the callback is needed,
7060 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
7061 */
7062 }
7063
7064 /**
7065 * @brief Callback function invoked when the timer x output 2 is reset
7066 * @param hhrtim pointer to HAL HRTIM handle
7067 * @param TimerIdx Timer index
7068 * This parameter can be one of the following values:
7069 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7070 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7071 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7072 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7073 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7074 * @retval None
7075 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7076 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
7077 uint32_t TimerIdx)
7078 {
7079 /* Prevent unused argument(s) compilation warning */
7080 UNUSED(hhrtim);
7081 UNUSED(TimerIdx);
7082
7083 /* NOTE : This function should not be modified, when the callback is needed,
7084 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
7085 */
7086 }
7087
7088 /**
7089 * @brief Callback function invoked when a DMA burst transfer is completed
7090 * @param hhrtim pointer to HAL HRTIM handle
7091 * @param TimerIdx Timer index
7092 * This parameter can be one of the following values:
7093 * @arg HRTIM_TIMERINDEX_MASTER for master timer
7094 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7095 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7096 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7097 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7098 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7099 * @retval None
7100 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7101 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
7102 uint32_t TimerIdx)
7103 {
7104 /* Prevent unused argument(s) compilation warning */
7105 UNUSED(hhrtim);
7106 UNUSED(TimerIdx);
7107
7108 /* NOTE : This function should not be modified, when the callback is needed,
7109 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
7110 */
7111 }
7112
7113 /**
7114 * @brief Callback function invoked when a DMA error occurs
7115 * @param hhrtim pointer to HAL HRTIM handle
7116 * @retval None
7117 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)7118 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
7119 {
7120 /* Prevent unused argument(s) compilation warning */
7121 UNUSED(hhrtim);
7122
7123 /* NOTE : This function should not be modified, when the callback is needed,
7124 the HAL_HRTIM_ErrorCallback could be implemented in the user file
7125 */
7126 }
7127
7128 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
7129 /**
7130 * @brief HRTIM callback function registration
7131 * @param hhrtim pointer to HAL HRTIM handle
7132 * @param CallbackID ID of the HRTIM callback function to register
7133 * This parameter can be one of the following values:
7134 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7135 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7136 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7137 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7138 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7139 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7140 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
7141 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7142 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7143 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7144 * @arg HAL_HRTIM_MSPINIT_CB_ID
7145 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7146 * @param pCallback Callback function pointer
7147 * @retval HAL status
7148 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)7149 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7150 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7151 pHRTIM_CallbackTypeDef pCallback)
7152 {
7153 HAL_StatusTypeDef status = HAL_OK;
7154
7155 if (pCallback == NULL)
7156 {
7157 /* Update the state */
7158 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7159
7160 return HAL_ERROR;
7161 }
7162
7163 /* Process locked */
7164 __HAL_LOCK(hhrtim);
7165
7166 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7167 {
7168 switch (CallbackID)
7169 {
7170 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7171 hhrtim->Fault1Callback = pCallback;
7172 break;
7173
7174 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7175 hhrtim->Fault2Callback = pCallback;
7176 break;
7177
7178 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7179 hhrtim->Fault3Callback = pCallback;
7180 break;
7181
7182 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7183 hhrtim->Fault4Callback = pCallback;
7184 break;
7185
7186 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7187 hhrtim->Fault5Callback = pCallback;
7188 break;
7189
7190 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7191 hhrtim->SystemFaultCallback = pCallback;
7192 break;
7193
7194 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
7195 hhrtim->DLLCalibrationReadyCallback = pCallback;
7196 break;
7197
7198 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7199 hhrtim->BurstModePeriodCallback = pCallback;
7200 break;
7201
7202 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7203 hhrtim->SynchronizationEventCallback = pCallback;
7204 break;
7205
7206 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7207 hhrtim->ErrorCallback = pCallback;
7208 break;
7209
7210 case HAL_HRTIM_MSPINIT_CB_ID :
7211 hhrtim->MspInitCallback = pCallback;
7212 break;
7213
7214 case HAL_HRTIM_MSPDEINIT_CB_ID :
7215 hhrtim->MspDeInitCallback = pCallback;
7216 break;
7217
7218 default :
7219 /* Update the state */
7220 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7221
7222 /* Return error status */
7223 status = HAL_ERROR;
7224 break;
7225 }
7226 }
7227 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7228 {
7229 switch (CallbackID)
7230 {
7231 case HAL_HRTIM_MSPINIT_CB_ID :
7232 hhrtim->MspInitCallback = pCallback;
7233 break;
7234
7235 case HAL_HRTIM_MSPDEINIT_CB_ID :
7236 hhrtim->MspDeInitCallback = pCallback;
7237 break;
7238
7239 default :
7240 /* Update the state */
7241 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7242
7243 /* Return error status */
7244 status = HAL_ERROR;
7245 break;
7246 }
7247 }
7248 else
7249 {
7250 /* Update the state */
7251 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7252
7253 /* Return error status */
7254 status = HAL_ERROR;
7255 }
7256
7257 /* Release Lock */
7258 __HAL_UNLOCK(hhrtim);
7259
7260 return status;
7261 }
7262
7263 /**
7264 * @brief HRTIM callback function un-registration
7265 * @param hhrtim pointer to HAL HRTIM handle
7266 * @param CallbackID ID of the HRTIM callback function to unregister
7267 * This parameter can be one of the following values:
7268 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7269 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7270 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7271 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7272 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7273 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7274 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
7275 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7276 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7277 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7278 * @arg HAL_HRTIM_MSPINIT_CB_ID
7279 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7280 * @retval HAL status
7281 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7282 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7283 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7284 {
7285 HAL_StatusTypeDef status = HAL_OK;
7286
7287 /* Process locked */
7288 __HAL_LOCK(hhrtim);
7289
7290 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7291 {
7292 switch (CallbackID)
7293 {
7294 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7295 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7296 break;
7297
7298 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7299 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7300 break;
7301
7302 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7303 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7304 break;
7305
7306 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7307 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7308 break;
7309
7310 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7311 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7312 break;
7313
7314 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7315 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7316 break;
7317
7318 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
7319 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
7320 break;
7321
7322 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7323 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7324 break;
7325
7326 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7327 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7328 break;
7329
7330 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7331 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7332 break;
7333
7334 case HAL_HRTIM_MSPINIT_CB_ID :
7335 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7336 break;
7337
7338 case HAL_HRTIM_MSPDEINIT_CB_ID :
7339 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7340 break;
7341
7342 default :
7343 /* Update the state */
7344 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7345
7346 /* Return error status */
7347 status = HAL_ERROR;
7348 break;
7349 }
7350 }
7351 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7352 {
7353 switch (CallbackID)
7354 {
7355 case HAL_HRTIM_MSPINIT_CB_ID :
7356 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7357 break;
7358
7359 case HAL_HRTIM_MSPDEINIT_CB_ID :
7360 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7361 break;
7362
7363 default :
7364 /* Update the state */
7365 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7366
7367 /* Return error status */
7368 status = HAL_ERROR;
7369 break;
7370 }
7371 }
7372 else
7373 {
7374 /* Update the state */
7375 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7376
7377 /* Return error status */
7378 status = HAL_ERROR;
7379 }
7380
7381 /* Release Lock */
7382 __HAL_UNLOCK(hhrtim);
7383
7384 return status;
7385 }
7386
7387 /**
7388 * @brief HRTIM Timer x callback function registration
7389 * @param hhrtim pointer to HAL HRTIM handle
7390 * @param CallbackID ID of the HRTIM Timer x callback function to register
7391 * This parameter can be one of the following values:
7392 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7393 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7394 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7395 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7396 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7397 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7398 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7399 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7400 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7401 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7402 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7403 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7404 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7405 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7406 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7407 * @param pCallback Callback function pointer
7408 * @retval HAL status
7409 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)7410 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7411 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7412 pHRTIM_TIMxCallbackTypeDef pCallback)
7413 {
7414 HAL_StatusTypeDef status = HAL_OK;
7415
7416 if (pCallback == NULL)
7417 {
7418 /* Update the state */
7419 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7420
7421 return HAL_ERROR;
7422 }
7423
7424 /* Process locked */
7425 __HAL_LOCK(hhrtim);
7426
7427 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7428 {
7429 switch (CallbackID)
7430 {
7431 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7432 hhrtim->RegistersUpdateCallback = pCallback;
7433 break;
7434
7435 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7436 hhrtim->RepetitionEventCallback = pCallback;
7437 break;
7438
7439 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7440 hhrtim->Compare1EventCallback = pCallback;
7441 break;
7442
7443 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7444 hhrtim->Compare2EventCallback = pCallback;
7445 break;
7446
7447 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7448 hhrtim->Compare3EventCallback = pCallback;
7449 break;
7450
7451 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7452 hhrtim->Compare4EventCallback = pCallback;
7453 break;
7454
7455 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7456 hhrtim->Capture1EventCallback = pCallback;
7457 break;
7458
7459 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7460 hhrtim->Capture2EventCallback = pCallback;
7461 break;
7462
7463 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7464 hhrtim->DelayedProtectionCallback = pCallback;
7465 break;
7466
7467 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7468 hhrtim->CounterResetCallback = pCallback;
7469 break;
7470
7471 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7472 hhrtim->Output1SetCallback = pCallback;
7473 break;
7474
7475 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7476 hhrtim->Output1ResetCallback = pCallback;
7477 break;
7478
7479 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7480 hhrtim->Output2SetCallback = pCallback;
7481 break;
7482
7483 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7484 hhrtim->Output2ResetCallback = pCallback;
7485 break;
7486
7487 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7488 hhrtim->BurstDMATransferCallback = pCallback;
7489 break;
7490
7491 default :
7492 /* Update the state */
7493 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7494
7495 /* Return error status */
7496 status = HAL_ERROR;
7497 break;
7498 }
7499 }
7500 else
7501 {
7502 /* Update the state */
7503 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7504
7505 /* Return error status */
7506 status = HAL_ERROR;
7507 }
7508
7509 /* Release Lock */
7510 __HAL_UNLOCK(hhrtim);
7511
7512 return status;
7513 }
7514
7515 /**
7516 * @brief HRTIM Timer x callback function un-registration
7517 * @param hhrtim pointer to HAL HRTIM handle
7518 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
7519 * This parameter can be one of the following values:
7520 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7521 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7522 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7523 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7524 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7525 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7526 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7527 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7528 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7529 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7530 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7531 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7532 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7533 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7534 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7535 * @retval HAL status
7536 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7537 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
7538 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7539 {
7540 HAL_StatusTypeDef status = HAL_OK;
7541
7542 /* Process locked */
7543 __HAL_LOCK(hhrtim);
7544
7545 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7546 {
7547 switch (CallbackID)
7548 {
7549 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7550 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7551 break;
7552
7553 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7554 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7555 break;
7556
7557 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7558 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7559 break;
7560
7561 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7562 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7563 break;
7564
7565 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7566 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7567 break;
7568
7569 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7570 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7571 break;
7572
7573 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7574 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7575 break;
7576
7577 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7578 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7579 break;
7580
7581 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7582 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7583 break;
7584
7585 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7586 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7587 break;
7588
7589 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7590 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7591 break;
7592
7593 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7594 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7595 break;
7596
7597 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7598 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7599 break;
7600
7601 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7602 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7603 break;
7604
7605 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7606 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7607 break;
7608
7609 default :
7610 /* Update the state */
7611 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7612
7613 /* Return error status */
7614 status = HAL_ERROR;
7615 break;
7616 }
7617 }
7618 else
7619 {
7620 /* Update the state */
7621 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7622
7623 /* Return error status */
7624 status = HAL_ERROR;
7625 }
7626
7627 /* Release Lock */
7628 __HAL_UNLOCK(hhrtim);
7629
7630 return status;
7631 }
7632 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
7633 /**
7634 * @}
7635 */
7636
7637 /**
7638 * @}
7639 */
7640
7641 /** @addtogroup HRTIM_Private_Functions
7642 * @{
7643 */
7644
7645 /**
7646 * @brief Configure the master timer time base
7647 * @param hhrtim pointer to HAL HRTIM handle
7648 * @param pTimeBaseCfg pointer to the time base configuration structure
7649 * @retval None
7650 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7651 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
7652 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7653 {
7654 uint32_t hrtim_mcr;
7655
7656 /* Configure master timer */
7657 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7658
7659 /* Set the prescaler ratio */
7660 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7661 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7662
7663 /* Set the operating mode */
7664 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7665 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7666
7667 /* Update the HRTIM registers */
7668 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7669 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7670 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7671 }
7672
7673 /**
7674 * @brief Configure timing unit (Timer A to Timer E) time base
7675 * @param hhrtim pointer to HAL HRTIM handle
7676 * @param TimerIdx Timer index
7677 * @param pTimeBaseCfg pointer to the time base configuration structure
7678 * @retval None
7679 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7680 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
7681 uint32_t TimerIdx ,
7682 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
7683 {
7684 uint32_t hrtim_timcr;
7685
7686 /* Configure master timing unit */
7687 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7688
7689 /* Set the prescaler ratio */
7690 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7691 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7692
7693 /* Set the operating mode */
7694 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7695 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7696
7697 /* Update the HRTIM registers */
7698 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7699 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7700 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7701 }
7702
7703 /**
7704 * @brief Configure the master timer in waveform mode
7705 * @param hhrtim pointer to HAL HRTIM handle
7706 * @param pTimerCfg pointer to the timer configuration data structure
7707 * @retval None
7708 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimerCfgTypeDef * pTimerCfg)7709 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7710 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7711 {
7712 uint32_t hrtim_mcr;
7713 uint32_t hrtim_bmcr;
7714
7715 /* Configure master timer */
7716 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7717 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7718
7719 /* Enable/Disable the half mode */
7720 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7721 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7722
7723 /* Enable/Disable the timer start upon synchronization event reception */
7724 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7725 hrtim_mcr |= pTimerCfg->StartOnSync;
7726
7727 /* Enable/Disable the timer reset upon synchronization event reception */
7728 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7729 hrtim_mcr |= pTimerCfg->ResetOnSync;
7730
7731 /* Enable/Disable the DAC synchronization event generation */
7732 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7733 hrtim_mcr |= pTimerCfg->DACSynchro;
7734
7735 /* Enable/Disable preload mechanism for timer registers */
7736 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7737 hrtim_mcr |= pTimerCfg->PreloadEnable;
7738
7739 /* Master timer registers update handling */
7740 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7741 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7742
7743 /* Enable/Disable registers update on repetition */
7744 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7745 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7746
7747 /* Set the timer burst mode */
7748 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7749 hrtim_bmcr |= pTimerCfg->BurstMode;
7750
7751 /* Update the HRTIM registers */
7752 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7753 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7754 }
7755
7756 /**
7757 * @brief Configure timing unit (Timer A to Timer E) in waveform mode
7758 * @param hhrtim pointer to HAL HRTIM handle
7759 * @param TimerIdx Timer index
7760 * @param pTimerCfg pointer to the timer configuration data structure
7761 * @retval None
7762 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)7763 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
7764 uint32_t TimerIdx,
7765 const HRTIM_TimerCfgTypeDef * pTimerCfg)
7766 {
7767 uint32_t hrtim_timcr;
7768 uint32_t hrtim_timfltr;
7769 uint32_t hrtim_timoutr;
7770 uint32_t hrtim_timrstr;
7771 uint32_t hrtim_bmcr;
7772
7773 /* UPDGAT bitfield must be reset before programming a new value */
7774 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7775
7776 /* Configure timing unit (Timer A to Timer E) */
7777 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7778 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7779 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7780 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7781
7782 /* Enable/Disable the half mode */
7783 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7784 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7785
7786 /* Enable/Disable the timer start upon synchronization event reception */
7787 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7788 hrtim_timcr |= pTimerCfg->StartOnSync;
7789
7790 /* Enable/Disable the timer reset upon synchronization event reception */
7791 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7792 hrtim_timcr |= pTimerCfg->ResetOnSync;
7793
7794 /* Enable/Disable the DAC synchronization event generation */
7795 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7796 hrtim_timcr |= pTimerCfg->DACSynchro;
7797
7798 /* Enable/Disable preload mechanism for timer registers */
7799 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7800 hrtim_timcr |= pTimerCfg->PreloadEnable;
7801
7802 /* Timing unit registers update handling */
7803 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7804 hrtim_timcr |= pTimerCfg->UpdateGating;
7805
7806 /* Enable/Disable registers update on repetition */
7807 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7808 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7809 {
7810 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7811 }
7812
7813 /* Set the push-pull mode */
7814 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7815 hrtim_timcr |= pTimerCfg->PushPull;
7816
7817 /* Enable/Disable registers update on timer counter reset */
7818 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7819 hrtim_timcr |= pTimerCfg->ResetUpdate;
7820
7821 /* Set the timer update trigger */
7822 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7823 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7824
7825 /* Enable/Disable the fault channel at timer level */
7826 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7827 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7828
7829 /* Lock/Unlock fault sources at timer level */
7830 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7831 hrtim_timfltr |= pTimerCfg->FaultLock;
7832
7833 /* The deadtime cannot be used simultaneously with the push-pull mode */
7834 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7835 {
7836 /* Enable/Disable dead time insertion at timer level */
7837 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7838 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7839 }
7840
7841 /* Enable/Disable delayed protection at timer level
7842 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
7843 Balanced Idle is only available in push-pull mode
7844 */
7845 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7846 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7847 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7848 {
7849 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
7850 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7851 }
7852
7853 /* Set the timer counter reset trigger */
7854 hrtim_timrstr = pTimerCfg->ResetTrigger;
7855
7856 /* Set the timer burst mode */
7857 switch (TimerIdx)
7858 {
7859 case HRTIM_TIMERINDEX_TIMER_A:
7860 {
7861 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7862 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
7863 break;
7864 }
7865
7866 case HRTIM_TIMERINDEX_TIMER_B:
7867 {
7868 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7869 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
7870 break;
7871 }
7872
7873 case HRTIM_TIMERINDEX_TIMER_C:
7874 {
7875 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7876 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
7877 break;
7878 }
7879
7880 case HRTIM_TIMERINDEX_TIMER_D:
7881 {
7882 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7883 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
7884 break;
7885 }
7886
7887 case HRTIM_TIMERINDEX_TIMER_E:
7888 {
7889 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7890 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
7891 break;
7892 }
7893
7894 default:
7895 break;
7896 }
7897
7898 /* Update the HRTIM registers */
7899 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7900 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7901 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7902 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7903 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7904 }
7905
7906 /**
7907 * @brief Configure a capture unit
7908 * @param hhrtim pointer to HAL HRTIM handle
7909 * @param TimerIdx Timer index
7910 * @param CaptureUnit Capture unit identifier
7911 * @param Event Event reference
7912 * @retval None
7913 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)7914 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
7915 uint32_t TimerIdx,
7916 uint32_t CaptureUnit,
7917 uint32_t Event)
7918 {
7919 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7920
7921 switch (Event)
7922 {
7923 case HRTIM_EVENT_1:
7924 {
7925 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7926 break;
7927 }
7928
7929 case HRTIM_EVENT_2:
7930 {
7931 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7932 break;
7933 }
7934
7935 case HRTIM_EVENT_3:
7936 {
7937 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7938 break;
7939 }
7940
7941 case HRTIM_EVENT_4:
7942 {
7943 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7944 break;
7945 }
7946
7947 case HRTIM_EVENT_5:
7948 {
7949 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7950 break;
7951 }
7952
7953 case HRTIM_EVENT_6:
7954 {
7955 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7956 break;
7957 }
7958
7959 case HRTIM_EVENT_7:
7960 {
7961 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7962 break;
7963 }
7964
7965 case HRTIM_EVENT_8:
7966 {
7967 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7968 break;
7969 }
7970
7971 case HRTIM_EVENT_9:
7972 {
7973 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7974 break;
7975 }
7976
7977 case HRTIM_EVENT_10:
7978 {
7979 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7980 break;
7981 }
7982
7983 default:
7984 break;
7985 }
7986
7987 switch (CaptureUnit)
7988 {
7989 case HRTIM_CAPTUREUNIT_1:
7990 {
7991 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7992 break;
7993 }
7994
7995 case HRTIM_CAPTUREUNIT_2:
7996 {
7997 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7998 break;
7999 }
8000
8001 default:
8002 break;
8003 }
8004 }
8005
8006 /**
8007 * @brief Configure the output of a timing unit
8008 * @param hhrtim pointer to HAL HRTIM handle
8009 * @param TimerIdx Timer index
8010 * @param Output timing unit output identifier
8011 * @param pOutputCfg pointer to the output configuration data structure
8012 * @retval None
8013 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)8014 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
8015 uint32_t TimerIdx,
8016 uint32_t Output,
8017 const HRTIM_OutputCfgTypeDef * pOutputCfg)
8018 {
8019 uint32_t hrtim_outr;
8020 uint32_t hrtim_dtr;
8021
8022 uint32_t shift = 0U;
8023
8024 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
8025 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
8026
8027 switch (Output)
8028 {
8029 case HRTIM_OUTPUT_TA1:
8030 case HRTIM_OUTPUT_TB1:
8031 case HRTIM_OUTPUT_TC1:
8032 case HRTIM_OUTPUT_TD1:
8033 case HRTIM_OUTPUT_TE1:
8034 {
8035 /* Set the output set/reset crossbar */
8036 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
8037 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
8038 break;
8039 }
8040
8041 case HRTIM_OUTPUT_TA2:
8042 case HRTIM_OUTPUT_TB2:
8043 case HRTIM_OUTPUT_TC2:
8044 case HRTIM_OUTPUT_TD2:
8045 case HRTIM_OUTPUT_TE2:
8046 {
8047 /* Set the output set/reset crossbar */
8048 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
8049 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
8050 shift = 16U;
8051 break;
8052 }
8053
8054 default:
8055 break;
8056 }
8057
8058 /* Clear output config */
8059 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
8060 HRTIM_OUTR_IDLM1 |
8061 HRTIM_OUTR_IDLES1|
8062 HRTIM_OUTR_FAULT1|
8063 HRTIM_OUTR_CHP1 |
8064 HRTIM_OUTR_DIDL1) << shift);
8065
8066 /* Set the polarity */
8067 hrtim_outr |= (pOutputCfg->Polarity << shift);
8068
8069 /* Set the IDLE mode */
8070 hrtim_outr |= (pOutputCfg->IdleMode << shift);
8071
8072 /* Set the IDLE state */
8073 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
8074
8075 /* Set the FAULT state */
8076 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
8077
8078 /* Set the chopper mode */
8079 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
8080
8081 /* Set the burst mode entry mode : deadtime insertion when entering the idle
8082 state during a burst mode operation is allowed only under the following
8083 conditions:
8084 - the outputs is active during the burst mode (IDLES=1U)
8085 - positive deadtimes (SDTR/SDTF set to 0U)
8086 */
8087 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
8088 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
8089 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
8090 {
8091 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
8092 }
8093
8094 /* Update HRTIM register */
8095 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
8096 }
8097
8098 /**
8099 * @brief Configure an external event channel
8100 * @param hhrtim pointer to HAL HRTIM handle
8101 * @param Event Event channel identifier
8102 * @param pEventCfg pointer to the event channel configuration data structure
8103 * @retval None
8104 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)8105 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
8106 uint32_t Event,
8107 const HRTIM_EventCfgTypeDef *pEventCfg)
8108 {
8109 uint32_t hrtim_eecr1;
8110 uint32_t hrtim_eecr2;
8111 uint32_t hrtim_eecr3;
8112
8113 /* Configure external event channel */
8114 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
8115 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
8116 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
8117
8118 switch (Event)
8119 {
8120 case HRTIM_EVENT_NONE:
8121 {
8122 /* Update the HRTIM registers */
8123 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
8124 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
8125 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
8126 break;
8127 }
8128
8129 case HRTIM_EVENT_1:
8130 {
8131 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
8132 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
8133 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
8134 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
8135 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
8136 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8137 /* Update the HRTIM registers (EE1FAST bit) */
8138 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
8139 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8140 break;
8141 }
8142
8143 case HRTIM_EVENT_2:
8144 {
8145 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
8146 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
8147 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
8148 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
8149 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
8150 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8151 /* Update the HRTIM registers (EE2FAST bit) */
8152 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
8153 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8154 break;
8155 }
8156
8157 case HRTIM_EVENT_3:
8158 {
8159 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
8160 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
8161 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
8162 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
8163 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
8164 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8165 /* Update the HRTIM registers (EE3FAST bit) */
8166 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
8167 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8168 break;
8169 }
8170
8171 case HRTIM_EVENT_4:
8172 {
8173 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8174 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8175 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8176 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8177 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
8178 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8179 /* Update the HRTIM registers (EE4FAST bit) */
8180 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8181 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8182 break;
8183 }
8184
8185 case HRTIM_EVENT_5:
8186 {
8187 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8188 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8189 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8190 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8191 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
8192 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8193 /* Update the HRTIM registers (EE5FAST bit) */
8194 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8195 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8196 break;
8197 }
8198
8199 case HRTIM_EVENT_6:
8200 {
8201 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8202 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8203 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8204 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8205 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8206 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8207 /* Update the HRTIM registers */
8208 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8209 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8210 break;
8211 }
8212
8213 case HRTIM_EVENT_7:
8214 {
8215 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8216 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8217 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8218 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8219 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8220 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8221 /* Update the HRTIM registers */
8222 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8223 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8224 break;
8225 }
8226
8227 case HRTIM_EVENT_8:
8228 {
8229 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8230 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8231 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8232 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8233 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8234 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
8235 /* Update the HRTIM registers */
8236 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8237 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8238 break;
8239 }
8240
8241 case HRTIM_EVENT_9:
8242 {
8243 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8244 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8245 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8246 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8247 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8248 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8249 /* Update the HRTIM registers */
8250 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8251 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8252 break;
8253 }
8254
8255 case HRTIM_EVENT_10:
8256 {
8257 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8258 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8259 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8260 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8261 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8262 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8263 /* Update the HRTIM registers */
8264 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8265 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8266 break;
8267 }
8268
8269 default:
8270 break;
8271 }
8272 }
8273
8274 /**
8275 * @brief Configure the timer counter reset
8276 * @param hhrtim pointer to HAL HRTIM handle
8277 * @param TimerIdx Timer index
8278 * @param Event Event channel identifier
8279 * @retval None
8280 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)8281 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
8282 uint32_t TimerIdx,
8283 uint32_t Event)
8284 {
8285 switch (Event)
8286 {
8287 case HRTIM_EVENT_1:
8288 {
8289 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8290 break;
8291 }
8292
8293 case HRTIM_EVENT_2:
8294 {
8295 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8296 break;
8297 }
8298
8299 case HRTIM_EVENT_3:
8300 {
8301 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8302 break;
8303 }
8304
8305 case HRTIM_EVENT_4:
8306 {
8307 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8308 break;
8309 }
8310
8311 case HRTIM_EVENT_5:
8312 {
8313 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8314 break;
8315 }
8316
8317 case HRTIM_EVENT_6:
8318 {
8319 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8320 break;
8321 }
8322
8323 case HRTIM_EVENT_7:
8324 {
8325 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8326 break;
8327 }
8328
8329 case HRTIM_EVENT_8:
8330 {
8331 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8332 break;
8333 }
8334
8335 case HRTIM_EVENT_9:
8336 {
8337 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8338 break;
8339 }
8340
8341 case HRTIM_EVENT_10:
8342 {
8343 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8344 break;
8345 }
8346
8347 default:
8348 break;
8349 }
8350 }
8351
8352 /**
8353 * @brief Return the interrupt to enable or disable according to the
8354 * OC mode.
8355 * @param hhrtim pointer to HAL HRTIM handle
8356 * @param TimerIdx Timer index
8357 * @param OCChannel Timer output
8358 * This parameter can be one of the following values:
8359 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8360 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8361 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8362 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8363 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8364 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8365 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8366 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8367 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8368 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8369 * @retval Interrupt to enable or disable
8370 */
HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8371 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8372 uint32_t TimerIdx,
8373 uint32_t OCChannel)
8374 {
8375 uint32_t hrtim_set;
8376 uint32_t hrtim_reset;
8377 uint32_t interrupt = 0U;
8378
8379 switch (OCChannel)
8380 {
8381 case HRTIM_OUTPUT_TA1:
8382 case HRTIM_OUTPUT_TB1:
8383 case HRTIM_OUTPUT_TC1:
8384 case HRTIM_OUTPUT_TD1:
8385 case HRTIM_OUTPUT_TE1:
8386 {
8387 /* Retrieves actual OC mode and set interrupt accordingly */
8388 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8389 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8390
8391 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8392 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8393 {
8394 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8395 interrupt = HRTIM_TIM_IT_CMP1;
8396 }
8397 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8398 (hrtim_reset == 0U))
8399 {
8400 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8401 interrupt = HRTIM_TIM_IT_SET1;
8402 }
8403 else if ((hrtim_set == 0U) &&
8404 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8405 {
8406 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8407 interrupt = HRTIM_TIM_IT_RST1;
8408 }
8409 else
8410 {
8411 /* nothing to do */
8412 }
8413 break;
8414 }
8415
8416 case HRTIM_OUTPUT_TA2:
8417 case HRTIM_OUTPUT_TB2:
8418 case HRTIM_OUTPUT_TC2:
8419 case HRTIM_OUTPUT_TD2:
8420 case HRTIM_OUTPUT_TE2:
8421 {
8422 /* Retrieves actual OC mode and set interrupt accordingly */
8423 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8424 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8425
8426 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8427 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8428 {
8429 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8430 interrupt = HRTIM_TIM_IT_CMP2;
8431 }
8432 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8433 (hrtim_reset == 0U))
8434 {
8435 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8436 interrupt = HRTIM_TIM_IT_SET2;
8437 }
8438 else if ((hrtim_set == 0U) &&
8439 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8440 {
8441 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8442 interrupt = HRTIM_TIM_IT_RST2;
8443 }
8444 else
8445 {
8446 /* nothing to do */
8447 }
8448 break;
8449 }
8450
8451 default:
8452 break;
8453 }
8454
8455 return interrupt;
8456 }
8457
8458 /**
8459 * @brief Return the DMA request to enable or disable according to the
8460 * OC mode.
8461 * @param hhrtim pointer to HAL HRTIM handle
8462 * @param TimerIdx Timer index
8463 * @param OCChannel Timer output
8464 * This parameter can be one of the following values:
8465 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8466 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8467 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8468 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8469 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8470 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8471 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8472 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8473 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8474 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8475 * @retval DMA request to enable or disable
8476 */
HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8477 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
8478 uint32_t TimerIdx,
8479 uint32_t OCChannel)
8480 {
8481 uint32_t hrtim_set;
8482 uint32_t hrtim_reset;
8483 uint32_t dma_request = 0U;
8484
8485 switch (OCChannel)
8486 {
8487 case HRTIM_OUTPUT_TA1:
8488 case HRTIM_OUTPUT_TB1:
8489 case HRTIM_OUTPUT_TC1:
8490 case HRTIM_OUTPUT_TD1:
8491 case HRTIM_OUTPUT_TE1:
8492 {
8493 /* Retrieves actual OC mode and set dma_request accordingly */
8494 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8495 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8496
8497 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8498 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8499 {
8500 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8501 dma_request = HRTIM_TIM_DMA_CMP1;
8502 }
8503 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8504 (hrtim_reset == 0U))
8505 {
8506 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8507 dma_request = HRTIM_TIM_DMA_SET1;
8508 }
8509 else if ((hrtim_set == 0U) &&
8510 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8511 {
8512 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8513 dma_request = HRTIM_TIM_DMA_RST1;
8514 }
8515 else
8516 {
8517 /* nothing to do */
8518 }
8519 break;
8520 }
8521
8522 case HRTIM_OUTPUT_TA2:
8523 case HRTIM_OUTPUT_TB2:
8524 case HRTIM_OUTPUT_TC2:
8525 case HRTIM_OUTPUT_TD2:
8526 case HRTIM_OUTPUT_TE2:
8527 {
8528 /* Retrieves actual OC mode and set dma_request accordingly */
8529 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8530 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8531
8532 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8533 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8534 {
8535 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8536 dma_request = HRTIM_TIM_DMA_CMP2;
8537 }
8538 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8539 (hrtim_reset == 0U))
8540 {
8541 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8542 dma_request = HRTIM_TIM_DMA_SET2;
8543 }
8544 else if ((hrtim_set == 0U) &&
8545 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8546 {
8547 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8548 dma_request = HRTIM_TIM_DMA_RST2;
8549 }
8550 else
8551 {
8552 /* nothing to do */
8553 }
8554 break;
8555 }
8556
8557 default:
8558 break;
8559 }
8560
8561 return dma_request;
8562 }
8563
HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8564 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
8565 uint32_t TimerIdx)
8566 {
8567 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
8568
8569 switch (TimerIdx)
8570 {
8571 case HRTIM_TIMERINDEX_MASTER:
8572 {
8573 hdma = hhrtim->hdmaMaster;
8574 break;
8575 }
8576
8577 case HRTIM_TIMERINDEX_TIMER_A:
8578 {
8579 hdma = hhrtim->hdmaTimerA;
8580 break;
8581 }
8582
8583 case HRTIM_TIMERINDEX_TIMER_B:
8584 {
8585 hdma = hhrtim->hdmaTimerB;
8586 break;
8587 }
8588
8589 case HRTIM_TIMERINDEX_TIMER_C:
8590 {
8591 hdma = hhrtim->hdmaTimerC;
8592 break;
8593 }
8594
8595 case HRTIM_TIMERINDEX_TIMER_D:
8596 {
8597 hdma = hhrtim->hdmaTimerD;
8598 break;
8599 }
8600
8601 case HRTIM_TIMERINDEX_TIMER_E:
8602 {
8603 hdma = hhrtim->hdmaTimerE;
8604 break;
8605 }
8606
8607 default:
8608 break;
8609 }
8610
8611 return hdma;
8612 }
8613
GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,const DMA_HandleTypeDef * hdma)8614 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
8615 const DMA_HandleTypeDef * hdma)
8616 {
8617 uint32_t timed_idx = 0xFFFFFFFFU;
8618
8619 if (hdma == hhrtim->hdmaMaster)
8620 {
8621 timed_idx = HRTIM_TIMERINDEX_MASTER;
8622 }
8623 else if (hdma == hhrtim->hdmaTimerA)
8624 {
8625 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8626 }
8627 else if (hdma == hhrtim->hdmaTimerB)
8628 {
8629 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8630 }
8631 else if (hdma == hhrtim->hdmaTimerC)
8632 {
8633 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8634 }
8635 else if (hdma == hhrtim->hdmaTimerD)
8636 {
8637 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8638 }
8639 else if (hdma == hhrtim->hdmaTimerE)
8640 {
8641 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8642 }
8643 else
8644 {
8645 /* nothing to do */
8646 }
8647 return timed_idx;
8648 }
8649
8650 /**
8651 * @brief Force an immediate transfer from the preload to the active
8652 * registers.
8653 * @param hhrtim pointer to HAL HRTIM handle
8654 * @param TimerIdx Timer index
8655 * @retval None
8656 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8657 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
8658 uint32_t TimerIdx)
8659 {
8660 switch (TimerIdx)
8661 {
8662 case HRTIM_TIMERINDEX_MASTER:
8663 {
8664 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8665 break;
8666 }
8667
8668 case HRTIM_TIMERINDEX_TIMER_A:
8669 {
8670 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8671 break;
8672 }
8673
8674 case HRTIM_TIMERINDEX_TIMER_B:
8675 {
8676 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8677 break;
8678 }
8679
8680 case HRTIM_TIMERINDEX_TIMER_C:
8681 {
8682 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8683 break;
8684 }
8685
8686 case HRTIM_TIMERINDEX_TIMER_D:
8687 {
8688 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8689 break;
8690 }
8691
8692 case HRTIM_TIMERINDEX_TIMER_E:
8693 {
8694 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8695 break;
8696 }
8697
8698 default:
8699 break;
8700 }
8701 }
8702
8703
8704 /**
8705 * @brief HRTIM interrupts service routine
8706 * @param hhrtim pointer to HAL HRTIM handle
8707 * @retval None
8708 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)8709 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
8710 {
8711 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8712 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8713
8714 /* Fault 1 event */
8715 if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8716 {
8717 if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
8718 {
8719 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8720
8721 /* Invoke Fault 1 event callback */
8722 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8723 hhrtim->Fault1Callback(hhrtim);
8724 #else
8725 HAL_HRTIM_Fault1Callback(hhrtim);
8726 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8727 }
8728 }
8729
8730 /* Fault 2 event */
8731 if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8732 {
8733 if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
8734 {
8735 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8736
8737 /* Invoke Fault 2 event callback */
8738 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8739 hhrtim->Fault2Callback(hhrtim);
8740 #else
8741 HAL_HRTIM_Fault2Callback(hhrtim);
8742 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8743 }
8744 }
8745
8746 /* Fault 3 event */
8747 if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8748 {
8749 if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
8750 {
8751 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8752
8753 /* Invoke Fault 3 event callback */
8754 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8755 hhrtim->Fault3Callback(hhrtim);
8756 #else
8757 HAL_HRTIM_Fault3Callback(hhrtim);
8758 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8759 }
8760 }
8761
8762 /* Fault 4 event */
8763 if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8764 {
8765 if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
8766 {
8767 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8768
8769 /* Invoke Fault 4 event callback */
8770 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8771 hhrtim->Fault4Callback(hhrtim);
8772 #else
8773 HAL_HRTIM_Fault4Callback(hhrtim);
8774 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8775 }
8776 }
8777
8778 /* Fault 5 event */
8779 if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8780 {
8781 if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
8782 {
8783 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8784
8785 /* Invoke Fault 5 event callback */
8786 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8787 hhrtim->Fault5Callback(hhrtim);
8788 #else
8789 HAL_HRTIM_Fault5Callback(hhrtim);
8790 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8791 }
8792 }
8793
8794 /* System fault event */
8795 if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8796 {
8797 if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
8798 {
8799 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8800
8801 /* Invoke System fault event callback */
8802 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8803 hhrtim->SystemFaultCallback(hhrtim);
8804 #else
8805 HAL_HRTIM_SystemFaultCallback(hhrtim);
8806 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8807 }
8808 }
8809 }
8810
8811 /**
8812 * @brief Master timer interrupts service routine
8813 * @param hhrtim pointer to HAL HRTIM handle
8814 * @retval None
8815 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)8816 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
8817 {
8818 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8819 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8820 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
8821 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
8822
8823 /* DLL calibration ready event */
8824 if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
8825 {
8826 if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
8827 {
8828 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
8829
8830 /* Set HRTIM State */
8831 hhrtim->State = HAL_HRTIM_STATE_READY;
8832
8833 /* Process unlocked */
8834 __HAL_UNLOCK(hhrtim);
8835
8836 /* Invoke System fault event callback */
8837 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8838 hhrtim->DLLCalibrationReadyCallback(hhrtim);
8839 #else
8840 HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
8841 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8842 }
8843 }
8844
8845 /* Burst mode period event */
8846 if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8847 {
8848 if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
8849 {
8850 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8851
8852 /* Invoke Burst mode period event callback */
8853 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8854 hhrtim->BurstModePeriodCallback(hhrtim);
8855 #else
8856 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8857 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8858 }
8859 }
8860
8861 /* Master timer compare 1 event */
8862 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8863 {
8864 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
8865 {
8866 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8867
8868 /* Invoke compare 1 event callback */
8869 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8870 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8871 #else
8872 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8873 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8874 }
8875 }
8876
8877 /* Master timer compare 2 event */
8878 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8879 {
8880 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
8881 {
8882 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8883
8884 /* Invoke compare 2 event callback */
8885 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8886 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8887 #else
8888 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8889 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8890 }
8891 }
8892
8893 /* Master timer compare 3 event */
8894 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8895 {
8896 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
8897 {
8898 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8899
8900 /* Invoke compare 3 event callback */
8901 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8902 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8903 #else
8904 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8905 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8906 }
8907 }
8908
8909 /* Master timer compare 4 event */
8910 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8911 {
8912 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
8913 {
8914 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8915
8916 /* Invoke compare 4 event callback */
8917 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8918 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8919 #else
8920 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8921 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8922 }
8923 }
8924
8925 /* Master timer repetition event */
8926 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8927 {
8928 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
8929 {
8930 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8931
8932 /* Invoke repetition event callback */
8933 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8934 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8935 #else
8936 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8937 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8938 }
8939 }
8940
8941 /* Synchronization input event */
8942 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8943 {
8944 if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
8945 {
8946 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8947
8948 /* Invoke synchronization event callback */
8949 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8950 hhrtim->SynchronizationEventCallback(hhrtim);
8951 #else
8952 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8953 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8954 }
8955 }
8956
8957 /* Master timer registers update event */
8958 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8959 {
8960 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
8961 {
8962 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8963
8964 /* Invoke registers update event callback */
8965 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8966 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8967 #else
8968 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8969 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8970 }
8971 }
8972 }
8973
8974 /**
8975 * @brief Timer interrupts service routine
8976 * @param hhrtim pointer to HAL HRTIM handle
8977 * @param TimerIdx Timer index
8978 * This parameter can be one of the following values:
8979 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8980 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8981 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8982 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8983 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8984 * @retval None
8985 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8986 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
8987 uint32_t TimerIdx)
8988 {
8989 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
8990 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
8991
8992 /* Timer compare 1 event */
8993 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8994 {
8995 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
8996 {
8997 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8998
8999 /* Invoke compare 1 event callback */
9000 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9001 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
9002 #else
9003 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
9004 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9005 }
9006 }
9007
9008 /* Timer compare 2 event */
9009 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
9010 {
9011 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
9012 {
9013 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
9014
9015 /* Invoke compare 2 event callback */
9016 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9017 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
9018 #else
9019 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
9020 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9021 }
9022 }
9023
9024 /* Timer compare 3 event */
9025 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
9026 {
9027 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
9028 {
9029 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
9030
9031 /* Invoke compare 3 event callback */
9032 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9033 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
9034 #else
9035 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
9036 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9037 }
9038 }
9039
9040 /* Timer compare 4 event */
9041 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
9042 {
9043 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
9044 {
9045 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
9046
9047 /* Invoke compare 4 event callback */
9048 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9049 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
9050 #else
9051 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
9052 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9053 }
9054 }
9055
9056 /* Timer repetition event */
9057 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
9058 {
9059 if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
9060 {
9061 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
9062
9063 /* Invoke repetition event callback */
9064 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9065 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
9066 #else
9067 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
9068 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9069 }
9070 }
9071
9072 /* Timer registers update event */
9073 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
9074 {
9075 if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
9076 {
9077 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
9078
9079 /* Invoke registers update event callback */
9080 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9081 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
9082 #else
9083 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
9084 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9085 }
9086 }
9087
9088 /* Timer capture 1 event */
9089 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
9090 {
9091 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
9092 {
9093 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
9094
9095 /* Invoke capture 1 event callback */
9096 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9097 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
9098 #else
9099 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
9100 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9101 }
9102 }
9103
9104 /* Timer capture 2 event */
9105 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
9106 {
9107 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
9108 {
9109 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
9110
9111 /* Invoke capture 2 event callback */
9112 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9113 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
9114 #else
9115 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
9116 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9117 }
9118 }
9119
9120 /* Timer output 1 set event */
9121 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
9122 {
9123 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
9124 {
9125 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
9126
9127 /* Invoke output 1 set event callback */
9128 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9129 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
9130 #else
9131 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
9132 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9133 }
9134 }
9135
9136 /* Timer output 1 reset event */
9137 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
9138 {
9139 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
9140 {
9141 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
9142
9143 /* Invoke output 1 reset event callback */
9144 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9145 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
9146 #else
9147 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
9148 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9149 }
9150 }
9151
9152 /* Timer output 2 set event */
9153 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
9154 {
9155 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
9156 {
9157 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
9158
9159 /* Invoke output 2 set event callback */
9160 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9161 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
9162 #else
9163 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
9164 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9165 }
9166 }
9167
9168 /* Timer output 2 reset event */
9169 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
9170 {
9171 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
9172 {
9173 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
9174
9175 /* Invoke output 2 reset event callback */
9176 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9177 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
9178 #else
9179 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
9180 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9181 }
9182 }
9183
9184 /* Timer reset event */
9185 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
9186 {
9187 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
9188 {
9189 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
9190
9191 /* Invoke timer reset callback */
9192 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9193 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
9194 #else
9195 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
9196 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9197 }
9198 }
9199
9200 /* Delayed protection event */
9201 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9202 {
9203 if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
9204 {
9205 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9206
9207 /* Invoke delayed protection callback */
9208 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9209 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9210 #else
9211 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9212 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9213 }
9214 }
9215 }
9216
9217 /**
9218 * @brief DMA callback invoked upon master timer related DMA request completion
9219 * @param hdma pointer to DMA handle.
9220 * @retval None
9221 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)9222 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9223 {
9224 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9225
9226 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9227 {
9228 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9229 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9230 #else
9231 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9232 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9233 }
9234 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9235 {
9236 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9237 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9238 #else
9239 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9240 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9241 }
9242 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9243 {
9244 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9245 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9246 #else
9247 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9248 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9249 }
9250 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9251 {
9252 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9253 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9254 #else
9255 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9256 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9257 }
9258 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9259 {
9260 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9261 hrtim->SynchronizationEventCallback(hrtim);
9262 #else
9263 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9264 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9265 }
9266 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9267 {
9268 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9269 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9270 #else
9271 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9272 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9273 }
9274 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9275 {
9276 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9277 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9278 #else
9279 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9280 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9281 }
9282 else
9283 {
9284 /* nothing to do */
9285 }
9286 }
9287
9288 /**
9289 * @brief DMA callback invoked upon timer A..E related DMA request completion
9290 * @param hdma pointer to DMA handle.
9291 * @retval None
9292 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)9293 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9294 {
9295 uint8_t timer_idx;
9296
9297 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9298
9299 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9300
9301 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
9302
9303 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9304 {
9305 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9306 hrtim->Compare1EventCallback(hrtim, timer_idx);
9307 #else
9308 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9309 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9310 }
9311 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9312 {
9313 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9314 hrtim->Compare2EventCallback(hrtim, timer_idx);
9315 #else
9316 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9317 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9318 }
9319 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9320 {
9321 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9322 hrtim->Compare3EventCallback(hrtim, timer_idx);
9323 #else
9324 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9325 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9326 }
9327 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9328 {
9329 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9330 hrtim->Compare4EventCallback(hrtim, timer_idx);
9331 #else
9332 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9333 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9334 }
9335 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9336 {
9337 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9338 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9339 #else
9340 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9341 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9342 }
9343 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9344 {
9345 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9346 hrtim->Capture1EventCallback(hrtim, timer_idx);
9347 #else
9348 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9349 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9350 }
9351 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9352 {
9353 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9354 hrtim->Capture2EventCallback(hrtim, timer_idx);
9355 #else
9356 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9357 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9358 }
9359 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9360 {
9361 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9362 hrtim->Output1SetCallback(hrtim, timer_idx);
9363 #else
9364 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9365 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9366 }
9367 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9368 {
9369 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9370 hrtim->Output1ResetCallback(hrtim, timer_idx);
9371 #else
9372 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9373 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9374 }
9375 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9376 {
9377 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9378 hrtim->Output2SetCallback(hrtim, timer_idx);
9379 #else
9380 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9381 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9382 }
9383 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9384 {
9385 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9386 hrtim->Output2ResetCallback(hrtim, timer_idx);
9387 #else
9388 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9389 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9390 }
9391 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9392 {
9393 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9394 hrtim->CounterResetCallback(hrtim, timer_idx);
9395 #else
9396 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9397 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9398 }
9399 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9400 {
9401 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9402 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9403 #else
9404 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9405 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9406 }
9407 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9408 {
9409 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9410 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9411 #else
9412 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9413 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9414 }
9415 else
9416 {
9417 /* nothing to do */
9418 }
9419 }
9420
9421 /**
9422 * @brief DMA error callback
9423 * @param hdma pointer to DMA handle.
9424 * @retval None
9425 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)9426 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9427 {
9428 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9429
9430 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9431 hrtim->ErrorCallback(hrtim);
9432 #else
9433 HAL_HRTIM_ErrorCallback(hrtim);
9434 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9435 }
9436
9437 /**
9438 * @brief DMA callback invoked upon burst DMA transfer completion
9439 * @param hdma pointer to DMA handle.
9440 * @retval None
9441 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)9442 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9443 {
9444 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
9445
9446 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9447 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9448 #else
9449 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9450 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9451 }
9452
9453 /**
9454 * @}
9455 */
9456
9457 /**
9458 * @}
9459 */
9460
9461 #endif /* HRTIM1 */
9462
9463 #endif /* HAL_HRTIM_MODULE_ENABLED */
9464
9465 /**
9466 * @}
9467 */
9468
