1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 * @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX HAL driver ***
18 ===========================================================
19 [..]
20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M4 exceptions are managed by CMSIS functions.
22
23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
24
25 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
26
27 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
28
29
30 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
31 The pending IRQ priority will be managed only by the sub priority.
32
33 -@- IRQ priority order (sorted by highest to lowest priority):
34 (+@) Lowest pre-emption priority
35 (+@) Lowest sub priority
36 (+@) Lowest hardware priority (IRQ number)
37
38 [..]
39 *** How to configure Systick using CORTEX HAL driver ***
40 ========================================================
41 [..]
42 Setup SysTick Timer for time base
43
44 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
45 is a CMSIS function that:
46 (++) Configures the SysTick Reload register with value passed as function parameter.
47 (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
48 (++) Resets the SysTick Counter register.
49 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
50 (++) Enables the SysTick Interrupt.
51 (++) Starts the SysTick Counter.
52
53 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
54 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
55 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
56 inside the stm32f3xx_hal_cortex.h file.
57
58 (+) You can change the SysTick IRQ priority by calling the
59 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
60 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
61
62 (+) To adjust the SysTick time base, use the following formula:
63
64 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
65 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
66 (++) Reload Value should not exceed 0xFFFFFF
67
68 @endverbatim
69 ******************************************************************************
70 * @attention
71 *
72 * Copyright (c) 2016 STMicroelectronics.
73 * All rights reserved.
74 *
75 * This software is licensed under terms that can be found in the LICENSE file in
76 * the root directory of this software component.
77 * If no LICENSE file comes with this software, it is provided AS-IS.
78 *
79 ******************************************************************************
80 */
81
82 /*
83 Additional Tables: CORTEX_NVIC_Priority_Table
84 The table below gives the allowed values of the pre-emption priority and subpriority according
85 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
86 ==========================================================================================================================
87 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
88 ==========================================================================================================================
89 NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority
90 | | | 4 bits for subpriority
91 --------------------------------------------------------------------------------------------------------------------------
92 NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority
93 | | | 3 bits for subpriority
94 --------------------------------------------------------------------------------------------------------------------------
95 NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority
96 | | | 2 bits for subpriority
97 --------------------------------------------------------------------------------------------------------------------------
98 NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority
99 | | | 1 bits for subpriority
100 --------------------------------------------------------------------------------------------------------------------------
101 NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority
102 | | | 0 bits for subpriority
103 ==========================================================================================================================
104
105 */
106
107 /* Includes ------------------------------------------------------------------*/
108 #include "stm32f3xx_hal.h"
109
110 /** @addtogroup STM32F3xx_HAL_Driver
111 * @{
112 */
113
114 /** @defgroup CORTEX CORTEX
115 * @brief CORTEX CORTEX HAL module driver
116 * @{
117 */
118
119 #ifdef HAL_CORTEX_MODULE_ENABLED
120
121 /* Private typedef -----------------------------------------------------------*/
122 /* Private define ------------------------------------------------------------*/
123 /* Private macro -------------------------------------------------------------*/
124 /* Private variables ---------------------------------------------------------*/
125 /* Private function prototypes -----------------------------------------------*/
126 /* Exported functions ---------------------------------------------------------*/
127
128 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
129 * @{
130 */
131
132
133 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
134 * @brief Initialization and Configuration functions
135 *
136 @verbatim
137 ==============================================================================
138 ##### Initialization and de-initialization functions #####
139 ==============================================================================
140 [..]
141 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
142 Systick functionalities
143
144 @endverbatim
145 * @{
146 */
147
148
149 /**
150 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
151 * using the required unlock sequence.
152 * @param PriorityGroup The priority grouping bits length.
153 * This parameter can be one of the following values:
154 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
155 * 4 bits for subpriority
156 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
157 * 3 bits for subpriority
158 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
159 * 2 bits for subpriority
160 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
161 * 1 bits for subpriority
162 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
163 * 0 bits for subpriority
164 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
165 * The pending IRQ priority will be managed only by the subpriority.
166 * @retval None
167 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)168 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
169 {
170 /* Check the parameters */
171 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
172
173 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
174 NVIC_SetPriorityGrouping(PriorityGroup);
175 }
176
177 /**
178 * @brief Sets the priority of an interrupt.
179 * @param IRQn External interrupt number
180 * This parameter can be an enumerator of IRQn_Type enumeration
181 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
182 * @param PreemptPriority The pre-emption priority for the IRQn channel.
183 * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
184 * A lower priority value indicates a higher priority
185 * @param SubPriority the subpriority level for the IRQ channel.
186 * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
187 * A lower priority value indicates a higher priority.
188 * @retval None
189 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)190 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
191 {
192 uint32_t prioritygroup = 0x00U;
193
194 /* Check the parameters */
195 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
196 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
197
198 prioritygroup = NVIC_GetPriorityGrouping();
199
200 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
201 }
202
203 /**
204 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
205 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
206 * function should be called before.
207 * @param IRQn External interrupt number
208 * This parameter can be an enumerator of IRQn_Type enumeration
209 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
210 * @retval None
211 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)212 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
213 {
214 /* Check the parameters */
215 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
216
217 /* Enable interrupt */
218 NVIC_EnableIRQ(IRQn);
219 }
220
221 /**
222 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
223 * @param IRQn External interrupt number
224 * This parameter can be an enumerator of IRQn_Type enumeration
225 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
226 * @retval None
227 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)228 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
229 {
230 /* Check the parameters */
231 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
232
233 /* Disable interrupt */
234 NVIC_DisableIRQ(IRQn);
235 }
236
237 /**
238 * @brief Initiates a system reset request to reset the MCU.
239 * @retval None
240 */
HAL_NVIC_SystemReset(void)241 void HAL_NVIC_SystemReset(void)
242 {
243 /* System Reset */
244 NVIC_SystemReset();
245 }
246
247 /**
248 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
249 * Counter is in free running mode to generate periodic interrupts.
250 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
251 * @retval status: - 0 Function succeeded.
252 * - 1 Function failed.
253 */
HAL_SYSTICK_Config(uint32_t TicksNumb)254 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
255 {
256 return SysTick_Config(TicksNumb);
257 }
258 /**
259 * @}
260 */
261
262 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
263 * @brief Cortex control functions
264 *
265 @verbatim
266 ==============================================================================
267 ##### Peripheral Control functions #####
268 ==============================================================================
269 [..]
270 This subsection provides a set of functions allowing to control the CORTEX
271 (NVIC, SYSTICK, MPU) functionalities.
272
273
274 @endverbatim
275 * @{
276 */
277
278 #if (__MPU_PRESENT == 1U)
279
280 /**
281 * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
282 * @retval None
283 */
HAL_MPU_Disable(void)284 void HAL_MPU_Disable(void)
285 {
286 /* Disable fault exceptions */
287 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
288
289 /* Disable the MPU */
290 MPU->CTRL = 0U;
291 }
292
293 /**
294 * @brief Enables the MPU
295 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
296 * NMI, FAULTMASK and privileged access to the default memory
297 * This parameter can be one of the following values:
298 * @arg MPU_HFNMI_PRIVDEF_NONE
299 * @arg MPU_HARDFAULT_NMI
300 * @arg MPU_PRIVILEGED_DEFAULT
301 * @arg MPU_HFNMI_PRIVDEF
302 * @retval None
303 */
HAL_MPU_Enable(uint32_t MPU_Control)304 void HAL_MPU_Enable(uint32_t MPU_Control)
305 {
306 /* Enable the MPU */
307 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
308
309 /* Enable fault exceptions */
310 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
311 }
312
313 /**
314 * @brief Initializes and configures the Region and the memory to be protected.
315 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
316 * the initialization and configuration information.
317 * @retval None
318 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)319 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
320 {
321 /* Check the parameters */
322 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
323 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
324
325 /* Set the Region number */
326 MPU->RNR = MPU_Init->Number;
327
328 if ((MPU_Init->Enable) != RESET)
329 {
330 /* Check the parameters */
331 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
332 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
333 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
334 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
335 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
336 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
337 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
338 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
339
340 MPU->RBAR = MPU_Init->BaseAddress;
341 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
342 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
343 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
344 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
345 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
346 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
347 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
348 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
349 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
350 }
351 else
352 {
353 MPU->RBAR = 0x00U;
354 MPU->RASR = 0x00U;
355 }
356 }
357 #endif /* __MPU_PRESENT */
358
359 /**
360 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
361 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
362 */
HAL_NVIC_GetPriorityGrouping(void)363 uint32_t HAL_NVIC_GetPriorityGrouping(void)
364 {
365 /* Get the PRIGROUP[10:8] field value */
366 return NVIC_GetPriorityGrouping();
367 }
368
369 /**
370 * @brief Gets the priority of an interrupt.
371 * @param IRQn External interrupt number
372 * This parameter can be an enumerator of IRQn_Type enumeration
373 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
374 * @param PriorityGroup: the priority grouping bits length.
375 * This parameter can be one of the following values:
376 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
377 * 4 bits for subpriority
378 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
379 * 3 bits for subpriority
380 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
381 * 2 bits for subpriority
382 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
383 * 1 bits for subpriority
384 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
385 * 0 bits for subpriority
386 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
387 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
388 * @retval None
389 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)390 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
391 {
392 /* Check the parameters */
393 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
394 /* Get priority for Cortex-M system or device specific interrupts */
395 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
396 }
397
398 /**
399 * @brief Sets Pending bit of an external interrupt.
400 * @param IRQn External interrupt number
401 * This parameter can be an enumerator of IRQn_Type enumeration
402 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
403 * @retval None
404 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)405 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
406 {
407 /* Set interrupt pending */
408 NVIC_SetPendingIRQ(IRQn);
409 }
410
411 /**
412 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
413 * and returns the pending bit for the specified interrupt).
414 * @param IRQn External interrupt number
415 * This parameter can be an enumerator of IRQn_Type enumeration
416 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
417 * @retval status: - 0 Interrupt status is not pending.
418 * - 1 Interrupt status is pending.
419 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)420 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
421 {
422 /* Return 1 if pending else 0U */
423 return NVIC_GetPendingIRQ(IRQn);
424 }
425
426 /**
427 * @brief Clears the pending bit of an external interrupt.
428 * @param IRQn External interrupt number
429 * This parameter can be an enumerator of IRQn_Type enumeration
430 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
431 * @retval None
432 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)433 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
434 {
435 /* Clear pending interrupt */
436 NVIC_ClearPendingIRQ(IRQn);
437 }
438
439 /**
440 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
441 * @param IRQn External interrupt number
442 * This parameter can be an enumerator of IRQn_Type enumeration
443 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
444 * @retval status: - 0 Interrupt status is not pending.
445 * - 1 Interrupt status is pending.
446 */
HAL_NVIC_GetActive(IRQn_Type IRQn)447 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
448 {
449 /* Return 1 if active else 0U */
450 return NVIC_GetActive(IRQn);
451 }
452
453 /**
454 * @brief Configures the SysTick clock source.
455 * @param CLKSource specifies the SysTick clock source.
456 * This parameter can be one of the following values:
457 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
458 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
459 * @retval None
460 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)461 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
462 {
463 /* Check the parameters */
464 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
465 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
466 {
467 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
468 }
469 else
470 {
471 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
472 }
473 }
474
475 /**
476 * @brief This function handles SYSTICK interrupt request.
477 * @retval None
478 */
HAL_SYSTICK_IRQHandler(void)479 void HAL_SYSTICK_IRQHandler(void)
480 {
481 HAL_SYSTICK_Callback();
482 }
483
484 /**
485 * @brief SYSTICK callback.
486 * @retval None
487 */
HAL_SYSTICK_Callback(void)488 __weak void HAL_SYSTICK_Callback(void)
489 {
490 /* NOTE : This function Should not be modified, when the callback is needed,
491 the HAL_SYSTICK_Callback could be implemented in the user file
492 */
493 }
494
495 /**
496 * @}
497 */
498
499 /**
500 * @}
501 */
502
503 #endif /* HAL_CORTEX_MODULE_ENABLED */
504 /**
505 * @}
506 */
507
508 /**
509 * @}
510 */
511
512
