1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F3xx_LL_UTILS_H
34 #define __STM32F3xx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f3xx.h"
42
43 /** @addtogroup STM32F3xx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @brief Package data register base address
74 */
75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 /* Exported types ------------------------------------------------------------*/
89 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
90 * @{
91 */
92 /**
93 * @brief UTILS PLL structure definition
94 */
95 typedef struct
96 {
97 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102
103 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
104 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
105 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
109 #else
110 uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
111 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
115 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
116 } LL_UTILS_PLLInitTypeDef;
117
118 /**
119 * @brief UTILS System, AHB and APB buses clock configuration structure definition
120 */
121 typedef struct
122 {
123 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
124 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_RCC_SetAHBPrescaler(). */
128
129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
130 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
131
132 This feature can be modified afterwards using unitary function
133 @ref LL_RCC_SetAPB1Prescaler(). */
134
135 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
136 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
137
138 This feature can be modified afterwards using unitary function
139 @ref LL_RCC_SetAPB2Prescaler(). */
140
141 } LL_UTILS_ClkInitTypeDef;
142
143 /**
144 * @}
145 */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
149 * @{
150 */
151
152 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
153 * @{
154 */
155 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
156 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
157 /**
158 * @}
159 */
160
161 /**
162 * @}
163 */
164
165 /* Exported macro ------------------------------------------------------------*/
166
167 /* Exported functions --------------------------------------------------------*/
168 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
169 * @{
170 */
171
172 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
173 * @{
174 */
175
176 /**
177 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
178 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
179 */
LL_GetUID_Word0(void)180 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
181 {
182 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
183 }
184
185 /**
186 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
187 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
188 */
LL_GetUID_Word1(void)189 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
190 {
191 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
192 }
193
194 /**
195 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
196 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
197 */
LL_GetUID_Word2(void)198 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
199 {
200 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
201 }
202
203 /**
204 * @brief Get Flash memory size
205 * @note This bitfield indicates the size of the device Flash memory expressed in
206 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
207 * @retval FLASH_SIZE[15:0]: Flash memory size
208 */
LL_GetFlashSize(void)209 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
210 {
211 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
212 }
213
214
215 /**
216 * @}
217 */
218
219 /** @defgroup UTILS_LL_EF_DELAY DELAY
220 * @{
221 */
222
223 /**
224 * @brief This function configures the Cortex-M SysTick source of the time base.
225 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
226 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
227 * configuration by calling this function, for a delay use rather osDelay RTOS service.
228 * @param Ticks Number of ticks
229 * @retval None
230 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)231 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
232 {
233 /* Configure the SysTick to have interrupt in 1ms time base */
234 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
235 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
236 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
237 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
238 }
239
240 void LL_Init1msTick(uint32_t HCLKFrequency);
241 void LL_mDelay(uint32_t Delay);
242
243 /**
244 * @}
245 */
246
247 /** @defgroup UTILS_EF_SYSTEM SYSTEM
248 * @{
249 */
250
251 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
252 #if defined(FLASH_ACR_LATENCY)
253 ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
254 #endif /* FLASH_ACR_LATENCY */
255 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
256 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
257 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
258 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
259 ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
260
261 /**
262 * @}
263 */
264
265 /**
266 * @}
267 */
268
269 /**
270 * @}
271 */
272
273 /**
274 * @}
275 */
276
277 #ifdef __cplusplus
278 }
279 #endif
280
281 #endif /* __STM32F3xx_LL_UTILS_H */
282
