1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_TIM_H
21 #define __STM32F3xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118
119 #define TIMx_OR_RMP_SHIFT 16U
120 #define TIMx_OR_RMP_MASK 0x0000FFFFU
121 #if defined(TIM1)
122 #define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
123 #endif /* TIM1 */
124 #if defined (TIM8)
125 #define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
126 #endif /* TIM8 */
127 #if defined(TIM14)
128 #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
129 #endif /* TIM14 */
130 #if defined(TIM16)
131 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132 #endif /* TIM16 */
133 #if defined(TIM20)
134 #define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
135 #endif /* TIM20 */
136
137 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
138 #define DT_DELAY_1 ((uint8_t)0x7F)
139 #define DT_DELAY_2 ((uint8_t)0x3F)
140 #define DT_DELAY_3 ((uint8_t)0x1F)
141 #define DT_DELAY_4 ((uint8_t)0x1F)
142
143 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
144 #define DT_RANGE_1 ((uint8_t)0x00)
145 #define DT_RANGE_2 ((uint8_t)0x80)
146 #define DT_RANGE_3 ((uint8_t)0xC0)
147 #define DT_RANGE_4 ((uint8_t)0xE0)
148
149
150 /**
151 * @}
152 */
153
154 /* Private macros ------------------------------------------------------------*/
155 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
156 * @{
157 */
158 /** @brief Convert channel id into channel index.
159 * @param __CHANNEL__ This parameter can be one of the following values:
160 * @arg @ref LL_TIM_CHANNEL_CH1
161 * @arg @ref LL_TIM_CHANNEL_CH1N
162 * @arg @ref LL_TIM_CHANNEL_CH2
163 * @arg @ref LL_TIM_CHANNEL_CH2N
164 * @arg @ref LL_TIM_CHANNEL_CH3
165 * @arg @ref LL_TIM_CHANNEL_CH3N
166 * @arg @ref LL_TIM_CHANNEL_CH4
167 * @arg @ref LL_TIM_CHANNEL_CH5
168 * @arg @ref LL_TIM_CHANNEL_CH6
169 * @note CH5 and CH6 channels are not available for all F3 devices
170 * @retval none
171 */
172 #if defined(TIM_CCR5_CCR5)
173 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
174 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
182 #else
183 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
184 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
186 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
187 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
189 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
190 #endif
191
192 /** @brief Calculate the deadtime sampling period(in ps).
193 * @param __TIMCLK__ timer input clock frequency (in Hz).
194 * @param __CKD__ This parameter can be one of the following values:
195 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
196 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
197 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
198 * @retval none
199 */
200 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
201 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
202 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
203 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
204 /**
205 * @}
206 */
207
208
209 /* Exported types ------------------------------------------------------------*/
210 #if defined(USE_FULL_LL_DRIVER)
211 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
212 * @{
213 */
214
215 /**
216 * @brief TIM Time Base configuration structure definition.
217 */
218 typedef struct
219 {
220 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
221 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetPrescaler().*/
225
226 uint32_t CounterMode; /*!< Specifies the counter mode.
227 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetCounterMode().*/
231
232 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
233 Auto-Reload Register at the next update event.
234 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
235 Some timer instances may support 32 bits counters. In that case this parameter must
236 be a number between 0x0000 and 0xFFFFFFFF.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetAutoReload().*/
240
241 uint32_t ClockDivision; /*!< Specifies the clock division.
242 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetClockDivision().*/
246
247 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
248 reaches zero, an update event is generated and counting restarts
249 from the RCR value (N).
250 This means in PWM mode that (N+1) corresponds to:
251 - the number of PWM periods in edge-aligned mode
252 - the number of half PWM period in center-aligned mode
253 GP timers: this parameter must be a number between Min_Data = 0x00 and
254 Max_Data = 0xFF.
255 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
256 Max_Data = 0xFFFF.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_SetRepetitionCounter().*/
260 } LL_TIM_InitTypeDef;
261
262 /**
263 * @brief TIM Output Compare configuration structure definition.
264 */
265 typedef struct
266 {
267 uint32_t OCMode; /*!< Specifies the output mode.
268 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
269
270 This feature can be modified afterwards using unitary function
271 @ref LL_TIM_OC_SetMode().*/
272
273 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
280 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
281
282 This feature can be modified afterwards using unitary functions
283 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
284
285 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
286 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
287
288 This feature can be modified afterwards using unitary function
289 LL_TIM_OC_SetCompareCHx (x=1..6).*/
290
291 uint32_t OCPolarity; /*!< Specifies the output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
298 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetPolarity().*/
302
303
304 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309
310 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
311 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_OC_SetIdleState().*/
315 } LL_TIM_OC_InitTypeDef;
316
317 /**
318 * @brief TIM Input Capture configuration structure definition.
319 */
320
321 typedef struct
322 {
323
324 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
325 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetPolarity().*/
329
330 uint32_t ICActiveInput; /*!< Specifies the input.
331 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetActiveInput().*/
335
336 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
337 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetPrescaler().*/
341
342 uint32_t ICFilter; /*!< Specifies the input capture filter.
343 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
344
345 This feature can be modified afterwards using unitary function
346 @ref LL_TIM_IC_SetFilter().*/
347 } LL_TIM_IC_InitTypeDef;
348
349
350 /**
351 * @brief TIM Encoder interface configuration structure definition.
352 */
353 typedef struct
354 {
355 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
356 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_SetEncoderMode().*/
360
361 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
362 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetPolarity().*/
366
367 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
368 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetActiveInput().*/
372
373 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
374 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetPrescaler().*/
378
379 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
380 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetFilter().*/
384
385 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
386 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetPolarity().*/
390
391 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
392 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetActiveInput().*/
396
397 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
398 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetPrescaler().*/
402
403 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
404 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetFilter().*/
408
409 } LL_TIM_ENCODER_InitTypeDef;
410
411 /**
412 * @brief TIM Hall sensor interface configuration structure definition.
413 */
414 typedef struct
415 {
416
417 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
418 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetPolarity().*/
422
423 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
424 Prescaler must be set to get a maximum counter period longer than the
425 time interval between 2 consecutive changes on the Hall inputs.
426 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_IC_SetPrescaler().*/
430
431 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
432 This parameter can be a value of
433 @ref TIM_LL_EC_IC_FILTER.
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_IC_SetFilter().*/
437
438 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
439 A positive pulse (TRGO event) is generated with a programmable delay every time
440 a change occurs on the Hall inputs.
441 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
442
443 This feature can be modified afterwards using unitary function
444 @ref LL_TIM_OC_SetCompareCH2().*/
445 } LL_TIM_HALLSENSOR_InitTypeDef;
446
447 /**
448 * @brief BDTR (Break and Dead Time) structure definition
449 */
450 typedef struct
451 {
452 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
453 This parameter can be a value of @ref TIM_LL_EC_OSSR
454
455 This feature can be modified afterwards using unitary function
456 @ref LL_TIM_SetOffStates()
457
458 @note This bit-field cannot be modified as long as LOCK level 2 has been
459 programmed. */
460
461 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
462 This parameter can be a value of @ref TIM_LL_EC_OSSI
463
464 This feature can be modified afterwards using unitary function
465 @ref LL_TIM_SetOffStates()
466
467 @note This bit-field cannot be modified as long as LOCK level 2 has been
468 programmed. */
469
470 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
471 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
472
473 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
474 register has been written, their content is frozen until the next reset.*/
475
476 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
477 switching-on of the outputs.
478 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
479
480 This feature can be modified afterwards using unitary function
481 @ref LL_TIM_OC_SetDeadTime()
482
483 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
484 programmed. */
485
486 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
487 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
488
489 This feature can be modified afterwards using unitary functions
490 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
491
492 @note This bit-field can not be modified as long as LOCK level 1 has been
493 programmed. */
494
495 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
496 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
497
498 This feature can be modified afterwards using unitary function
499 @ref LL_TIM_ConfigBRK()
500
501 @note This bit-field can not be modified as long as LOCK level 1 has been
502 programmed. */
503
504 #if defined(TIM_BDTR_BKF)
505 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
506 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
507
508 This feature can be modified afterwards using unitary function
509 @ref LL_TIM_ConfigBRK()
510
511 @note This bit-field can not be modified as long as LOCK level 1 has been
512 programmed. */
513
514 #endif /* TIM_BDTR_BKF */
515 #if defined(TIM_BDTR_BK2E)
516 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
518
519 This feature can be modified afterwards using unitary functions
520 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
526 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
527
528 This feature can be modified afterwards using unitary function
529 @ref LL_TIM_ConfigBRK2()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533
534 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
536
537 This feature can be modified afterwards using unitary function
538 @ref LL_TIM_ConfigBRK2()
539
540 @note This bit-field can not be modified as long as LOCK level 1 has been
541 programmed. */
542
543 #endif /* TIM_BDTR_BK2E */
544 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
545 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
546
547 This feature can be modified afterwards using unitary functions
548 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
549
550 @note This bit-field can not be modified as long as LOCK level 1 has been
551 programmed. */
552 } LL_TIM_BDTR_InitTypeDef;
553
554 /**
555 * @}
556 */
557 #endif /* USE_FULL_LL_DRIVER */
558
559 /* Exported constants --------------------------------------------------------*/
560 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
561 * @{
562 */
563
564 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
565 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
566 * @{
567 */
568 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
569 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
570 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
571 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
572 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
573 #if defined(TIM_CCMR1_OC1M_3)
574 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
575 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
576 #endif /* TIM_CCMR1_OC1M_3 */
577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
580 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
581 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
582 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
583 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
584 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
585 /**
586 * @}
587 */
588
589 #if defined(USE_FULL_LL_DRIVER)
590 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
591 * @{
592 */
593 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
594 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
595 /**
596 * @}
597 */
598 #if defined(TIM_BDTR_BK2E)
599
600 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
601 * @{
602 */
603 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
604 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
605 /**
606 * @}
607 */
608 #endif /* TIM_BDTR_BK2E */
609
610 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
611 * @{
612 */
613 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
614 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
615 /**
616 * @}
617 */
618 #endif /* USE_FULL_LL_DRIVER */
619
620 /** @defgroup TIM_LL_EC_IT IT Defines
621 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
622 * @{
623 */
624 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
625 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
626 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
627 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
628 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
629 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
630 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
631 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
632 /**
633 * @}
634 */
635
636 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
637 * @{
638 */
639 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
640 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
641 /**
642 * @}
643 */
644
645 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
646 * @{
647 */
648 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
649 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
650 /**
651 * @}
652 */
653
654 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
655 * @{
656 */
657 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
658 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
659 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
660 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
661 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
662 /**
663 * @}
664 */
665
666 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
667 * @{
668 */
669 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
670 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
671 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
677 * @{
678 */
679 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
680 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
681 /**
682 * @}
683 */
684
685 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
686 * @{
687 */
688 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
689 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
695 * @{
696 */
697 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
698 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
699 /**
700 * @}
701 */
702
703 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
704 * @{
705 */
706 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
707 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
708 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
709 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
710 /**
711 * @}
712 */
713
714 /** @defgroup TIM_LL_EC_CHANNEL Channel
715 * @{
716 */
717 #if defined(TIM_CCMR1_OC1M_3)
718 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
719 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
720 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
721 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
722 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
723 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
724 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
725 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
726 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
727 #else
728 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
729 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
730 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
731 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
732 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
733 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
734 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
735 #endif
736 /**
737 * @}
738 */
739
740 #if defined(USE_FULL_LL_DRIVER)
741 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
742 * @{
743 */
744 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
745 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
746 /**
747 * @}
748 */
749 #endif /* USE_FULL_LL_DRIVER */
750
751 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
752 * @{
753 */
754 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
755 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
756 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
757 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
758 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
759 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
760 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
761 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
762 #if defined(TIM_CCMR1_OC1M_3)
763 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
764 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
765 #endif
766 #if defined(TIM_CCMR1_OC1M_3)
767 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
768 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
769 #endif
770 #if defined(TIM_CCMR1_OC1M_3)
771 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
772 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
773 #endif
774 /**
775 * @}
776 */
777
778 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
779 * @{
780 */
781 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
782 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
783 /**
784 * @}
785 */
786
787 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
788 * @{
789 */
790 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
791 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
792 /**
793 * @}
794 */
795
796 #if defined(TIM_CCR5_CCR5)
797 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
798 * @{
799 */
800 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
801 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
802 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
803 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
804 /**
805 * @}
806 */
807 #endif /* TIM_CCR5_CCR5 */
808
809 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
810 * @{
811 */
812 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
813 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
814 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
815 /**
816 * @}
817 */
818
819 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
820 * @{
821 */
822 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
823 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
824 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
825 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
826 /**
827 * @}
828 */
829
830 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
831 * @{
832 */
833 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
834 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
835 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
836 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
837 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
838 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
839 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
842 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
843 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
844 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
845 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
846 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
847 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
848 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
849 /**
850 * @}
851 */
852
853 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
854 * @{
855 */
856 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
857 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
858 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
859 /**
860 * @}
861 */
862
863 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
864 * @{
865 */
866 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
867 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
868 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
869 /**
870 * @}
871 */
872
873 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
874 * @{
875 */
876 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
877 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
878 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
879 /**
880 * @}
881 */
882
883 /** @defgroup TIM_LL_EC_TRGO Trigger Output
884 * @{
885 */
886 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
887 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
888 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
889 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
890 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
891 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
892 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
893 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
894 /**
895 * @}
896 */
897
898 #if defined(TIM_CR2_MMS2)
899 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
900 * @{
901 */
902 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
903 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
904 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
905 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
912 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
913 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
916 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
917 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
918 /**
919 * @}
920 */
921 #endif /* TIM_CR2_MMS2 */
922
923 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
924 * @{
925 */
926 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
927 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
928 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
929 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
930 #if defined (TIM_SMCR_SMS_3)
931 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
932 #endif /* TIM_SMCR_SMS_3 */
933 /**
934 * @}
935 */
936
937 /** @defgroup TIM_LL_EC_TS Trigger Selection
938 * @{
939 */
940 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
941 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
942 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
943 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
944 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
945 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
946 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
947 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
948 /**
949 * @}
950 */
951
952 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
953 * @{
954 */
955 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
956 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
957 /**
958 * @}
959 */
960
961 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
962 * @{
963 */
964 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
965 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
966 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
967 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
968 /**
969 * @}
970 */
971
972 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
973 * @{
974 */
975 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
976 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
977 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
978 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
979 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
980 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
981 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
982 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
983 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
984 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
985 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
986 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
987 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
988 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
989 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
990 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
991 /**
992 * @}
993 */
994
995
996 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
997 * @{
998 */
999 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1000 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1001 /**
1002 * @}
1003 */
1004
1005 #if defined(TIM_BDTR_BKF)
1006 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1007 * @{
1008 */
1009 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1010 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1011 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1012 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1013 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1014 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1015 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1016 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1017 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1018 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1019 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1020 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1021 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1022 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1023 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1024 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1025 /**
1026 * @}
1027 */
1028 #endif /* TIM_BDTR_BKF */
1029
1030 #if defined(TIM_BDTR_BK2P)
1031 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1032 * @{
1033 */
1034 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1035 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1036 /**
1037 * @}
1038 */
1039 #endif /* TIM_BDTR_BK2P */
1040
1041 #if defined(TIM_BDTR_BK2F)
1042 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1043 * @{
1044 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1046 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1061 /**
1062 * @}
1063 */
1064 #endif /* TIM_BDTR_BK2F */
1065
1066 /** @defgroup TIM_LL_EC_OSSI OSSI
1067 * @{
1068 */
1069 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1070 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup TIM_LL_EC_OSSR OSSR
1076 * @{
1077 */
1078 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1079 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1080 /**
1081 * @}
1082 */
1083
1084
1085 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1086 * @{
1087 */
1088 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1089 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1090 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1091 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1092 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1093 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1094 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1095 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1096 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1097 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1098 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1099 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1100 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1101 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1102 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1103 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1104 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1105 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1106 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1107 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
1108 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1109 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1110 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1111 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1117 * @{
1118 */
1119 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1120 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1121 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1122 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1123 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1124 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1125 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1126 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1127 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1128 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1129 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1130 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1131 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1132 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1133 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1134 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1135 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1136 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1137 /**
1138 * @}
1139 */
1140
1141 #if defined(TIM1)
1142 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1143 * @{
1144 */
1145 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1146 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1147 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1148 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1149 /**
1150 * @}
1151 */
1152 #if defined(ADC4)
1153 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP TIM1 External Trigger ADC4 Remap
1154 * @{
1155 */
1156 #define LL_TIM_TIM1_ETR_ADC4_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/
1157 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
1158 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
1159 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
1160 /**
1161 * @}
1162 */
1163 #else
1164 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
1165 * @{
1166 */
1167 #define LL_TIM_TIM1_ETR_ADC2_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/
1168 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
1169 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
1170 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
1171 /**
1172 * @}
1173 */
1174 #endif /* ADC4 */
1175 #endif /* TIM1 */
1176 #if defined(TIM8)
1177 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1178 * @{
1179 */
1180 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1181 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1182 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1183 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1189 * @{
1190 */
1191 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1192 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1193 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1194 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1195 /**
1196 * @}
1197 */
1198 #endif /* TIM8 */
1199 #if defined(TIM16)
1200 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1201 * @{
1202 */
1203 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */
1204 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1205 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */
1206 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1207 /**
1208 * @}
1209 */
1210 #endif /* TIM16 */
1211 #if defined(TIM20)
1212 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
1213 * @{
1214 */
1215 #define LL_TIM_TIM20_ETR_ADC3_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
1216 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */
1217 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
1218 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
1224 * @{
1225 */
1226 #define LL_TIM_TIM20_ETR_ADC4_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
1227 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
1228 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
1229 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
1230 /**
1231 * @}
1232 */
1233 #endif /* TIM20 */
1234 #if defined(TIM14)
1235 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
1236 * @{
1237 */
1238 #define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to GPIO */
1239 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */
1240 #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */
1241 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
1242 /**
1243 * @}
1244 */
1245 #endif /* TIM14 */
1246
1247 #if defined(TIM_SMCR_OCCS)
1248 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1249 * @{
1250 */
1251 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1252 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1253 /**
1254 * @}
1255 */
1256
1257 #endif /* TIM_SMCR_OCCS*/
1258
1259 /**
1260 * @}
1261 */
1262
1263 /* Exported macro ------------------------------------------------------------*/
1264 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1265 * @{
1266 */
1267
1268 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1269 * @{
1270 */
1271 /**
1272 * @brief Write a value in TIM register.
1273 * @param __INSTANCE__ TIM Instance
1274 * @param __REG__ Register to be written
1275 * @param __VALUE__ Value to be written in the register
1276 * @retval None
1277 */
1278 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1279
1280 /**
1281 * @brief Read a value in TIM register.
1282 * @param __INSTANCE__ TIM Instance
1283 * @param __REG__ Register to be read
1284 * @retval Register value
1285 */
1286 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1287 /**
1288 * @}
1289 */
1290
1291 /**
1292 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1293 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1294 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1295 * to TIMx_CNT register bit 31)
1296 * @param __CNT__ Counter value
1297 * @retval UIF status bit
1298 */
1299 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1300 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1301
1302 /**
1303 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1304 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1305 * @param __TIMCLK__ timer input clock frequency (in Hz)
1306 * @param __CKD__ This parameter can be one of the following values:
1307 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1308 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1309 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1310 * @param __DT__ deadtime duration (in ns)
1311 * @retval DTG[0:7]
1312 */
1313 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1314 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1315 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1316 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1317 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1318 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1319 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1320 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1321 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1322 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1323 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1324 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1325 0U)
1326
1327 /**
1328 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1329 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1330 * @param __TIMCLK__ timer input clock frequency (in Hz)
1331 * @param __CNTCLK__ counter clock frequency (in Hz)
1332 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1333 */
1334 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1335 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1336
1337 /**
1338 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1339 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1340 * @param __TIMCLK__ timer input clock frequency (in Hz)
1341 * @param __PSC__ prescaler
1342 * @param __FREQ__ output signal frequency (in Hz)
1343 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1344 */
1345 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1346 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1347
1348 /**
1349 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1350 * active/inactive delay.
1351 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1352 * @param __TIMCLK__ timer input clock frequency (in Hz)
1353 * @param __PSC__ prescaler
1354 * @param __DELAY__ timer output compare active/inactive delay (in us)
1355 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1356 */
1357 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1358 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1359 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1360
1361 /**
1362 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1363 * (when the timer operates in one pulse mode).
1364 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1365 * @param __TIMCLK__ timer input clock frequency (in Hz)
1366 * @param __PSC__ prescaler
1367 * @param __DELAY__ timer output compare active/inactive delay (in us)
1368 * @param __PULSE__ pulse duration (in us)
1369 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1370 */
1371 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1372 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1373 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1374
1375 /**
1376 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1377 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1378 * @param __ICPSC__ This parameter can be one of the following values:
1379 * @arg @ref LL_TIM_ICPSC_DIV1
1380 * @arg @ref LL_TIM_ICPSC_DIV2
1381 * @arg @ref LL_TIM_ICPSC_DIV4
1382 * @arg @ref LL_TIM_ICPSC_DIV8
1383 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1384 */
1385 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1386 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1387
1388
1389 /**
1390 * @}
1391 */
1392
1393 /* Exported functions --------------------------------------------------------*/
1394 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1395 * @{
1396 */
1397
1398 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1399 * @{
1400 */
1401 /**
1402 * @brief Enable timer counter.
1403 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1404 * @param TIMx Timer instance
1405 * @retval None
1406 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1407 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1408 {
1409 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1410 }
1411
1412 /**
1413 * @brief Disable timer counter.
1414 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1415 * @param TIMx Timer instance
1416 * @retval None
1417 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1418 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1419 {
1420 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1421 }
1422
1423 /**
1424 * @brief Indicates whether the timer counter is enabled.
1425 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1426 * @param TIMx Timer instance
1427 * @retval State of bit (1 or 0).
1428 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1429 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1430 {
1431 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @brief Enable update event generation.
1436 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1437 * @param TIMx Timer instance
1438 * @retval None
1439 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1440 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1441 {
1442 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1443 }
1444
1445 /**
1446 * @brief Disable update event generation.
1447 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1448 * @param TIMx Timer instance
1449 * @retval None
1450 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1451 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1452 {
1453 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1454 }
1455
1456 /**
1457 * @brief Indicates whether update event generation is enabled.
1458 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1459 * @param TIMx Timer instance
1460 * @retval Inverted state of bit (0 or 1).
1461 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1462 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1463 {
1464 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1465 }
1466
1467 /**
1468 * @brief Set update event source
1469 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1470 * generate an update interrupt or DMA request if enabled:
1471 * - Counter overflow/underflow
1472 * - Setting the UG bit
1473 * - Update generation through the slave mode controller
1474 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1475 * overflow/underflow generates an update interrupt or DMA request if enabled.
1476 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1477 * @param TIMx Timer instance
1478 * @param UpdateSource This parameter can be one of the following values:
1479 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1480 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1481 * @retval None
1482 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1483 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1484 {
1485 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1486 }
1487
1488 /**
1489 * @brief Get actual event update source
1490 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1491 * @param TIMx Timer instance
1492 * @retval Returned value can be one of the following values:
1493 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1494 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1495 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1496 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1497 {
1498 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1499 }
1500
1501 /**
1502 * @brief Set one pulse mode (one shot v.s. repetitive).
1503 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1504 * @param TIMx Timer instance
1505 * @param OnePulseMode This parameter can be one of the following values:
1506 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1507 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1508 * @retval None
1509 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1510 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1511 {
1512 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1513 }
1514
1515 /**
1516 * @brief Get actual one pulse mode.
1517 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1518 * @param TIMx Timer instance
1519 * @retval Returned value can be one of the following values:
1520 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1521 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1522 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1523 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1524 {
1525 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1526 }
1527
1528 /**
1529 * @brief Set the timer counter counting mode.
1530 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1531 * check whether or not the counter mode selection feature is supported
1532 * by a timer instance.
1533 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1534 * requires a timer reset to avoid unexpected direction
1535 * due to DIR bit readonly in center aligned mode.
1536 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1537 * CR1 CMS LL_TIM_SetCounterMode
1538 * @param TIMx Timer instance
1539 * @param CounterMode This parameter can be one of the following values:
1540 * @arg @ref LL_TIM_COUNTERMODE_UP
1541 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1542 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1543 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1544 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1545 * @retval None
1546 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1547 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1548 {
1549 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1550 }
1551
1552 /**
1553 * @brief Get actual counter mode.
1554 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1555 * check whether or not the counter mode selection feature is supported
1556 * by a timer instance.
1557 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1558 * CR1 CMS LL_TIM_GetCounterMode
1559 * @param TIMx Timer instance
1560 * @retval Returned value can be one of the following values:
1561 * @arg @ref LL_TIM_COUNTERMODE_UP
1562 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1563 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1564 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1565 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1566 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1567 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1568 {
1569 uint32_t counter_mode;
1570
1571 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1572
1573 if (counter_mode == 0U)
1574 {
1575 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1576 }
1577
1578 return counter_mode;
1579 }
1580
1581 /**
1582 * @brief Enable auto-reload (ARR) preload.
1583 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1584 * @param TIMx Timer instance
1585 * @retval None
1586 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1587 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1588 {
1589 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1590 }
1591
1592 /**
1593 * @brief Disable auto-reload (ARR) preload.
1594 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1595 * @param TIMx Timer instance
1596 * @retval None
1597 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1598 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1599 {
1600 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1601 }
1602
1603 /**
1604 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1605 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1606 * @param TIMx Timer instance
1607 * @retval State of bit (1 or 0).
1608 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1609 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1610 {
1611 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1612 }
1613
1614 /**
1615 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1616 * (when supported) and the digital filters.
1617 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1618 * whether or not the clock division feature is supported by the timer
1619 * instance.
1620 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1621 * @param TIMx Timer instance
1622 * @param ClockDivision This parameter can be one of the following values:
1623 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1624 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1625 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1626 * @retval None
1627 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1628 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1629 {
1630 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1631 }
1632
1633 /**
1634 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1635 * generators (when supported) and the digital filters.
1636 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1637 * whether or not the clock division feature is supported by the timer
1638 * instance.
1639 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1640 * @param TIMx Timer instance
1641 * @retval Returned value can be one of the following values:
1642 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1643 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1644 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1645 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1646 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1647 {
1648 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1649 }
1650
1651 /**
1652 * @brief Set the counter value.
1653 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1654 * whether or not a timer instance supports a 32 bits counter.
1655 * @rmtoll CNT CNT LL_TIM_SetCounter
1656 * @param TIMx Timer instance
1657 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1658 * @retval None
1659 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1660 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1661 {
1662 WRITE_REG(TIMx->CNT, Counter);
1663 }
1664
1665 /**
1666 * @brief Get the counter value.
1667 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1668 * whether or not a timer instance supports a 32 bits counter.
1669 * @rmtoll CNT CNT LL_TIM_GetCounter
1670 * @param TIMx Timer instance
1671 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1672 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1673 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1674 {
1675 return (uint32_t)(READ_REG(TIMx->CNT));
1676 }
1677
1678 /**
1679 * @brief Get the current direction of the counter
1680 * @rmtoll CR1 DIR LL_TIM_GetDirection
1681 * @param TIMx Timer instance
1682 * @retval Returned value can be one of the following values:
1683 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1684 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1685 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1686 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1687 {
1688 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1689 }
1690
1691 /**
1692 * @brief Set the prescaler value.
1693 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1694 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1695 * prescaler ratio is taken into account at the next update event.
1696 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1697 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1698 * @param TIMx Timer instance
1699 * @param Prescaler between Min_Data=0 and Max_Data=65535
1700 * @retval None
1701 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1702 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1703 {
1704 WRITE_REG(TIMx->PSC, Prescaler);
1705 }
1706
1707 /**
1708 * @brief Get the prescaler value.
1709 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1710 * @param TIMx Timer instance
1711 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1712 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1713 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1714 {
1715 return (uint32_t)(READ_REG(TIMx->PSC));
1716 }
1717
1718 /**
1719 * @brief Set the auto-reload value.
1720 * @note The counter is blocked while the auto-reload value is null.
1721 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1722 * whether or not a timer instance supports a 32 bits counter.
1723 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1724 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1725 * @param TIMx Timer instance
1726 * @param AutoReload between Min_Data=0 and Max_Data=65535
1727 * @retval None
1728 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1729 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1730 {
1731 WRITE_REG(TIMx->ARR, AutoReload);
1732 }
1733
1734 /**
1735 * @brief Get the auto-reload value.
1736 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1737 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1738 * whether or not a timer instance supports a 32 bits counter.
1739 * @param TIMx Timer instance
1740 * @retval Auto-reload value
1741 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1742 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1743 {
1744 return (uint32_t)(READ_REG(TIMx->ARR));
1745 }
1746
1747 /**
1748 * @brief Set the repetition counter value.
1749 * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
1750 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1751 * whether or not a timer instance supports a repetition counter.
1752 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1753 * @param TIMx Timer instance
1754 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1755 * @retval None
1756 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1757 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1758 {
1759 WRITE_REG(TIMx->RCR, RepetitionCounter);
1760 }
1761
1762 /**
1763 * @brief Get the repetition counter value.
1764 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1765 * whether or not a timer instance supports a repetition counter.
1766 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1767 * @param TIMx Timer instance
1768 * @retval Repetition counter value
1769 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1770 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1771 {
1772 return (uint32_t)(READ_REG(TIMx->RCR));
1773 }
1774
1775 #if defined(TIM_CR1_UIFREMAP)
1776 /**
1777 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1778 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1779 * in an atomic way.
1780 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1781 * @param TIMx Timer instance
1782 * @retval None
1783 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1784 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1785 {
1786 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1787 }
1788
1789 /**
1790 * @brief Disable update interrupt flag (UIF) remapping.
1791 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1792 * @param TIMx Timer instance
1793 * @retval None
1794 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1795 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1796 {
1797 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1798 }
1799
1800 /**
1801 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1802 * @param Counter Counter value
1803 * @retval State of bit (1 or 0).
1804 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1805 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1806 {
1807 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1808 }
1809
1810 #endif /* TIM_CR1_UIFREMAP */
1811 /**
1812 * @}
1813 */
1814
1815 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1816 * @{
1817 */
1818 /**
1819 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1820 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1821 * they are updated only when a commutation event (COM) occurs.
1822 * @note Only on channels that have a complementary output.
1823 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1824 * whether or not a timer instance is able to generate a commutation event.
1825 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1826 * @param TIMx Timer instance
1827 * @retval None
1828 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1829 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1830 {
1831 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1832 }
1833
1834 /**
1835 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1836 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1837 * whether or not a timer instance is able to generate a commutation event.
1838 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1839 * @param TIMx Timer instance
1840 * @retval None
1841 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1842 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1843 {
1844 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1845 }
1846
1847 /**
1848 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1849 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1850 * whether or not a timer instance is able to generate a commutation event.
1851 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1852 * @param TIMx Timer instance
1853 * @param CCUpdateSource This parameter can be one of the following values:
1854 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1855 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1856 * @retval None
1857 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1858 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1859 {
1860 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1861 }
1862
1863 /**
1864 * @brief Set the trigger of the capture/compare DMA request.
1865 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1866 * @param TIMx Timer instance
1867 * @param DMAReqTrigger This parameter can be one of the following values:
1868 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1869 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1870 * @retval None
1871 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1872 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1873 {
1874 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1875 }
1876
1877 /**
1878 * @brief Get actual trigger of the capture/compare DMA request.
1879 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1880 * @param TIMx Timer instance
1881 * @retval Returned value can be one of the following values:
1882 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1883 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1884 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1885 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1886 {
1887 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1888 }
1889
1890 /**
1891 * @brief Set the lock level to freeze the
1892 * configuration of several capture/compare parameters.
1893 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1894 * the lock mechanism is supported by a timer instance.
1895 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1896 * @param TIMx Timer instance
1897 * @param LockLevel This parameter can be one of the following values:
1898 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1899 * @arg @ref LL_TIM_LOCKLEVEL_1
1900 * @arg @ref LL_TIM_LOCKLEVEL_2
1901 * @arg @ref LL_TIM_LOCKLEVEL_3
1902 * @retval None
1903 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1904 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1905 {
1906 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1907 }
1908
1909 /**
1910 * @brief Enable capture/compare channels.
1911 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1912 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1913 * CCER CC2E LL_TIM_CC_EnableChannel\n
1914 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1915 * CCER CC3E LL_TIM_CC_EnableChannel\n
1916 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1917 * CCER CC4E LL_TIM_CC_EnableChannel\n
1918 * CCER CC5E LL_TIM_CC_EnableChannel\n
1919 * CCER CC6E LL_TIM_CC_EnableChannel
1920 * @param TIMx Timer instance
1921 * @param Channels This parameter can be a combination of the following values:
1922 * @arg @ref LL_TIM_CHANNEL_CH1
1923 * @arg @ref LL_TIM_CHANNEL_CH1N
1924 * @arg @ref LL_TIM_CHANNEL_CH2
1925 * @arg @ref LL_TIM_CHANNEL_CH2N
1926 * @arg @ref LL_TIM_CHANNEL_CH3
1927 * @arg @ref LL_TIM_CHANNEL_CH3N
1928 * @arg @ref LL_TIM_CHANNEL_CH4
1929 * @arg @ref LL_TIM_CHANNEL_CH5
1930 * @arg @ref LL_TIM_CHANNEL_CH6
1931 * @note CH5 and CH6 channels are not available for all F3 devices
1932 * @retval None
1933 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1934 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1935 {
1936 SET_BIT(TIMx->CCER, Channels);
1937 }
1938
1939 /**
1940 * @brief Disable capture/compare channels.
1941 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1942 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1943 * CCER CC2E LL_TIM_CC_DisableChannel\n
1944 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1945 * CCER CC3E LL_TIM_CC_DisableChannel\n
1946 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1947 * CCER CC4E LL_TIM_CC_DisableChannel\n
1948 * CCER CC5E LL_TIM_CC_DisableChannel\n
1949 * CCER CC6E LL_TIM_CC_DisableChannel
1950 * @param TIMx Timer instance
1951 * @param Channels This parameter can be a combination of the following values:
1952 * @arg @ref LL_TIM_CHANNEL_CH1
1953 * @arg @ref LL_TIM_CHANNEL_CH1N
1954 * @arg @ref LL_TIM_CHANNEL_CH2
1955 * @arg @ref LL_TIM_CHANNEL_CH2N
1956 * @arg @ref LL_TIM_CHANNEL_CH3
1957 * @arg @ref LL_TIM_CHANNEL_CH3N
1958 * @arg @ref LL_TIM_CHANNEL_CH4
1959 * @arg @ref LL_TIM_CHANNEL_CH5
1960 * @arg @ref LL_TIM_CHANNEL_CH6
1961 * @note CH5 and CH6 channels are not available for all F3 devices
1962 * @retval None
1963 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1964 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1965 {
1966 CLEAR_BIT(TIMx->CCER, Channels);
1967 }
1968
1969 /**
1970 * @brief Indicate whether channel(s) is(are) enabled.
1971 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1972 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1973 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1974 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1975 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1976 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1977 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1978 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1979 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1980 * @param TIMx Timer instance
1981 * @param Channels This parameter can be a combination of the following values:
1982 * @arg @ref LL_TIM_CHANNEL_CH1
1983 * @arg @ref LL_TIM_CHANNEL_CH1N
1984 * @arg @ref LL_TIM_CHANNEL_CH2
1985 * @arg @ref LL_TIM_CHANNEL_CH2N
1986 * @arg @ref LL_TIM_CHANNEL_CH3
1987 * @arg @ref LL_TIM_CHANNEL_CH3N
1988 * @arg @ref LL_TIM_CHANNEL_CH4
1989 * @arg @ref LL_TIM_CHANNEL_CH5
1990 * @arg @ref LL_TIM_CHANNEL_CH6
1991 * @note CH5 and CH6 channels are not available for all F3 devices
1992 * @retval State of bit (1 or 0).
1993 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1994 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1995 {
1996 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1997 }
1998
1999 /**
2000 * @}
2001 */
2002
2003 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2004 * @{
2005 */
2006 /**
2007 * @brief Configure an output channel.
2008 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2009 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2010 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2011 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2012 * @if STM32F334x8
2013 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2014 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2015 * @elseif STM32F303xC
2016 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2017 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2018 * @elseif STM32F302x8
2019 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2020 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2021 * @endif
2022 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2023 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2024 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2025 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2026 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2027 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2028 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2029 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2030 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2031 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2032 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2033 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2034 * @param TIMx Timer instance
2035 * @param Channel This parameter can be one of the following values:
2036 * @arg @ref LL_TIM_CHANNEL_CH1
2037 * @arg @ref LL_TIM_CHANNEL_CH2
2038 * @arg @ref LL_TIM_CHANNEL_CH3
2039 * @arg @ref LL_TIM_CHANNEL_CH4
2040 * @arg @ref LL_TIM_CHANNEL_CH5
2041 * @arg @ref LL_TIM_CHANNEL_CH6
2042 * @param Configuration This parameter must be a combination of all the following values:
2043 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2044 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2045 * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
2046 * @retval None
2047 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2048 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2049 {
2050 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2052 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2053 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2054 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2055 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2056 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2057 }
2058
2059 /**
2060 * @brief Define the behavior of the output reference signal OCxREF from which
2061 * OCx and OCxN (when relevant) are derived.
2062 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2063 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2064 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2065 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2066 * @if STM32F334x8
2067 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2068 * CCMR3 OC6M LL_TIM_OC_SetMode
2069 * @elseif STM32F303xC
2070 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2071 * CCMR3 OC6M LL_TIM_OC_SetMode
2072 * @elseif STM32F302x8
2073 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2074 * CCMR3 OC6M LL_TIM_OC_SetMode
2075 * @endif
2076 * @param TIMx Timer instance
2077 * @param Channel This parameter can be one of the following values:
2078 * @arg @ref LL_TIM_CHANNEL_CH1
2079 * @arg @ref LL_TIM_CHANNEL_CH2
2080 * @arg @ref LL_TIM_CHANNEL_CH3
2081 * @arg @ref LL_TIM_CHANNEL_CH4
2082 * @arg @ref LL_TIM_CHANNEL_CH5
2083 * @arg @ref LL_TIM_CHANNEL_CH6
2084 * @param Mode This parameter can be one of the following values:
2085 * @arg @ref LL_TIM_OCMODE_FROZEN
2086 * @arg @ref LL_TIM_OCMODE_ACTIVE
2087 * @arg @ref LL_TIM_OCMODE_INACTIVE
2088 * @arg @ref LL_TIM_OCMODE_TOGGLE
2089 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2090 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2091 * @arg @ref LL_TIM_OCMODE_PWM1
2092 * @arg @ref LL_TIM_OCMODE_PWM2
2093 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2094 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2095 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2096 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2097 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2098 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2099 * @note The following OC modes are not available on all F3 devices :
2100 * - LL_TIM_OCMODE_RETRIG_OPM1
2101 * - LL_TIM_OCMODE_RETRIG_OPM2
2102 * - LL_TIM_OCMODE_COMBINED_PWM1
2103 * - LL_TIM_OCMODE_COMBINED_PWM2
2104 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
2105 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
2106 * @note CH5 and CH6 channels are not available for all F3 devices
2107 * @retval None
2108 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2109 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2110 {
2111 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2112 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2113 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2114 }
2115
2116 /**
2117 * @brief Get the output compare mode of an output channel.
2118 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2119 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2120 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2121 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2122 * @if STM32F334x8
2123 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2124 * CCMR3 OC6M LL_TIM_OC_GetMode
2125 * @elseif STM32F303xC
2126 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2127 * CCMR3 OC6M LL_TIM_OC_GetMode
2128 * @elseif STM32F302x8
2129 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2130 * CCMR3 OC6M LL_TIM_OC_GetMode
2131 * @endif
2132 * @param TIMx Timer instance
2133 * @param Channel This parameter can be one of the following values:
2134 * @arg @ref LL_TIM_CHANNEL_CH1
2135 * @arg @ref LL_TIM_CHANNEL_CH2
2136 * @arg @ref LL_TIM_CHANNEL_CH3
2137 * @arg @ref LL_TIM_CHANNEL_CH4
2138 * @arg @ref LL_TIM_CHANNEL_CH5
2139 * @arg @ref LL_TIM_CHANNEL_CH6
2140 * @note The following OC modes are not available on all F3 devices :
2141 * - LL_TIM_OCMODE_RETRIG_OPM1
2142 * - LL_TIM_OCMODE_RETRIG_OPM2
2143 * - LL_TIM_OCMODE_COMBINED_PWM1
2144 * - LL_TIM_OCMODE_COMBINED_PWM2
2145 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
2146 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
2147 * @note CH5 and CH6 channels are not available for all F3 devices
2148 * @retval Returned value can be one of the following values:
2149 * @arg @ref LL_TIM_OCMODE_FROZEN
2150 * @arg @ref LL_TIM_OCMODE_ACTIVE
2151 * @arg @ref LL_TIM_OCMODE_INACTIVE
2152 * @arg @ref LL_TIM_OCMODE_TOGGLE
2153 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2154 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2155 * @arg @ref LL_TIM_OCMODE_PWM1
2156 * @arg @ref LL_TIM_OCMODE_PWM2
2157 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2158 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2159 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2160 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2161 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2162 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2163 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2164 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2165 {
2166 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2167 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2168 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2169 }
2170
2171 /**
2172 * @brief Set the polarity of an output channel.
2173 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2174 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2175 * CCER CC2P LL_TIM_OC_SetPolarity\n
2176 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2177 * CCER CC3P LL_TIM_OC_SetPolarity\n
2178 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2179 * CCER CC4P LL_TIM_OC_SetPolarity\n
2180 * CCER CC5P LL_TIM_OC_SetPolarity\n
2181 * CCER CC6P LL_TIM_OC_SetPolarity
2182 * @param TIMx Timer instance
2183 * @param Channel This parameter can be one of the following values:
2184 * @arg @ref LL_TIM_CHANNEL_CH1
2185 * @arg @ref LL_TIM_CHANNEL_CH1N
2186 * @arg @ref LL_TIM_CHANNEL_CH2
2187 * @arg @ref LL_TIM_CHANNEL_CH2N
2188 * @arg @ref LL_TIM_CHANNEL_CH3
2189 * @arg @ref LL_TIM_CHANNEL_CH3N
2190 * @arg @ref LL_TIM_CHANNEL_CH4
2191 * @arg @ref LL_TIM_CHANNEL_CH5
2192 * @arg @ref LL_TIM_CHANNEL_CH6
2193 * @param Polarity This parameter can be one of the following values:
2194 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2195 * @arg @ref LL_TIM_OCPOLARITY_LOW
2196 * @note CH5 and CH6 channels are not available for all F3 devices
2197 * @retval None
2198 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2199 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2200 {
2201 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2202 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2203 }
2204
2205 /**
2206 * @brief Get the polarity of an output channel.
2207 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2208 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2209 * CCER CC2P LL_TIM_OC_GetPolarity\n
2210 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2211 * CCER CC3P LL_TIM_OC_GetPolarity\n
2212 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2213 * CCER CC4P LL_TIM_OC_GetPolarity\n
2214 * CCER CC5P LL_TIM_OC_GetPolarity\n
2215 * CCER CC6P LL_TIM_OC_GetPolarity
2216 * @param TIMx Timer instance
2217 * @param Channel This parameter can be one of the following values:
2218 * @arg @ref LL_TIM_CHANNEL_CH1
2219 * @arg @ref LL_TIM_CHANNEL_CH1N
2220 * @arg @ref LL_TIM_CHANNEL_CH2
2221 * @arg @ref LL_TIM_CHANNEL_CH2N
2222 * @arg @ref LL_TIM_CHANNEL_CH3
2223 * @arg @ref LL_TIM_CHANNEL_CH3N
2224 * @arg @ref LL_TIM_CHANNEL_CH4
2225 * @arg @ref LL_TIM_CHANNEL_CH5
2226 * @arg @ref LL_TIM_CHANNEL_CH6
2227 * @note CH5 and CH6 channels are not available for all F3 devices
2228 * @retval Returned value can be one of the following values:
2229 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2230 * @arg @ref LL_TIM_OCPOLARITY_LOW
2231 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2232 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2233 {
2234 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2235 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2236 }
2237
2238 /**
2239 * @brief Set the IDLE state of an output channel
2240 * @note This function is significant only for the timer instances
2241 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2242 * can be used to check whether or not a timer instance provides
2243 * a break input.
2244 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2245 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2246 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2247 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2248 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2249 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2250 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2251 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2252 * CR2 OIS6 LL_TIM_OC_SetIdleState
2253 * @param TIMx Timer instance
2254 * @param Channel This parameter can be one of the following values:
2255 * @arg @ref LL_TIM_CHANNEL_CH1
2256 * @arg @ref LL_TIM_CHANNEL_CH1N
2257 * @arg @ref LL_TIM_CHANNEL_CH2
2258 * @arg @ref LL_TIM_CHANNEL_CH2N
2259 * @arg @ref LL_TIM_CHANNEL_CH3
2260 * @arg @ref LL_TIM_CHANNEL_CH3N
2261 * @arg @ref LL_TIM_CHANNEL_CH4
2262 * @arg @ref LL_TIM_CHANNEL_CH5
2263 * @arg @ref LL_TIM_CHANNEL_CH6
2264 * @param IdleState This parameter can be one of the following values:
2265 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2266 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2267 * @note CH5 and CH6 channels are not available for all F3 devices
2268 * @retval None
2269 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2270 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2271 {
2272 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2273 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2274 }
2275
2276 /**
2277 * @brief Get the IDLE state of an output channel
2278 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2279 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2280 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2281 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2282 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2283 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2284 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2285 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2286 * CR2 OIS6 LL_TIM_OC_GetIdleState
2287 * @param TIMx Timer instance
2288 * @param Channel This parameter can be one of the following values:
2289 * @arg @ref LL_TIM_CHANNEL_CH1
2290 * @arg @ref LL_TIM_CHANNEL_CH1N
2291 * @arg @ref LL_TIM_CHANNEL_CH2
2292 * @arg @ref LL_TIM_CHANNEL_CH2N
2293 * @arg @ref LL_TIM_CHANNEL_CH3
2294 * @arg @ref LL_TIM_CHANNEL_CH3N
2295 * @arg @ref LL_TIM_CHANNEL_CH4
2296 * @arg @ref LL_TIM_CHANNEL_CH5
2297 * @arg @ref LL_TIM_CHANNEL_CH6
2298 * @note CH5 and CH6 channels are not available for all F3 devices
2299 * @retval Returned value can be one of the following values:
2300 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2301 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2302 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2303 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2304 {
2305 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2306 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2307 }
2308
2309 /**
2310 * @brief Enable fast mode for the output channel.
2311 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2312 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2313 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2314 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2315 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2316 * @if STM32F334x8
2317 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2318 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2319 * @elseif STM32F303xC
2320 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2321 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2322 * @elseif STM32F302x8
2323 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2324 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2325 * @endif
2326 * @param TIMx Timer instance
2327 * @param Channel This parameter can be one of the following values:
2328 * @arg @ref LL_TIM_CHANNEL_CH1
2329 * @arg @ref LL_TIM_CHANNEL_CH2
2330 * @arg @ref LL_TIM_CHANNEL_CH3
2331 * @arg @ref LL_TIM_CHANNEL_CH4
2332 * @arg @ref LL_TIM_CHANNEL_CH5
2333 * @arg @ref LL_TIM_CHANNEL_CH6
2334 * @note OC5FE and OC6FE are not available for all F3 devices
2335 * @note CH5 and CH6 channels are not available for all F3 devices
2336 * @retval None
2337 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2338 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2339 {
2340 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2341 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2342 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2343
2344 }
2345
2346 /**
2347 * @brief Disable fast mode for the output channel.
2348 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2349 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2350 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2351 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2352 * @if STM32F334x8
2353 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2354 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2355 * @elseif STM32F303xC
2356 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2357 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2358 * @elseif STM32F302x8
2359 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2360 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2361 * @endif
2362 * @param TIMx Timer instance
2363 * @param Channel This parameter can be one of the following values:
2364 * @arg @ref LL_TIM_CHANNEL_CH1
2365 * @arg @ref LL_TIM_CHANNEL_CH2
2366 * @arg @ref LL_TIM_CHANNEL_CH3
2367 * @arg @ref LL_TIM_CHANNEL_CH4
2368 * @arg @ref LL_TIM_CHANNEL_CH5
2369 * @arg @ref LL_TIM_CHANNEL_CH6
2370 * @note OC5FE and OC6FE are not available for all F3 devices
2371 * @note CH5 and CH6 channels are not available for all F3 devices
2372 * @retval None
2373 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2374 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2375 {
2376 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2377 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2378 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2379
2380 }
2381
2382 /**
2383 * @brief Indicates whether fast mode is enabled for the output channel.
2384 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2385 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2386 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2387 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2388 * @if STM32F334x8
2389 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2390 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2391 * @elseif STM32F303xC
2392 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2393 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2394 * @elseif STM32F302x8
2395 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2396 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2397 * @endif
2398 * @param TIMx Timer instance
2399 * @param Channel This parameter can be one of the following values:
2400 * @arg @ref LL_TIM_CHANNEL_CH1
2401 * @arg @ref LL_TIM_CHANNEL_CH2
2402 * @arg @ref LL_TIM_CHANNEL_CH3
2403 * @arg @ref LL_TIM_CHANNEL_CH4
2404 * @arg @ref LL_TIM_CHANNEL_CH5
2405 * @arg @ref LL_TIM_CHANNEL_CH6
2406 * @note OC5FE and OC6FE are not available for all F3 devices
2407 * @note CH5 and CH6 channels are not available for all F3 devices
2408 * @retval State of bit (1 or 0).
2409 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2410 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2411 {
2412 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2413 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2414 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2415 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2416 }
2417
2418 /**
2419 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2420 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2421 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2422 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2423 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2424 * @if STM32F334x8
2425 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2426 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2427 * @elseif STM32F303xC
2428 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2429 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2430 * @elseif STM32F302x8
2431 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2432 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2433 * @endif
2434 * @param TIMx Timer instance
2435 * @param Channel This parameter can be one of the following values:
2436 * @arg @ref LL_TIM_CHANNEL_CH1
2437 * @arg @ref LL_TIM_CHANNEL_CH2
2438 * @arg @ref LL_TIM_CHANNEL_CH3
2439 * @arg @ref LL_TIM_CHANNEL_CH4
2440 * @arg @ref LL_TIM_CHANNEL_CH5
2441 * @arg @ref LL_TIM_CHANNEL_CH6
2442 * @note OC5PE and OC6PE are not available for all F3 devices
2443 * @note CH5 and CH6 channels are not available for all F3 devices
2444 * @retval None
2445 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2446 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2447 {
2448 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2449 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2450 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2451 }
2452
2453 /**
2454 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2455 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2456 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2457 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2458 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2459 * @if STM32F334x8
2460 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2461 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2462 * @elseif STM32F303xC
2463 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2464 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2465 * @elseif STM32F302x8
2466 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2467 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2468 * @endif
2469 * @param TIMx Timer instance
2470 * @param Channel This parameter can be one of the following values:
2471 * @arg @ref LL_TIM_CHANNEL_CH1
2472 * @arg @ref LL_TIM_CHANNEL_CH2
2473 * @arg @ref LL_TIM_CHANNEL_CH3
2474 * @arg @ref LL_TIM_CHANNEL_CH4
2475 * @arg @ref LL_TIM_CHANNEL_CH5
2476 * @arg @ref LL_TIM_CHANNEL_CH6
2477 * @note OC5PE and OC6PE are not available for all F3 devices
2478 * @note CH5 and CH6 channels are not available for all F3 devices
2479 * @retval None
2480 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2481 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2482 {
2483 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2484 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2485 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2486 }
2487
2488 /**
2489 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2490 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2491 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2492 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2493 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2494 * @if STM32F334x8
2495 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2496 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2497 * @elseif STM32F303xC
2498 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2499 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2500 * @elseif STM32F302x8
2501 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2502 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2503 * @endif
2504 * @param TIMx Timer instance
2505 * @param Channel This parameter can be one of the following values:
2506 * @arg @ref LL_TIM_CHANNEL_CH1
2507 * @arg @ref LL_TIM_CHANNEL_CH2
2508 * @arg @ref LL_TIM_CHANNEL_CH3
2509 * @arg @ref LL_TIM_CHANNEL_CH4
2510 * @arg @ref LL_TIM_CHANNEL_CH5
2511 * @arg @ref LL_TIM_CHANNEL_CH6
2512 * @note OC5PE and OC6PE are not available for all F3 devices
2513 * @note CH5 and CH6 channels are not available for all F3 devices
2514 * @retval State of bit (1 or 0).
2515 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2516 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2517 {
2518 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2519 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2520 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2521 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2522 }
2523
2524 /**
2525 * @brief Enable clearing the output channel on an external event.
2526 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2527 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2528 * or not a timer instance can clear the OCxREF signal on an external event.
2529 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2530 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2531 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2532 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2533 * @if STM32F334x8
2534 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2535 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2536 * @elseif STM32F303xC
2537 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2538 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2539 * @elseif STM32F302x8
2540 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2541 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2542 * @endif
2543 * @param TIMx Timer instance
2544 * @param Channel This parameter can be one of the following values:
2545 * @arg @ref LL_TIM_CHANNEL_CH1
2546 * @arg @ref LL_TIM_CHANNEL_CH2
2547 * @arg @ref LL_TIM_CHANNEL_CH3
2548 * @arg @ref LL_TIM_CHANNEL_CH4
2549 * @arg @ref LL_TIM_CHANNEL_CH5
2550 * @arg @ref LL_TIM_CHANNEL_CH6
2551 * @note OC5CE and OC6CE are not available for all F3 devices
2552 * @note CH5 and CH6 channels are not available for all F3 devices
2553 * @retval None
2554 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2555 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2556 {
2557 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2558 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2559 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2560 }
2561
2562 /**
2563 * @brief Disable clearing the output channel on an external event.
2564 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2565 * or not a timer instance can clear the OCxREF signal on an external event.
2566 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2567 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2568 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2569 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2570 * @if STM32F334x8
2571 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2572 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2573 * @elseif STM32F303xC
2574 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2575 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2576 * @elseif STM32F302x8
2577 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2578 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2579 * @endif
2580 * @param TIMx Timer instance
2581 * @param Channel This parameter can be one of the following values:
2582 * @arg @ref LL_TIM_CHANNEL_CH1
2583 * @arg @ref LL_TIM_CHANNEL_CH2
2584 * @arg @ref LL_TIM_CHANNEL_CH3
2585 * @arg @ref LL_TIM_CHANNEL_CH4
2586 * @arg @ref LL_TIM_CHANNEL_CH5
2587 * @arg @ref LL_TIM_CHANNEL_CH6
2588 * @note OC5CE and OC6CE are not available for all F3 devices
2589 * @note CH5 and CH6 channels are not available for all F3 devices
2590 * @retval None
2591 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2592 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2593 {
2594 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2595 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2596 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2597 }
2598
2599 /**
2600 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2601 * @note This function enables clearing the output channel on an external event.
2602 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2603 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2604 * or not a timer instance can clear the OCxREF signal on an external event.
2605 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2606 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2607 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2608 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2609 * @if STM32F334x8
2610 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2611 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2612 * @elseif STM32F303xC
2613 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2614 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2615 * @elseif STM32F302x8
2616 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2617 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2618 * @endif
2619 * @param TIMx Timer instance
2620 * @param Channel This parameter can be one of the following values:
2621 * @arg @ref LL_TIM_CHANNEL_CH1
2622 * @arg @ref LL_TIM_CHANNEL_CH2
2623 * @arg @ref LL_TIM_CHANNEL_CH3
2624 * @arg @ref LL_TIM_CHANNEL_CH4
2625 * @arg @ref LL_TIM_CHANNEL_CH5
2626 * @arg @ref LL_TIM_CHANNEL_CH6
2627 * @note OC5CE and OC6CE are not available for all F3 devices
2628 * @note CH5 and CH6 channels are not available for all F3 devices
2629 * @retval State of bit (1 or 0).
2630 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2631 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2632 {
2633 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2634 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2635 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2636 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2637 }
2638
2639 /**
2640 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2641 * the Ocx and OCxN signals).
2642 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2643 * dead-time insertion feature is supported by a timer instance.
2644 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2645 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2646 * @param TIMx Timer instance
2647 * @param DeadTime between Min_Data=0 and Max_Data=255
2648 * @retval None
2649 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2650 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2651 {
2652 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2653 }
2654
2655 /**
2656 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2657 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2658 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2659 * whether or not a timer instance supports a 32 bits counter.
2660 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2661 * output channel 1 is supported by a timer instance.
2662 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2663 * @param TIMx Timer instance
2664 * @param CompareValue between Min_Data=0 and Max_Data=65535
2665 * @retval None
2666 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2667 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2668 {
2669 WRITE_REG(TIMx->CCR1, CompareValue);
2670 }
2671
2672 /**
2673 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2674 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2675 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2676 * whether or not a timer instance supports a 32 bits counter.
2677 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2678 * output channel 2 is supported by a timer instance.
2679 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2680 * @param TIMx Timer instance
2681 * @param CompareValue between Min_Data=0 and Max_Data=65535
2682 * @retval None
2683 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2684 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2685 {
2686 WRITE_REG(TIMx->CCR2, CompareValue);
2687 }
2688
2689 /**
2690 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2691 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2692 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2693 * whether or not a timer instance supports a 32 bits counter.
2694 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2695 * output channel is supported by a timer instance.
2696 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2697 * @param TIMx Timer instance
2698 * @param CompareValue between Min_Data=0 and Max_Data=65535
2699 * @retval None
2700 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2701 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2702 {
2703 WRITE_REG(TIMx->CCR3, CompareValue);
2704 }
2705
2706 /**
2707 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2708 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2709 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2710 * whether or not a timer instance supports a 32 bits counter.
2711 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2712 * output channel 4 is supported by a timer instance.
2713 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2714 * @param TIMx Timer instance
2715 * @param CompareValue between Min_Data=0 and Max_Data=65535
2716 * @retval None
2717 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2718 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2719 {
2720 WRITE_REG(TIMx->CCR4, CompareValue);
2721 }
2722
2723 #if defined(TIM_CCR5_CCR5)
2724 /**
2725 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2726 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2727 * output channel 5 is supported by a timer instance.
2728 * @if STM32F334x8
2729 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2730 * @elseif STM32F303xC
2731 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2732 * @elseif STM32F302x8
2733 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2734 * @endif
2735 * @param TIMx Timer instance
2736 * @param CompareValue between Min_Data=0 and Max_Data=65535
2737 * @note CH5 channel is not available for all F3 devices
2738 * @retval None
2739 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2740 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2741 {
2742 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2743 }
2744
2745 #endif /* TIM_CCR5_CCR5 */
2746 #if defined(TIM_CCR6_CCR6)
2747 /**
2748 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2749 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2750 * output channel 6 is supported by a timer instance.
2751 * @if STM32F344x8
2752 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2753 * @elseif STM32F303xC
2754 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2755 * @elseif STM32F302x8
2756 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2757 * @endif
2758 * @param TIMx Timer instance
2759 * @param CompareValue between Min_Data=0 and Max_Data=65535
2760 * @note CH6 channel is not available for all F3 devices
2761 * @retval None
2762 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2763 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2764 {
2765 WRITE_REG(TIMx->CCR6, CompareValue);
2766 }
2767
2768 #endif /* TIM_CCR6_CCR6 */
2769 /**
2770 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2771 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2772 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2773 * whether or not a timer instance supports a 32 bits counter.
2774 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2775 * output channel 1 is supported by a timer instance.
2776 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2777 * @param TIMx Timer instance
2778 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2779 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2780 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2781 {
2782 return (uint32_t)(READ_REG(TIMx->CCR1));
2783 }
2784
2785 /**
2786 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2787 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2788 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2789 * whether or not a timer instance supports a 32 bits counter.
2790 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2791 * output channel 2 is supported by a timer instance.
2792 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2793 * @param TIMx Timer instance
2794 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2795 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2796 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2797 {
2798 return (uint32_t)(READ_REG(TIMx->CCR2));
2799 }
2800
2801 /**
2802 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2803 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2804 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2805 * whether or not a timer instance supports a 32 bits counter.
2806 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2807 * output channel 3 is supported by a timer instance.
2808 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2809 * @param TIMx Timer instance
2810 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2811 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2812 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2813 {
2814 return (uint32_t)(READ_REG(TIMx->CCR3));
2815 }
2816
2817 /**
2818 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2819 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2820 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2821 * whether or not a timer instance supports a 32 bits counter.
2822 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2823 * output channel 4 is supported by a timer instance.
2824 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2825 * @param TIMx Timer instance
2826 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2827 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2828 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2829 {
2830 return (uint32_t)(READ_REG(TIMx->CCR4));
2831 }
2832
2833 #if defined(TIM_CCR5_CCR5)
2834 /**
2835 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2836 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2837 * output channel 5 is supported by a timer instance.
2838 * @if STM32F334x8
2839 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2840 * @elseif STM32F303xC
2841 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2842 * @elseif STM32F302x8
2843 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2844 * @endif
2845 * @param TIMx Timer instance
2846 * @note CH5 channel is not available for all F3 devices
2847 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2848 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2849 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2850 {
2851 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2852 }
2853
2854 #endif /* TIM_CCR5_CCR5 */
2855 #if defined(TIM_CCR6_CCR6)
2856 /**
2857 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2858 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2859 * output channel 6 is supported by a timer instance.
2860 * @if STM32F334x8
2861 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2862 * @elseif STM32F303xC
2863 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2864 * @elseif STM32F302x8
2865 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2866 * @endif
2867 * @param TIMx Timer instance
2868 * @note CH6 channel is not available for all F3 devices
2869 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2870 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2871 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2872 {
2873 return (uint32_t)(READ_REG(TIMx->CCR6));
2874 }
2875
2876 #endif /* TIM_CCR6_CCR6 */
2877 #if defined(TIM_CCR5_CCR5)
2878 /**
2879 * @brief Select on which reference signal the OC5REF is combined to.
2880 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2881 * whether or not a timer instance supports the combined 3-phase PWM mode.
2882 * @if STM32F334x8
2883 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2884 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2885 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2886 * @elseif STM32F303xC
2887 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2888 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2889 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2890 * @elseif STM32F302x8
2891 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2892 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2893 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2894 * @endif
2895 * @param TIMx Timer instance
2896 * @param GroupCH5 This parameter can be a combination of the following values:
2897 * @arg @ref LL_TIM_GROUPCH5_NONE
2898 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2899 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2900 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2901 * @note CH5 channel is not available for all F3 devices
2902 * @retval None
2903 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2904 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2905 {
2906 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2907 }
2908
2909 #endif /* TIM_CCR5_CCR5 */
2910 /**
2911 * @}
2912 */
2913
2914 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2915 * @{
2916 */
2917 /**
2918 * @brief Configure input channel.
2919 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2920 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2921 * CCMR1 IC1F LL_TIM_IC_Config\n
2922 * CCMR1 CC2S LL_TIM_IC_Config\n
2923 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2924 * CCMR1 IC2F LL_TIM_IC_Config\n
2925 * CCMR2 CC3S LL_TIM_IC_Config\n
2926 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2927 * CCMR2 IC3F LL_TIM_IC_Config\n
2928 * CCMR2 CC4S LL_TIM_IC_Config\n
2929 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2930 * CCMR2 IC4F LL_TIM_IC_Config\n
2931 * CCER CC1P LL_TIM_IC_Config\n
2932 * CCER CC1NP LL_TIM_IC_Config\n
2933 * CCER CC2P LL_TIM_IC_Config\n
2934 * CCER CC2NP LL_TIM_IC_Config\n
2935 * CCER CC3P LL_TIM_IC_Config\n
2936 * CCER CC3NP LL_TIM_IC_Config\n
2937 * CCER CC4P LL_TIM_IC_Config\n
2938 * CCER CC4NP LL_TIM_IC_Config
2939 * @param TIMx Timer instance
2940 * @param Channel This parameter can be one of the following values:
2941 * @arg @ref LL_TIM_CHANNEL_CH1
2942 * @arg @ref LL_TIM_CHANNEL_CH2
2943 * @arg @ref LL_TIM_CHANNEL_CH3
2944 * @arg @ref LL_TIM_CHANNEL_CH4
2945 * @param Configuration This parameter must be a combination of all the following values:
2946 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2947 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2948 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2949 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2950 * @retval None
2951 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2952 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2953 {
2954 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2955 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2956 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2957 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2958 << SHIFT_TAB_ICxx[iChannel]);
2959 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2960 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2961 }
2962
2963 /**
2964 * @brief Set the active input.
2965 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2966 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2967 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2968 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2969 * @param TIMx Timer instance
2970 * @param Channel This parameter can be one of the following values:
2971 * @arg @ref LL_TIM_CHANNEL_CH1
2972 * @arg @ref LL_TIM_CHANNEL_CH2
2973 * @arg @ref LL_TIM_CHANNEL_CH3
2974 * @arg @ref LL_TIM_CHANNEL_CH4
2975 * @param ICActiveInput This parameter can be one of the following values:
2976 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2977 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2978 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2979 * @retval None
2980 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2981 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2982 {
2983 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2984 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2985 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2986 }
2987
2988 /**
2989 * @brief Get the current active input.
2990 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2991 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2992 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2993 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2994 * @param TIMx Timer instance
2995 * @param Channel This parameter can be one of the following values:
2996 * @arg @ref LL_TIM_CHANNEL_CH1
2997 * @arg @ref LL_TIM_CHANNEL_CH2
2998 * @arg @ref LL_TIM_CHANNEL_CH3
2999 * @arg @ref LL_TIM_CHANNEL_CH4
3000 * @retval Returned value can be one of the following values:
3001 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3002 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3003 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3004 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3005 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3006 {
3007 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3008 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3009 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3010 }
3011
3012 /**
3013 * @brief Set the prescaler of input channel.
3014 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3015 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3016 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3017 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3018 * @param TIMx Timer instance
3019 * @param Channel This parameter can be one of the following values:
3020 * @arg @ref LL_TIM_CHANNEL_CH1
3021 * @arg @ref LL_TIM_CHANNEL_CH2
3022 * @arg @ref LL_TIM_CHANNEL_CH3
3023 * @arg @ref LL_TIM_CHANNEL_CH4
3024 * @param ICPrescaler This parameter can be one of the following values:
3025 * @arg @ref LL_TIM_ICPSC_DIV1
3026 * @arg @ref LL_TIM_ICPSC_DIV2
3027 * @arg @ref LL_TIM_ICPSC_DIV4
3028 * @arg @ref LL_TIM_ICPSC_DIV8
3029 * @retval None
3030 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3031 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3032 {
3033 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3034 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3035 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3036 }
3037
3038 /**
3039 * @brief Get the current prescaler value acting on an input channel.
3040 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3041 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3042 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3043 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3044 * @param TIMx Timer instance
3045 * @param Channel This parameter can be one of the following values:
3046 * @arg @ref LL_TIM_CHANNEL_CH1
3047 * @arg @ref LL_TIM_CHANNEL_CH2
3048 * @arg @ref LL_TIM_CHANNEL_CH3
3049 * @arg @ref LL_TIM_CHANNEL_CH4
3050 * @retval Returned value can be one of the following values:
3051 * @arg @ref LL_TIM_ICPSC_DIV1
3052 * @arg @ref LL_TIM_ICPSC_DIV2
3053 * @arg @ref LL_TIM_ICPSC_DIV4
3054 * @arg @ref LL_TIM_ICPSC_DIV8
3055 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3056 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3057 {
3058 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3059 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3060 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3061 }
3062
3063 /**
3064 * @brief Set the input filter duration.
3065 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3066 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3067 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3068 * CCMR2 IC4F LL_TIM_IC_SetFilter
3069 * @param TIMx Timer instance
3070 * @param Channel This parameter can be one of the following values:
3071 * @arg @ref LL_TIM_CHANNEL_CH1
3072 * @arg @ref LL_TIM_CHANNEL_CH2
3073 * @arg @ref LL_TIM_CHANNEL_CH3
3074 * @arg @ref LL_TIM_CHANNEL_CH4
3075 * @param ICFilter This parameter can be one of the following values:
3076 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3077 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3078 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3079 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3080 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3081 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3082 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3083 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3084 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3085 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3086 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3087 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3088 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3089 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3090 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3091 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3092 * @retval None
3093 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3094 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3095 {
3096 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3097 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3098 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3099 }
3100
3101 /**
3102 * @brief Get the input filter duration.
3103 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3104 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3105 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3106 * CCMR2 IC4F LL_TIM_IC_GetFilter
3107 * @param TIMx Timer instance
3108 * @param Channel This parameter can be one of the following values:
3109 * @arg @ref LL_TIM_CHANNEL_CH1
3110 * @arg @ref LL_TIM_CHANNEL_CH2
3111 * @arg @ref LL_TIM_CHANNEL_CH3
3112 * @arg @ref LL_TIM_CHANNEL_CH4
3113 * @retval Returned value can be one of the following values:
3114 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3115 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3116 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3117 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3118 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3119 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3120 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3121 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3122 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3123 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3124 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3125 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3126 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3127 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3128 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3129 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3130 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3131 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3132 {
3133 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3134 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3135 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3136 }
3137
3138 /**
3139 * @brief Set the input channel polarity.
3140 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3141 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3142 * CCER CC2P LL_TIM_IC_SetPolarity\n
3143 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3144 * CCER CC3P LL_TIM_IC_SetPolarity\n
3145 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3146 * CCER CC4P LL_TIM_IC_SetPolarity\n
3147 * CCER CC4NP LL_TIM_IC_SetPolarity
3148 * @param TIMx Timer instance
3149 * @param Channel This parameter can be one of the following values:
3150 * @arg @ref LL_TIM_CHANNEL_CH1
3151 * @arg @ref LL_TIM_CHANNEL_CH2
3152 * @arg @ref LL_TIM_CHANNEL_CH3
3153 * @arg @ref LL_TIM_CHANNEL_CH4
3154 * @param ICPolarity This parameter can be one of the following values:
3155 * @arg @ref LL_TIM_IC_POLARITY_RISING
3156 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3157 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3158 * @retval None
3159 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3160 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3161 {
3162 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3163 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3164 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3165 }
3166
3167 /**
3168 * @brief Get the current input channel polarity.
3169 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3170 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3171 * CCER CC2P LL_TIM_IC_GetPolarity\n
3172 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3173 * CCER CC3P LL_TIM_IC_GetPolarity\n
3174 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3175 * CCER CC4P LL_TIM_IC_GetPolarity\n
3176 * CCER CC4NP LL_TIM_IC_GetPolarity
3177 * @param TIMx Timer instance
3178 * @param Channel This parameter can be one of the following values:
3179 * @arg @ref LL_TIM_CHANNEL_CH1
3180 * @arg @ref LL_TIM_CHANNEL_CH2
3181 * @arg @ref LL_TIM_CHANNEL_CH3
3182 * @arg @ref LL_TIM_CHANNEL_CH4
3183 * @retval Returned value can be one of the following values:
3184 * @arg @ref LL_TIM_IC_POLARITY_RISING
3185 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3186 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3187 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3188 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3189 {
3190 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3191 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3192 SHIFT_TAB_CCxP[iChannel]);
3193 }
3194
3195 /**
3196 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3197 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3198 * a timer instance provides an XOR input.
3199 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3200 * @param TIMx Timer instance
3201 * @retval None
3202 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3203 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3204 {
3205 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3206 }
3207
3208 /**
3209 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3210 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3211 * a timer instance provides an XOR input.
3212 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3213 * @param TIMx Timer instance
3214 * @retval None
3215 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3216 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3217 {
3218 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3219 }
3220
3221 /**
3222 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3223 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3224 * a timer instance provides an XOR input.
3225 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3226 * @param TIMx Timer instance
3227 * @retval State of bit (1 or 0).
3228 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3229 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3230 {
3231 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3232 }
3233
3234 /**
3235 * @brief Get captured value for input channel 1.
3236 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3237 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3238 * whether or not a timer instance supports a 32 bits counter.
3239 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3240 * input channel 1 is supported by a timer instance.
3241 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3242 * @param TIMx Timer instance
3243 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3244 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3245 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3246 {
3247 return (uint32_t)(READ_REG(TIMx->CCR1));
3248 }
3249
3250 /**
3251 * @brief Get captured value for input channel 2.
3252 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3253 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3254 * whether or not a timer instance supports a 32 bits counter.
3255 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3256 * input channel 2 is supported by a timer instance.
3257 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3258 * @param TIMx Timer instance
3259 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3260 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3261 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3262 {
3263 return (uint32_t)(READ_REG(TIMx->CCR2));
3264 }
3265
3266 /**
3267 * @brief Get captured value for input channel 3.
3268 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3269 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3270 * whether or not a timer instance supports a 32 bits counter.
3271 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3272 * input channel 3 is supported by a timer instance.
3273 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3274 * @param TIMx Timer instance
3275 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3276 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3277 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3278 {
3279 return (uint32_t)(READ_REG(TIMx->CCR3));
3280 }
3281
3282 /**
3283 * @brief Get captured value for input channel 4.
3284 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3285 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3286 * whether or not a timer instance supports a 32 bits counter.
3287 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3288 * input channel 4 is supported by a timer instance.
3289 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3290 * @param TIMx Timer instance
3291 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3292 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3293 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3294 {
3295 return (uint32_t)(READ_REG(TIMx->CCR4));
3296 }
3297
3298 /**
3299 * @}
3300 */
3301
3302 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3303 * @{
3304 */
3305 /**
3306 * @brief Enable external clock mode 2.
3307 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3308 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3309 * whether or not a timer instance supports external clock mode2.
3310 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3311 * @param TIMx Timer instance
3312 * @retval None
3313 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3314 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3315 {
3316 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3317 }
3318
3319 /**
3320 * @brief Disable external clock mode 2.
3321 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3322 * whether or not a timer instance supports external clock mode2.
3323 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3324 * @param TIMx Timer instance
3325 * @retval None
3326 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3327 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3328 {
3329 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3330 }
3331
3332 /**
3333 * @brief Indicate whether external clock mode 2 is enabled.
3334 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3335 * whether or not a timer instance supports external clock mode2.
3336 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3337 * @param TIMx Timer instance
3338 * @retval State of bit (1 or 0).
3339 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3340 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3341 {
3342 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3343 }
3344
3345 /**
3346 * @brief Set the clock source of the counter clock.
3347 * @note when selected clock source is external clock mode 1, the timer input
3348 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3349 * function. This timer input must be configured by calling
3350 * the @ref LL_TIM_IC_Config() function.
3351 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3352 * whether or not a timer instance supports external clock mode1.
3353 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3354 * whether or not a timer instance supports external clock mode2.
3355 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3356 * SMCR ECE LL_TIM_SetClockSource
3357 * @param TIMx Timer instance
3358 * @param ClockSource This parameter can be one of the following values:
3359 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3360 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3361 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3362 * @retval None
3363 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3364 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3365 {
3366 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3367 }
3368
3369 /**
3370 * @brief Set the encoder interface mode.
3371 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3372 * whether or not a timer instance supports the encoder mode.
3373 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3374 * @param TIMx Timer instance
3375 * @param EncoderMode This parameter can be one of the following values:
3376 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3377 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3378 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3379 * @retval None
3380 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3381 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3382 {
3383 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3384 }
3385
3386 /**
3387 * @}
3388 */
3389
3390 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3391 * @{
3392 */
3393 /**
3394 * @brief Set the trigger output (TRGO) used for timer synchronization .
3395 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3396 * whether or not a timer instance can operate as a master timer.
3397 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3398 * @param TIMx Timer instance
3399 * @param TimerSynchronization This parameter can be one of the following values:
3400 * @arg @ref LL_TIM_TRGO_RESET
3401 * @arg @ref LL_TIM_TRGO_ENABLE
3402 * @arg @ref LL_TIM_TRGO_UPDATE
3403 * @arg @ref LL_TIM_TRGO_CC1IF
3404 * @arg @ref LL_TIM_TRGO_OC1REF
3405 * @arg @ref LL_TIM_TRGO_OC2REF
3406 * @arg @ref LL_TIM_TRGO_OC3REF
3407 * @arg @ref LL_TIM_TRGO_OC4REF
3408 * @retval None
3409 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3410 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3411 {
3412 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3413 }
3414
3415 #if defined(TIM_CR2_MMS2)
3416 /**
3417 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3418 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3419 * whether or not a timer instance can be used for ADC synchronization.
3420 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3421 * @param TIMx Timer Instance
3422 * @param ADCSynchronization This parameter can be one of the following values:
3423 * @arg @ref LL_TIM_TRGO2_RESET
3424 * @arg @ref LL_TIM_TRGO2_ENABLE
3425 * @arg @ref LL_TIM_TRGO2_UPDATE
3426 * @arg @ref LL_TIM_TRGO2_CC1F
3427 * @arg @ref LL_TIM_TRGO2_OC1
3428 * @arg @ref LL_TIM_TRGO2_OC2
3429 * @arg @ref LL_TIM_TRGO2_OC3
3430 * @arg @ref LL_TIM_TRGO2_OC4
3431 * @arg @ref LL_TIM_TRGO2_OC5
3432 * @arg @ref LL_TIM_TRGO2_OC6
3433 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3434 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3435 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3436 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3437 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3438 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3439 * @note OC5 and OC6 are not available for all F3 devices
3440 * @retval None
3441 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3442 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3443 {
3444 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3445 }
3446
3447 #endif /* TIM_CR2_MMS2 */
3448 /**
3449 * @brief Set the synchronization mode of a slave timer.
3450 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3451 * a timer instance can operate as a slave timer.
3452 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3453 * @param TIMx Timer instance
3454 * @param SlaveMode This parameter can be one of the following values:
3455 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3456 * @arg @ref LL_TIM_SLAVEMODE_RESET
3457 * @arg @ref LL_TIM_SLAVEMODE_GATED
3458 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3459 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3460 * @retval None
3461 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3462 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3463 {
3464 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3465 }
3466
3467 /**
3468 * @brief Set the selects the trigger input to be used to synchronize the counter.
3469 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3470 * a timer instance can operate as a slave timer.
3471 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3472 * @param TIMx Timer instance
3473 * @param TriggerInput This parameter can be one of the following values:
3474 * @arg @ref LL_TIM_TS_ITR0
3475 * @arg @ref LL_TIM_TS_ITR1
3476 * @arg @ref LL_TIM_TS_ITR2
3477 * @arg @ref LL_TIM_TS_ITR3
3478 * @arg @ref LL_TIM_TS_TI1F_ED
3479 * @arg @ref LL_TIM_TS_TI1FP1
3480 * @arg @ref LL_TIM_TS_TI2FP2
3481 * @arg @ref LL_TIM_TS_ETRF
3482 * @retval None
3483 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3484 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3485 {
3486 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3487 }
3488
3489 /**
3490 * @brief Enable the Master/Slave mode.
3491 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3492 * a timer instance can operate as a slave timer.
3493 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3494 * @param TIMx Timer instance
3495 * @retval None
3496 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3497 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3498 {
3499 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3500 }
3501
3502 /**
3503 * @brief Disable the Master/Slave mode.
3504 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3505 * a timer instance can operate as a slave timer.
3506 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3507 * @param TIMx Timer instance
3508 * @retval None
3509 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3510 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3511 {
3512 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3513 }
3514
3515 /**
3516 * @brief Indicates whether the Master/Slave mode is enabled.
3517 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3518 * a timer instance can operate as a slave timer.
3519 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3520 * @param TIMx Timer instance
3521 * @retval State of bit (1 or 0).
3522 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3523 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3524 {
3525 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3526 }
3527
3528 /**
3529 * @brief Configure the external trigger (ETR) input.
3530 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3531 * a timer instance provides an external trigger input.
3532 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3533 * SMCR ETPS LL_TIM_ConfigETR\n
3534 * SMCR ETF LL_TIM_ConfigETR
3535 * @param TIMx Timer instance
3536 * @param ETRPolarity This parameter can be one of the following values:
3537 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3538 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3539 * @param ETRPrescaler This parameter can be one of the following values:
3540 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3541 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3542 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3543 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3544 * @param ETRFilter This parameter can be one of the following values:
3545 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3546 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3547 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3548 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3549 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3550 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3551 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3552 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3553 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3554 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3555 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3556 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3557 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3558 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3559 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3560 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3561 * @retval None
3562 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3563 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3564 uint32_t ETRFilter)
3565 {
3566 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3567 }
3568
3569 /**
3570 * @}
3571 */
3572
3573 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3574 * @{
3575 */
3576 /**
3577 * @brief Enable the break function.
3578 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3579 * a timer instance provides a break input.
3580 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3581 * @param TIMx Timer instance
3582 * @retval None
3583 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3584 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3585 {
3586 #if defined(TIM_IP_V2_1)
3587 __IO uint32_t tmpreg;
3588 #endif /* TIM_IP_V2_1 */
3589 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3590 #if defined(TIM_IP_V2_1)
3591 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3592 tmpreg = READ_REG(TIMx->BDTR);
3593 (void)(tmpreg);
3594 #endif /* TIM_IP_V2_1 */
3595 }
3596
3597 /**
3598 * @brief Disable the break function.
3599 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3600 * @param TIMx Timer instance
3601 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3602 * a timer instance provides a break input.
3603 * @retval None
3604 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3605 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3606 {
3607 #if defined(TIM_IP_V2_1)
3608 __IO uint32_t tmpreg;
3609 #endif /* TIM_IP_V2_1 */
3610 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3611 #if defined(TIM_IP_V2_1)
3612 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3613 tmpreg = READ_REG(TIMx->BDTR);
3614 (void)(tmpreg);
3615 #endif /* TIM_IP_V2_1 */
3616 }
3617
3618 #if defined(TIM_BDTR_BKF)
3619 /**
3620 * @brief Configure the break input.
3621 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3622 * a timer instance provides a break input.
3623 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3624 * BDTR BKF LL_TIM_ConfigBRK
3625 * @param TIMx Timer instance
3626 * @param BreakPolarity This parameter can be one of the following values:
3627 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3628 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3629 * @param BreakFilter This parameter can be one of the following values:
3630 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3631 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3632 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3633 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3634 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3635 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3636 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3637 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3638 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3639 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3640 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3641 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3642 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3643 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3644 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3645 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3646 * @retval None
3647 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3648 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3649 uint32_t BreakFilter)
3650 {
3651 #if defined(TIM_IP_V2_1)
3652 __IO uint32_t tmpreg;
3653 #endif /* TIM_IP_V2_1 */
3654 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3655 #if defined(TIM_IP_V2_1)
3656 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
3657 tmpreg = READ_REG(TIMx->BDTR);
3658 (void)(tmpreg);
3659 #endif /* TIM_IP_V2_1 */
3660 }
3661
3662 #else
3663 /**
3664 * @brief Configure the break input.
3665 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3666 * a timer instance provides a break input.
3667 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
3668 * @param TIMx Timer instance
3669 * @param BreakPolarity This parameter can be one of the following values:
3670 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3671 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3672 * @retval None
3673 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)3674 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
3675 {
3676 #if defined(TIM_IP_V2_1)
3677 __IO uint32_t tmpreg;
3678 #endif /* TIM_IP_V2_1 */
3679 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
3680 #if defined(TIM_IP_V2_1)
3681 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
3682 tmpreg = READ_REG(TIMx->BDTR);
3683 (void)(tmpreg);
3684 #endif /* TIM_IP_V2_1 */
3685 }
3686
3687 #endif /* TIM_BDTR_BKF */
3688 #if defined(TIM_BDTR_BK2E)
3689 /**
3690 * @brief Enable the break 2 function.
3691 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3692 * a timer instance provides a second break input.
3693 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3694 * @param TIMx Timer instance
3695 * @retval None
3696 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3697 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3698 {
3699 #if defined(TIM_IP_V2_1)
3700 __IO uint32_t tmpreg;
3701 #endif /* TIM_IP_V2_1 */
3702 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3703 #if defined(TIM_IP_V2_1)
3704 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3705 tmpreg = READ_REG(TIMx->BDTR);
3706 (void)(tmpreg);
3707 #endif /* TIM_IP_V2_1 */
3708 }
3709
3710 /**
3711 * @brief Disable the break 2 function.
3712 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3713 * a timer instance provides a second break input.
3714 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3715 * @param TIMx Timer instance
3716 * @retval None
3717 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3718 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3719 {
3720 #if defined(TIM_IP_V2_1)
3721 __IO uint32_t tmpreg;
3722 #endif /* TIM_IP_V2_1 */
3723 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3724 #if defined(TIM_IP_V2_1)
3725 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3726 tmpreg = READ_REG(TIMx->BDTR);
3727 (void)(tmpreg);
3728 #endif /* TIM_IP_V2_1 */
3729 }
3730
3731 /**
3732 * @brief Configure the break 2 input.
3733 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3734 * a timer instance provides a second break input.
3735 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3736 * BDTR BK2F LL_TIM_ConfigBRK2
3737 * @param TIMx Timer instance
3738 * @param Break2Polarity This parameter can be one of the following values:
3739 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3740 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3741 * @param Break2Filter This parameter can be one of the following values:
3742 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3743 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3744 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3745 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3746 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3747 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3748 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3749 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3750 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3751 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3752 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3753 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3754 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3755 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3756 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3757 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3758 * @retval None
3759 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3760 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3761 {
3762 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3763 }
3764
3765 #endif /* TIM_BDTR_BK2E */
3766 /**
3767 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3768 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3769 * a timer instance provides a break input.
3770 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3771 * BDTR OSSR LL_TIM_SetOffStates
3772 * @param TIMx Timer instance
3773 * @param OffStateIdle This parameter can be one of the following values:
3774 * @arg @ref LL_TIM_OSSI_DISABLE
3775 * @arg @ref LL_TIM_OSSI_ENABLE
3776 * @param OffStateRun This parameter can be one of the following values:
3777 * @arg @ref LL_TIM_OSSR_DISABLE
3778 * @arg @ref LL_TIM_OSSR_ENABLE
3779 * @retval None
3780 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3781 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3782 {
3783 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3784 }
3785
3786 /**
3787 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3788 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3789 * a timer instance provides a break input.
3790 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3791 * @param TIMx Timer instance
3792 * @retval None
3793 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3794 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3795 {
3796 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3797 }
3798
3799 /**
3800 * @brief Disable automatic output (MOE can be set only by software).
3801 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3802 * a timer instance provides a break input.
3803 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3804 * @param TIMx Timer instance
3805 * @retval None
3806 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3807 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3808 {
3809 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3810 }
3811
3812 /**
3813 * @brief Indicate whether automatic output is enabled.
3814 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3815 * a timer instance provides a break input.
3816 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3817 * @param TIMx Timer instance
3818 * @retval State of bit (1 or 0).
3819 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3820 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3821 {
3822 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3823 }
3824
3825 /**
3826 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3827 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3828 * software and is reset in case of break or break2 event
3829 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3830 * a timer instance provides a break input.
3831 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3832 * @param TIMx Timer instance
3833 * @retval None
3834 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3835 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3836 {
3837 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3838 }
3839
3840 /**
3841 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3842 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3843 * software and is reset in case of break or break2 event.
3844 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3845 * a timer instance provides a break input.
3846 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3847 * @param TIMx Timer instance
3848 * @retval None
3849 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3850 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3851 {
3852 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3853 }
3854
3855 /**
3856 * @brief Indicates whether outputs are enabled.
3857 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3858 * a timer instance provides a break input.
3859 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3860 * @param TIMx Timer instance
3861 * @retval State of bit (1 or 0).
3862 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3863 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3864 {
3865 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3866 }
3867
3868 /**
3869 * @}
3870 */
3871
3872 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3873 * @{
3874 */
3875 /**
3876 * @brief Configures the timer DMA burst feature.
3877 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3878 * not a timer instance supports the DMA burst mode.
3879 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3880 * DCR DBA LL_TIM_ConfigDMABurst
3881 * @param TIMx Timer instance
3882 * @param DMABurstBaseAddress This parameter can be one of the following values:
3883 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3884 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3885 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3886 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3887 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3888 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3889 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3890 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3891 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3892 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3893 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3894 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3895 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3896 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3897 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3898 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3899 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3900 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3901 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3902 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
3903 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
3904 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
3905 * (*) value not defined in all devices
3906 * @param DMABurstLength This parameter can be one of the following values:
3907 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3908 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3909 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3910 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3911 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3912 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3913 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3914 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3915 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3916 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3917 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3918 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3919 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3920 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3921 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3922 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3923 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3924 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3925 * @retval None
3926 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3927 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3928 {
3929 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3930 }
3931
3932 /**
3933 * @}
3934 */
3935
3936 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3937 * @{
3938 */
3939 /**
3940 * @brief Remap TIM inputs (input channel, internal/external triggers).
3941 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3942 * a some timer inputs can be remapped.
3943 * @if STM32F334x8
3944 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3945 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3946 * @elseif STM32F302x8
3947 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3948 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3949 * @elseif STM32F303xC
3950 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3951 * TIM8_OR ETR_RMP LL_TIM_SetRemap\n
3952 * TIM20_OR ETR_RMP LL_TIM_SetRemap\n
3953 * @elseif STM32F373xC
3954 * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
3955 * @endif
3956 * @param TIMx Timer instance
3957 * @param Remap Remap params depends on the TIMx. Description available only
3958 * in CHM version of the User Manual (not in .pdf).
3959 * Otherwise see Reference Manual description of OR registers.
3960 *
3961 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3962 *
3963 * TIM1: any combination of ETR_RMP where (**)
3964 *
3965 * . . ETR_RMP can be one of the following values
3966 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3967 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
3968 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
3969 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
3970 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
3971 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
3972 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
3973 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
3974 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
3975 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
3976 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
3977 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
3978 *
3979 * TIM8: any combination of ETR_RMP where (**)
3980 *
3981 * . . ETR_RMP can be one of the following values
3982 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
3983 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
3984 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
3985 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
3986 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
3987 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
3988 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
3989 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
3990 *
3991 * TIM14: any combination of TI1_RMP where (**)
3992 *
3993 * . . TI1_RMP can be one of the following values
3994 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
3995 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
3996 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
3997 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
3998 *
3999 * TIM16: any combination of TI1_RMP where (**)
4000 *
4001 * . . TI1_RMP can be one of the following values
4002 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
4003 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
4004 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
4005 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
4006 *
4007 * TIM20: any combination of ETR_RMP where (**)
4008 *
4009 * . . ETR_RMP can be one of the following values
4010 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
4011 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
4012 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
4013 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
4014 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
4015 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
4016 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
4017 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
4018 *
4019 * (*) Value not defined in all devices. \n
4020 * (**) Register not available in all devices.
4021 * @retval None
4022 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4023 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4024 {
4025 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
4026 }
4027
4028 /**
4029 * @}
4030 */
4031 #if defined(TIM_SMCR_OCCS)
4032
4033 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4034 * @{
4035 */
4036 /**
4037 * @brief Set the OCREF clear input source
4038 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4039 * @note This function can only be used in Output compare and PWM modes.
4040 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4041 * @param TIMx Timer instance
4042 * @param OCRefClearInputSource This parameter can be one of the following values:
4043 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
4044 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4045 * @retval None
4046 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4047 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4048 {
4049 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4050 }
4051 /**
4052 * @}
4053 */
4054 #endif /* TIM_SMCR_OCCS */
4055
4056 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4057 * @{
4058 */
4059 /**
4060 * @brief Clear the update interrupt flag (UIF).
4061 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4062 * @param TIMx Timer instance
4063 * @retval None
4064 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4065 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4066 {
4067 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4068 }
4069
4070 /**
4071 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4072 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4073 * @param TIMx Timer instance
4074 * @retval State of bit (1 or 0).
4075 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4076 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4077 {
4078 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4079 }
4080
4081 /**
4082 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4083 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4084 * @param TIMx Timer instance
4085 * @retval None
4086 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4087 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4088 {
4089 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4090 }
4091
4092 /**
4093 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4094 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4095 * @param TIMx Timer instance
4096 * @retval State of bit (1 or 0).
4097 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4098 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4099 {
4100 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4101 }
4102
4103 /**
4104 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4105 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4106 * @param TIMx Timer instance
4107 * @retval None
4108 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4109 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4110 {
4111 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4112 }
4113
4114 /**
4115 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4116 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4117 * @param TIMx Timer instance
4118 * @retval State of bit (1 or 0).
4119 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4120 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4121 {
4122 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4123 }
4124
4125 /**
4126 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4127 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4128 * @param TIMx Timer instance
4129 * @retval None
4130 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4131 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4132 {
4133 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4134 }
4135
4136 /**
4137 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4138 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4139 * @param TIMx Timer instance
4140 * @retval State of bit (1 or 0).
4141 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4142 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4143 {
4144 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4145 }
4146
4147 /**
4148 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4149 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4150 * @param TIMx Timer instance
4151 * @retval None
4152 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4153 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4154 {
4155 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4156 }
4157
4158 /**
4159 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4160 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4161 * @param TIMx Timer instance
4162 * @retval State of bit (1 or 0).
4163 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4164 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4165 {
4166 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4167 }
4168
4169 #if defined (TIM_SR_CC5IF)
4170 /**
4171 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4172 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4173 * @param TIMx Timer instance
4174 * @retval None
4175 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4176 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4177 {
4178 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4179 }
4180
4181 /**
4182 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4183 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4184 * @param TIMx Timer instance
4185 * @retval State of bit (1 or 0).
4186 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4187 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4188 {
4189 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4190 }
4191
4192 #endif /* TIM_SR_CC5IF */
4193 #if defined (TIM_SR_CC6IF)
4194 /**
4195 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4196 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4197 * @param TIMx Timer instance
4198 * @retval None
4199 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4200 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4201 {
4202 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4203 }
4204
4205 /**
4206 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4207 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4208 * @param TIMx Timer instance
4209 * @retval State of bit (1 or 0).
4210 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4211 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4212 {
4213 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4214 }
4215
4216 #endif /* TIM_SR_CC6IF */
4217 /**
4218 * @brief Clear the commutation interrupt flag (COMIF).
4219 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4220 * @param TIMx Timer instance
4221 * @retval None
4222 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4223 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4224 {
4225 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4226 }
4227
4228 /**
4229 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4230 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4231 * @param TIMx Timer instance
4232 * @retval State of bit (1 or 0).
4233 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4234 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4235 {
4236 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4237 }
4238
4239 /**
4240 * @brief Clear the trigger interrupt flag (TIF).
4241 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4242 * @param TIMx Timer instance
4243 * @retval None
4244 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4245 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4246 {
4247 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4248 }
4249
4250 /**
4251 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4252 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4253 * @param TIMx Timer instance
4254 * @retval State of bit (1 or 0).
4255 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4256 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4257 {
4258 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4259 }
4260
4261 /**
4262 * @brief Clear the break interrupt flag (BIF).
4263 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4264 * @param TIMx Timer instance
4265 * @retval None
4266 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4267 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4268 {
4269 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4270 }
4271
4272 /**
4273 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4274 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4275 * @param TIMx Timer instance
4276 * @retval State of bit (1 or 0).
4277 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4278 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4279 {
4280 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4281 }
4282
4283 #if defined(TIM_SR_B2IF)
4284 /**
4285 * @brief Clear the break 2 interrupt flag (B2IF).
4286 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4287 * @param TIMx Timer instance
4288 * @retval None
4289 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4290 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4291 {
4292 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4293 }
4294
4295 /**
4296 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4297 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4298 * @param TIMx Timer instance
4299 * @retval State of bit (1 or 0).
4300 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4301 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4302 {
4303 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4304 }
4305
4306 #endif /* TIM_SR_B2IF */
4307 /**
4308 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4309 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4310 * @param TIMx Timer instance
4311 * @retval None
4312 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4313 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4314 {
4315 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4316 }
4317
4318 /**
4319 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4320 * (Capture/Compare 1 interrupt is pending).
4321 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4322 * @param TIMx Timer instance
4323 * @retval State of bit (1 or 0).
4324 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4325 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4326 {
4327 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4328 }
4329
4330 /**
4331 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4332 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4333 * @param TIMx Timer instance
4334 * @retval None
4335 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4336 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4337 {
4338 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4339 }
4340
4341 /**
4342 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4343 * (Capture/Compare 2 over-capture interrupt is pending).
4344 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4345 * @param TIMx Timer instance
4346 * @retval State of bit (1 or 0).
4347 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4348 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4349 {
4350 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4351 }
4352
4353 /**
4354 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4355 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4356 * @param TIMx Timer instance
4357 * @retval None
4358 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4359 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4360 {
4361 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4362 }
4363
4364 /**
4365 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4366 * (Capture/Compare 3 over-capture interrupt is pending).
4367 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4368 * @param TIMx Timer instance
4369 * @retval State of bit (1 or 0).
4370 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4371 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4372 {
4373 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4374 }
4375
4376 /**
4377 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4378 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4379 * @param TIMx Timer instance
4380 * @retval None
4381 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4382 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4383 {
4384 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4385 }
4386
4387 /**
4388 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4389 * (Capture/Compare 4 over-capture interrupt is pending).
4390 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4391 * @param TIMx Timer instance
4392 * @retval State of bit (1 or 0).
4393 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4394 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4395 {
4396 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4397 }
4398
4399 /**
4400 * @}
4401 */
4402
4403 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4404 * @{
4405 */
4406 /**
4407 * @brief Enable update interrupt (UIE).
4408 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4409 * @param TIMx Timer instance
4410 * @retval None
4411 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4412 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4413 {
4414 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4415 }
4416
4417 /**
4418 * @brief Disable update interrupt (UIE).
4419 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4420 * @param TIMx Timer instance
4421 * @retval None
4422 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4423 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4424 {
4425 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4426 }
4427
4428 /**
4429 * @brief Indicates whether the update interrupt (UIE) is enabled.
4430 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4431 * @param TIMx Timer instance
4432 * @retval State of bit (1 or 0).
4433 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4434 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4435 {
4436 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4437 }
4438
4439 /**
4440 * @brief Enable capture/compare 1 interrupt (CC1IE).
4441 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4445 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4446 {
4447 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4448 }
4449
4450 /**
4451 * @brief Disable capture/compare 1 interrupt (CC1IE).
4452 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4453 * @param TIMx Timer instance
4454 * @retval None
4455 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4456 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4457 {
4458 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4459 }
4460
4461 /**
4462 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4463 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4464 * @param TIMx Timer instance
4465 * @retval State of bit (1 or 0).
4466 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4467 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4468 {
4469 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4470 }
4471
4472 /**
4473 * @brief Enable capture/compare 2 interrupt (CC2IE).
4474 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4475 * @param TIMx Timer instance
4476 * @retval None
4477 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4478 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4479 {
4480 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4481 }
4482
4483 /**
4484 * @brief Disable capture/compare 2 interrupt (CC2IE).
4485 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4486 * @param TIMx Timer instance
4487 * @retval None
4488 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4489 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4490 {
4491 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4492 }
4493
4494 /**
4495 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4496 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4497 * @param TIMx Timer instance
4498 * @retval State of bit (1 or 0).
4499 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4500 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4501 {
4502 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4503 }
4504
4505 /**
4506 * @brief Enable capture/compare 3 interrupt (CC3IE).
4507 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4508 * @param TIMx Timer instance
4509 * @retval None
4510 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4511 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4512 {
4513 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4514 }
4515
4516 /**
4517 * @brief Disable capture/compare 3 interrupt (CC3IE).
4518 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4519 * @param TIMx Timer instance
4520 * @retval None
4521 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4522 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4523 {
4524 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4525 }
4526
4527 /**
4528 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4529 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4530 * @param TIMx Timer instance
4531 * @retval State of bit (1 or 0).
4532 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4533 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4534 {
4535 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4536 }
4537
4538 /**
4539 * @brief Enable capture/compare 4 interrupt (CC4IE).
4540 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4541 * @param TIMx Timer instance
4542 * @retval None
4543 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4544 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4545 {
4546 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4547 }
4548
4549 /**
4550 * @brief Disable capture/compare 4 interrupt (CC4IE).
4551 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4552 * @param TIMx Timer instance
4553 * @retval None
4554 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4555 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4556 {
4557 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4558 }
4559
4560 /**
4561 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4562 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4563 * @param TIMx Timer instance
4564 * @retval State of bit (1 or 0).
4565 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4566 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4567 {
4568 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4569 }
4570
4571 /**
4572 * @brief Enable commutation interrupt (COMIE).
4573 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4574 * @param TIMx Timer instance
4575 * @retval None
4576 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4577 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4578 {
4579 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4580 }
4581
4582 /**
4583 * @brief Disable commutation interrupt (COMIE).
4584 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4585 * @param TIMx Timer instance
4586 * @retval None
4587 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4588 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4589 {
4590 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4591 }
4592
4593 /**
4594 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4595 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4596 * @param TIMx Timer instance
4597 * @retval State of bit (1 or 0).
4598 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4599 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4600 {
4601 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4602 }
4603
4604 /**
4605 * @brief Enable trigger interrupt (TIE).
4606 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4607 * @param TIMx Timer instance
4608 * @retval None
4609 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4610 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4611 {
4612 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4613 }
4614
4615 /**
4616 * @brief Disable trigger interrupt (TIE).
4617 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4618 * @param TIMx Timer instance
4619 * @retval None
4620 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4621 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4622 {
4623 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4624 }
4625
4626 /**
4627 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4628 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4629 * @param TIMx Timer instance
4630 * @retval State of bit (1 or 0).
4631 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4632 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4633 {
4634 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4635 }
4636
4637 /**
4638 * @brief Enable break interrupt (BIE).
4639 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4640 * @param TIMx Timer instance
4641 * @retval None
4642 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4643 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4644 {
4645 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4646 }
4647
4648 /**
4649 * @brief Disable break interrupt (BIE).
4650 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4651 * @param TIMx Timer instance
4652 * @retval None
4653 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4654 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4655 {
4656 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4657 }
4658
4659 /**
4660 * @brief Indicates whether the break interrupt (BIE) is enabled.
4661 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4662 * @param TIMx Timer instance
4663 * @retval State of bit (1 or 0).
4664 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4665 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4666 {
4667 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4668 }
4669
4670 /**
4671 * @}
4672 */
4673
4674 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4675 * @{
4676 */
4677 /**
4678 * @brief Enable update DMA request (UDE).
4679 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4680 * @param TIMx Timer instance
4681 * @retval None
4682 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4683 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4684 {
4685 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4686 }
4687
4688 /**
4689 * @brief Disable update DMA request (UDE).
4690 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4691 * @param TIMx Timer instance
4692 * @retval None
4693 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4694 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4695 {
4696 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4697 }
4698
4699 /**
4700 * @brief Indicates whether the update DMA request (UDE) is enabled.
4701 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4702 * @param TIMx Timer instance
4703 * @retval State of bit (1 or 0).
4704 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4705 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4706 {
4707 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4708 }
4709
4710 /**
4711 * @brief Enable capture/compare 1 DMA request (CC1DE).
4712 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4713 * @param TIMx Timer instance
4714 * @retval None
4715 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4716 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4717 {
4718 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4719 }
4720
4721 /**
4722 * @brief Disable capture/compare 1 DMA request (CC1DE).
4723 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4724 * @param TIMx Timer instance
4725 * @retval None
4726 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4727 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4728 {
4729 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4730 }
4731
4732 /**
4733 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4734 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4735 * @param TIMx Timer instance
4736 * @retval State of bit (1 or 0).
4737 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4738 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4739 {
4740 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4741 }
4742
4743 /**
4744 * @brief Enable capture/compare 2 DMA request (CC2DE).
4745 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4746 * @param TIMx Timer instance
4747 * @retval None
4748 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4749 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4750 {
4751 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4752 }
4753
4754 /**
4755 * @brief Disable capture/compare 2 DMA request (CC2DE).
4756 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4757 * @param TIMx Timer instance
4758 * @retval None
4759 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4760 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4761 {
4762 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4763 }
4764
4765 /**
4766 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4767 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4768 * @param TIMx Timer instance
4769 * @retval State of bit (1 or 0).
4770 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4771 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4772 {
4773 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4774 }
4775
4776 /**
4777 * @brief Enable capture/compare 3 DMA request (CC3DE).
4778 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4779 * @param TIMx Timer instance
4780 * @retval None
4781 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4782 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4783 {
4784 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4785 }
4786
4787 /**
4788 * @brief Disable capture/compare 3 DMA request (CC3DE).
4789 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4790 * @param TIMx Timer instance
4791 * @retval None
4792 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4793 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4794 {
4795 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4796 }
4797
4798 /**
4799 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4800 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4801 * @param TIMx Timer instance
4802 * @retval State of bit (1 or 0).
4803 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4804 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4805 {
4806 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4807 }
4808
4809 /**
4810 * @brief Enable capture/compare 4 DMA request (CC4DE).
4811 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4812 * @param TIMx Timer instance
4813 * @retval None
4814 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4815 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4816 {
4817 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4818 }
4819
4820 /**
4821 * @brief Disable capture/compare 4 DMA request (CC4DE).
4822 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4823 * @param TIMx Timer instance
4824 * @retval None
4825 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4826 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4827 {
4828 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4829 }
4830
4831 /**
4832 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4833 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4834 * @param TIMx Timer instance
4835 * @retval State of bit (1 or 0).
4836 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4837 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4838 {
4839 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4840 }
4841
4842 /**
4843 * @brief Enable commutation DMA request (COMDE).
4844 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4845 * @param TIMx Timer instance
4846 * @retval None
4847 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4848 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4849 {
4850 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4851 }
4852
4853 /**
4854 * @brief Disable commutation DMA request (COMDE).
4855 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4859 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4860 {
4861 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4862 }
4863
4864 /**
4865 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4866 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4867 * @param TIMx Timer instance
4868 * @retval State of bit (1 or 0).
4869 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4870 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4871 {
4872 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4873 }
4874
4875 /**
4876 * @brief Enable trigger interrupt (TDE).
4877 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4881 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4882 {
4883 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4884 }
4885
4886 /**
4887 * @brief Disable trigger interrupt (TDE).
4888 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4889 * @param TIMx Timer instance
4890 * @retval None
4891 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4892 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4893 {
4894 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4895 }
4896
4897 /**
4898 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4899 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4900 * @param TIMx Timer instance
4901 * @retval State of bit (1 or 0).
4902 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4903 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4904 {
4905 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4906 }
4907
4908 /**
4909 * @}
4910 */
4911
4912 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4913 * @{
4914 */
4915 /**
4916 * @brief Generate an update event.
4917 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4918 * @param TIMx Timer instance
4919 * @retval None
4920 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4921 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4922 {
4923 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4924 }
4925
4926 /**
4927 * @brief Generate Capture/Compare 1 event.
4928 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4929 * @param TIMx Timer instance
4930 * @retval None
4931 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4932 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4933 {
4934 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4935 }
4936
4937 /**
4938 * @brief Generate Capture/Compare 2 event.
4939 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4940 * @param TIMx Timer instance
4941 * @retval None
4942 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4943 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4944 {
4945 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4946 }
4947
4948 /**
4949 * @brief Generate Capture/Compare 3 event.
4950 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4951 * @param TIMx Timer instance
4952 * @retval None
4953 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4954 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4955 {
4956 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4957 }
4958
4959 /**
4960 * @brief Generate Capture/Compare 4 event.
4961 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4962 * @param TIMx Timer instance
4963 * @retval None
4964 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4965 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4966 {
4967 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4968 }
4969
4970 /**
4971 * @brief Generate commutation event.
4972 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4973 * @param TIMx Timer instance
4974 * @retval None
4975 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4976 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4977 {
4978 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4979 }
4980
4981 /**
4982 * @brief Generate trigger event.
4983 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4984 * @param TIMx Timer instance
4985 * @retval None
4986 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4987 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4988 {
4989 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4990 }
4991
4992 /**
4993 * @brief Generate break event.
4994 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4995 * @param TIMx Timer instance
4996 * @retval None
4997 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4998 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4999 {
5000 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5001 }
5002
5003 #if defined(TIM_EGR_B2G)
5004 /**
5005 * @brief Generate break 2 event.
5006 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5007 * @param TIMx Timer instance
5008 * @retval None
5009 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5010 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5011 {
5012 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5013 }
5014
5015 #endif /* TIM_EGR_B2G */
5016 /**
5017 * @}
5018 */
5019
5020 #if defined(USE_FULL_LL_DRIVER)
5021 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5022 * @{
5023 */
5024
5025 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5026 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5027 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5028 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5029 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5030 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5031 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5032 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5033 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5034 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5035 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5036 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5037 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5038 /**
5039 * @}
5040 */
5041 #endif /* USE_FULL_LL_DRIVER */
5042
5043 /**
5044 * @}
5045 */
5046
5047 /**
5048 * @}
5049 */
5050
5051 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
5052
5053 /**
5054 * @}
5055 */
5056
5057 #ifdef __cplusplus
5058 }
5059 #endif
5060
5061 #endif /* __STM32F3xx_LL_TIM_H */
5062
