1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2016 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32F3xx_LL_SYSTEM_H
35 #define __STM32F3xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32f3xx.h"
43
44 /** @addtogroup STM32F3xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
63 #define SYSCFG_OFFSET_CFGR1 0x00000000U
64 #define SYSCFG_OFFSET_CFGR3 0x00000050U
65
66 /* Mask used for TIM breaks functions */
67 #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
68 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
69 #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
70 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
71 #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
72 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
73 #else
74 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
75 #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82
83 /* Exported types ------------------------------------------------------------*/
84 /* Exported constants --------------------------------------------------------*/
85 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
86 * @{
87 */
88
89 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
90 * @{
91 */
92 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
93 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
94 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
95 #if defined(FMC_BANK1)
96 #define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
97 #endif /* FMC_BANK1 */
98 /**
99 * @}
100 */
101
102 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
103 /** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
104 * @{
105 */
106 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
107 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
108 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
109 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
110 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
111 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
112 /**
113 * @}
114 */
115 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
116
117 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
118 /** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
119 * @{
120 */
121 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
122 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
123 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
124 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
125 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
126 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
127 /**
128 * @}
129 */
130
131 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
132
133 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
134 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
135 * @{
136 */
137 #if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
138 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
139 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
140 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
141 #if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
142 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
143 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
144 #define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
145 #define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
146 #endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
147 /**
148 * @}
149 */
150
151 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
152
153 /** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
154 * @{
155 */
156 #define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
157 #define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
158 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
159 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
160 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
161 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
162 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
163 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
164 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
165 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
166 #if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
167 #define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
168 #define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
169 #endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
170 /**
171 * @}
172 */
173
174 /** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
175 * @{
176 */
177 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
178 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
179 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
180 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
181 #define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
182 #define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
183 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
184 #define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
185 #define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
186 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
187 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
188 #define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
189 #define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
190 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
191 /**
192 * @}
193 */
194
195 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
196 /** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
197 * @{
198 */
199 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
200 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
201 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
202 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
203 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
204 #define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
205 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
206 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
207 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
208 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
209 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
210 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
211 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
212 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
213 /**
214 * @}
215 */
216
217 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
218
219 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
220 /** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
221 * @{
222 */
223 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
224 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
225 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
226 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
227 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
228 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
229 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
230 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
231 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
232 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
233 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
234 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
235 #define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
236 #define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
237 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
238 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
239 #define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
240 #define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
241 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
242 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
243 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
244 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
245 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
246 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
247 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
248 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
249 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
250 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
251 /**
252 * @}
253 */
254
255 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
256
257 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
258 /** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
259 * @{
260 */
261 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
262 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
263 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
264 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
265 #if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
266 #define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
267 #define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
268 #endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
269 #if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
270 #define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
271 #define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
272 #endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
273 /**
274 * @}
275 */
276
277 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
278
279 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
280 * @{
281 */
282 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
283 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
284 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
285 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
286 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
287 #if defined(SYSCFG_CFGR1_I2C2_FMP)
288 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
289 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
290 #if defined(SYSCFG_CFGR1_I2C3_FMP)
291 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
292 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
293 /**
294 * @}
295 */
296
297 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
298 * @{
299 */
300 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
301 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
302 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
303 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
304 #if defined(GPIOE)
305 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
306 #endif /* GPIOE */
307 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
308 #if defined(GPIOG)
309 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
310 #endif /* GPIOG */
311 #if defined(GPIOH)
312 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
313 #endif /* GPIOH */
314 /**
315 * @}
316 */
317
318 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
319 * @{
320 */
321 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
322 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
323 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
324 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
325 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
326 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
327 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
328 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
329 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
330 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
331 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
332 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
333 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
334 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
335 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
336 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
337 /**
338 * @}
339 */
340
341 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
342 * @{
343 */
344 #if defined(SYSCFG_CFGR2_PVD_LOCK)
345 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
346 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
347 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
348 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
349 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
350 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
351 /**
352 * @}
353 */
354
355 #if defined(SYSCFG_RCR_PAGE0)
356 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
357 * @{
358 */
359 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
360 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
361 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
362 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
363 #if defined(SYSCFG_RCR_PAGE4)
364 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
365 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
366 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
367 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
368 #endif
369 #if defined(SYSCFG_RCR_PAGE8)
370 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
371 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
372 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
373 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
374 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
375 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
376 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
377 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
378 #endif
379 /**
380 * @}
381 */
382
383 #endif /* SYSCFG_RCR_PAGE0 */
384
385 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
386 * @{
387 */
388 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
389 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
390 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
391 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
392 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
393 /**
394 * @}
395 */
396
397 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
398 * @{
399 */
400 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
401 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
402 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
403 #endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
404 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
405 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
406 #endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
407 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
408 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
409 #endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
410 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
411 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
412 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
413 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
414 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
415 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
416 #endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
417 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
418 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
419 #endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
420 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
421 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
422 #endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
423 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
424 #define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
425 #endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
426 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
427 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
428 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
429 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
430 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
431 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
432 #endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
433 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
434 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
435 #endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
436 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
437 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
438 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
439 /**
440 * @}
441 */
442
443 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
444 * @{
445 */
446 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
447 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
448 #endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
449 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
450 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
451 #endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
452 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
453 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
454 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
455 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
456 #define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
457 #endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
458 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
459 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
460 #endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
461 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
462 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
463 #endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
464 /**
465 * @}
466 */
467
468 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
469 * @{
470 */
471 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
472 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
473 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
474 /**
475 * @}
476 */
477
478 /**
479 * @}
480 */
481
482 /* Exported macro ------------------------------------------------------------*/
483
484 /* Exported functions --------------------------------------------------------*/
485 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
486 * @{
487 */
488
489 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
490 * @{
491 */
492
493 /**
494 * @brief Set memory mapping at address 0x00000000
495 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
496 * @param Memory This parameter can be one of the following values:
497 * @arg @ref LL_SYSCFG_REMAP_FLASH
498 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
499 * @arg @ref LL_SYSCFG_REMAP_SRAM
500 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
501 *
502 * (*) value not defined in all devices.
503 * @retval None
504 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)505 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
506 {
507 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
508 }
509
510 /**
511 * @brief Get memory mapping at address 0x00000000
512 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
513 * @retval Returned value can be one of the following values:
514 * @arg @ref LL_SYSCFG_REMAP_FLASH
515 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
516 * @arg @ref LL_SYSCFG_REMAP_SRAM
517 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
518 *
519 * (*) value not defined in all devices.
520 */
LL_SYSCFG_GetRemapMemory(void)521 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
522 {
523 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
524 }
525
526 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
527 /**
528 * @brief Set DMA request remapping bits for SPI
529 * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
530 * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
531 * @param Remap This parameter can be one of the following values:
532 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
533 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
534 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
535 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
536 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
537 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
538 * @retval None
539 */
LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)540 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
541 {
542 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
543 }
544 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
545
546 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
547 /**
548 * @brief Set DMA request remapping bits for I2C
549 * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
550 * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
551 * @param Remap This parameter can be one of the following values:
552 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
553 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
554 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
555 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
556 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
557 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
558 * @retval None
559 */
LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)560 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
561 {
562 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
563 }
564 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
565
566 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
567 /**
568 * @brief Set DMA request remapping bits for ADC
569 * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
570 * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
571 * @param Remap This parameter can be one of the following values:
572 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
573 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
574 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
575 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
576 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
577 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
578 *
579 * (*) value not defined in all devices.
580 * @retval None
581 */
LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)582 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
583 {
584 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
585 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
586 }
587 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
588
589 /**
590 * @brief Set DMA request remapping bits for DAC
591 * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
592 * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
593 * @param Remap This parameter can be one of the following values:
594 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
595 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
596 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
597 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
598 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
599 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
600 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
601 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
602 *
603 * (*) value not defined in all devices.
604 * @retval None
605 */
LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)606 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
607 {
608 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
609 }
610
611 /**
612 * @brief Set DMA request remapping bits for TIM
613 * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
614 * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
615 * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
616 * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
617 * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
618 * @param Remap This parameter can be a combination of the following values:
619 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
620 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
621 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
622 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
623 * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
624 *
625 * (*) value not defined in all devices.
626 * @retval None
627 */
LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)628 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
629 {
630 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
631 }
632
633 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
634 /**
635 * @brief Set Timer input remap
636 * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
637 * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
638 * @param Remap This parameter can be one of the following values:
639 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
640 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
641 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
642 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
643 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
644 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
645 *
646 * (*) value not defined in all devices.
647 * @retval None
648 */
LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)649 __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
650 {
651 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
652 }
653 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
654
655 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
656 /**
657 * @brief Set ADC Trigger remap
658 * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
659 * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
660 * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
661 * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
662 * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
663 * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
664 * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
665 * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
666 * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
667 * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
668 * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
669 * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
670 * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
671 * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
672 * @param Remap This parameter can be one of the following values:
673 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
674 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
675 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
676 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
677 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
678 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
679 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
680 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
681 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
682 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
683 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
684 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
685 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
686 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
687 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
688 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
689 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
690 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
691 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
692 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
693 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
694 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
695 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
696 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
697 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
698 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
699 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
700 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
701 * @retval None
702 */
LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)703 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
704 {
705 MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
706 }
707 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
708
709 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
710 /**
711 * @brief Set DAC Trigger remap
712 * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
713 * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
714 * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
715 * @param Remap This parameter can be one of the following values:
716 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
717 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
718 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
719 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
720 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
721 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
722 * (*) value not defined in all devices.
723 * @retval None
724 */
LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)725 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
726 {
727 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
728 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
729 }
730 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
731
732 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
733 /**
734 * @brief Enable USB interrupt remap
735 * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
736 * respectively
737 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
738 * @retval None
739 */
LL_SYSCFG_EnableRemapIT_USB(void)740 __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
741 {
742 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
743 }
744
745 /**
746 * @brief Disable USB interrupt remap
747 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
748 * @retval None
749 */
LL_SYSCFG_DisableRemapIT_USB(void)750 __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
751 {
752 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
753 }
754 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
755
756 #if defined(SYSCFG_CFGR1_VBAT)
757 /**
758 * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
759 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
760 * @retval None
761 */
LL_SYSCFG_EnableVBATMonitoring(void)762 __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
763 {
764 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
765 }
766
767 /**
768 * @brief Disable VBAT monitoring
769 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
770 * @retval None
771 */
LL_SYSCFG_DisableVBATMonitoring(void)772 __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
773 {
774 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
775 }
776 #endif /* SYSCFG_CFGR1_VBAT */
777
778 /**
779 * @brief Enable the I2C fast mode plus driving capability.
780 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
781 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
782 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
783 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
784 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
785 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
786 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
787 * @param ConfigFastModePlus This parameter can be a combination of the following values:
788 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
789 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
790 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
791 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
792 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
793 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
794 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
795 *
796 * (*) value not defined in all devices.
797 * @retval None
798 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)799 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
800 {
801 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
802 }
803
804 /**
805 * @brief Disable the I2C fast mode plus driving capability.
806 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
807 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
808 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
809 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
810 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
811 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
812 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
813 * @param ConfigFastModePlus This parameter can be a combination of the following values:
814 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
815 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
816 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
817 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
818 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
819 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
820 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
821 *
822 * (*) value not defined in all devices.
823 * @retval None
824 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)825 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
826 {
827 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
828 }
829
830 /**
831 * @brief Enable Floating Point Unit Invalid operation Interrupt
832 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
833 * @retval None
834 */
LL_SYSCFG_EnableIT_FPU_IOC(void)835 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
836 {
837 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
838 }
839
840 /**
841 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
842 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
843 * @retval None
844 */
LL_SYSCFG_EnableIT_FPU_DZC(void)845 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
846 {
847 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
848 }
849
850 /**
851 * @brief Enable Floating Point Unit Underflow Interrupt
852 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
853 * @retval None
854 */
LL_SYSCFG_EnableIT_FPU_UFC(void)855 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
856 {
857 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
858 }
859
860 /**
861 * @brief Enable Floating Point Unit Overflow Interrupt
862 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
863 * @retval None
864 */
LL_SYSCFG_EnableIT_FPU_OFC(void)865 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
866 {
867 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
868 }
869
870 /**
871 * @brief Enable Floating Point Unit Input denormal Interrupt
872 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
873 * @retval None
874 */
LL_SYSCFG_EnableIT_FPU_IDC(void)875 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
876 {
877 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
878 }
879
880 /**
881 * @brief Enable Floating Point Unit Inexact Interrupt
882 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
883 * @retval None
884 */
LL_SYSCFG_EnableIT_FPU_IXC(void)885 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
886 {
887 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
888 }
889
890 /**
891 * @brief Disable Floating Point Unit Invalid operation Interrupt
892 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
893 * @retval None
894 */
LL_SYSCFG_DisableIT_FPU_IOC(void)895 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
896 {
897 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
898 }
899
900 /**
901 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
902 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
903 * @retval None
904 */
LL_SYSCFG_DisableIT_FPU_DZC(void)905 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
906 {
907 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
908 }
909
910 /**
911 * @brief Disable Floating Point Unit Underflow Interrupt
912 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
913 * @retval None
914 */
LL_SYSCFG_DisableIT_FPU_UFC(void)915 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
916 {
917 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
918 }
919
920 /**
921 * @brief Disable Floating Point Unit Overflow Interrupt
922 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
923 * @retval None
924 */
LL_SYSCFG_DisableIT_FPU_OFC(void)925 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
926 {
927 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
928 }
929
930 /**
931 * @brief Disable Floating Point Unit Input denormal Interrupt
932 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
933 * @retval None
934 */
LL_SYSCFG_DisableIT_FPU_IDC(void)935 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
936 {
937 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
938 }
939
940 /**
941 * @brief Disable Floating Point Unit Inexact Interrupt
942 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
943 * @retval None
944 */
LL_SYSCFG_DisableIT_FPU_IXC(void)945 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
946 {
947 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
948 }
949
950 /**
951 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
952 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
953 * @retval State of bit (1 or 0).
954 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)955 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
956 {
957 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
958 }
959
960 /**
961 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
962 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
963 * @retval State of bit (1 or 0).
964 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)965 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
966 {
967 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
968 }
969
970 /**
971 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
972 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
973 * @retval State of bit (1 or 0).
974 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)975 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
976 {
977 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
978 }
979
980 /**
981 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
982 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
983 * @retval State of bit (1 or 0).
984 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)985 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
986 {
987 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
988 }
989
990 /**
991 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
992 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
993 * @retval State of bit (1 or 0).
994 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)995 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
996 {
997 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
998 }
999
1000 /**
1001 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
1002 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
1003 * @retval State of bit (1 or 0).
1004 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)1005 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
1006 {
1007 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
1008 }
1009
1010 /**
1011 * @brief Configure source input for the EXTI external interrupt.
1012 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
1013 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
1014 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
1015 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
1016 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
1017 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
1018 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
1019 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
1020 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
1021 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
1022 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
1023 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
1024 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
1025 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
1026 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
1027 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
1028 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
1029 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
1030 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
1031 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
1032 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
1033 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
1034 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
1035 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
1036 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
1037 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
1038 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
1039 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
1040 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
1041 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
1042 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
1043 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
1044 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
1045 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
1046 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
1047 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
1048 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
1049 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
1050 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
1051 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
1052 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
1053 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
1054 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
1055 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
1056 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
1057 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
1058 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
1059 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
1060 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
1061 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
1062 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
1063 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
1064 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
1065 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
1066 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
1067 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
1068 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
1069 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
1070 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
1071 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
1072 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
1073 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
1074 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
1075 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
1076 * @param Port This parameter can be one of the following values:
1077 * @arg @ref LL_SYSCFG_EXTI_PORTA
1078 * @arg @ref LL_SYSCFG_EXTI_PORTB
1079 * @arg @ref LL_SYSCFG_EXTI_PORTC
1080 * @arg @ref LL_SYSCFG_EXTI_PORTD
1081 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1082 * @arg @ref LL_SYSCFG_EXTI_PORTF
1083 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1084 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1085 *
1086 * (*) value not defined in all devices.
1087 * @param Line This parameter can be one of the following values:
1088 * @arg @ref LL_SYSCFG_EXTI_LINE0
1089 * @arg @ref LL_SYSCFG_EXTI_LINE1
1090 * @arg @ref LL_SYSCFG_EXTI_LINE2
1091 * @arg @ref LL_SYSCFG_EXTI_LINE3
1092 * @arg @ref LL_SYSCFG_EXTI_LINE4
1093 * @arg @ref LL_SYSCFG_EXTI_LINE5
1094 * @arg @ref LL_SYSCFG_EXTI_LINE6
1095 * @arg @ref LL_SYSCFG_EXTI_LINE7
1096 * @arg @ref LL_SYSCFG_EXTI_LINE8
1097 * @arg @ref LL_SYSCFG_EXTI_LINE9
1098 * @arg @ref LL_SYSCFG_EXTI_LINE10
1099 * @arg @ref LL_SYSCFG_EXTI_LINE11
1100 * @arg @ref LL_SYSCFG_EXTI_LINE12
1101 * @arg @ref LL_SYSCFG_EXTI_LINE13
1102 * @arg @ref LL_SYSCFG_EXTI_LINE14
1103 * @arg @ref LL_SYSCFG_EXTI_LINE15
1104 * @retval None
1105 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)1106 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
1107 {
1108 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
1109 }
1110
1111 /**
1112 * @brief Get the configured defined for specific EXTI Line
1113 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
1114 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
1115 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
1116 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
1117 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
1118 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
1119 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
1120 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
1121 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
1122 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
1123 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
1124 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
1125 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
1126 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
1127 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
1128 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
1129 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
1130 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
1131 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
1132 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
1133 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
1134 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
1135 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
1136 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
1137 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
1138 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
1139 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
1140 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
1141 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
1142 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
1143 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
1144 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
1145 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
1146 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
1147 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
1148 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
1149 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
1150 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
1151 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
1152 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
1153 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
1154 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
1155 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
1156 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
1157 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
1158 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
1159 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
1160 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
1161 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
1162 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
1163 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
1164 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
1165 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
1166 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
1167 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
1168 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
1169 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
1170 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
1171 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
1172 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
1173 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
1174 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
1175 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
1176 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
1177 * @param Line This parameter can be one of the following values:
1178 * @arg @ref LL_SYSCFG_EXTI_LINE0
1179 * @arg @ref LL_SYSCFG_EXTI_LINE1
1180 * @arg @ref LL_SYSCFG_EXTI_LINE2
1181 * @arg @ref LL_SYSCFG_EXTI_LINE3
1182 * @arg @ref LL_SYSCFG_EXTI_LINE4
1183 * @arg @ref LL_SYSCFG_EXTI_LINE5
1184 * @arg @ref LL_SYSCFG_EXTI_LINE6
1185 * @arg @ref LL_SYSCFG_EXTI_LINE7
1186 * @arg @ref LL_SYSCFG_EXTI_LINE8
1187 * @arg @ref LL_SYSCFG_EXTI_LINE9
1188 * @arg @ref LL_SYSCFG_EXTI_LINE10
1189 * @arg @ref LL_SYSCFG_EXTI_LINE11
1190 * @arg @ref LL_SYSCFG_EXTI_LINE12
1191 * @arg @ref LL_SYSCFG_EXTI_LINE13
1192 * @arg @ref LL_SYSCFG_EXTI_LINE14
1193 * @arg @ref LL_SYSCFG_EXTI_LINE15
1194 * @retval Returned value can be one of the following values:
1195 * @arg @ref LL_SYSCFG_EXTI_PORTA
1196 * @arg @ref LL_SYSCFG_EXTI_PORTB
1197 * @arg @ref LL_SYSCFG_EXTI_PORTC
1198 * @arg @ref LL_SYSCFG_EXTI_PORTD
1199 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1200 * @arg @ref LL_SYSCFG_EXTI_PORTF
1201 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1202 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1203 *
1204 * (*) value not defined in all devices.
1205 */
LL_SYSCFG_GetEXTISource(uint32_t Line)1206 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
1207 {
1208 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
1209 }
1210
1211 /**
1212 * @brief Set connections to TIMx Break inputs
1213 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1214 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1215 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
1216 * @param Break This parameter can be a combination of the following values:
1217 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1218 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1219 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1220 *
1221 * (*) value not defined in all devices.
1222 * @retval None
1223 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)1224 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1225 {
1226 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
1227 }
1228
1229 /**
1230 * @brief Get connections to TIMx Break inputs
1231 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1232 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1233 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
1234 * @retval Returned value can be can be a combination of the following values:
1235 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1236 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1237 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1238 *
1239 * (*) value not defined in all devices.
1240 */
LL_SYSCFG_GetTIMBreakInputs(void)1241 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1242 {
1243 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
1244 }
1245
1246 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
1247 /**
1248 * @brief Disable RAM Parity Check Disable
1249 * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
1250 * @retval None
1251 */
LL_SYSCFG_DisableSRAMParityCheck(void)1252 __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
1253 {
1254 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
1255 }
1256 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
1257
1258 #if defined(SYSCFG_CFGR2_SRAM_PE)
1259 /**
1260 * @brief Check if SRAM parity error detected
1261 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
1262 * @retval State of bit (1 or 0).
1263 */
LL_SYSCFG_IsActiveFlag_SP(void)1264 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1265 {
1266 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
1267 }
1268
1269 /**
1270 * @brief Clear SRAM parity error flag
1271 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
1272 * @retval None
1273 */
LL_SYSCFG_ClearFlag_SP(void)1274 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1275 {
1276 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
1277 }
1278 #endif /* SYSCFG_CFGR2_SRAM_PE */
1279
1280 #if defined(SYSCFG_RCR_PAGE0)
1281 /**
1282 * @brief Enable CCM SRAM page write protection
1283 * @note Write protection is cleared only by a system reset
1284 * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1285 * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1286 * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1287 * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1288 * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1289 * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1290 * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1291 * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1292 * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1293 * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1294 * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1295 * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1296 * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1297 * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1298 * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1299 * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
1300 * @param PageWRP This parameter can be a combination of the following values:
1301 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
1302 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
1303 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
1304 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
1305 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
1306 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
1307 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
1308 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
1309 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
1310 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
1311 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
1312 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
1313 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
1314 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
1315 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
1316 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
1317 *
1318 * (*) value not defined in all devices.
1319 * @retval None
1320 */
LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)1321 __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
1322 {
1323 SET_BIT(SYSCFG->RCR, PageWRP);
1324 }
1325 #endif /* SYSCFG_RCR_PAGE0 */
1326
1327 /**
1328 * @}
1329 */
1330
1331 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1332 * @{
1333 */
1334
1335 /**
1336 * @brief Return the device identifier
1337 * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
1338 * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
1339 * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
1340 * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
1341 * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
1342 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1343 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1344 */
LL_DBGMCU_GetDeviceID(void)1345 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1346 {
1347 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1348 }
1349
1350 /**
1351 * @brief Return the device revision identifier
1352 * @note This field indicates the revision of the device.
1353 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1354 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1355 */
LL_DBGMCU_GetRevisionID(void)1356 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1357 {
1358 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1359 }
1360
1361 /**
1362 * @brief Enable the Debug Module during SLEEP mode
1363 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1364 * @retval None
1365 */
LL_DBGMCU_EnableDBGSleepMode(void)1366 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1367 {
1368 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1369 }
1370
1371 /**
1372 * @brief Disable the Debug Module during SLEEP mode
1373 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1374 * @retval None
1375 */
LL_DBGMCU_DisableDBGSleepMode(void)1376 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1377 {
1378 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1379 }
1380
1381 /**
1382 * @brief Enable the Debug Module during STOP mode
1383 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1384 * @retval None
1385 */
LL_DBGMCU_EnableDBGStopMode(void)1386 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1387 {
1388 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1389 }
1390
1391 /**
1392 * @brief Disable the Debug Module during STOP mode
1393 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1394 * @retval None
1395 */
LL_DBGMCU_DisableDBGStopMode(void)1396 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1397 {
1398 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1399 }
1400
1401 /**
1402 * @brief Enable the Debug Module during STANDBY mode
1403 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1404 * @retval None
1405 */
LL_DBGMCU_EnableDBGStandbyMode(void)1406 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1407 {
1408 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1409 }
1410
1411 /**
1412 * @brief Disable the Debug Module during STANDBY mode
1413 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1414 * @retval None
1415 */
LL_DBGMCU_DisableDBGStandbyMode(void)1416 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1417 {
1418 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1419 }
1420
1421 /**
1422 * @brief Set Trace pin assignment control
1423 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1424 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1425 * @param PinAssignment This parameter can be one of the following values:
1426 * @arg @ref LL_DBGMCU_TRACE_NONE
1427 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1428 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1429 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1430 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1431 * @retval None
1432 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1433 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1434 {
1435 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1436 }
1437
1438 /**
1439 * @brief Get Trace pin assignment control
1440 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1441 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1442 * @retval Returned value can be one of the following values:
1443 * @arg @ref LL_DBGMCU_TRACE_NONE
1444 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1445 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1446 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1447 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1448 */
LL_DBGMCU_GetTracePinAssignment(void)1449 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1450 {
1451 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1452 }
1453
1454 /**
1455 * @brief Freeze APB1 peripherals (group1 peripherals)
1456 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1457 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1458 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1459 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1460 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1461 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1462 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1463 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1464 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1465 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1466 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1467 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1468 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1469 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1470 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1471 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1472 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1473 * @param Periphs This parameter can be a combination of the following values:
1474 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1475 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1476 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1477 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1478 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1479 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1480 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1481 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1482 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1483 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1484 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1485 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1486 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1487 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1488 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1489 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1490 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1491 *
1492 * (*) value not defined in all devices.
1493 * @retval None
1494 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1495 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1496 {
1497 SET_BIT(DBGMCU->APB1FZ, Periphs);
1498 }
1499
1500 /**
1501 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1502 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1503 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1504 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1505 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1506 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1507 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1508 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1509 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1510 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1511 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1512 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1513 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1514 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1515 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1516 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1517 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1518 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1519 * @param Periphs This parameter can be a combination of the following values:
1520 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1521 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1522 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1523 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1524 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1525 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1526 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1527 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1528 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1529 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1530 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1531 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1532 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1533 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1534 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1535 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1536 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1537 *
1538 * (*) value not defined in all devices.
1539 * @retval None
1540 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1541 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1542 {
1543 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1544 }
1545
1546 /**
1547 * @brief Freeze APB2 peripherals
1548 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1549 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1550 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1551 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1552 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1553 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1554 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1555 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1556 * @param Periphs This parameter can be a combination of the following values:
1557 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1558 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1559 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1560 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1561 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1562 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1563 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1564 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1565 *
1566 * (*) value not defined in all devices.
1567 * @retval None
1568 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1569 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1570 {
1571 SET_BIT(DBGMCU->APB2FZ, Periphs);
1572 }
1573
1574 /**
1575 * @brief Unfreeze APB2 peripherals
1576 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1577 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1578 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1579 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1580 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1581 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1582 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1583 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1584 * @param Periphs This parameter can be a combination of the following values:
1585 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1586 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1587 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1588 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1589 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1590 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1591 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1592 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1593 *
1594 * (*) value not defined in all devices.
1595 * @retval None
1596 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1597 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1598 {
1599 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1600 }
1601
1602 /**
1603 * @}
1604 */
1605
1606 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1607 * @{
1608 */
1609
1610 /**
1611 * @brief Set FLASH Latency
1612 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1613 * @param Latency This parameter can be one of the following values:
1614 * @arg @ref LL_FLASH_LATENCY_0
1615 * @arg @ref LL_FLASH_LATENCY_1
1616 * @arg @ref LL_FLASH_LATENCY_2
1617 * @retval None
1618 */
LL_FLASH_SetLatency(uint32_t Latency)1619 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1620 {
1621 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1622 }
1623
1624 /**
1625 * @brief Get FLASH Latency
1626 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1627 * @retval Returned value can be one of the following values:
1628 * @arg @ref LL_FLASH_LATENCY_0
1629 * @arg @ref LL_FLASH_LATENCY_1
1630 * @arg @ref LL_FLASH_LATENCY_2
1631 */
LL_FLASH_GetLatency(void)1632 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1633 {
1634 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1635 }
1636
1637 /**
1638 * @brief Enable Prefetch
1639 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
1640 * @retval None
1641 */
LL_FLASH_EnablePrefetch(void)1642 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1643 {
1644 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1645 }
1646
1647 /**
1648 * @brief Disable Prefetch
1649 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
1650 * @retval None
1651 */
LL_FLASH_DisablePrefetch(void)1652 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1653 {
1654 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1655 }
1656
1657 /**
1658 * @brief Check if Prefetch buffer is enabled
1659 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
1660 * @retval State of bit (1 or 0).
1661 */
LL_FLASH_IsPrefetchEnabled(void)1662 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1663 {
1664 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
1665 }
1666
1667 #if defined(FLASH_ACR_HLFCYA)
1668 /**
1669 * @brief Enable Flash Half Cycle Access
1670 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
1671 * @retval None
1672 */
LL_FLASH_EnableHalfCycleAccess(void)1673 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
1674 {
1675 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1676 }
1677
1678 /**
1679 * @brief Disable Flash Half Cycle Access
1680 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
1681 * @retval None
1682 */
LL_FLASH_DisableHalfCycleAccess(void)1683 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
1684 {
1685 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1686 }
1687
1688 /**
1689 * @brief Check if Flash Half Cycle Access is enabled or not
1690 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
1691 * @retval State of bit (1 or 0).
1692 */
LL_FLASH_IsHalfCycleAccessEnabled(void)1693 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
1694 {
1695 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
1696 }
1697 #endif /* FLASH_ACR_HLFCYA */
1698
1699
1700
1701 /**
1702 * @}
1703 */
1704
1705 /**
1706 * @}
1707 */
1708
1709 /**
1710 * @}
1711 */
1712
1713 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1714
1715 /**
1716 * @}
1717 */
1718
1719 #ifdef __cplusplus
1720 }
1721 #endif
1722
1723 #endif /* __STM32F3xx_LL_SYSTEM_H */
1724
1725
