1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F3xx_LL_RCC_H
20 #define __STM32F3xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f3xx.h"
28
29 /** @addtogroup STM32F3xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
43 * @{
44 */
45 /* Defines used for the bit position in the register and perform offsets*/
46 #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
47 #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
48 #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
49 #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
50 #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
51 #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
52 #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
53 #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
54 #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
55 #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
56 #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
57 #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
58 #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
59 #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
60 #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
61 #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
62 #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
63
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69 #if defined(USE_FULL_LL_DRIVER)
70 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
71 * @{
72 */
73 /**
74 * @}
75 */
76 #endif /*USE_FULL_LL_DRIVER*/
77 /* Exported types ------------------------------------------------------------*/
78 #if defined(USE_FULL_LL_DRIVER)
79 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
80 * @{
81 */
82
83 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
84 * @{
85 */
86
87 /**
88 * @brief RCC Clocks Frequency Structure
89 */
90 typedef struct
91 {
92 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
93 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
94 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
95 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
96 } LL_RCC_ClocksTypeDef;
97
98 /**
99 * @}
100 */
101
102 /**
103 * @}
104 */
105 #endif /* USE_FULL_LL_DRIVER */
106
107 /* Exported constants --------------------------------------------------------*/
108 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
109 * @{
110 */
111
112 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
113 * @brief Defines used to adapt values of different oscillators
114 * @note These values could be modified in the user environment according to
115 * HW set-up.
116 * @{
117 */
118 #if !defined (HSE_VALUE)
119 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
120 #endif /* HSE_VALUE */
121
122 #if !defined (HSI_VALUE)
123 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
124 #endif /* HSI_VALUE */
125
126 #if !defined (LSE_VALUE)
127 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
128 #endif /* LSE_VALUE */
129
130 #if !defined (LSI_VALUE)
131 #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
132 #endif /* LSI_VALUE */
133
134 #if !defined (EXTERNAL_CLOCK_VALUE)
135 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
136 #endif /* EXTERNAL_CLOCK_VALUE */
137 /**
138 * @}
139 */
140
141 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
142 * @brief Flags defines which can be used with LL_RCC_WriteReg function
143 * @{
144 */
145 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
146 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
147 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
148 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
149 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
150 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
151 /**
152 * @}
153 */
154
155 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_RCC_ReadReg function
157 * @{
158 */
159 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
160 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
161 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
162 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
163 #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
164 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
165 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
166 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
167 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
168 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
169 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
170 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
171 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
172 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
173 #if defined(RCC_CSR_V18PWRRSTF)
174 #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
175 #endif /* RCC_CSR_V18PWRRSTF */
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_LL_EC_IT IT Defines
181 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
182 * @{
183 */
184 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
185 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
186 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
187 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
188 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
189 /**
190 * @}
191 */
192
193 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
194 * @{
195 */
196 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
197 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
198 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
199 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
200 /**
201 * @}
202 */
203
204 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
205 * @{
206 */
207 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
208 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
209 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
210 /**
211 * @}
212 */
213
214 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
215 * @{
216 */
217 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
218 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
219 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
220 /**
221 * @}
222 */
223
224 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
225 * @{
226 */
227 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
228 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
229 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
230 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
231 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
232 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
233 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
234 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
235 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
236 /**
237 * @}
238 */
239
240 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
241 * @{
242 */
243 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
244 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
245 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
246 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
247 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
248 /**
249 * @}
250 */
251
252 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
253 * @{
254 */
255 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
256 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
257 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
258 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
259 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
260 /**
261 * @}
262 */
263
264 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
265 * @{
266 */
267 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
268 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
269 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
270 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
271 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
272 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
273 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
274 #if defined(RCC_CFGR_PLLNODIV)
275 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
276 #endif /* RCC_CFGR_PLLNODIV */
277 /**
278 * @}
279 */
280
281 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
282 * @{
283 */
284 #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
285 #if defined(RCC_CFGR_MCOPRE)
286 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
287 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
288 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
289 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
290 #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
291 #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
292 #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
293 #endif /* RCC_CFGR_MCOPRE */
294 /**
295 * @}
296 */
297
298 #if defined(USE_FULL_LL_DRIVER)
299 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
300 * @{
301 */
302 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
303 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
304 /**
305 * @}
306 */
307 #endif /* USE_FULL_LL_DRIVER */
308
309 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
310 * @{
311 */
312 #if defined(RCC_CFGR3_USART1SW_PCLK1)
313 #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
314 #else
315 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
316 #endif /*RCC_CFGR3_USART1SW_PCLK1*/
317 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
318 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
319 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
320 #if defined(RCC_CFGR3_USART2SW)
321 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
322 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
323 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
324 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
325 #endif /* RCC_CFGR3_USART2SW */
326 #if defined(RCC_CFGR3_USART3SW)
327 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
328 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
329 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
330 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
331 #endif /* RCC_CFGR3_USART3SW */
332 /**
333 * @}
334 */
335
336 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
337 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
338 * @{
339 */
340 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
341 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
342 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
343 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
344 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
345 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
346 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
347 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
348 /**
349 * @}
350 */
351
352 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
353
354 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
355 * @{
356 */
357 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
358 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
359 #if defined(RCC_CFGR3_I2C2SW)
360 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
361 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
362 #endif /*RCC_CFGR3_I2C2SW*/
363 #if defined(RCC_CFGR3_I2C3SW)
364 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
365 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
366 #endif /*RCC_CFGR3_I2C3SW*/
367 /**
368 * @}
369 */
370
371 #if defined(RCC_CFGR_I2SSRC)
372 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
373 * @{
374 */
375 #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
376 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
377 /**
378 * @}
379 */
380
381 #endif /* RCC_CFGR_I2SSRC */
382
383 #if defined(RCC_CFGR3_TIMSW)
384 /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
385 * @{
386 */
387 #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
388 #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
389 #if defined(RCC_CFGR3_TIM8SW)
390 #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
391 #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
392 #endif /*RCC_CFGR3_TIM8SW*/
393 #if defined(RCC_CFGR3_TIM15SW)
394 #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
395 #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
396 #endif /*RCC_CFGR3_TIM15SW*/
397 #if defined(RCC_CFGR3_TIM16SW)
398 #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
399 #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
400 #endif /*RCC_CFGR3_TIM16SW*/
401 #if defined(RCC_CFGR3_TIM17SW)
402 #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
403 #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
404 #endif /*RCC_CFGR3_TIM17SW*/
405 #if defined(RCC_CFGR3_TIM20SW)
406 #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
407 #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
408 #endif /*RCC_CFGR3_TIM20SW*/
409 #if defined(RCC_CFGR3_TIM2SW)
410 #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
411 #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
412 #endif /*RCC_CFGR3_TIM2SW*/
413 #if defined(RCC_CFGR3_TIM34SW)
414 #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
415 #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
416 #endif /*RCC_CFGR3_TIM34SW*/
417 /**
418 * @}
419 */
420
421 #endif /* RCC_CFGR3_TIMSW */
422
423 #if defined(HRTIM1)
424 /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
425 * @{
426 */
427 #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
428 #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
429 /**
430 * @}
431 */
432
433 #endif /* HRTIM1 */
434
435 #if defined(CEC)
436 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
437 * @{
438 */
439 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
440 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
441 /**
442 * @}
443 */
444
445 #endif /* CEC */
446
447 #if defined(USB)
448 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
449 * @{
450 */
451 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
452 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
453 /**
454 * @}
455 */
456
457 #endif /* USB */
458
459 #if defined(RCC_CFGR_ADCPRE)
460 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
461 * @{
462 */
463 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
464 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
465 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
466 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
467 /**
468 * @}
469 */
470
471 #elif defined(RCC_CFGR2_ADC1PRES)
472 /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
473 * @{
474 */
475 #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
476 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
477 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
478 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
479 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
480 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
481 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
482 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
483 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
484 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
485 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
486 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
487 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
488 /**
489 * @}
490 */
491
492 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
493 #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
494 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
495 * @{
496 */
497 #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
498 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
499 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
500 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
501 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
502 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
503 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
504 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
505 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
506 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
507 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
508 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
509 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
510 /**
511 * @}
512 */
513
514 /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
515 * @{
516 */
517 #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
518 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
519 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
520 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
521 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
522 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
523 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
524 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
525 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
526 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
527 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
528 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
529 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
530 /**
531 * @}
532 */
533
534 #else
535 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
536 * @{
537 */
538 #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
539 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
540 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
541 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
542 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
543 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
544 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
545 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
546 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
547 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
548 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
549 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
550 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
551 /**
552 * @}
553 */
554
555 #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
556
557 #endif /* RCC_CFGR_ADCPRE */
558
559 #if defined(RCC_CFGR_SDPRE)
560 /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
561 * @{
562 */
563 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
564 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
565 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
566 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
567 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
568 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
569 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
570 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
571 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
572 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
573 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
574 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
575 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
576 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
577 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
578 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
579 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
580 /**
581 * @}
582 */
583
584 #endif /* RCC_CFGR_SDPRE */
585
586 /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
587 * @{
588 */
589 #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
590 #if defined(RCC_CFGR3_USART2SW)
591 #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
592 #endif /* RCC_CFGR3_USART2SW */
593 #if defined(RCC_CFGR3_USART3SW)
594 #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
595 #endif /* RCC_CFGR3_USART3SW */
596 /**
597 * @}
598 */
599
600 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
601 /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
602 * @{
603 */
604 #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
605 #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
606 /**
607 * @}
608 */
609
610 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
611
612 /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
613 * @{
614 */
615 #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
616 #if defined(RCC_CFGR3_I2C2SW)
617 #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
618 #endif /*RCC_CFGR3_I2C2SW*/
619 #if defined(RCC_CFGR3_I2C3SW)
620 #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
621 #endif /*RCC_CFGR3_I2C3SW*/
622 /**
623 * @}
624 */
625
626 #if defined(RCC_CFGR_I2SSRC)
627 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
628 * @{
629 */
630 #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
631 /**
632 * @}
633 */
634
635 #endif /* RCC_CFGR_I2SSRC */
636
637 #if defined(RCC_CFGR3_TIMSW)
638 /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
639 * @{
640 */
641 #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
642 #if defined(RCC_CFGR3_TIM2SW)
643 #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
644 #endif /*RCC_CFGR3_TIM2SW*/
645 #if defined(RCC_CFGR3_TIM8SW)
646 #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
647 #endif /*RCC_CFGR3_TIM8SW*/
648 #if defined(RCC_CFGR3_TIM15SW)
649 #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
650 #endif /*RCC_CFGR3_TIM15SW*/
651 #if defined(RCC_CFGR3_TIM16SW)
652 #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
653 #endif /*RCC_CFGR3_TIM16SW*/
654 #if defined(RCC_CFGR3_TIM17SW)
655 #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
656 #endif /*RCC_CFGR3_TIM17SW*/
657 #if defined(RCC_CFGR3_TIM20SW)
658 #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
659 #endif /*RCC_CFGR3_TIM20SW*/
660 #if defined(RCC_CFGR3_TIM34SW)
661 #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
662 #endif /*RCC_CFGR3_TIM34SW*/
663 /**
664 * @}
665 */
666
667 #endif /* RCC_CFGR3_TIMSW */
668
669 #if defined(HRTIM1)
670 /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
671 * @{
672 */
673 #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
674 /**
675 * @}
676 */
677
678 #endif /* HRTIM1 */
679
680 #if defined(CEC)
681 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
682 * @{
683 */
684 #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
685 /**
686 * @}
687 */
688
689 #endif /* CEC */
690
691 #if defined(USB)
692 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
693 * @{
694 */
695 #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
696 /**
697 * @}
698 */
699
700 #endif /* USB */
701
702 #if defined(RCC_CFGR_ADCPRE)
703 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
704 * @{
705 */
706 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
707 /**
708 * @}
709 */
710
711 #endif /* RCC_CFGR_ADCPRE */
712
713 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
714 /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
715 * @{
716 */
717 #if defined(RCC_CFGR2_ADC1PRES)
718 #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
719 #else
720 #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
721 #if defined(RCC_CFGR2_ADCPRE34)
722 #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
723 #endif /*RCC_CFGR2_ADCPRE34*/
724 #endif /*RCC_CFGR2_ADC1PRES*/
725 /**
726 * @}
727 */
728
729 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
730
731 #if defined(RCC_CFGR_SDPRE)
732 /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
733 * @{
734 */
735 #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
736 /**
737 * @}
738 */
739
740 #endif /* RCC_CFGR_SDPRE */
741
742
743 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
744 * @{
745 */
746 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
747 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
748 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
749 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
750 /**
751 * @}
752 */
753
754 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
755 * @{
756 */
757 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
758 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
759 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
760 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
761 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
762 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
763 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
764 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
765 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
766 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
767 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
768 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
769 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
770 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
771 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
772 /**
773 * @}
774 */
775
776 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
777 * @{
778 */
779 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */
780 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
781 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
782 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
783 #else
784 #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
785 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
786 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
787 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
788 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
789 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
790 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
791 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
792 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
793 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
794 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
795 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
796 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
797 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
798 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
799 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
800 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
801 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
802 /**
803 * @}
804 */
805
806 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
807 * @{
808 */
809 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
810 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
811 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
812 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
813 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
814 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
815 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
816 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
817 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
818 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
819 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
820 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
821 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
822 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
823 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
824 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
825 /**
826 * @}
827 */
828
829 /**
830 * @}
831 */
832
833 /* Exported macro ------------------------------------------------------------*/
834 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
835 * @{
836 */
837
838 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
839 * @{
840 */
841
842 /**
843 * @brief Write a value in RCC register
844 * @param __REG__ Register to be written
845 * @param __VALUE__ Value to be written in the register
846 * @retval None
847 */
848 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
849
850 /**
851 * @brief Read a value in RCC register
852 * @param __REG__ Register to be read
853 * @retval Register value
854 */
855 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
856 /**
857 * @}
858 */
859
860 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
861 * @{
862 */
863
864 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
865 /**
866 * @brief Helper macro to calculate the PLLCLK frequency
867 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
868 * , @ref LL_RCC_PLL_GetPrediv());
869 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
870 * @param __PLLMUL__ This parameter can be one of the following values:
871 * @arg @ref LL_RCC_PLL_MUL_2
872 * @arg @ref LL_RCC_PLL_MUL_3
873 * @arg @ref LL_RCC_PLL_MUL_4
874 * @arg @ref LL_RCC_PLL_MUL_5
875 * @arg @ref LL_RCC_PLL_MUL_6
876 * @arg @ref LL_RCC_PLL_MUL_7
877 * @arg @ref LL_RCC_PLL_MUL_8
878 * @arg @ref LL_RCC_PLL_MUL_9
879 * @arg @ref LL_RCC_PLL_MUL_10
880 * @arg @ref LL_RCC_PLL_MUL_11
881 * @arg @ref LL_RCC_PLL_MUL_12
882 * @arg @ref LL_RCC_PLL_MUL_13
883 * @arg @ref LL_RCC_PLL_MUL_14
884 * @arg @ref LL_RCC_PLL_MUL_15
885 * @arg @ref LL_RCC_PLL_MUL_16
886 * @param __PLLPREDIV__ This parameter can be one of the following values:
887 * @arg @ref LL_RCC_PREDIV_DIV_1
888 * @arg @ref LL_RCC_PREDIV_DIV_2
889 * @arg @ref LL_RCC_PREDIV_DIV_3
890 * @arg @ref LL_RCC_PREDIV_DIV_4
891 * @arg @ref LL_RCC_PREDIV_DIV_5
892 * @arg @ref LL_RCC_PREDIV_DIV_6
893 * @arg @ref LL_RCC_PREDIV_DIV_7
894 * @arg @ref LL_RCC_PREDIV_DIV_8
895 * @arg @ref LL_RCC_PREDIV_DIV_9
896 * @arg @ref LL_RCC_PREDIV_DIV_10
897 * @arg @ref LL_RCC_PREDIV_DIV_11
898 * @arg @ref LL_RCC_PREDIV_DIV_12
899 * @arg @ref LL_RCC_PREDIV_DIV_13
900 * @arg @ref LL_RCC_PREDIV_DIV_14
901 * @arg @ref LL_RCC_PREDIV_DIV_15
902 * @arg @ref LL_RCC_PREDIV_DIV_16
903 * @retval PLL clock frequency (in Hz)
904 */
905 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
906 (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
907
908 #else
909 /**
910 * @brief Helper macro to calculate the PLLCLK frequency
911 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
912 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
913 * @param __PLLMUL__ This parameter can be one of the following values:
914 * @arg @ref LL_RCC_PLL_MUL_2
915 * @arg @ref LL_RCC_PLL_MUL_3
916 * @arg @ref LL_RCC_PLL_MUL_4
917 * @arg @ref LL_RCC_PLL_MUL_5
918 * @arg @ref LL_RCC_PLL_MUL_6
919 * @arg @ref LL_RCC_PLL_MUL_7
920 * @arg @ref LL_RCC_PLL_MUL_8
921 * @arg @ref LL_RCC_PLL_MUL_9
922 * @arg @ref LL_RCC_PLL_MUL_10
923 * @arg @ref LL_RCC_PLL_MUL_11
924 * @arg @ref LL_RCC_PLL_MUL_12
925 * @arg @ref LL_RCC_PLL_MUL_13
926 * @arg @ref LL_RCC_PLL_MUL_14
927 * @arg @ref LL_RCC_PLL_MUL_15
928 * @arg @ref LL_RCC_PLL_MUL_16
929 * @retval PLL clock frequency (in Hz)
930 */
931 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
932 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
933 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
934 /**
935 * @brief Helper macro to calculate the HCLK frequency
936 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
937 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
938 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
939 * @param __AHBPRESCALER__ This parameter can be one of the following values:
940 * @arg @ref LL_RCC_SYSCLK_DIV_1
941 * @arg @ref LL_RCC_SYSCLK_DIV_2
942 * @arg @ref LL_RCC_SYSCLK_DIV_4
943 * @arg @ref LL_RCC_SYSCLK_DIV_8
944 * @arg @ref LL_RCC_SYSCLK_DIV_16
945 * @arg @ref LL_RCC_SYSCLK_DIV_64
946 * @arg @ref LL_RCC_SYSCLK_DIV_128
947 * @arg @ref LL_RCC_SYSCLK_DIV_256
948 * @arg @ref LL_RCC_SYSCLK_DIV_512
949 * @retval HCLK clock frequency (in Hz)
950 */
951 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
952
953 /**
954 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
955 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
956 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
957 * @param __HCLKFREQ__ HCLK frequency
958 * @param __APB1PRESCALER__: This parameter can be one of the following values:
959 * @arg @ref LL_RCC_APB1_DIV_1
960 * @arg @ref LL_RCC_APB1_DIV_2
961 * @arg @ref LL_RCC_APB1_DIV_4
962 * @arg @ref LL_RCC_APB1_DIV_8
963 * @arg @ref LL_RCC_APB1_DIV_16
964 * @retval PCLK1 clock frequency (in Hz)
965 */
966 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
967
968 /**
969 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
970 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
971 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
972 * @param __HCLKFREQ__ HCLK frequency
973 * @param __APB2PRESCALER__: This parameter can be one of the following values:
974 * @arg @ref LL_RCC_APB2_DIV_1
975 * @arg @ref LL_RCC_APB2_DIV_2
976 * @arg @ref LL_RCC_APB2_DIV_4
977 * @arg @ref LL_RCC_APB2_DIV_8
978 * @arg @ref LL_RCC_APB2_DIV_16
979 * @retval PCLK2 clock frequency (in Hz)
980 */
981 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
982
983 /**
984 * @}
985 */
986
987 /**
988 * @}
989 */
990
991 /* Exported functions --------------------------------------------------------*/
992 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
993 * @{
994 */
995
996 /** @defgroup RCC_LL_EF_HSE HSE
997 * @{
998 */
999
1000 /**
1001 * @brief Enable the Clock Security System.
1002 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1003 * @retval None
1004 */
LL_RCC_HSE_EnableCSS(void)1005 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1006 {
1007 SET_BIT(RCC->CR, RCC_CR_CSSON);
1008 }
1009
1010 /**
1011 * @brief Disable the Clock Security System.
1012 * @note Cannot be disabled in HSE is ready (only by hardware)
1013 * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
1014 * @retval None
1015 */
LL_RCC_HSE_DisableCSS(void)1016 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
1017 {
1018 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
1019 }
1020
1021 /**
1022 * @brief Enable HSE external oscillator (HSE Bypass)
1023 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1024 * @retval None
1025 */
LL_RCC_HSE_EnableBypass(void)1026 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1027 {
1028 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1029 }
1030
1031 /**
1032 * @brief Disable HSE external oscillator (HSE Bypass)
1033 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1034 * @retval None
1035 */
LL_RCC_HSE_DisableBypass(void)1036 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1037 {
1038 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1039 }
1040
1041 /**
1042 * @brief Enable HSE crystal oscillator (HSE ON)
1043 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1044 * @retval None
1045 */
LL_RCC_HSE_Enable(void)1046 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1047 {
1048 SET_BIT(RCC->CR, RCC_CR_HSEON);
1049 }
1050
1051 /**
1052 * @brief Disable HSE crystal oscillator (HSE ON)
1053 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1054 * @retval None
1055 */
LL_RCC_HSE_Disable(void)1056 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1057 {
1058 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1059 }
1060
1061 /**
1062 * @brief Check if HSE oscillator Ready
1063 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1064 * @retval State of bit (1 or 0).
1065 */
LL_RCC_HSE_IsReady(void)1066 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1067 {
1068 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1069 }
1070
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup RCC_LL_EF_HSI HSI
1076 * @{
1077 */
1078
1079 /**
1080 * @brief Enable HSI oscillator
1081 * @rmtoll CR HSION LL_RCC_HSI_Enable
1082 * @retval None
1083 */
LL_RCC_HSI_Enable(void)1084 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1085 {
1086 SET_BIT(RCC->CR, RCC_CR_HSION);
1087 }
1088
1089 /**
1090 * @brief Disable HSI oscillator
1091 * @rmtoll CR HSION LL_RCC_HSI_Disable
1092 * @retval None
1093 */
LL_RCC_HSI_Disable(void)1094 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1095 {
1096 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1097 }
1098
1099 /**
1100 * @brief Check if HSI clock is ready
1101 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1102 * @retval State of bit (1 or 0).
1103 */
LL_RCC_HSI_IsReady(void)1104 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1105 {
1106 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
1107 }
1108
1109 /**
1110 * @brief Get HSI Calibration value
1111 * @note When HSITRIM is written, HSICAL is updated with the sum of
1112 * HSITRIM and the factory trim value
1113 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
1114 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1115 */
LL_RCC_HSI_GetCalibration(void)1116 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1117 {
1118 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
1119 }
1120
1121 /**
1122 * @brief Set HSI Calibration trimming
1123 * @note user-programmable trimming value that is added to the HSICAL
1124 * @note Default value is 16, which, when added to the HSICAL value,
1125 * should trim the HSI to 16 MHz +/- 1 %
1126 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
1127 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
1128 * @retval None
1129 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1130 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1131 {
1132 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
1133 }
1134
1135 /**
1136 * @brief Get HSI Calibration trimming
1137 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
1138 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
1139 */
LL_RCC_HSI_GetCalibTrimming(void)1140 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1141 {
1142 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1143 }
1144
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup RCC_LL_EF_LSE LSE
1150 * @{
1151 */
1152
1153 /**
1154 * @brief Enable Low Speed External (LSE) crystal.
1155 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1156 * @retval None
1157 */
LL_RCC_LSE_Enable(void)1158 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1159 {
1160 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1161 }
1162
1163 /**
1164 * @brief Disable Low Speed External (LSE) crystal.
1165 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1166 * @retval None
1167 */
LL_RCC_LSE_Disable(void)1168 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1169 {
1170 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1171 }
1172
1173 /**
1174 * @brief Enable external clock source (LSE bypass).
1175 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1176 * @retval None
1177 */
LL_RCC_LSE_EnableBypass(void)1178 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1179 {
1180 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1181 }
1182
1183 /**
1184 * @brief Disable external clock source (LSE bypass).
1185 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1186 * @retval None
1187 */
LL_RCC_LSE_DisableBypass(void)1188 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1189 {
1190 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1191 }
1192
1193 /**
1194 * @brief Set LSE oscillator drive capability
1195 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1196 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1197 * @param LSEDrive This parameter can be one of the following values:
1198 * @arg @ref LL_RCC_LSEDRIVE_LOW
1199 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1200 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1201 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1202 * @retval None
1203 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1204 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1205 {
1206 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1207 }
1208
1209 /**
1210 * @brief Get LSE oscillator drive capability
1211 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1212 * @retval Returned value can be one of the following values:
1213 * @arg @ref LL_RCC_LSEDRIVE_LOW
1214 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1215 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1216 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1217 */
LL_RCC_LSE_GetDriveCapability(void)1218 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1219 {
1220 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1221 }
1222
1223 /**
1224 * @brief Check if LSE oscillator Ready
1225 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1226 * @retval State of bit (1 or 0).
1227 */
LL_RCC_LSE_IsReady(void)1228 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1229 {
1230 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
1231 }
1232
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup RCC_LL_EF_LSI LSI
1238 * @{
1239 */
1240
1241 /**
1242 * @brief Enable LSI Oscillator
1243 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1244 * @retval None
1245 */
LL_RCC_LSI_Enable(void)1246 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1247 {
1248 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1249 }
1250
1251 /**
1252 * @brief Disable LSI Oscillator
1253 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1254 * @retval None
1255 */
LL_RCC_LSI_Disable(void)1256 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1257 {
1258 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1259 }
1260
1261 /**
1262 * @brief Check if LSI is Ready
1263 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1264 * @retval State of bit (1 or 0).
1265 */
LL_RCC_LSI_IsReady(void)1266 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1267 {
1268 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
1269 }
1270
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup RCC_LL_EF_System System
1276 * @{
1277 */
1278
1279 /**
1280 * @brief Configure the system clock source
1281 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1282 * @param Source This parameter can be one of the following values:
1283 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1284 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1285 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1286 * @retval None
1287 */
LL_RCC_SetSysClkSource(uint32_t Source)1288 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1289 {
1290 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1291 }
1292
1293 /**
1294 * @brief Get the system clock source
1295 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1296 * @retval Returned value can be one of the following values:
1297 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1298 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1299 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1300 */
LL_RCC_GetSysClkSource(void)1301 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1302 {
1303 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1304 }
1305
1306 /**
1307 * @brief Set AHB prescaler
1308 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1309 * @param Prescaler This parameter can be one of the following values:
1310 * @arg @ref LL_RCC_SYSCLK_DIV_1
1311 * @arg @ref LL_RCC_SYSCLK_DIV_2
1312 * @arg @ref LL_RCC_SYSCLK_DIV_4
1313 * @arg @ref LL_RCC_SYSCLK_DIV_8
1314 * @arg @ref LL_RCC_SYSCLK_DIV_16
1315 * @arg @ref LL_RCC_SYSCLK_DIV_64
1316 * @arg @ref LL_RCC_SYSCLK_DIV_128
1317 * @arg @ref LL_RCC_SYSCLK_DIV_256
1318 * @arg @ref LL_RCC_SYSCLK_DIV_512
1319 * @retval None
1320 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1321 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1322 {
1323 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1324 }
1325
1326 /**
1327 * @brief Set APB1 prescaler
1328 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1329 * @param Prescaler This parameter can be one of the following values:
1330 * @arg @ref LL_RCC_APB1_DIV_1
1331 * @arg @ref LL_RCC_APB1_DIV_2
1332 * @arg @ref LL_RCC_APB1_DIV_4
1333 * @arg @ref LL_RCC_APB1_DIV_8
1334 * @arg @ref LL_RCC_APB1_DIV_16
1335 * @retval None
1336 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1337 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1338 {
1339 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1340 }
1341
1342 /**
1343 * @brief Set APB2 prescaler
1344 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1345 * @param Prescaler This parameter can be one of the following values:
1346 * @arg @ref LL_RCC_APB2_DIV_1
1347 * @arg @ref LL_RCC_APB2_DIV_2
1348 * @arg @ref LL_RCC_APB2_DIV_4
1349 * @arg @ref LL_RCC_APB2_DIV_8
1350 * @arg @ref LL_RCC_APB2_DIV_16
1351 * @retval None
1352 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1353 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1354 {
1355 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1356 }
1357
1358 /**
1359 * @brief Get AHB prescaler
1360 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1361 * @retval Returned value can be one of the following values:
1362 * @arg @ref LL_RCC_SYSCLK_DIV_1
1363 * @arg @ref LL_RCC_SYSCLK_DIV_2
1364 * @arg @ref LL_RCC_SYSCLK_DIV_4
1365 * @arg @ref LL_RCC_SYSCLK_DIV_8
1366 * @arg @ref LL_RCC_SYSCLK_DIV_16
1367 * @arg @ref LL_RCC_SYSCLK_DIV_64
1368 * @arg @ref LL_RCC_SYSCLK_DIV_128
1369 * @arg @ref LL_RCC_SYSCLK_DIV_256
1370 * @arg @ref LL_RCC_SYSCLK_DIV_512
1371 */
LL_RCC_GetAHBPrescaler(void)1372 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1373 {
1374 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1375 }
1376
1377 /**
1378 * @brief Get APB1 prescaler
1379 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1380 * @retval Returned value can be one of the following values:
1381 * @arg @ref LL_RCC_APB1_DIV_1
1382 * @arg @ref LL_RCC_APB1_DIV_2
1383 * @arg @ref LL_RCC_APB1_DIV_4
1384 * @arg @ref LL_RCC_APB1_DIV_8
1385 * @arg @ref LL_RCC_APB1_DIV_16
1386 */
LL_RCC_GetAPB1Prescaler(void)1387 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1388 {
1389 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1390 }
1391
1392 /**
1393 * @brief Get APB2 prescaler
1394 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1395 * @retval Returned value can be one of the following values:
1396 * @arg @ref LL_RCC_APB2_DIV_1
1397 * @arg @ref LL_RCC_APB2_DIV_2
1398 * @arg @ref LL_RCC_APB2_DIV_4
1399 * @arg @ref LL_RCC_APB2_DIV_8
1400 * @arg @ref LL_RCC_APB2_DIV_16
1401 */
LL_RCC_GetAPB2Prescaler(void)1402 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1403 {
1404 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1405 }
1406
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup RCC_LL_EF_MCO MCO
1412 * @{
1413 */
1414
1415 /**
1416 * @brief Configure MCOx
1417 * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
1418 * CFGR MCOPRE LL_RCC_ConfigMCO\n
1419 * CFGR PLLNODIV LL_RCC_ConfigMCO
1420 * @param MCOxSource This parameter can be one of the following values:
1421 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1422 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1423 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1424 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1425 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1426 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1427 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
1428 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
1429 *
1430 * (*) value not defined in all devices
1431 * @param MCOxPrescaler This parameter can be one of the following values:
1432 * @arg @ref LL_RCC_MCO1_DIV_1
1433 * @arg @ref LL_RCC_MCO1_DIV_2 (*)
1434 * @arg @ref LL_RCC_MCO1_DIV_4 (*)
1435 * @arg @ref LL_RCC_MCO1_DIV_8 (*)
1436 * @arg @ref LL_RCC_MCO1_DIV_16 (*)
1437 * @arg @ref LL_RCC_MCO1_DIV_32 (*)
1438 * @arg @ref LL_RCC_MCO1_DIV_64 (*)
1439 * @arg @ref LL_RCC_MCO1_DIV_128 (*)
1440 *
1441 * (*) value not defined in all devices
1442 * @retval None
1443 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1444 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1445 {
1446 #if defined(RCC_CFGR_MCOPRE)
1447 #if defined(RCC_CFGR_PLLNODIV)
1448 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
1449 #else
1450 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1451 #endif /* RCC_CFGR_PLLNODIV */
1452 #else
1453 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
1454 #endif /* RCC_CFGR_MCOPRE */
1455 }
1456
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1462 * @{
1463 */
1464
1465 /**
1466 * @brief Configure USARTx clock source
1467 * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
1468 * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
1469 * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
1470 * @param USARTxSource This parameter can be one of the following values:
1471 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1472 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1473 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1474 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1475 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1476 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1477 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1478 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1479 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1480 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1481 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1482 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1483 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1484 *
1485 * (*) value not defined in all devices.
1486 * @retval None
1487 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1488 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1489 {
1490 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
1491 }
1492
1493 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1494 /**
1495 * @brief Configure UARTx clock source
1496 * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
1497 * CFGR3 UART5SW LL_RCC_SetUARTClockSource
1498 * @param UARTxSource This parameter can be one of the following values:
1499 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1500 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1501 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1502 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1503 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1504 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1505 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1506 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1507 * @retval None
1508 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)1509 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1510 {
1511 MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
1512 }
1513 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1514
1515 /**
1516 * @brief Configure I2Cx clock source
1517 * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
1518 * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
1519 * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
1520 * @param I2CxSource This parameter can be one of the following values:
1521 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1522 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1523 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1524 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1525 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1526 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1527 *
1528 * (*) value not defined in all devices.
1529 * @retval None
1530 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1531 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1532 {
1533 MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
1534 }
1535
1536 #if defined(RCC_CFGR_I2SSRC)
1537 /**
1538 * @brief Configure I2Sx clock source
1539 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
1540 * @param I2SxSource This parameter can be one of the following values:
1541 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1542 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1543 * @retval None
1544 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1545 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1546 {
1547 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
1548 }
1549 #endif /* RCC_CFGR_I2SSRC */
1550
1551 #if defined(RCC_CFGR3_TIMSW)
1552 /**
1553 * @brief Configure TIMx clock source
1554 * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
1555 * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
1556 * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
1557 * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
1558 * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
1559 * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
1560 * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
1561 * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
1562 * @param TIMxSource This parameter can be one of the following values:
1563 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1564 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1565 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1566 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1567 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1568 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1569 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1570 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1571 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1572 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1573 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1574 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1575 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1576 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1577 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1578 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1579 *
1580 * (*) value not defined in all devices.
1581 * @retval None
1582 */
LL_RCC_SetTIMClockSource(uint32_t TIMxSource)1583 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1584 {
1585 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
1586 }
1587 #endif /* RCC_CFGR3_TIMSW */
1588
1589 #if defined(HRTIM1)
1590 /**
1591 * @brief Configure HRTIMx clock source
1592 * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
1593 * @param HRTIMxSource This parameter can be one of the following values:
1594 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1595 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1596 * @retval None
1597 */
LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)1598 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
1599 {
1600 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
1601 }
1602 #endif /* HRTIM1 */
1603
1604 #if defined(CEC)
1605 /**
1606 * @brief Configure CEC clock source
1607 * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
1608 * @param CECxSource This parameter can be one of the following values:
1609 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1610 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1611 * @retval None
1612 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)1613 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
1614 {
1615 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
1616 }
1617 #endif /* CEC */
1618
1619 #if defined(USB)
1620 /**
1621 * @brief Configure USB clock source
1622 * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
1623 * @param USBxSource This parameter can be one of the following values:
1624 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1625 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1626 * @retval None
1627 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1628 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1629 {
1630 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
1631 }
1632 #endif /* USB */
1633
1634 #if defined(RCC_CFGR_ADCPRE)
1635 /**
1636 * @brief Configure ADC clock source
1637 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
1638 * @param ADCxSource This parameter can be one of the following values:
1639 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1640 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1641 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1642 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1643 * @retval None
1644 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1645 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1646 {
1647 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
1648 }
1649
1650 #elif defined(RCC_CFGR2_ADC1PRES)
1651 /**
1652 * @brief Configure ADC clock source
1653 * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
1654 * @param ADCxSource This parameter can be one of the following values:
1655 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1656 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1657 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1658 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1659 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1660 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1661 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1662 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1663 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1664 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1665 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1666 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1667 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1668 * @retval None
1669 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1670 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1671 {
1672 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
1673 }
1674
1675 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1676 /**
1677 * @brief Configure ADC clock source
1678 * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
1679 * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
1680 * @param ADCxSource This parameter can be one of the following values:
1681 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
1682 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
1683 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
1684 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
1685 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
1686 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
1687 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
1688 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
1689 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
1690 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
1691 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
1692 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
1693 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
1694 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
1695 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
1696 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
1697 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
1698 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
1699 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
1700 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
1701 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
1702 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
1703 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
1704 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
1705 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
1706 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
1707 *
1708 * (*) value not defined in all devices.
1709 * @retval None
1710 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1711 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1712 {
1713 #if defined(RCC_CFGR2_ADCPRE34)
1714 MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
1715 #else
1716 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
1717 #endif /* RCC_CFGR2_ADCPRE34 */
1718 }
1719 #endif /* RCC_CFGR_ADCPRE */
1720
1721 #if defined(RCC_CFGR_SDPRE)
1722 /**
1723 * @brief Configure SDADCx clock source
1724 * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
1725 * @param SDADCxSource This parameter can be one of the following values:
1726 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
1727 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
1728 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
1729 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
1730 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
1731 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
1732 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
1733 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
1734 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
1735 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
1736 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
1737 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
1738 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
1739 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
1740 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
1741 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
1742 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
1743 * @retval None
1744 */
LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)1745 __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
1746 {
1747 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
1748 }
1749 #endif /* RCC_CFGR_SDPRE */
1750
1751 /**
1752 * @brief Get USARTx clock source
1753 * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
1754 * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
1755 * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
1756 * @param USARTx This parameter can be one of the following values:
1757 * @arg @ref LL_RCC_USART1_CLKSOURCE
1758 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
1759 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
1760 *
1761 * (*) value not defined in all devices.
1762 * @retval Returned value can be one of the following values:
1763 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1764 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1765 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1766 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1767 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1768 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1769 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1770 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1771 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1772 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1773 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1774 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1775 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1776 *
1777 * (*) value not defined in all devices.
1778 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1779 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1780 {
1781 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
1782 }
1783
1784 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1785 /**
1786 * @brief Get UARTx clock source
1787 * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
1788 * CFGR3 UART5SW LL_RCC_GetUARTClockSource
1789 * @param UARTx This parameter can be one of the following values:
1790 * @arg @ref LL_RCC_UART4_CLKSOURCE
1791 * @arg @ref LL_RCC_UART5_CLKSOURCE
1792 * @retval Returned value can be one of the following values:
1793 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1794 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1795 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1796 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1797 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1798 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1799 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1800 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1801 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)1802 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1803 {
1804 return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
1805 }
1806 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1807
1808 /**
1809 * @brief Get I2Cx clock source
1810 * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
1811 * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
1812 * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
1813 * @param I2Cx This parameter can be one of the following values:
1814 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1815 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
1816 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
1817 *
1818 * (*) value not defined in all devices.
1819 * @retval Returned value can be one of the following values:
1820 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1821 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1822 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1823 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1824 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1825 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1826 *
1827 * (*) value not defined in all devices.
1828 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1829 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1830 {
1831 return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
1832 }
1833
1834 #if defined(RCC_CFGR_I2SSRC)
1835 /**
1836 * @brief Get I2Sx clock source
1837 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
1838 * @param I2Sx This parameter can be one of the following values:
1839 * @arg @ref LL_RCC_I2S_CLKSOURCE
1840 * @retval Returned value can be one of the following values:
1841 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1842 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1843 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1844 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1845 {
1846 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
1847 }
1848 #endif /* RCC_CFGR_I2SSRC */
1849
1850 #if defined(RCC_CFGR3_TIMSW)
1851 /**
1852 * @brief Get TIMx clock source
1853 * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
1854 * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
1855 * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
1856 * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
1857 * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
1858 * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
1859 * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
1860 * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
1861 * @param TIMx This parameter can be one of the following values:
1862 * @arg @ref LL_RCC_TIM1_CLKSOURCE
1863 * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
1864 * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
1865 * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
1866 * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
1867 * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
1868 * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
1869 * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
1870 *
1871 * (*) value not defined in all devices.
1872 * @retval Returned value can be one of the following values:
1873 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1874 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1875 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1876 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1877 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1878 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1879 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1880 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1881 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1882 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1883 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1884 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1885 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1886 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1887 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1888 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1889 *
1890 * (*) value not defined in all devices.
1891 */
LL_RCC_GetTIMClockSource(uint32_t TIMx)1892 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
1893 {
1894 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
1895 }
1896 #endif /* RCC_CFGR3_TIMSW */
1897
1898 #if defined(HRTIM1)
1899 /**
1900 * @brief Get HRTIMx clock source
1901 * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
1902 * @param HRTIMx This parameter can be one of the following values:
1903 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
1904 * @retval Returned value can be one of the following values:
1905 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1906 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1907 */
LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)1908 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
1909 {
1910 return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
1911 }
1912 #endif /* HRTIM1 */
1913
1914 #if defined(CEC)
1915 /**
1916 * @brief Get CEC clock source
1917 * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
1918 * @param CECx This parameter can be one of the following values:
1919 * @arg @ref LL_RCC_CEC_CLKSOURCE
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1922 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1923 */
LL_RCC_GetCECClockSource(uint32_t CECx)1924 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
1925 {
1926 return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
1927 }
1928 #endif /* CEC */
1929
1930 #if defined(USB)
1931 /**
1932 * @brief Get USBx clock source
1933 * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
1934 * @param USBx This parameter can be one of the following values:
1935 * @arg @ref LL_RCC_USB_CLKSOURCE
1936 * @retval Returned value can be one of the following values:
1937 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1938 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1939 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1940 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1941 {
1942 return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
1943 }
1944 #endif /* USB */
1945
1946 #if defined(RCC_CFGR_ADCPRE)
1947 /**
1948 * @brief Get ADCx clock source
1949 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
1950 * @param ADCx This parameter can be one of the following values:
1951 * @arg @ref LL_RCC_ADC_CLKSOURCE
1952 * @retval Returned value can be one of the following values:
1953 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1954 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1955 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1956 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1957 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1958 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1959 {
1960 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
1961 }
1962
1963 #elif defined(RCC_CFGR2_ADC1PRES)
1964 /**
1965 * @brief Get ADCx clock source
1966 * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
1967 * @param ADCx This parameter can be one of the following values:
1968 * @arg @ref LL_RCC_ADC1_CLKSOURCE
1969 * @retval Returned value can be one of the following values:
1970 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1971 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1972 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1973 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1974 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1975 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1976 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1977 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1978 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1979 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1980 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1981 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1982 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1983 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1984 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1985 {
1986 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
1987 }
1988
1989 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1990 /**
1991 * @brief Get ADCx clock source
1992 * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
1993 * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
1994 * @param ADCx This parameter can be one of the following values:
1995 * @arg @ref LL_RCC_ADC12_CLKSOURCE
1996 * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
1997 *
1998 * (*) value not defined in all devices.
1999 * @retval Returned value can be one of the following values:
2000 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
2001 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
2002 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
2003 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
2004 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
2005 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
2006 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
2007 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
2008 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
2009 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
2010 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
2011 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
2012 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
2013 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
2014 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
2015 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
2016 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
2017 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
2018 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
2019 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
2020 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
2021 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
2022 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
2023 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
2024 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
2025 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
2026 *
2027 * (*) value not defined in all devices.
2028 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2029 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2030 {
2031 #if defined(RCC_CFGR2_ADCPRE34)
2032 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
2033 #else
2034 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
2035 #endif /*RCC_CFGR2_ADCPRE34*/
2036 }
2037 #endif /* RCC_CFGR_ADCPRE */
2038
2039 #if defined(RCC_CFGR_SDPRE)
2040 /**
2041 * @brief Get SDADCx clock source
2042 * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
2043 * @param SDADCx This parameter can be one of the following values:
2044 * @arg @ref LL_RCC_SDADC_CLKSOURCE
2045 * @retval Returned value can be one of the following values:
2046 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
2047 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
2048 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
2049 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
2050 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
2051 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
2052 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
2053 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
2054 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
2055 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
2056 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
2057 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
2058 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
2059 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
2060 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
2061 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
2062 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
2063 */
LL_RCC_GetSDADCClockSource(uint32_t SDADCx)2064 __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
2065 {
2066 return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
2067 }
2068 #endif /* RCC_CFGR_SDPRE */
2069
2070 /**
2071 * @}
2072 */
2073
2074 /** @defgroup RCC_LL_EF_RTC RTC
2075 * @{
2076 */
2077
2078 /**
2079 * @brief Set RTC Clock Source
2080 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
2081 * the Backup domain is reset. The BDRST bit can be used to reset them.
2082 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2083 * @param Source This parameter can be one of the following values:
2084 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2085 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2086 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2087 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2088 * @retval None
2089 */
LL_RCC_SetRTCClockSource(uint32_t Source)2090 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2091 {
2092 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2093 }
2094
2095 /**
2096 * @brief Get RTC Clock Source
2097 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2098 * @retval Returned value can be one of the following values:
2099 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2100 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2101 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2102 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2103 */
LL_RCC_GetRTCClockSource(void)2104 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2105 {
2106 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2107 }
2108
2109 /**
2110 * @brief Enable RTC
2111 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2112 * @retval None
2113 */
LL_RCC_EnableRTC(void)2114 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2115 {
2116 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2117 }
2118
2119 /**
2120 * @brief Disable RTC
2121 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2122 * @retval None
2123 */
LL_RCC_DisableRTC(void)2124 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2125 {
2126 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2127 }
2128
2129 /**
2130 * @brief Check if RTC has been enabled or not
2131 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2132 * @retval State of bit (1 or 0).
2133 */
LL_RCC_IsEnabledRTC(void)2134 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2135 {
2136 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2137 }
2138
2139 /**
2140 * @brief Force the Backup domain reset
2141 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2142 * @retval None
2143 */
LL_RCC_ForceBackupDomainReset(void)2144 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2145 {
2146 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2147 }
2148
2149 /**
2150 * @brief Release the Backup domain reset
2151 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2152 * @retval None
2153 */
LL_RCC_ReleaseBackupDomainReset(void)2154 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2155 {
2156 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2157 }
2158
2159 /**
2160 * @}
2161 */
2162
2163 /** @defgroup RCC_LL_EF_PLL PLL
2164 * @{
2165 */
2166
2167 /**
2168 * @brief Enable PLL
2169 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2170 * @retval None
2171 */
LL_RCC_PLL_Enable(void)2172 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2173 {
2174 SET_BIT(RCC->CR, RCC_CR_PLLON);
2175 }
2176
2177 /**
2178 * @brief Disable PLL
2179 * @note Cannot be disabled if the PLL clock is used as the system clock
2180 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2181 * @retval None
2182 */
LL_RCC_PLL_Disable(void)2183 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2184 {
2185 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2186 }
2187
2188 /**
2189 * @brief Check if PLL Ready
2190 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2191 * @retval State of bit (1 or 0).
2192 */
LL_RCC_PLL_IsReady(void)2193 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2194 {
2195 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
2196 }
2197
2198 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
2199 /**
2200 * @brief Configure PLL used for SYSCLK Domain
2201 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2202 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2203 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2204 * @param Source This parameter can be one of the following values:
2205 * @arg @ref LL_RCC_PLLSOURCE_HSI
2206 * @arg @ref LL_RCC_PLLSOURCE_HSE
2207 * @param PLLMul This parameter can be one of the following values:
2208 * @arg @ref LL_RCC_PLL_MUL_2
2209 * @arg @ref LL_RCC_PLL_MUL_3
2210 * @arg @ref LL_RCC_PLL_MUL_4
2211 * @arg @ref LL_RCC_PLL_MUL_5
2212 * @arg @ref LL_RCC_PLL_MUL_6
2213 * @arg @ref LL_RCC_PLL_MUL_7
2214 * @arg @ref LL_RCC_PLL_MUL_8
2215 * @arg @ref LL_RCC_PLL_MUL_9
2216 * @arg @ref LL_RCC_PLL_MUL_10
2217 * @arg @ref LL_RCC_PLL_MUL_11
2218 * @arg @ref LL_RCC_PLL_MUL_12
2219 * @arg @ref LL_RCC_PLL_MUL_13
2220 * @arg @ref LL_RCC_PLL_MUL_14
2221 * @arg @ref LL_RCC_PLL_MUL_15
2222 * @arg @ref LL_RCC_PLL_MUL_16
2223 * @param PLLDiv This parameter can be one of the following values:
2224 * @arg @ref LL_RCC_PREDIV_DIV_1
2225 * @arg @ref LL_RCC_PREDIV_DIV_2
2226 * @arg @ref LL_RCC_PREDIV_DIV_3
2227 * @arg @ref LL_RCC_PREDIV_DIV_4
2228 * @arg @ref LL_RCC_PREDIV_DIV_5
2229 * @arg @ref LL_RCC_PREDIV_DIV_6
2230 * @arg @ref LL_RCC_PREDIV_DIV_7
2231 * @arg @ref LL_RCC_PREDIV_DIV_8
2232 * @arg @ref LL_RCC_PREDIV_DIV_9
2233 * @arg @ref LL_RCC_PREDIV_DIV_10
2234 * @arg @ref LL_RCC_PREDIV_DIV_11
2235 * @arg @ref LL_RCC_PREDIV_DIV_12
2236 * @arg @ref LL_RCC_PREDIV_DIV_13
2237 * @arg @ref LL_RCC_PREDIV_DIV_14
2238 * @arg @ref LL_RCC_PREDIV_DIV_15
2239 * @arg @ref LL_RCC_PREDIV_DIV_16
2240 * @retval None
2241 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul,uint32_t PLLDiv)2242 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
2243 {
2244 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
2245 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
2246 }
2247
2248 #else
2249
2250 /**
2251 * @brief Configure PLL used for SYSCLK Domain
2252 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2253 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2254 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2255 * @param Source This parameter can be one of the following values:
2256 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
2257 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
2258 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
2259 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
2260 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
2261 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
2262 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
2263 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
2264 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
2265 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
2266 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
2267 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
2268 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
2269 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
2270 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
2271 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
2272 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
2273 * @param PLLMul This parameter can be one of the following values:
2274 * @arg @ref LL_RCC_PLL_MUL_2
2275 * @arg @ref LL_RCC_PLL_MUL_3
2276 * @arg @ref LL_RCC_PLL_MUL_4
2277 * @arg @ref LL_RCC_PLL_MUL_5
2278 * @arg @ref LL_RCC_PLL_MUL_6
2279 * @arg @ref LL_RCC_PLL_MUL_7
2280 * @arg @ref LL_RCC_PLL_MUL_8
2281 * @arg @ref LL_RCC_PLL_MUL_9
2282 * @arg @ref LL_RCC_PLL_MUL_10
2283 * @arg @ref LL_RCC_PLL_MUL_11
2284 * @arg @ref LL_RCC_PLL_MUL_12
2285 * @arg @ref LL_RCC_PLL_MUL_13
2286 * @arg @ref LL_RCC_PLL_MUL_14
2287 * @arg @ref LL_RCC_PLL_MUL_15
2288 * @arg @ref LL_RCC_PLL_MUL_16
2289 * @retval None
2290 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul)2291 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
2292 {
2293 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
2294 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
2295 }
2296 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
2297
2298 /**
2299 * @brief Configure PLL clock source
2300 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
2301 * @param PLLSource This parameter can be one of the following values:
2302 * @arg @ref LL_RCC_PLLSOURCE_NONE
2303 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
2304 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
2305 * @arg @ref LL_RCC_PLLSOURCE_HSE
2306 * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
2307 *
2308 * (*) value not defined in all devices
2309 * @retval None
2310 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)2311 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2312 {
2313 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
2314 }
2315
2316 /**
2317 * @brief Get the oscillator used as PLL clock source.
2318 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
2319 * @retval Returned value can be one of the following values:
2320 * @arg @ref LL_RCC_PLLSOURCE_NONE
2321 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
2322 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
2323 * @arg @ref LL_RCC_PLLSOURCE_HSE
2324 *
2325 * (*) value not defined in all devices
2326 */
LL_RCC_PLL_GetMainSource(void)2327 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2328 {
2329 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
2330 }
2331
2332 /**
2333 * @brief Get PLL multiplication Factor
2334 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
2335 * @retval Returned value can be one of the following values:
2336 * @arg @ref LL_RCC_PLL_MUL_2
2337 * @arg @ref LL_RCC_PLL_MUL_3
2338 * @arg @ref LL_RCC_PLL_MUL_4
2339 * @arg @ref LL_RCC_PLL_MUL_5
2340 * @arg @ref LL_RCC_PLL_MUL_6
2341 * @arg @ref LL_RCC_PLL_MUL_7
2342 * @arg @ref LL_RCC_PLL_MUL_8
2343 * @arg @ref LL_RCC_PLL_MUL_9
2344 * @arg @ref LL_RCC_PLL_MUL_10
2345 * @arg @ref LL_RCC_PLL_MUL_11
2346 * @arg @ref LL_RCC_PLL_MUL_12
2347 * @arg @ref LL_RCC_PLL_MUL_13
2348 * @arg @ref LL_RCC_PLL_MUL_14
2349 * @arg @ref LL_RCC_PLL_MUL_15
2350 * @arg @ref LL_RCC_PLL_MUL_16
2351 */
LL_RCC_PLL_GetMultiplicator(void)2352 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
2353 {
2354 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
2355 }
2356
2357 /**
2358 * @brief Get PREDIV division factor for the main PLL
2359 * @note They can be written only when the PLL is disabled
2360 * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
2361 * @retval Returned value can be one of the following values:
2362 * @arg @ref LL_RCC_PREDIV_DIV_1
2363 * @arg @ref LL_RCC_PREDIV_DIV_2
2364 * @arg @ref LL_RCC_PREDIV_DIV_3
2365 * @arg @ref LL_RCC_PREDIV_DIV_4
2366 * @arg @ref LL_RCC_PREDIV_DIV_5
2367 * @arg @ref LL_RCC_PREDIV_DIV_6
2368 * @arg @ref LL_RCC_PREDIV_DIV_7
2369 * @arg @ref LL_RCC_PREDIV_DIV_8
2370 * @arg @ref LL_RCC_PREDIV_DIV_9
2371 * @arg @ref LL_RCC_PREDIV_DIV_10
2372 * @arg @ref LL_RCC_PREDIV_DIV_11
2373 * @arg @ref LL_RCC_PREDIV_DIV_12
2374 * @arg @ref LL_RCC_PREDIV_DIV_13
2375 * @arg @ref LL_RCC_PREDIV_DIV_14
2376 * @arg @ref LL_RCC_PREDIV_DIV_15
2377 * @arg @ref LL_RCC_PREDIV_DIV_16
2378 */
LL_RCC_PLL_GetPrediv(void)2379 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
2380 {
2381 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
2382 }
2383
2384 /**
2385 * @}
2386 */
2387
2388 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2389 * @{
2390 */
2391
2392 /**
2393 * @brief Clear LSI ready interrupt flag
2394 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2395 * @retval None
2396 */
LL_RCC_ClearFlag_LSIRDY(void)2397 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2398 {
2399 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
2400 }
2401
2402 /**
2403 * @brief Clear LSE ready interrupt flag
2404 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
2405 * @retval None
2406 */
LL_RCC_ClearFlag_LSERDY(void)2407 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2408 {
2409 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
2410 }
2411
2412 /**
2413 * @brief Clear HSI ready interrupt flag
2414 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2415 * @retval None
2416 */
LL_RCC_ClearFlag_HSIRDY(void)2417 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2418 {
2419 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
2420 }
2421
2422 /**
2423 * @brief Clear HSE ready interrupt flag
2424 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
2425 * @retval None
2426 */
LL_RCC_ClearFlag_HSERDY(void)2427 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2428 {
2429 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
2430 }
2431
2432 /**
2433 * @brief Clear PLL ready interrupt flag
2434 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2435 * @retval None
2436 */
LL_RCC_ClearFlag_PLLRDY(void)2437 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2438 {
2439 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
2440 }
2441
2442 /**
2443 * @brief Clear Clock security system interrupt flag
2444 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
2445 * @retval None
2446 */
LL_RCC_ClearFlag_HSECSS(void)2447 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2448 {
2449 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
2450 }
2451
2452 /**
2453 * @brief Check if LSI ready interrupt occurred or not
2454 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2455 * @retval State of bit (1 or 0).
2456 */
LL_RCC_IsActiveFlag_LSIRDY(void)2457 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2458 {
2459 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
2460 }
2461
2462 /**
2463 * @brief Check if LSE ready interrupt occurred or not
2464 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2465 * @retval State of bit (1 or 0).
2466 */
LL_RCC_IsActiveFlag_LSERDY(void)2467 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2468 {
2469 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
2470 }
2471
2472 /**
2473 * @brief Check if HSI ready interrupt occurred or not
2474 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2475 * @retval State of bit (1 or 0).
2476 */
LL_RCC_IsActiveFlag_HSIRDY(void)2477 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2478 {
2479 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
2480 }
2481
2482 /**
2483 * @brief Check if HSE ready interrupt occurred or not
2484 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2485 * @retval State of bit (1 or 0).
2486 */
LL_RCC_IsActiveFlag_HSERDY(void)2487 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2488 {
2489 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
2490 }
2491
2492 #if defined(RCC_CFGR_MCOF)
2493 /**
2494 * @brief Check if switch to new MCO source is effective or not
2495 * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
2496 * @retval State of bit (1 or 0).
2497 */
LL_RCC_IsActiveFlag_MCO1(void)2498 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
2499 {
2500 return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
2501 }
2502 #endif /* RCC_CFGR_MCOF */
2503
2504 /**
2505 * @brief Check if PLL ready interrupt occurred or not
2506 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2507 * @retval State of bit (1 or 0).
2508 */
LL_RCC_IsActiveFlag_PLLRDY(void)2509 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2510 {
2511 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
2512 }
2513
2514 /**
2515 * @brief Check if Clock security system interrupt occurred or not
2516 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
2517 * @retval State of bit (1 or 0).
2518 */
LL_RCC_IsActiveFlag_HSECSS(void)2519 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2520 {
2521 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
2522 }
2523
2524 /**
2525 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2526 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2527 * @retval State of bit (1 or 0).
2528 */
LL_RCC_IsActiveFlag_IWDGRST(void)2529 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2530 {
2531 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
2532 }
2533
2534 /**
2535 * @brief Check if RCC flag Low Power reset is set or not.
2536 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2537 * @retval State of bit (1 or 0).
2538 */
LL_RCC_IsActiveFlag_LPWRRST(void)2539 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2540 {
2541 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
2542 }
2543
2544 /**
2545 * @brief Check if RCC flag is set or not.
2546 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2547 * @retval State of bit (1 or 0).
2548 */
LL_RCC_IsActiveFlag_OBLRST(void)2549 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2550 {
2551 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
2552 }
2553
2554 /**
2555 * @brief Check if RCC flag Pin reset is set or not.
2556 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2557 * @retval State of bit (1 or 0).
2558 */
LL_RCC_IsActiveFlag_PINRST(void)2559 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2560 {
2561 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
2562 }
2563
2564 /**
2565 * @brief Check if RCC flag POR/PDR reset is set or not.
2566 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
2567 * @retval State of bit (1 or 0).
2568 */
LL_RCC_IsActiveFlag_PORRST(void)2569 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
2570 {
2571 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
2572 }
2573
2574 /**
2575 * @brief Check if RCC flag Software reset is set or not.
2576 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2577 * @retval State of bit (1 or 0).
2578 */
LL_RCC_IsActiveFlag_SFTRST(void)2579 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2580 {
2581 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
2582 }
2583
2584 /**
2585 * @brief Check if RCC flag Window Watchdog reset is set or not.
2586 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2587 * @retval State of bit (1 or 0).
2588 */
LL_RCC_IsActiveFlag_WWDGRST(void)2589 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2590 {
2591 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
2592 }
2593
2594 #if defined(RCC_CSR_V18PWRRSTF)
2595 /**
2596 * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
2597 * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
2598 * @retval State of bit (1 or 0).
2599 */
LL_RCC_IsActiveFlag_V18PWRRST(void)2600 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
2601 {
2602 return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
2603 }
2604 #endif /* RCC_CSR_V18PWRRSTF */
2605
2606 /**
2607 * @brief Set RMVF bit to clear the reset flags.
2608 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2609 * @retval None
2610 */
LL_RCC_ClearResetFlags(void)2611 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2612 {
2613 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2614 }
2615
2616 /**
2617 * @}
2618 */
2619
2620 /** @defgroup RCC_LL_EF_IT_Management IT Management
2621 * @{
2622 */
2623
2624 /**
2625 * @brief Enable LSI ready interrupt
2626 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
2627 * @retval None
2628 */
LL_RCC_EnableIT_LSIRDY(void)2629 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2630 {
2631 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2632 }
2633
2634 /**
2635 * @brief Enable LSE ready interrupt
2636 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
2637 * @retval None
2638 */
LL_RCC_EnableIT_LSERDY(void)2639 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2640 {
2641 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2642 }
2643
2644 /**
2645 * @brief Enable HSI ready interrupt
2646 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
2647 * @retval None
2648 */
LL_RCC_EnableIT_HSIRDY(void)2649 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2650 {
2651 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2652 }
2653
2654 /**
2655 * @brief Enable HSE ready interrupt
2656 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
2657 * @retval None
2658 */
LL_RCC_EnableIT_HSERDY(void)2659 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2660 {
2661 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2662 }
2663
2664 /**
2665 * @brief Enable PLL ready interrupt
2666 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
2667 * @retval None
2668 */
LL_RCC_EnableIT_PLLRDY(void)2669 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2670 {
2671 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2672 }
2673
2674 /**
2675 * @brief Disable LSI ready interrupt
2676 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
2677 * @retval None
2678 */
LL_RCC_DisableIT_LSIRDY(void)2679 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2680 {
2681 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2682 }
2683
2684 /**
2685 * @brief Disable LSE ready interrupt
2686 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
2687 * @retval None
2688 */
LL_RCC_DisableIT_LSERDY(void)2689 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2690 {
2691 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2692 }
2693
2694 /**
2695 * @brief Disable HSI ready interrupt
2696 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
2697 * @retval None
2698 */
LL_RCC_DisableIT_HSIRDY(void)2699 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2700 {
2701 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2702 }
2703
2704 /**
2705 * @brief Disable HSE ready interrupt
2706 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
2707 * @retval None
2708 */
LL_RCC_DisableIT_HSERDY(void)2709 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2710 {
2711 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2712 }
2713
2714 /**
2715 * @brief Disable PLL ready interrupt
2716 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
2717 * @retval None
2718 */
LL_RCC_DisableIT_PLLRDY(void)2719 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2720 {
2721 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2722 }
2723
2724 /**
2725 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2726 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2727 * @retval State of bit (1 or 0).
2728 */
LL_RCC_IsEnabledIT_LSIRDY(void)2729 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2730 {
2731 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
2732 }
2733
2734 /**
2735 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2736 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2737 * @retval State of bit (1 or 0).
2738 */
LL_RCC_IsEnabledIT_LSERDY(void)2739 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2740 {
2741 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
2742 }
2743
2744 /**
2745 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2746 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2747 * @retval State of bit (1 or 0).
2748 */
LL_RCC_IsEnabledIT_HSIRDY(void)2749 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2750 {
2751 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
2752 }
2753
2754 /**
2755 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2756 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2757 * @retval State of bit (1 or 0).
2758 */
LL_RCC_IsEnabledIT_HSERDY(void)2759 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2760 {
2761 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
2762 }
2763
2764 /**
2765 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2766 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2767 * @retval State of bit (1 or 0).
2768 */
LL_RCC_IsEnabledIT_PLLRDY(void)2769 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2770 {
2771 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
2772 }
2773
2774 /**
2775 * @}
2776 */
2777
2778 #if defined(USE_FULL_LL_DRIVER)
2779 /** @defgroup RCC_LL_EF_Init De-initialization function
2780 * @{
2781 */
2782 ErrorStatus LL_RCC_DeInit(void);
2783 /**
2784 * @}
2785 */
2786
2787 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2788 * @{
2789 */
2790 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2791 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2792 #if defined(UART4) || defined(UART5)
2793 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2794 #endif /* UART4 || UART5 */
2795 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2796 #if defined(RCC_CFGR_I2SSRC)
2797 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2798 #endif /* RCC_CFGR_I2SSRC */
2799 #if defined(USB_OTG_FS) || defined(USB)
2800 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2801 #endif /* USB_OTG_FS || USB */
2802 #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
2803 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2804 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
2805 #if defined(RCC_CFGR_SDPRE)
2806 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
2807 #endif /*RCC_CFGR_SDPRE */
2808 #if defined(CEC)
2809 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
2810 #endif /* CEC */
2811 #if defined(RCC_CFGR3_TIMSW)
2812 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
2813 #endif /*RCC_CFGR3_TIMSW*/
2814 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
2815 /**
2816 * @}
2817 */
2818 #endif /* USE_FULL_LL_DRIVER */
2819
2820 /**
2821 * @}
2822 */
2823
2824 /**
2825 * @}
2826 */
2827
2828 #endif /* RCC */
2829
2830 /**
2831 * @}
2832 */
2833
2834 #ifdef __cplusplus
2835 }
2836 #endif
2837
2838 #endif /* __STM32F3xx_LL_RCC_H */
2839
2840
