1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F3xx_LL_HRTIM_H
21 #define STM32F3xx_LL_HRTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (HRTIM1)
35
36 /** @defgroup HRTIM_LL HRTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
43 * @{
44 */
45 static const uint16_t REG_OFFSET_TAB_TIMER[] =
46 {
47 0x00U, /* 0: MASTER */
48 0x80U, /* 1: TIMER A */
49 0x100U, /* 2: TIMER B */
50 0x180U, /* 3: TIMER C */
51 0x200U, /* 4: TIMER D */
52 0x280U /* 5: TIMER E */
53 };
54
55 static const uint8_t REG_OFFSET_TAB_ADCxR[] =
56 {
57 0x00U, /* 0: HRTIM_ADC1R */
58 0x04U, /* 1: HRTIM_ADC2R */
59 0x08U, /* 2: HRTIM_ADC3R */
60 0x0CU, /* 3: HRTIM_ADC4R */
61 };
62
63 static const uint16_t REG_OFFSET_TAB_SETxR[] =
64 {
65 0x00U, /* 0: TA1 */
66 0x08U, /* 1: TA2 */
67 0x80U, /* 2: TB1 */
68 0x88U, /* 3: TB2 */
69 0x100U, /* 4: TC1 */
70 0x108U, /* 5: TC2 */
71 0x180U, /* 6: TD1 */
72 0x188U, /* 7: TD2 */
73 0x200U, /* 8: TE1 */
74 0x208U /* 9: TE2 */
75 };
76
77 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
78 {
79 0x00U, /* 0: TA1 */
80 0x00U, /* 1: TA2 */
81 0x80U, /* 2: TB1 */
82 0x80U, /* 3: TB2 */
83 0x100U, /* 4: TC1 */
84 0x100U, /* 5: TC2 */
85 0x180U, /* 6: TD1 */
86 0x180U, /* 7: TD2 */
87 0x200U, /* 8: TE1 */
88 0x200U /* 9: TE2 */
89 };
90
91 static const uint8_t REG_OFFSET_TAB_EECR[] =
92 {
93 0x00U, /* LL_HRTIM_EVENT_1 */
94 0x00U, /* LL_HRTIM_EVENT_2 */
95 0x00U, /* LL_HRTIM_EVENT_3 */
96 0x00U, /* LL_HRTIM_EVENT_4 */
97 0x00U, /* LL_HRTIM_EVENT_5 */
98 0x04U, /* LL_HRTIM_EVENT_6 */
99 0x04U, /* LL_HRTIM_EVENT_7 */
100 0x04U, /* LL_HRTIM_EVENT_8 */
101 0x04U, /* LL_HRTIM_EVENT_9 */
102 0x04U /* LL_HRTIM_EVENT_10 */
103 };
104
105 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
106 {
107 0x00U, /* LL_HRTIM_FAULT_1 */
108 0x00U, /* LL_HRTIM_FAULT_2 */
109 0x00U, /* LL_HRTIM_FAULT_3 */
110 0x00U, /* LL_HRTIM_FAULT_4 */
111 0x04U /* LL_HRTIM_FAULT_5 */
112 };
113
114 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
115 {
116 0x20000000U, /* 0: MASTER */
117 0x01FE0000U, /* 1: TIMER A */
118 0x01FE0000U, /* 2: TIMER B */
119 0x01FE0000U, /* 3: TIMER C */
120 0x01FE0000U, /* 4: TIMER D */
121 0x01FE0000U /* 5: TIMER E */
122 };
123
124 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
125 {
126 12U, /* 0: MASTER */
127 0U, /* 1: TIMER A */
128 0U, /* 2: TIMER B */
129 0U, /* 3: TIMER C */
130 0U, /* 4: TIMER D */
131 0U /* 5: TIMER E */
132 };
133
134 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
135 {
136 0U, /* LL_HRTIM_EVENT_1 */
137 6U, /* LL_HRTIM_EVENT_2 */
138 12U, /* LL_HRTIM_EVENT_3 */
139 18U, /* LL_HRTIM_EVENT_4 */
140 24U, /* LL_HRTIM_EVENT_5 */
141 0U, /* LL_HRTIM_EVENT_6 */
142 6U, /* LL_HRTIM_EVENT_7 */
143 12U, /* LL_HRTIM_EVENT_8 */
144 18U, /* LL_HRTIM_EVENT_9 */
145 24U /* LL_HRTIM_EVENT_10 */
146 };
147
148 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
149 {
150 HRTIM_MCR_BRSTDMA, /* 0: MASTER */
151 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
152 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
153 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
154 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
155 HRTIM_TIMCR_UPDGAT /* 5: TIMER E */
156 };
157
158 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
159 {
160 2U, /* 0: MASTER */
161 0U, /* 1: TIMER A */
162 0U, /* 2: TIMER B */
163 0U, /* 3: TIMER C */
164 0U, /* 4: TIMER D */
165 0U /* 5: TIMER E */
166 };
167
168 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
169 {
170 0U, /* 0: TA1 */
171 16U, /* 1: TA2 */
172 0U, /* 2: TB1 */
173 16U, /* 3: TB2 */
174 0U, /* 4: TC1 */
175 16U, /* 5: TC2 */
176 0U, /* 6: TD1 */
177 16U, /* 7: TD2 */
178 0U, /* 8: TE1 */
179 16U /* 9: TE2 */
180 };
181
182 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
183 {
184 0U, /* 0: TA1 */
185 1U, /* 1: TA2 */
186 0U, /* 2: TB1 */
187 1U, /* 3: TB2 */
188 0U, /* 4: TC1 */
189 1U, /* 5: TC2 */
190 0U, /* 6: TD1 */
191 1U, /* 7: TD2 */
192 0U, /* 8: TE1 */
193 1U /* 9: TE2 */
194 };
195
196 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
197 {
198 0U, /* LL_HRTIM_FAULT_1 */
199 8U, /* LL_HRTIM_FAULT_2 */
200 16U, /* LL_HRTIM_FAULT_3 */
201 24U, /* LL_HRTIM_FAULT_4 */
202 0U /* LL_HRTIM_FAULT_5 */
203 };
204
205 /**
206 * @}
207 */
208
209
210 /* Private constants ---------------------------------------------------------*/
211 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
212 * @{
213 */
214 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
215 HRTIM_CR1_TAUDIS |\
216 HRTIM_CR1_TBUDIS |\
217 HRTIM_CR1_TCUDIS |\
218 HRTIM_CR1_TDUDIS |\
219 HRTIM_CR1_TEUDIS))
220
221 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
222 HRTIM_CR2_TASWU |\
223 HRTIM_CR2_TBSWU |\
224 HRTIM_CR2_TCSWU |\
225 HRTIM_CR2_TDSWU |\
226 HRTIM_CR2_TESWU))
227
228 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
229 HRTIM_CR2_TARST |\
230 HRTIM_CR2_TBRST |\
231 HRTIM_CR2_TCRST |\
232 HRTIM_CR2_TDRST |\
233 HRTIM_CR2_TERST))
234
235 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
236 HRTIM_OENR_TA2OEN |\
237 HRTIM_OENR_TB1OEN |\
238 HRTIM_OENR_TB2OEN |\
239 HRTIM_OENR_TC1OEN |\
240 HRTIM_OENR_TC2OEN |\
241 HRTIM_OENR_TD1OEN |\
242 HRTIM_OENR_TD2OEN |\
243 HRTIM_OENR_TE1OEN |\
244 HRTIM_OENR_TE2OEN))
245
246 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
247 HRTIM_ODISR_TA2ODIS |\
248 HRTIM_ODISR_TB1ODIS |\
249 HRTIM_ODISR_TB2ODIS |\
250 HRTIM_ODISR_TC1ODIS |\
251 HRTIM_ODISR_TC2ODIS |\
252 HRTIM_ODISR_TD1ODIS |\
253 HRTIM_ODISR_TD2ODIS |\
254 HRTIM_ODISR_TE1ODIS |\
255 HRTIM_ODISR_TE2ODIS))
256
257 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
258 HRTIM_OUTR_IDLM1 |\
259 HRTIM_OUTR_IDLES1 |\
260 HRTIM_OUTR_FAULT1 |\
261 HRTIM_OUTR_CHP1 |\
262 HRTIM_OUTR_DIDL1))
263
264 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
265 HRTIM_EECR1_EE1POL |\
266 HRTIM_EECR1_EE1SNS |\
267 HRTIM_EECR1_EE1FAST))
268
269 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
270 HRTIM_FLTINR1_FLT1SRC))
271
272 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
273 HRTIM_BMCR_BMCLK |\
274 HRTIM_BMCR_BMOM))
275
276 /**
277 * @}
278 */
279
280
281 /* Private macros ------------------------------------------------------------*/
282 /* Exported types ------------------------------------------------------------*/
283 /* Exported constants --------------------------------------------------------*/
284 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
285 * @{
286 */
287
288 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
289 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
290 * @{
291 */
292 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
293 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
294 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
295 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
296 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
297 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
298 #define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
299 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
300
301 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
302 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
303 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
304 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
305 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
306 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
307 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
308
309 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
310 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
311 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
312 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
313 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
314 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
315 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
316 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
317 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
318 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
319 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
320 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
321 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
322 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
323 /**
324 * @}
325 */
326
327 /** @defgroup HRTIM_LL_EC_IT IT Defines
328 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
329 * @{
330 */
331 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
332 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
333 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
334 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
335 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
336 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
337 #define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
338 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
339
340 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
341 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
342 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
343 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
344 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
345 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
346 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
347
348 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
349 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
350 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
351 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
352 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
353 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
354 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
355 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
356 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
357 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
358 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
359 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
360 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
361 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
362 /**
363 * @}
364 */
365
366 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
367 * @{
368 * @brief Constants defining defining the synchronization input source.
369 */
370 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
371 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
372 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
373 /**
374 * @}
375 */
376
377 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
378 * @{
379 * @brief Constants defining the source and event to be sent on the synchronization output.
380 */
381 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
382 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
383 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
384 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
385 /**
386 * @}
387 */
388
389 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
390 * @{
391 * @brief Constants defining the routing and conditioning of the synchronization output event.
392 */
393 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
394 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
395 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
396 /**
397 * @}
398 */
399
400 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
401 * @{
402 * @brief Constants identifying a timing unit.
403 */
404 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
405 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
406 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
407 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
408 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
409 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
410 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
411 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TACEN |\
412 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
413 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
414 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
415
416 /**
417 * @}
418 */
419
420 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
421 * @{
422 * @brief Constants identifying an HRTIM output.
423 */
424 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
425 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
426 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
427 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
428 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
429 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
430 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
431 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
432 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
433 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
434 /**
435 * @}
436 */
437
438 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
439 * @{
440 * @brief Constants identifying a compare unit.
441 */
442 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
443 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
444 /**
445 * @}
446 */
447
448 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
449 * @{
450 * @brief Constants identifying a capture unit.
451 */
452 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
453 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
454 /**
455 * @}
456 */
457
458 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
459 * @{
460 * @brief Constants identifying a fault channel.
461 */
462 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
463 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
464 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
465 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
466 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
467 /**
468 * @}
469 */
470
471 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
472 * @{
473 * @brief Constants identifying an external event channel.
474 */
475 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
476 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
477 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
478 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
479 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
480 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
481 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
482 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
483 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
484 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
485 /**
486 * @}
487 */
488
489 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
490 * @{
491 * @brief Constants defining the state of an HRTIM output.
492 */
493 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
494 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
495 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
496 /**
497 * @}
498 */
499
500 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
501 * @{
502 * @brief Constants identifying an ADC trigger.
503 */
504 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
505 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
506 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
507 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
508 /**
509 * @}
510 */
511
512 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
513 * @{
514 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
515 */
516 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
517 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
518 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
519 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
520 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
521 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
522 /**
523 * @}
524 */
525
526 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
527 * @{
528 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
529 */
530 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
531 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
532 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
533 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
534 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
535 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
536 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
537 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
538 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
539 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
540 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
541 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
542 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
543 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
544 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
545 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
546 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
547 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
548 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
549 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
550 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
551 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
552 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
553 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
554 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
555 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
556 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
557 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
558 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
559 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
560 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
561 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
562 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
563 /**
564 * @}
565 */
566
567 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
568 * @{
569 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
570 */
571 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
572 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
573 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
574 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
575 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
576 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
577 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
578 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
579 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
580 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
581 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
582 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
583 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
584 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
585 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
586 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
587 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
588 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
589 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
590 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
591 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
592 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
593 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
594 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
595 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
596 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
597 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
598 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
599 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
600 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
601 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
602 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
603 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
604 /**
605 * @}
606 */
607
608 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
609 * @{
610 * @brief Constants defining the DLL calibration mode.
611 */
612 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is performed only once */
613 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
614 /**
615 * @}
616 */
617
618 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
619 * @{
620 * @brief Constants defining the DLL calibration periods (in micro seconds).
621 */
622 #define LL_HRTIM_DLLCALIBRATION_RATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.300 ms) */
623 #define LL_HRTIM_DLLCALIBRATION_RATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.910 ms) */
624 #define LL_HRTIM_DLLCALIBRATION_RATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.114 ms) */
625 #define LL_HRTIM_DLLCALIBRATION_RATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.014 ms) */
626 /**
627 * @}
628 */
629
630 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
631 * @{
632 * @brief Constants defining timer high-resolution clock prescaler ratio.
633 */
634 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
635 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
636 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
637 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
638 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
639 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
640 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
641 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
642 /**
643 * @}
644 */
645
646 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
647 * @{
648 * @brief Constants defining timer counter operating mode.
649 */
650 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
651 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
652 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
653 /**
654 * @}
655 */
656
657 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
658 * @{
659 * @brief Constants defining on which output the DAC synchronization event is sent.
660 */
661 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
662 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
663 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
664 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
665 /**
666 * @}
667 */
668
669 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
670 * @{
671 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
672 */
673 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
674 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
675 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
676 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
677 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
678 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
679 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
680 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
681 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
682 /**
683 * @}
684 */
685
686 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
687 * @{
688 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
689 */
690 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
691 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
692 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
693 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
694 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
695 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
696 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
697 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
698 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
699 /**
700 * @}
701 */
702
703 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
704 * @{
705 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
706 */
707 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
708 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
709 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
710 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
711 /**
712 * @}
713 */
714
715 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
716 * @{
717 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
718 */
719 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
720 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
721 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
722 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
723 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
724 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
725 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
726 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
727 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
728 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
729 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
730 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
731 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
732 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
733 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
734 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
735 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
736 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
737 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
738 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
739 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
740 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
741 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
742 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
743 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
744 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
745 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
746 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
747 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
748 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
749 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
750 /**
751 * @}
752 */
753
754 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
755 * @{
756 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
757 */
758 #define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
759 #define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
760 #define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
761 #define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
762 #define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
763 #define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
764 #define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
765 #define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
766 #define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
767 #define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
768 #define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
769 #define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
770 #define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */
771 #define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */
772 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */
773 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */
774 #define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */
775 #define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */
776 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */
777 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */
778 #define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */
779 #define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */
780 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */
781 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */
782 #define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */
783 #define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */
784 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */
785 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */
786 #define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */
787 #define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */
788 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */
789 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */
790 /**
791 * @}
792 */
793
794 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
795 * @{
796 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
797 */
798 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
799 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
800 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
801 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
802 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
803 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
804 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
805 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
806
807 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
808 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
809 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
810 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
811 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
812 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
813 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
814 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
815 /**
816 * @}
817 */
818
819 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
820 * @{
821 * @brief Constants defining how the timer behaves during a burst mode operation.
822 */
823 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
824 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
825 /**
826 * @}
827 */
828
829 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
830 * @{
831 * @brief Constants defining the registers that can be written during a burst DMA operation.
832 */
833 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
834 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
835 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
836 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
837 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
838 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
839 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
840 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
841 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
842 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
843 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
844 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
845 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
846 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
847 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
848 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
849 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
850 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
851 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
852 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
853 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
854 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
855 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
856 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
857 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
858 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
859 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
860 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
861 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
862 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
863 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
864 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
865 /**
866 * @}
867 */
868
869 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
870 * @{
871 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
872 */
873 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
874 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
875 /**
876 * @}
877 */
878
879 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
880 * @{
881 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
882 */
883 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
884 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
885 /**
886 * @}
887 */
888
889 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
890 * @{
891 * @brief Constants defining the event filtering applied to external events by a timer.
892 */
893 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
894 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
895 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
896 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
897 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
898 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
899 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
900 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
901 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
902 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
903 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
904 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
905 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
906 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
907 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
908 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
909 /**
910 * @}
911 */
912
913 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
914 * @{
915 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
916 */
917 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
918 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
919 /**
920 * @}
921 */
922
923 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
924 * @{
925 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
926 */
927 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
928 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
929 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
930 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
931 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
932 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
933 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
934 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
935 /**
936 * @}
937 */
938
939 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
940 * @{
941 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
942 */
943 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
944 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
945 /**
946 * @}
947 */
948
949 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
950 * @{
951 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
952 */
953 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
954 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
955 /**
956 * @}
957 */
958
959 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
960 * @{
961 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
962 */
963 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
964 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
965 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
966 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
967 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
968 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
969 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
970 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
971 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
972 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
973 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
974 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
975 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
976 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
977 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
978 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
979 /**
980 * @}
981 */
982
983 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
984 * @{
985 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
986 */
987 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
988 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
989 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
990 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
991 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
992 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
993 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
994 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
995 /**
996 * @}
997 */
998
999 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
1000 * @{
1001 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
1002 */
1003 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
1004 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
1005 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
1006 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1007 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
1008 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1009 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1010 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1011 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
1012 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1013 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1014 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1015 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1016 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1017 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1018 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT
1024 * @{
1025 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1026 */
1027 #define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */
1028 #define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
1029 #define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
1030 #define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
1031 #define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
1032 #define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
1033 #define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
1034 #define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
1035 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
1036 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
1037 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
1038 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
1039 #define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */
1040 #define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */
1041 #define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */
1042 #define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */
1043 #define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */
1044 #define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */
1045 #define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */
1046 #define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */
1047 #define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */
1048 #define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
1049 #define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
1050 #define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
1051 #define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
1052 #define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
1053 #define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
1054 #define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
1055 #define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
1056 #define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
1057 #define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
1058 #define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1064 * @{
1065 * @brief Constants defining the polarity of a timer output.
1066 */
1067 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
1068 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1074 * @{
1075 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1076 */
1077 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1078 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1079 /**
1080 * @}
1081 */
1082
1083 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1084 * @{
1085 * @brief Constants defining the half mode of an HRTIM Timer instance.
1086 */
1087 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
1088 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
1089 /**
1090 * @}
1091 */
1092
1093 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1094 * @{
1095 * @brief Constants defining the output level when output is in IDLE state
1096 */
1097 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1098 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1104 * @{
1105 * @brief Constants defining the output level when output is in FAULT state.
1106 */
1107 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1108 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1109 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1110 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1111 /**
1112 * @}
1113 */
1114
1115 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1116 * @{
1117 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1118 */
1119 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
1120 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1121 /**
1122 * @}
1123 */
1124
1125 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1126 * @{
1127 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1128 during a programmable period before the output takes its idle state.
1129 */
1130 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1131 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1132 /**
1133 * @}
1134 */
1135 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1136 * @{
1137 * @brief Constants defining the level of a timer output.
1138 */
1139 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1140 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1141 /**
1142 * @}
1143 */
1144
1145 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1146 * @{
1147 * @brief Constants defining available sources associated to external events.
1148 */
1149 #define LL_HRTIM_EE_SRC_1 0x00000000U /*!< External event source 1 (EExSrc1)*/
1150 #define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */
1151 #define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */
1152 #define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */
1153 /**
1154 * @}
1155 */
1156 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1157 * @{
1158 * @brief Constants defining the polarity of an external event.
1159 */
1160 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
1161 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1167 * @{
1168 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1169 */
1170 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
1171 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1172 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1173 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1174 /**
1175 * @}
1176 */
1177
1178 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1179 * @{
1180 * @brief Constants defining whether or not an external event is programmed in fast mode.
1181 */
1182 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1183 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1189 * @{
1190 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1191 */
1192 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
1193 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
1194 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
1195 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1196 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
1197 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1198 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1199 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1200 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
1201 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1202 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1203 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1204 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1205 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1206 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1207 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1208 /**
1209 * @}
1210 */
1211
1212 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1213 * @{
1214 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1215 */
1216 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
1217 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
1218 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
1219 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1225 * @{
1226 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1227 */
1228 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
1229 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1230 /**
1231 * @}
1232 */
1233
1234 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1235 * @{
1236 * @brief Constants defining the polarity of a fault event.
1237 */
1238 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
1239 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1245 * @{
1246 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1247 */
1248 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
1249 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1250 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1251 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1252 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1253 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1254 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1255 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1256 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1257 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1258 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1259 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1260 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1261 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1262 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1263 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1264 /**
1265 * @}
1266 */
1267
1268 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1269 * @{
1270 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1271 */
1272 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
1273 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
1274 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
1275 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1281 * @{
1282 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1283 */
1284 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1285 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1286 /**
1287 * @}
1288 */
1289
1290 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1291 * @{
1292 * @brief Constants defining the clock source for the burst mode counter.
1293 */
1294 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1295 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1296 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1297 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1298 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1299 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1300 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1301 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1302 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1303 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1304 /**
1305 * @}
1306 */
1307
1308 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1309 * @{
1310 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1311 */
1312 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
1313 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
1314 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
1315 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1316 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
1317 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1318 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1319 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1320 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
1321 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1322 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1323 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1324 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1325 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1326 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1327 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1328 /**
1329 * @}
1330 */
1331
1332 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1333 * @{
1334 * @brief Constants defining the events that can be used to trig the burst mode operation.
1335 */
1336 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
1337 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1338 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1339 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1340 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1341 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1342 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1343 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1344 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1345 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1346 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1347 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1348 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1349 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1350 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1351 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1352 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1353 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1354 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
1355 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1356 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1357 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
1358 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1359 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
1360 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1361 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1362 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1363 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1364 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1365 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1366 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1367 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1368 /**
1369 * @}
1370 */
1371
1372 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1373 * @{
1374 * @brief Constants defining the operating state of the burst mode controller.
1375 */
1376 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
1377 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
1378 /**
1379 * @}
1380 */
1381
1382 /**
1383 * @}
1384 */
1385
1386 /* Exported macro ------------------------------------------------------------*/
1387 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
1388 * @{
1389 */
1390
1391 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
1392 * @{
1393 */
1394
1395 /**
1396 * @brief Write a value in HRTIM register
1397 * @param __INSTANCE__ HRTIM Instance
1398 * @param __REG__ Register to be written
1399 * @param __VALUE__ Value to be written in the register
1400 * @retval None
1401 */
1402 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1403
1404 /**
1405 * @brief Read a value in HRTIM register
1406 * @param __INSTANCE__ HRTIM Instance
1407 * @param __REG__ Register to be read
1408 * @retval Register value
1409 */
1410 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1411 /**
1412 * @}
1413 */
1414
1415 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
1416 * @{
1417 */
1418 /**
1419 * @brief HELPER macro returning the output state from output enable/disable status
1420 * @param __OUTPUT_STATUS_EN__ output enable status
1421 * @param __OUTPUT_STATUS_DIS__ output Disable status
1422 * @retval Returned value can be one of the following values:
1423 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
1424 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
1425 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
1426 */
1427 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
1428 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
1429 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
1430 /**
1431 * @}
1432 */
1433
1434 /**
1435 * @}
1436 */
1437
1438 /* Exported functions --------------------------------------------------------*/
1439 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
1440 * @{
1441 */
1442 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
1443 * @{
1444 */
1445
1446 /**
1447 * @brief Select the HRTIM synchronization input source.
1448 * @note This function must not be called when the concerned timer(s) is (are) enabled .
1449 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1450 * @param HRTIMx High Resolution Timer instance
1451 * @param SyncInSrc This parameter can be one of the following values:
1452 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1453 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1454 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1455 * @retval None
1456 */
LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncInSrc)1457 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
1458 {
1459 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
1460 }
1461
1462 /**
1463 * @brief Get actual HRTIM synchronization input source.
1464 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1465 * @param HRTIMx High Resolution Timer instance
1466 * @retval SyncInSrc Returned value can be one of the following values:
1467 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1468 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1469 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1470 */
LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef * HRTIMx)1471 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
1472 {
1473 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
1474 }
1475
1476 /**
1477 * @brief Configure the HRTIM synchronization output.
1478 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
1479 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
1480 * @param HRTIMx High Resolution Timer instance
1481 * @param Config This parameter can be one of the following values:
1482 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1483 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1484 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1485 * @param Src This parameter can be one of the following values:
1486 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1487 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1488 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1489 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1490 * @retval None
1491 */
LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef * HRTIMx,uint32_t Config,uint32_t Src)1492 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
1493 {
1494 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
1495 }
1496
1497 /**
1498 * @brief Set the routing and conditioning of the synchronization output event.
1499 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
1500 * @note This function can be called only when the master timer is enabled.
1501 * @param HRTIMx High Resolution Timer instance
1502 * @param SyncOutConfig This parameter can be one of the following values:
1503 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1504 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1505 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1506 * @retval None
1507 */
LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutConfig)1508 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
1509 {
1510 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
1511 }
1512
1513 /**
1514 * @brief Get actual routing and conditioning of the synchronization output event.
1515 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
1516 * @param HRTIMx High Resolution Timer instance
1517 * @retval SyncOutConfig Returned value can be one of the following values:
1518 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1519 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1520 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1521 */
LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef * HRTIMx)1522 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
1523 {
1524 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
1525 }
1526
1527 /**
1528 * @brief Set the source and event to be sent on the HRTIM synchronization output.
1529 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
1530 * @param HRTIMx High Resolution Timer instance
1531 * @param SyncOutSrc This parameter can be one of the following values:
1532 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1533 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1534 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1535 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1536 * @retval None
1537 */
LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutSrc)1538 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
1539 {
1540 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
1541 }
1542
1543 /**
1544 * @brief Get actual source and event sent on the HRTIM synchronization output.
1545 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
1546 * @param HRTIMx High Resolution Timer instance
1547 * @retval SyncOutSrc Returned value can be one of the following values:
1548 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1549 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1550 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1551 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1552 */
LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef * HRTIMx)1553 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
1554 {
1555 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
1556 }
1557
1558 /**
1559 * @brief Disable (temporarily) update event generation.
1560 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
1561 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
1562 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
1563 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
1564 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
1565 * CR1 TEUDIS LL_HRTIM_SuspendUpdate
1566 * @note Allow to temporarily disable the transfer from preload to active
1567 * registers, whatever the selected update event. This allows to modify
1568 * several registers in multiple timers.
1569 * @param HRTIMx High Resolution Timer instance
1570 * @param Timers This parameter can be a combination of the following values:
1571 * @arg @ref LL_HRTIM_TIMER_MASTER
1572 * @arg @ref LL_HRTIM_TIMER_A
1573 * @arg @ref LL_HRTIM_TIMER_B
1574 * @arg @ref LL_HRTIM_TIMER_C
1575 * @arg @ref LL_HRTIM_TIMER_D
1576 * @arg @ref LL_HRTIM_TIMER_E
1577 * @retval None
1578 */
LL_HRTIM_SuspendUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1579 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1580 {
1581 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
1582 }
1583
1584 /**
1585 * @brief Enable update event generation.
1586 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
1587 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
1588 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
1589 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
1590 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
1591 * CR1 TEUDIS LL_HRTIM_ResumeUpdate
1592 * @note The regular update event takes place.
1593 * @param HRTIMx High Resolution Timer instance
1594 * @param Timers This parameter can be a combination of the following values:
1595 * @arg @ref LL_HRTIM_TIMER_MASTER
1596 * @arg @ref LL_HRTIM_TIMER_A
1597 * @arg @ref LL_HRTIM_TIMER_B
1598 * @arg @ref LL_HRTIM_TIMER_C
1599 * @arg @ref LL_HRTIM_TIMER_D
1600 * @arg @ref LL_HRTIM_TIMER_E
1601 * @retval None
1602 */
LL_HRTIM_ResumeUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1603 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1604 {
1605 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
1606 }
1607
1608 /**
1609 * @brief Force an immediate transfer from the preload to the active register .
1610 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
1611 * CR2 TASWU LL_HRTIM_ForceUpdate\n
1612 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
1613 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
1614 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
1615 * CR2 TESWU LL_HRTIM_ForceUpdate
1616 * @note Any pending update request is cancelled.
1617 * @param HRTIMx High Resolution Timer instance
1618 * @param Timers This parameter can be a combination of the following values:
1619 * @arg @ref LL_HRTIM_TIMER_MASTER
1620 * @arg @ref LL_HRTIM_TIMER_A
1621 * @arg @ref LL_HRTIM_TIMER_B
1622 * @arg @ref LL_HRTIM_TIMER_C
1623 * @arg @ref LL_HRTIM_TIMER_D
1624 * @arg @ref LL_HRTIM_TIMER_E
1625 * @retval None
1626 */
LL_HRTIM_ForceUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1627 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1628 {
1629 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
1630 }
1631
1632 /**
1633 * @brief Reset the HRTIM timer(s) counter.
1634 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
1635 * CR2 TARST LL_HRTIM_CounterReset\n
1636 * CR2 TBRST LL_HRTIM_CounterReset\n
1637 * CR2 TCRST LL_HRTIM_CounterReset\n
1638 * CR2 TDRST LL_HRTIM_CounterReset\n
1639 * CR2 TERST LL_HRTIM_CounterReset
1640 * @param HRTIMx High Resolution Timer instance
1641 * @param Timers This parameter can be a combination of the following values:
1642 * @arg @ref LL_HRTIM_TIMER_MASTER
1643 * @arg @ref LL_HRTIM_TIMER_A
1644 * @arg @ref LL_HRTIM_TIMER_B
1645 * @arg @ref LL_HRTIM_TIMER_C
1646 * @arg @ref LL_HRTIM_TIMER_D
1647 * @arg @ref LL_HRTIM_TIMER_E
1648 * @retval None
1649 */
LL_HRTIM_CounterReset(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1650 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1651 {
1652 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
1653 }
1654
1655 /**
1656 * @brief Enable the HRTIM timer(s) output(s) .
1657 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
1658 * OENR TA2OEN LL_HRTIM_EnableOutput\n
1659 * OENR TB1OEN LL_HRTIM_EnableOutput\n
1660 * OENR TB2OEN LL_HRTIM_EnableOutput\n
1661 * OENR TC1OEN LL_HRTIM_EnableOutput\n
1662 * OENR TC2OEN LL_HRTIM_EnableOutput\n
1663 * OENR TD1OEN LL_HRTIM_EnableOutput\n
1664 * OENR TD2OEN LL_HRTIM_EnableOutput\n
1665 * OENR TE1OEN LL_HRTIM_EnableOutput\n
1666 * OENR TE2OEN LL_HRTIM_EnableOutput
1667 * @param HRTIMx High Resolution Timer instance
1668 * @param Outputs This parameter can be a combination of the following values:
1669 * @arg @ref LL_HRTIM_OUTPUT_TA1
1670 * @arg @ref LL_HRTIM_OUTPUT_TA2
1671 * @arg @ref LL_HRTIM_OUTPUT_TB1
1672 * @arg @ref LL_HRTIM_OUTPUT_TB2
1673 * @arg @ref LL_HRTIM_OUTPUT_TC1
1674 * @arg @ref LL_HRTIM_OUTPUT_TC2
1675 * @arg @ref LL_HRTIM_OUTPUT_TD1
1676 * @arg @ref LL_HRTIM_OUTPUT_TD2
1677 * @arg @ref LL_HRTIM_OUTPUT_TE1
1678 * @arg @ref LL_HRTIM_OUTPUT_TE2
1679 * @retval None
1680 */
LL_HRTIM_EnableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)1681 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
1682 {
1683 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
1684 }
1685
1686 /**
1687 * @brief Disable the HRTIM timer(s) output(s) .
1688 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
1689 * OENR TA2OEN LL_HRTIM_DisableOutput\n
1690 * OENR TB1OEN LL_HRTIM_DisableOutput\n
1691 * OENR TB2OEN LL_HRTIM_DisableOutput\n
1692 * OENR TC1OEN LL_HRTIM_DisableOutput\n
1693 * OENR TC2OEN LL_HRTIM_DisableOutput\n
1694 * OENR TD1OEN LL_HRTIM_DisableOutput\n
1695 * OENR TD2OEN LL_HRTIM_DisableOutput\n
1696 * OENR TE1OEN LL_HRTIM_DisableOutput\n
1697 * OENR TE2OEN LL_HRTIM_DisableOutput
1698 * @param HRTIMx High Resolution Timer instance
1699 * @param Outputs This parameter can be a combination of the following values:
1700 * @arg @ref LL_HRTIM_OUTPUT_TA1
1701 * @arg @ref LL_HRTIM_OUTPUT_TA2
1702 * @arg @ref LL_HRTIM_OUTPUT_TB1
1703 * @arg @ref LL_HRTIM_OUTPUT_TB2
1704 * @arg @ref LL_HRTIM_OUTPUT_TC1
1705 * @arg @ref LL_HRTIM_OUTPUT_TC2
1706 * @arg @ref LL_HRTIM_OUTPUT_TD1
1707 * @arg @ref LL_HRTIM_OUTPUT_TD2
1708 * @arg @ref LL_HRTIM_OUTPUT_TE1
1709 * @arg @ref LL_HRTIM_OUTPUT_TE2
1710 * @retval None
1711 */
LL_HRTIM_DisableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)1712 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
1713 {
1714 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
1715 }
1716
1717 /**
1718 * @brief Indicates whether the HRTIM timer output is enabled.
1719 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
1720 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
1721 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
1722 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
1723 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
1724 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
1725 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
1726 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
1727 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
1728 * OENR TE2OEN LL_HRTIM_IsEnabledOutput
1729 * @param HRTIMx High Resolution Timer instance
1730 * @param Output This parameter can be one of the following values:
1731 * @arg @ref LL_HRTIM_OUTPUT_TA1
1732 * @arg @ref LL_HRTIM_OUTPUT_TA2
1733 * @arg @ref LL_HRTIM_OUTPUT_TB1
1734 * @arg @ref LL_HRTIM_OUTPUT_TB2
1735 * @arg @ref LL_HRTIM_OUTPUT_TC1
1736 * @arg @ref LL_HRTIM_OUTPUT_TC2
1737 * @arg @ref LL_HRTIM_OUTPUT_TD1
1738 * @arg @ref LL_HRTIM_OUTPUT_TD2
1739 * @arg @ref LL_HRTIM_OUTPUT_TE1
1740 * @arg @ref LL_HRTIM_OUTPUT_TE2
1741 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
1742 */
LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)1743 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
1744 {
1745 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Indicates whether the HRTIM timer output is disabled.
1750 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
1751 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
1752 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
1753 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
1754 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
1755 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
1756 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
1757 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
1758 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
1759 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
1760 * @param HRTIMx High Resolution Timer instance
1761 * @param Output This parameter can be one of the following values:
1762 * @arg @ref LL_HRTIM_OUTPUT_TA1
1763 * @arg @ref LL_HRTIM_OUTPUT_TA2
1764 * @arg @ref LL_HRTIM_OUTPUT_TB1
1765 * @arg @ref LL_HRTIM_OUTPUT_TB2
1766 * @arg @ref LL_HRTIM_OUTPUT_TC1
1767 * @arg @ref LL_HRTIM_OUTPUT_TC2
1768 * @arg @ref LL_HRTIM_OUTPUT_TD1
1769 * @arg @ref LL_HRTIM_OUTPUT_TD2
1770 * @arg @ref LL_HRTIM_OUTPUT_TE1
1771 * @arg @ref LL_HRTIM_OUTPUT_TE2
1772 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
1773 */
LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)1774 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
1775 {
1776 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
1777 }
1778
1779 /**
1780 * @brief Configure an ADC trigger.
1781 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
1782 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
1783 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
1784 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
1785 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
1786 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
1787 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
1788 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
1789 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
1790 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
1791 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
1792 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
1793 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
1794 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
1795 * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
1796 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
1797 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
1798 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
1799 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
1800 * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
1801 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
1802 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
1803 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
1804 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
1805 * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
1806 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
1807 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
1808 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
1809 * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
1810 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
1811 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
1812 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
1813 * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
1814 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
1815 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
1816 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
1817 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
1818 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
1819 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
1820 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
1821 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
1822 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
1823 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
1824 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
1825 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
1826 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
1827 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
1828 * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
1829 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
1830 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
1831 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
1832 * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
1833 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
1834 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
1835 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
1836 * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
1837 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
1838 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
1839 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
1840 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
1841 * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
1842 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
1843 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
1844 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
1845 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
1846 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
1847 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
1848 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
1849 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
1850 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
1851 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
1852 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
1853 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
1854 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
1855 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
1856 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
1857 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
1858 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
1859 * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
1860 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
1861 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
1862 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
1863 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
1864 * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
1865 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
1866 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
1867 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
1868 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
1869 * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
1870 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
1871 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
1872 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
1873 * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
1874 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
1875 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
1876 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
1877 * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
1878 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
1879 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
1880 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
1881 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
1882 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
1883 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
1884 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
1885 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
1886 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
1887 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
1888 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
1889 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
1890 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
1891 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
1892 * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
1893 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
1894 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
1895 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
1896 * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
1897 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
1898 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
1899 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
1900 * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
1901 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
1902 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
1903 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
1904 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
1905 * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
1906 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
1907 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
1908 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
1909 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
1910 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
1911 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
1912 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
1913 * @param HRTIMx High Resolution Timer instance
1914 * @param ADCTrig This parameter can be one of the following values:
1915 * @arg @ref LL_HRTIM_ADCTRIG_1
1916 * @arg @ref LL_HRTIM_ADCTRIG_2
1917 * @arg @ref LL_HRTIM_ADCTRIG_3
1918 * @arg @ref LL_HRTIM_ADCTRIG_4
1919 * @param Update This parameter can be one of the following values:
1920 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
1921 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
1922 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
1923 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
1924 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
1925 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
1926 * @param Src This parameter can be a combination of the following values:
1927 *
1928 * For ADC trigger 1 and ADC trigger 3:
1929 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
1930 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
1931 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
1932 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
1933 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
1934 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
1935 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
1936 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
1937 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
1938 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
1939 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
1940 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
1941 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
1942 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
1943 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
1944 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
1945 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
1946 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
1947 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
1948 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
1949 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
1950 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
1951 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
1952 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
1953 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
1954 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
1955 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
1956 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
1957 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
1958 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
1959 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
1960 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
1961 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
1962 *
1963 * For ADC trigger 2 and ADC trigger 4:
1964 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
1965 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
1966 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
1967 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
1968 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
1969 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
1970 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
1971 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
1972 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
1973 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
1974 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
1975 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
1976 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
1977 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
1978 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
1979 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
1980 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
1981 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
1982 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
1983 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
1984 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
1985 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
1986 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
1987 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
1988 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
1989 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
1990 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
1991 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
1992 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
1993 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
1994 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
1995 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
1996 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
1997 *
1998 * @retval None
1999 */
LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update,uint32_t Src)2000 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
2001 {
2002 uint32_t shift = ((3U * ADCTrig) & 0x1FU);
2003 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2004 REG_OFFSET_TAB_ADCxR[ADCTrig]));
2005 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
2006 WRITE_REG(*pReg, Src);
2007 }
2008
2009 /**
2010 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
2011 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
2012 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
2013 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
2014 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
2015 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
2016 * registers are not preloaded either: a write access will result in an
2017 * immediate update of the trigger source.
2018 * @param HRTIMx High Resolution Timer instance
2019 * @param ADCTrig This parameter can be one of the following values:
2020 * @arg @ref LL_HRTIM_ADCTRIG_1
2021 * @arg @ref LL_HRTIM_ADCTRIG_2
2022 * @arg @ref LL_HRTIM_ADCTRIG_3
2023 * @arg @ref LL_HRTIM_ADCTRIG_4
2024 * @param Update This parameter can be one of the following values:
2025 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2026 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2027 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2028 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2029 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2030 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2031 * @retval None
2032 */
LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update)2033 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2034 {
2035 uint32_t shift = ((3U * ADCTrig) & 0x1FU);
2036 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
2037 }
2038
2039 /**
2040 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2041 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2042 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2043 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2044 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2045 * @param HRTIMx High Resolution Timer instance
2046 * @param ADCTrig This parameter can be one of the following values:
2047 * @arg @ref LL_HRTIM_ADCTRIG_1
2048 * @arg @ref LL_HRTIM_ADCTRIG_2
2049 * @arg @ref LL_HRTIM_ADCTRIG_3
2050 * @arg @ref LL_HRTIM_ADCTRIG_4
2051 * @retval Update Returned value can be one of the following values:
2052 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2053 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2054 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2055 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2056 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2057 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2058 */
LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2059 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2060 {
2061 const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
2062 return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
2063 }
2064
2065 /**
2066 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2067 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2068 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2069 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2070 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2071 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2072 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2073 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2074 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2075 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2076 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2077 * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
2078 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2079 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2080 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2081 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2082 * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
2083 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2084 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2085 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2086 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2087 * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
2088 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2089 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2090 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2091 * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
2092 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2093 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2094 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2095 * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
2096 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2097 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2098 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2099 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2100 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2101 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2102 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2103 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2104 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2105 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2106 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2107 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2108 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2109 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2110 * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
2111 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2112 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2113 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2114 * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
2115 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2116 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2117 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2118 * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
2119 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2120 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2121 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2122 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2123 * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
2124 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2125 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2126 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2127 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2128 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2129 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2130 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2131 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
2132 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
2133 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
2134 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
2135 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
2136 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
2137 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
2138 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
2139 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
2140 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
2141 * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
2142 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
2143 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
2144 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
2145 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
2146 * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
2147 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
2148 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
2149 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
2150 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
2151 * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
2152 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
2153 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
2154 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
2155 * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
2156 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
2157 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
2158 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
2159 * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
2160 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
2161 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
2162 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
2163 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
2164 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
2165 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
2166 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
2167 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
2168 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
2169 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
2170 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
2171 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
2172 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
2173 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
2174 * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
2175 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
2176 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
2177 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
2178 * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
2179 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
2180 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
2181 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
2182 * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
2183 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
2184 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
2185 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
2186 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
2187 * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
2188 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
2189 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
2190 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
2191 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
2192 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
2193 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
2194 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
2195 * @param HRTIMx High Resolution Timer instance
2196 * @param ADCTrig This parameter can be one of the following values:
2197 * @arg @ref LL_HRTIM_ADCTRIG_1
2198 * @arg @ref LL_HRTIM_ADCTRIG_2
2199 * @arg @ref LL_HRTIM_ADCTRIG_3
2200 * @arg @ref LL_HRTIM_ADCTRIG_4
2201 * @param Src
2202 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2203 * combination of the following values:
2204 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2205 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2206 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2207 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2208 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2209 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2210 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2211 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2212 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2213 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2214 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2215 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2216 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2217 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2218 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2219 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2220 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2221 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2222 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2223 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2224 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2225 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2226 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2227 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2228 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2229 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2230 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2231 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2232 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2233 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2234 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2235 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2236 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2237 *
2238 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2239 * combination of the following values:
2240 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2241 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2242 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2243 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2244 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2245 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2246 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2247 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2248 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2249 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2250 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2251 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2252 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2253 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2254 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2255 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2256 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2257 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2258 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2259 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2260 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2261 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2262 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2263 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2264 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2265 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2266 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2267 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2268 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2269 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2270 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2271 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2272 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2273 *
2274 * @retval None
2275 */
LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Src)2276 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
2277 {
2278 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2279 REG_OFFSET_TAB_ADCxR[ADCTrig]));
2280 WRITE_REG(*pReg, Src);
2281 }
2282
2283 /**
2284 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
2285 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
2286 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
2287 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
2288 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
2289 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
2290 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
2291 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
2292 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
2293 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
2294 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
2295 * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
2296 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
2297 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
2298 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
2299 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
2300 * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
2301 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
2302 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
2303 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
2304 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
2305 * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
2306 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
2307 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
2308 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
2309 * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
2310 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
2311 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
2312 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
2313 * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
2314 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
2315 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
2316 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
2317 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
2318 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
2319 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
2320 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
2321 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
2322 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
2323 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
2324 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
2325 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
2326 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
2327 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
2328 * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
2329 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
2330 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
2331 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
2332 * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
2333 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
2334 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
2335 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
2336 * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
2337 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
2338 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
2339 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
2340 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
2341 * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
2342 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
2343 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
2344 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
2345 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
2346 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
2347 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
2348 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
2349 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
2350 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
2351 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
2352 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
2353 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
2354 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
2355 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
2356 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
2357 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
2358 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
2359 * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
2360 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
2361 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
2362 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
2363 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
2364 * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
2365 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
2366 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
2367 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
2368 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
2369 * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
2370 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
2371 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
2372 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
2373 * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
2374 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
2375 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
2376 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
2377 * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
2378 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
2379 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
2380 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
2381 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
2382 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
2383 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
2384 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
2385 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
2386 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
2387 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
2388 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
2389 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
2390 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
2391 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
2392 * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
2393 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
2394 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
2395 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
2396 * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
2397 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
2398 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
2399 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
2400 * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
2401 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
2402 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
2403 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
2404 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
2405 * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
2406 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
2407 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
2408 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
2409 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
2410 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
2411 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
2412 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
2413 * @param HRTIMx High Resolution Timer instance
2414 * @param ADCTrig This parameter can be one of the following values:
2415 * @arg @ref LL_HRTIM_ADCTRIG_1
2416 * @arg @ref LL_HRTIM_ADCTRIG_2
2417 * @arg @ref LL_HRTIM_ADCTRIG_3
2418 * @arg @ref LL_HRTIM_ADCTRIG_4
2419 * @retval Src This parameter can be a combination of the following values:
2420 *
2421 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2422 * combination of the following values:
2423 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2424 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2425 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2426 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2427 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2428 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2429 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2430 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2431 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2432 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2433 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2434 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2435 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2436 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2437 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2438 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2439 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2440 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2441 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2442 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2443 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2444 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2445 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2446 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2447 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2448 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2449 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2450 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2451 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2452 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2453 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2454 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2455 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2456 *
2457 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2458 * combination of the following values:
2459 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2460 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2461 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2462 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2463 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2464 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2465 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2466 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2467 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2468 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2469 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2470 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2471 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2472 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2473 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2474 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2475 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2476 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2477 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2478 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2479 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2480 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2481 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2482 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2483 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2484 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2485 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2486 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2487 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2488 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2489 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2490 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2491 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2492 */
LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2493 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2494 {
2495 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2496 REG_OFFSET_TAB_ADCxR[ADCTrig]));
2497 return (*pReg);
2498
2499 }
2500
2501
2502 /**
2503 * @brief Configure the DLL calibration mode.
2504 * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
2505 * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
2506 * @param HRTIMx High Resolution Timer instance
2507 * @param Mode This parameter can be one of the following values:
2508 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
2509 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
2510 * @param Period This parameter can be one of the following values:
2511 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_7300
2512 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_910
2513 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_114
2514 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_14
2515 * @retval None
2516 */
LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef * HRTIMx,uint32_t Mode,uint32_t Period)2517 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
2518 {
2519 MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
2520 }
2521
2522 /**
2523 * @brief Launch DLL calibration
2524 * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
2525 * @param HRTIMx High Resolution Timer instance
2526 * @retval None
2527 */
LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef * HRTIMx)2528 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
2529 {
2530 SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
2531 }
2532
2533 /**
2534 * @}
2535 */
2536
2537 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
2538 * @{
2539 */
2540
2541 /**
2542 * @brief Enable timer(s) counter.
2543 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
2544 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
2545 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
2546 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
2547 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
2548 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
2549 * @param HRTIMx High Resolution Timer instance
2550 * @param Timers This parameter can be a combination of the following values:
2551 * @arg @ref LL_HRTIM_TIMER_MASTER
2552 * @arg @ref LL_HRTIM_TIMER_A
2553 * @arg @ref LL_HRTIM_TIMER_B
2554 * @arg @ref LL_HRTIM_TIMER_C
2555 * @arg @ref LL_HRTIM_TIMER_D
2556 * @arg @ref LL_HRTIM_TIMER_E
2557 * @retval None
2558 */
LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2559 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2560 {
2561 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
2562 }
2563
2564 /**
2565 * @brief Disable timer(s) counter.
2566 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
2567 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
2568 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
2569 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
2570 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
2571 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
2572 * @param HRTIMx High Resolution Timer instance
2573 * @param Timers This parameter can be a combination of the following values:
2574 * @arg @ref LL_HRTIM_TIMER_MASTER
2575 * @arg @ref LL_HRTIM_TIMER_A
2576 * @arg @ref LL_HRTIM_TIMER_B
2577 * @arg @ref LL_HRTIM_TIMER_C
2578 * @arg @ref LL_HRTIM_TIMER_D
2579 * @arg @ref LL_HRTIM_TIMER_E
2580 * @retval None
2581 */
LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2582 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2583 {
2584 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
2585 }
2586
2587 /**
2588 * @brief Indicate whether the timer counter is enabled.
2589 * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
2590 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
2591 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
2592 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
2593 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
2594 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
2595 * @param HRTIMx High Resolution Timer instance
2596 * @param Timer This parameter can be one of the following values:
2597 * @arg @ref LL_HRTIM_TIMER_MASTER
2598 * @arg @ref LL_HRTIM_TIMER_A
2599 * @arg @ref LL_HRTIM_TIMER_B
2600 * @arg @ref LL_HRTIM_TIMER_C
2601 * @arg @ref LL_HRTIM_TIMER_D
2602 * @arg @ref LL_HRTIM_TIMER_E
2603 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
2604 */
LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2605 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2606 {
2607 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
2608 }
2609
2610 /**
2611 * @brief Set the timer clock prescaler ratio.
2612 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
2613 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
2614 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
2615 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
2616 * @param HRTIMx High Resolution Timer instance
2617 * @param Timer This parameter can be one of the following values:
2618 * @arg @ref LL_HRTIM_TIMER_MASTER
2619 * @arg @ref LL_HRTIM_TIMER_A
2620 * @arg @ref LL_HRTIM_TIMER_B
2621 * @arg @ref LL_HRTIM_TIMER_C
2622 * @arg @ref LL_HRTIM_TIMER_D
2623 * @arg @ref LL_HRTIM_TIMER_E
2624 * @param Prescaler This parameter can be one of the following values:
2625 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
2626 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
2627 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
2628 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
2629 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
2630 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2631 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2632 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2633 * @retval None
2634 */
LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)2635 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
2636 {
2637 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2638 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2639 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
2640 }
2641
2642 /**
2643 * @brief Get the timer clock prescaler ratio
2644 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
2645 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
2646 * @param HRTIMx High Resolution Timer instance
2647 * @param Timer This parameter can be one of the following values:
2648 * @arg @ref LL_HRTIM_TIMER_MASTER
2649 * @arg @ref LL_HRTIM_TIMER_A
2650 * @arg @ref LL_HRTIM_TIMER_B
2651 * @arg @ref LL_HRTIM_TIMER_C
2652 * @arg @ref LL_HRTIM_TIMER_D
2653 * @arg @ref LL_HRTIM_TIMER_E
2654 * @retval Prescaler Returned value can be one of the following values:
2655 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
2656 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
2657 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
2658 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
2659 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
2660 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2661 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2662 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2663 */
LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2664 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2665 {
2666 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2667 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2668 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
2669 }
2670
2671 /**
2672 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
2673 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
2674 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
2675 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
2676 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
2677 * @param HRTIMx High Resolution Timer instance
2678 * @param Timer This parameter can be one of the following values:
2679 * @arg @ref LL_HRTIM_TIMER_MASTER
2680 * @arg @ref LL_HRTIM_TIMER_A
2681 * @arg @ref LL_HRTIM_TIMER_B
2682 * @arg @ref LL_HRTIM_TIMER_C
2683 * @arg @ref LL_HRTIM_TIMER_D
2684 * @arg @ref LL_HRTIM_TIMER_E
2685 * @param Mode This parameter can be one of the following values:
2686 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2687 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2688 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2689 * @retval None
2690 */
LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)2691 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
2692 {
2693 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2694 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2695 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
2696 }
2697
2698 /**
2699 * @brief Get the counter operating mode mode
2700 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
2701 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
2702 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
2703 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
2704 * @param HRTIMx High Resolution Timer instance
2705 * @param Timer This parameter can be one of the following values:
2706 * @arg @ref LL_HRTIM_TIMER_MASTER
2707 * @arg @ref LL_HRTIM_TIMER_A
2708 * @arg @ref LL_HRTIM_TIMER_B
2709 * @arg @ref LL_HRTIM_TIMER_C
2710 * @arg @ref LL_HRTIM_TIMER_D
2711 * @arg @ref LL_HRTIM_TIMER_E
2712 * @retval Mode Returned value can be one of the following values:
2713 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2714 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2715 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2716 */
LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2717 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2718 {
2719 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2720 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2721 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
2722 }
2723
2724 /**
2725 * @brief Enable the half duty-cycle mode.
2726 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
2727 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
2728 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
2729 * active register is automatically updated with HRTIM_MPER/2
2730 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
2731 * @param HRTIMx High Resolution Timer instance
2732 * @param Timer This parameter can be one of the following values:
2733 * @arg @ref LL_HRTIM_TIMER_MASTER
2734 * @arg @ref LL_HRTIM_TIMER_A
2735 * @arg @ref LL_HRTIM_TIMER_B
2736 * @arg @ref LL_HRTIM_TIMER_C
2737 * @arg @ref LL_HRTIM_TIMER_D
2738 * @arg @ref LL_HRTIM_TIMER_E
2739 * @retval None
2740 */
LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2741 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2742 {
2743 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2744 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2745 SET_BIT(*pReg, HRTIM_MCR_HALF);
2746 }
2747
2748 /**
2749 * @brief Disable the half duty-cycle mode.
2750 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
2751 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
2752 * @param HRTIMx High Resolution Timer instance
2753 * @param Timer This parameter can be one of the following values:
2754 * @arg @ref LL_HRTIM_TIMER_MASTER
2755 * @arg @ref LL_HRTIM_TIMER_A
2756 * @arg @ref LL_HRTIM_TIMER_B
2757 * @arg @ref LL_HRTIM_TIMER_C
2758 * @arg @ref LL_HRTIM_TIMER_D
2759 * @arg @ref LL_HRTIM_TIMER_E
2760 * @retval None
2761 */
LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2762 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2763 {
2764 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2765 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2766 CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
2767 }
2768
2769 /**
2770 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
2771 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
2772 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
2773 * @param HRTIMx High Resolution Timer instance
2774 * @param Timer This parameter can be one of the following values:
2775 * @arg @ref LL_HRTIM_TIMER_MASTER
2776 * @arg @ref LL_HRTIM_TIMER_A
2777 * @arg @ref LL_HRTIM_TIMER_B
2778 * @arg @ref LL_HRTIM_TIMER_C
2779 * @arg @ref LL_HRTIM_TIMER_D
2780 * @arg @ref LL_HRTIM_TIMER_E
2781 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2782 */
LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2783 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2784 {
2785 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2786 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2787
2788 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
2789 }
2790 /**
2791 * @brief Enable the timer start when receiving a synchronization input event.
2792 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
2793 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
2794 * @param HRTIMx High Resolution Timer instance
2795 * @param Timer This parameter can be one of the following values:
2796 * @arg @ref LL_HRTIM_TIMER_MASTER
2797 * @arg @ref LL_HRTIM_TIMER_A
2798 * @arg @ref LL_HRTIM_TIMER_B
2799 * @arg @ref LL_HRTIM_TIMER_C
2800 * @arg @ref LL_HRTIM_TIMER_D
2801 * @arg @ref LL_HRTIM_TIMER_E
2802 * @retval None
2803 */
LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2804 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2805 {
2806 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2807 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2808 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
2809 }
2810
2811 /**
2812 * @brief Disable the timer start when receiving a synchronization input event.
2813 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
2814 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
2815 * @param HRTIMx High Resolution Timer instance
2816 * @param Timer This parameter can be one of the following values:
2817 * @arg @ref LL_HRTIM_TIMER_MASTER
2818 * @arg @ref LL_HRTIM_TIMER_A
2819 * @arg @ref LL_HRTIM_TIMER_B
2820 * @arg @ref LL_HRTIM_TIMER_C
2821 * @arg @ref LL_HRTIM_TIMER_D
2822 * @arg @ref LL_HRTIM_TIMER_E
2823 * @retval None
2824 */
LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2825 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2826 {
2827 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2828 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2829 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
2830 }
2831
2832 /**
2833 * @brief Indicate whether the timer start when receiving a synchronization input event.
2834 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
2835 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
2836 * @param HRTIMx High Resolution Timer instance
2837 * @param Timer This parameter can be one of the following values:
2838 * @arg @ref LL_HRTIM_TIMER_MASTER
2839 * @arg @ref LL_HRTIM_TIMER_A
2840 * @arg @ref LL_HRTIM_TIMER_B
2841 * @arg @ref LL_HRTIM_TIMER_C
2842 * @arg @ref LL_HRTIM_TIMER_D
2843 * @arg @ref LL_HRTIM_TIMER_E
2844 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2845 */
LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2846 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2847 {
2848 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2849 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2850
2851 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
2852 }
2853
2854 /**
2855 * @brief Enable the timer reset when receiving a synchronization input event.
2856 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
2857 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
2858 * @param HRTIMx High Resolution Timer instance
2859 * @param Timer This parameter can be one of the following values:
2860 * @arg @ref LL_HRTIM_TIMER_MASTER
2861 * @arg @ref LL_HRTIM_TIMER_A
2862 * @arg @ref LL_HRTIM_TIMER_B
2863 * @arg @ref LL_HRTIM_TIMER_C
2864 * @arg @ref LL_HRTIM_TIMER_D
2865 * @arg @ref LL_HRTIM_TIMER_E
2866 * @retval None
2867 */
LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2868 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2869 {
2870 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2871 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2872 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
2873 }
2874
2875 /**
2876 * @brief Disable the timer reset when receiving a synchronization input event.
2877 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
2878 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
2879 * @param HRTIMx High Resolution Timer instance
2880 * @param Timer This parameter can be one of the following values:
2881 * @arg @ref LL_HRTIM_TIMER_MASTER
2882 * @arg @ref LL_HRTIM_TIMER_A
2883 * @arg @ref LL_HRTIM_TIMER_B
2884 * @arg @ref LL_HRTIM_TIMER_C
2885 * @arg @ref LL_HRTIM_TIMER_D
2886 * @arg @ref LL_HRTIM_TIMER_E
2887 * @retval None
2888 */
LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2889 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2890 {
2891 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2892 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2893 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
2894 }
2895
2896 /**
2897 * @brief Indicate whether the timer reset when receiving a synchronization input event.
2898 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
2899 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
2900 * @param HRTIMx High Resolution Timer instance
2901 * @param Timer This parameter can be one of the following values:
2902 * @arg @ref LL_HRTIM_TIMER_MASTER
2903 * @arg @ref LL_HRTIM_TIMER_A
2904 * @arg @ref LL_HRTIM_TIMER_B
2905 * @arg @ref LL_HRTIM_TIMER_C
2906 * @arg @ref LL_HRTIM_TIMER_D
2907 * @arg @ref LL_HRTIM_TIMER_E
2908 * @retval None
2909 */
LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2910 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2911 {
2912 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2913 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2914
2915 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
2916 }
2917
2918 /**
2919 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2920 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
2921 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
2922 * @param HRTIMx High Resolution Timer instance
2923 * @param Timer This parameter can be one of the following values:
2924 * @arg @ref LL_HRTIM_TIMER_MASTER
2925 * @arg @ref LL_HRTIM_TIMER_A
2926 * @arg @ref LL_HRTIM_TIMER_B
2927 * @arg @ref LL_HRTIM_TIMER_C
2928 * @arg @ref LL_HRTIM_TIMER_D
2929 * @arg @ref LL_HRTIM_TIMER_E
2930 * @param DACTrig This parameter can be one of the following values:
2931 * @arg @ref LL_HRTIM_DACTRIG_NONE
2932 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2933 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2934 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2935 * @retval None
2936 */
LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DACTrig)2937 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
2938 {
2939 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2941 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
2942 }
2943
2944 /**
2945 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2946 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
2947 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
2948 * @param HRTIMx High Resolution Timer instance
2949 * @param Timer This parameter can be one of the following values:
2950 * @arg @ref LL_HRTIM_TIMER_MASTER
2951 * @arg @ref LL_HRTIM_TIMER_A
2952 * @arg @ref LL_HRTIM_TIMER_B
2953 * @arg @ref LL_HRTIM_TIMER_C
2954 * @arg @ref LL_HRTIM_TIMER_D
2955 * @arg @ref LL_HRTIM_TIMER_E
2956 * @retval DACTrig Returned value can be one of the following values:
2957 * @arg @ref LL_HRTIM_DACTRIG_NONE
2958 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2959 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2960 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2961 */
LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2962 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2963 {
2964 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2965 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2966 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
2967 }
2968
2969 /**
2970 * @brief Enable the timer registers preload mechanism.
2971 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
2972 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
2973 * @note When the preload mode is enabled, accessed registers are shadow registers.
2974 * Their content is transferred into the active register after an update request,
2975 * either software or synchronized with an event.
2976 * @param HRTIMx High Resolution Timer instance
2977 * @param Timer This parameter can be one of the following values:
2978 * @arg @ref LL_HRTIM_TIMER_MASTER
2979 * @arg @ref LL_HRTIM_TIMER_A
2980 * @arg @ref LL_HRTIM_TIMER_B
2981 * @arg @ref LL_HRTIM_TIMER_C
2982 * @arg @ref LL_HRTIM_TIMER_D
2983 * @arg @ref LL_HRTIM_TIMER_E
2984 * @retval None
2985 */
LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2986 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2987 {
2988 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2989 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2990 SET_BIT(*pReg, HRTIM_MCR_PREEN);
2991 }
2992
2993 /**
2994 * @brief Disable the timer registers preload mechanism.
2995 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
2996 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
2997 * @param HRTIMx High Resolution Timer instance
2998 * @param Timer This parameter can be one of the following values:
2999 * @arg @ref LL_HRTIM_TIMER_MASTER
3000 * @arg @ref LL_HRTIM_TIMER_A
3001 * @arg @ref LL_HRTIM_TIMER_B
3002 * @arg @ref LL_HRTIM_TIMER_C
3003 * @arg @ref LL_HRTIM_TIMER_D
3004 * @arg @ref LL_HRTIM_TIMER_E
3005 * @retval None
3006 */
LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3007 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3008 {
3009 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3010 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3011 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
3012 }
3013
3014 /**
3015 * @brief Indicate whether the timer registers preload mechanism is enabled.
3016 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
3017 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
3018 * @param HRTIMx High Resolution Timer instance
3019 * @param Timer This parameter can be one of the following values:
3020 * @arg @ref LL_HRTIM_TIMER_MASTER
3021 * @arg @ref LL_HRTIM_TIMER_A
3022 * @arg @ref LL_HRTIM_TIMER_B
3023 * @arg @ref LL_HRTIM_TIMER_C
3024 * @arg @ref LL_HRTIM_TIMER_D
3025 * @arg @ref LL_HRTIM_TIMER_E
3026 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
3027 */
LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3028 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3029 {
3030 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3031 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3032
3033 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
3034 }
3035
3036 /**
3037 * @brief Set the timer register update trigger.
3038 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
3039 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
3040 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
3041 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
3042 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
3043 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
3044 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
3045 * @param HRTIMx High Resolution Timer instance
3046 * @param Timer This parameter can be one of the following values:
3047 * @arg @ref LL_HRTIM_TIMER_MASTER
3048 * @arg @ref LL_HRTIM_TIMER_A
3049 * @arg @ref LL_HRTIM_TIMER_B
3050 * @arg @ref LL_HRTIM_TIMER_C
3051 * @arg @ref LL_HRTIM_TIMER_D
3052 * @arg @ref LL_HRTIM_TIMER_E
3053 * @param UpdateTrig This parameter can be one of the following values:
3054 *
3055 * For the master timer this parameter can be one of the following values:
3056 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3057 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3058 *
3059 * For timer A..E this parameter can be:
3060 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3061 * or a combination of the following values:
3062 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
3063 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
3064 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
3065 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
3066 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
3067 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
3068 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3069 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3070 * @retval None
3071 */
LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateTrig)3072 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
3073 {
3074 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3075 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3076 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
3077 }
3078
3079 /**
3080 * @brief Get the timer register update trigger.
3081 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
3082 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
3083 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
3084 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
3085 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
3086 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
3087 * @param HRTIMx High Resolution Timer instance
3088 * @param Timer This parameter can be one of the following values:
3089 * @arg @ref LL_HRTIM_TIMER_MASTER
3090 * @arg @ref LL_HRTIM_TIMER_A
3091 * @arg @ref LL_HRTIM_TIMER_B
3092 * @arg @ref LL_HRTIM_TIMER_C
3093 * @arg @ref LL_HRTIM_TIMER_D
3094 * @arg @ref LL_HRTIM_TIMER_E
3095 * @retval UpdateTrig Returned value can be one of the following values:
3096 *
3097 * For the master timer this parameter can be one of the following values:
3098 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3099 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3100 *
3101 * For timer A..E this parameter can be:
3102 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3103 * or a combination of the following values:
3104 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
3105 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
3106 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
3107 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
3108 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
3109 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
3110 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3111 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3112 */
LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3113 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3114 {
3115 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3116 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3117 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
3118 }
3119
3120 /**
3121 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
3122 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
3123 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
3124 * @param HRTIMx High Resolution Timer instance
3125 * @param Timer This parameter can be one of the following values:
3126 * @arg @ref LL_HRTIM_TIMER_MASTER
3127 * @arg @ref LL_HRTIM_TIMER_A
3128 * @arg @ref LL_HRTIM_TIMER_B
3129 * @arg @ref LL_HRTIM_TIMER_C
3130 * @arg @ref LL_HRTIM_TIMER_D
3131 * @arg @ref LL_HRTIM_TIMER_E
3132 * @param UpdateGating This parameter can be one of the following values:
3133 *
3134 * For the master timer this parameter can be one of the following values:
3135 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3136 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3137 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3138 *
3139 * For the timer A..E this parameter can be one of the following values:
3140 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3141 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3142 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3143 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3144 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3145 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3146 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3147 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3148 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3149 * @retval None
3150 */
LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateGating)3151 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
3152 {
3153 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3154 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3155 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
3156 }
3157
3158 /**
3159 * @brief Get the timer registers update condition.
3160 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
3161 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
3162 * @param HRTIMx High Resolution Timer instance
3163 * @param Timer This parameter can be one of the following values:
3164 * @arg @ref LL_HRTIM_TIMER_MASTER
3165 * @arg @ref LL_HRTIM_TIMER_A
3166 * @arg @ref LL_HRTIM_TIMER_B
3167 * @arg @ref LL_HRTIM_TIMER_C
3168 * @arg @ref LL_HRTIM_TIMER_D
3169 * @arg @ref LL_HRTIM_TIMER_E
3170 * @retval UpdateGating Returned value can be one of the following values:
3171 *
3172 * For the master timer this parameter can be one of the following values:
3173 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3174 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3175 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3176 *
3177 * For the timer A..E this parameter can be one of the following values:
3178 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3179 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3180 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3181 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3182 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3183 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3184 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3185 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3186 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3187 */
LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3188 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3189 {
3190 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3191 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3192 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
3193 }
3194
3195 /**
3196 * @brief Enable the push-pull mode.
3197 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
3198 * @param HRTIMx High Resolution Timer instance
3199 * @param Timer This parameter can be one of the following values:
3200 * @arg @ref LL_HRTIM_TIMER_A
3201 * @arg @ref LL_HRTIM_TIMER_B
3202 * @arg @ref LL_HRTIM_TIMER_C
3203 * @arg @ref LL_HRTIM_TIMER_D
3204 * @arg @ref LL_HRTIM_TIMER_E
3205 * @retval None
3206 */
LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3207 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3208 {
3209 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3210 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3211 REG_OFFSET_TAB_TIMER[iTimer]));
3212 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
3213 }
3214
3215 /**
3216 * @brief Disable the push-pull mode.
3217 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
3218 * @param HRTIMx High Resolution Timer instance
3219 * @param Timer This parameter can be one of the following values:
3220 * @arg @ref LL_HRTIM_TIMER_A
3221 * @arg @ref LL_HRTIM_TIMER_B
3222 * @arg @ref LL_HRTIM_TIMER_C
3223 * @arg @ref LL_HRTIM_TIMER_D
3224 * @arg @ref LL_HRTIM_TIMER_E
3225 * @retval None
3226 */
LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3227 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3228 {
3229 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3230 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3231 REG_OFFSET_TAB_TIMER[iTimer]));
3232 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
3233 }
3234
3235 /**
3236 * @brief Indicate whether the push-pull mode is enabled.
3237 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
3238 * @param HRTIMx High Resolution Timer instance
3239 * @param Timer This parameter can be one of the following values:
3240 * @arg @ref LL_HRTIM_TIMER_A
3241 * @arg @ref LL_HRTIM_TIMER_B
3242 * @arg @ref LL_HRTIM_TIMER_C
3243 * @arg @ref LL_HRTIM_TIMER_D
3244 * @arg @ref LL_HRTIM_TIMER_E
3245 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
3246 */
LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3247 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3248 {
3249 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3250 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3251 REG_OFFSET_TAB_TIMER[iTimer]));
3252 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
3253 }
3254
3255 /**
3256 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
3257 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
3258 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
3259 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
3260 * @param HRTIMx High Resolution Timer instance
3261 * @param Timer This parameter can be one of the following values:
3262 * @arg @ref LL_HRTIM_TIMER_A
3263 * @arg @ref LL_HRTIM_TIMER_B
3264 * @arg @ref LL_HRTIM_TIMER_C
3265 * @arg @ref LL_HRTIM_TIMER_D
3266 * @arg @ref LL_HRTIM_TIMER_E
3267 * @param CompareUnit This parameter can be one of the following values:
3268 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3269 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3270 * @param Mode This parameter can be one of the following values:
3271 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3272 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3273 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3274 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3275 * @retval None
3276 */
LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit,uint32_t Mode)3277 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
3278 uint32_t Mode)
3279 {
3280 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3281 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3282 REG_OFFSET_TAB_TIMER[iTimer]));
3283 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3284 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
3285 }
3286
3287 /**
3288 * @brief Get the functioning mode of the compare unit.
3289 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
3290 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
3291 * @param HRTIMx High Resolution Timer instance
3292 * @param Timer This parameter can be one of the following values:
3293 * @arg @ref LL_HRTIM_TIMER_A
3294 * @arg @ref LL_HRTIM_TIMER_B
3295 * @arg @ref LL_HRTIM_TIMER_C
3296 * @arg @ref LL_HRTIM_TIMER_D
3297 * @arg @ref LL_HRTIM_TIMER_E
3298 * @param CompareUnit This parameter can be one of the following values:
3299 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3300 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3301 * @retval Mode Returned value can be one of the following values:
3302 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3303 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3304 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3305 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3306 */
LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit)3307 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
3308 {
3309 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3310 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3311 REG_OFFSET_TAB_TIMER[iTimer]));
3312 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3313 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
3314 }
3315
3316 /**
3317 * @brief Set the timer counter value.
3318 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
3319 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
3320 * @note This function can only be called when the timer is stopped.
3321 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
3322 * significant bits of the counter are not significant. They cannot be
3323 * written and return 0 when read.
3324 * @note The timer behavior is not guaranteed if the counter value is set above
3325 * the period.
3326 * @param HRTIMx High Resolution Timer instance
3327 * @param Timer This parameter can be one of the following values:
3328 * @arg @ref LL_HRTIM_TIMER_MASTER
3329 * @arg @ref LL_HRTIM_TIMER_A
3330 * @arg @ref LL_HRTIM_TIMER_B
3331 * @arg @ref LL_HRTIM_TIMER_C
3332 * @arg @ref LL_HRTIM_TIMER_D
3333 * @arg @ref LL_HRTIM_TIMER_E
3334 * @param Counter Value between 0 and 0xFFFF
3335 * @retval None
3336 */
LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Counter)3337 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
3338 {
3339 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3340 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3341 REG_OFFSET_TAB_TIMER[iTimer]));
3342 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
3343 }
3344
3345 /**
3346 * @brief Get actual timer counter value.
3347 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
3348 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
3349 * @param HRTIMx High Resolution Timer instance
3350 * @param Timer This parameter can be one of the following values:
3351 * @arg @ref LL_HRTIM_TIMER_MASTER
3352 * @arg @ref LL_HRTIM_TIMER_A
3353 * @arg @ref LL_HRTIM_TIMER_B
3354 * @arg @ref LL_HRTIM_TIMER_C
3355 * @arg @ref LL_HRTIM_TIMER_D
3356 * @arg @ref LL_HRTIM_TIMER_E
3357 * @retval Counter Value between 0 and 0xFFFF
3358 */
LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3359 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3360 {
3361 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3362 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3363 REG_OFFSET_TAB_TIMER[iTimer]));
3364 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
3365 }
3366
3367 /**
3368 * @brief Set the timer period value.
3369 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
3370 * PERxR PERx LL_HRTIM_TIM_SetPeriod
3371 * @param HRTIMx High Resolution Timer instance
3372 * @param Timer This parameter can be one of the following values:
3373 * @arg @ref LL_HRTIM_TIMER_MASTER
3374 * @arg @ref LL_HRTIM_TIMER_A
3375 * @arg @ref LL_HRTIM_TIMER_B
3376 * @arg @ref LL_HRTIM_TIMER_C
3377 * @arg @ref LL_HRTIM_TIMER_D
3378 * @arg @ref LL_HRTIM_TIMER_E
3379 * @param Period Value between 0 and 0xFFFF
3380 * @retval None
3381 */
LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Period)3382 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
3383 {
3384 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3385 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3386 REG_OFFSET_TAB_TIMER[iTimer]));
3387 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
3388 }
3389
3390 /**
3391 * @brief Get actual timer period value.
3392 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
3393 * PERxR PERx LL_HRTIM_TIM_GetPeriod
3394 * @param HRTIMx High Resolution Timer instance
3395 * @param Timer This parameter can be one of the following values:
3396 * @arg @ref LL_HRTIM_TIMER_MASTER
3397 * @arg @ref LL_HRTIM_TIMER_A
3398 * @arg @ref LL_HRTIM_TIMER_B
3399 * @arg @ref LL_HRTIM_TIMER_C
3400 * @arg @ref LL_HRTIM_TIMER_D
3401 * @arg @ref LL_HRTIM_TIMER_E
3402 * @retval Period Value between 0 and 0xFFFF
3403 */
LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3404 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3405 {
3406 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3407 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3408 REG_OFFSET_TAB_TIMER[iTimer]));
3409 return (READ_BIT(*pReg, HRTIM_MPER_MPER));
3410 }
3411
3412 /**
3413 * @brief Set the timer repetition period value.
3414 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
3415 * REPxR REPx LL_HRTIM_TIM_SetRepetition
3416 * @param HRTIMx High Resolution Timer instance
3417 * @param Timer This parameter can be one of the following values:
3418 * @arg @ref LL_HRTIM_TIMER_MASTER
3419 * @arg @ref LL_HRTIM_TIMER_A
3420 * @arg @ref LL_HRTIM_TIMER_B
3421 * @arg @ref LL_HRTIM_TIMER_C
3422 * @arg @ref LL_HRTIM_TIMER_D
3423 * @arg @ref LL_HRTIM_TIMER_E
3424 * @param Repetition Value between 0 and 0xFF
3425 * @retval None
3426 */
LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Repetition)3427 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
3428 {
3429 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3430 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3431 REG_OFFSET_TAB_TIMER[iTimer]));
3432 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
3433 }
3434
3435 /**
3436 * @brief Get actual timer repetition period value.
3437 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
3438 * REPxR REPx LL_HRTIM_TIM_GetRepetition
3439 * @param HRTIMx High Resolution Timer instance
3440 * @param Timer This parameter can be one of the following values:
3441 * @arg @ref LL_HRTIM_TIMER_MASTER
3442 * @arg @ref LL_HRTIM_TIMER_A
3443 * @arg @ref LL_HRTIM_TIMER_B
3444 * @arg @ref LL_HRTIM_TIMER_C
3445 * @arg @ref LL_HRTIM_TIMER_D
3446 * @arg @ref LL_HRTIM_TIMER_E
3447 * @retval Repetition Value between 0 and 0xFF
3448 */
LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3449 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3450 {
3451 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3452 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3453 REG_OFFSET_TAB_TIMER[iTimer]));
3454 return (READ_BIT(*pReg, HRTIM_MREP_MREP));
3455 }
3456
3457 /**
3458 * @brief Set the compare value of the compare unit 1.
3459 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
3460 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
3461 * @param HRTIMx High Resolution Timer instance
3462 * @param Timer This parameter can be one of the following values:
3463 * @arg @ref LL_HRTIM_TIMER_MASTER
3464 * @arg @ref LL_HRTIM_TIMER_A
3465 * @arg @ref LL_HRTIM_TIMER_B
3466 * @arg @ref LL_HRTIM_TIMER_C
3467 * @arg @ref LL_HRTIM_TIMER_D
3468 * @arg @ref LL_HRTIM_TIMER_E
3469 * @param CompareValue Compare value must be above or equal to 3
3470 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3471 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3472 * @retval None
3473 */
LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3474 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3475 {
3476 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3477 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3478 REG_OFFSET_TAB_TIMER[iTimer]));
3479 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
3480 }
3481
3482 /**
3483 * @brief Get actual compare value of the compare unit 1.
3484 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
3485 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
3486 * @param HRTIMx High Resolution Timer instance
3487 * @param Timer This parameter can be one of the following values:
3488 * @arg @ref LL_HRTIM_TIMER_MASTER
3489 * @arg @ref LL_HRTIM_TIMER_A
3490 * @arg @ref LL_HRTIM_TIMER_B
3491 * @arg @ref LL_HRTIM_TIMER_C
3492 * @arg @ref LL_HRTIM_TIMER_D
3493 * @arg @ref LL_HRTIM_TIMER_E
3494 * @retval CompareValue Compare value must be above or equal to 3
3495 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3496 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3497 */
LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3498 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3499 {
3500 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3501 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3502 REG_OFFSET_TAB_TIMER[iTimer]));
3503 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
3504 }
3505
3506 /**
3507 * @brief Set the compare value of the compare unit 2.
3508 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
3509 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
3510 * @param HRTIMx High Resolution Timer instance
3511 * @param Timer This parameter can be one of the following values:
3512 * @arg @ref LL_HRTIM_TIMER_MASTER
3513 * @arg @ref LL_HRTIM_TIMER_A
3514 * @arg @ref LL_HRTIM_TIMER_B
3515 * @arg @ref LL_HRTIM_TIMER_C
3516 * @arg @ref LL_HRTIM_TIMER_D
3517 * @arg @ref LL_HRTIM_TIMER_E
3518 * @param CompareValue Compare value must be above or equal to 3
3519 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3520 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3521 * @retval None
3522 */
LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3523 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3524 {
3525 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3526 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3527 REG_OFFSET_TAB_TIMER[iTimer]));
3528 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
3529 }
3530
3531 /**
3532 * @brief Get actual compare value of the compare unit 2.
3533 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
3534 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
3535 * @param HRTIMx High Resolution Timer instance
3536 * @param Timer This parameter can be one of the following values:
3537 * @arg @ref LL_HRTIM_TIMER_MASTER
3538 * @arg @ref LL_HRTIM_TIMER_A
3539 * @arg @ref LL_HRTIM_TIMER_B
3540 * @arg @ref LL_HRTIM_TIMER_C
3541 * @arg @ref LL_HRTIM_TIMER_D
3542 * @arg @ref LL_HRTIM_TIMER_E
3543 * @retval CompareValue Compare value must be above or equal to 3
3544 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3545 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3546 */
LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3547 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3548 {
3549 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3550 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3551 REG_OFFSET_TAB_TIMER[iTimer]));
3552 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
3553 }
3554
3555 /**
3556 * @brief Set the compare value of the compare unit 3.
3557 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
3558 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
3559 * @param HRTIMx High Resolution Timer instance
3560 * @param Timer This parameter can be one of the following values:
3561 * @arg @ref LL_HRTIM_TIMER_MASTER
3562 * @arg @ref LL_HRTIM_TIMER_A
3563 * @arg @ref LL_HRTIM_TIMER_B
3564 * @arg @ref LL_HRTIM_TIMER_C
3565 * @arg @ref LL_HRTIM_TIMER_D
3566 * @arg @ref LL_HRTIM_TIMER_E
3567 * @param CompareValue Compare value must be above or equal to 3
3568 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3569 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3570 * @retval None
3571 */
LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3572 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3573 {
3574 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3575 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3576 REG_OFFSET_TAB_TIMER[iTimer]));
3577 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
3578 }
3579
3580 /**
3581 * @brief Get actual compare value of the compare unit 3.
3582 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
3583 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
3584 * @param HRTIMx High Resolution Timer instance
3585 * @param Timer This parameter can be one of the following values:
3586 * @arg @ref LL_HRTIM_TIMER_MASTER
3587 * @arg @ref LL_HRTIM_TIMER_A
3588 * @arg @ref LL_HRTIM_TIMER_B
3589 * @arg @ref LL_HRTIM_TIMER_C
3590 * @arg @ref LL_HRTIM_TIMER_D
3591 * @arg @ref LL_HRTIM_TIMER_E
3592 * @retval CompareValue Compare value must be above or equal to 3
3593 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3594 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3595 */
LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3596 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3597 {
3598 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3599 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3600 REG_OFFSET_TAB_TIMER[iTimer]));
3601 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
3602 }
3603
3604 /**
3605 * @brief Set the compare value of the compare unit 4.
3606 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
3607 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
3608 * @param HRTIMx High Resolution Timer instance
3609 * @param Timer This parameter can be one of the following values:
3610 * @arg @ref LL_HRTIM_TIMER_MASTER
3611 * @arg @ref LL_HRTIM_TIMER_A
3612 * @arg @ref LL_HRTIM_TIMER_B
3613 * @arg @ref LL_HRTIM_TIMER_C
3614 * @arg @ref LL_HRTIM_TIMER_D
3615 * @arg @ref LL_HRTIM_TIMER_E
3616 * @param CompareValue Compare value must be above or equal to 3
3617 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3618 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3619 * @retval None
3620 */
LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3621 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3622 {
3623 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3624 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3625 REG_OFFSET_TAB_TIMER[iTimer]));
3626 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
3627 }
3628
3629 /**
3630 * @brief Get actual compare value of the compare unit 4.
3631 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
3632 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
3633 * @param HRTIMx High Resolution Timer instance
3634 * @param Timer This parameter can be one of the following values:
3635 * @arg @ref LL_HRTIM_TIMER_MASTER
3636 * @arg @ref LL_HRTIM_TIMER_A
3637 * @arg @ref LL_HRTIM_TIMER_B
3638 * @arg @ref LL_HRTIM_TIMER_C
3639 * @arg @ref LL_HRTIM_TIMER_D
3640 * @arg @ref LL_HRTIM_TIMER_E
3641 * @retval CompareValue Compare value must be above or equal to 3
3642 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3643 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3644 */
LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3645 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3646 {
3647 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3648 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3649 REG_OFFSET_TAB_TIMER[iTimer]));
3650 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
3651 }
3652
3653 /**
3654 * @brief Set the reset trigger of a timer counter.
3655 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
3656 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
3657 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
3658 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
3659 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
3660 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
3661 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
3662 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
3663 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
3664 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
3665 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
3666 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
3667 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
3668 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
3669 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
3670 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
3671 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
3672 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
3673 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
3674 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
3675 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
3676 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
3677 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
3678 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
3679 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
3680 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
3681 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
3682 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
3683 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
3684 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
3685 * @note The reset of the timer counter can be triggered by up to 30 events
3686 * that can be selected among the following sources:
3687 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
3688 * @arg The master timer: Reset and Compare 1..4 (5 events).
3689 * @arg The external events EXTEVNT1..10 (10 events).
3690 * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
3691 * @param HRTIMx High Resolution Timer instance
3692 * @param Timer This parameter can be one of the following values:
3693 * @arg @ref LL_HRTIM_TIMER_A
3694 * @arg @ref LL_HRTIM_TIMER_B
3695 * @arg @ref LL_HRTIM_TIMER_C
3696 * @arg @ref LL_HRTIM_TIMER_D
3697 * @arg @ref LL_HRTIM_TIMER_E
3698 * @param ResetTrig This parameter can be a combination of the following values:
3699 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3700 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3701 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3702 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3703 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3704 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3705 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3706 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3707 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3708 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3709 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3710 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3711 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3712 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3713 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3714 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3715 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3716 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3717 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3718 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3719 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3720 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3721 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3722 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3723 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3724 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3725 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3726 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3727 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3728 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3729 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3730 * @retval None
3731 */
LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t ResetTrig)3732 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
3733 {
3734 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3735 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3736 REG_OFFSET_TAB_TIMER[iTimer]));
3737 WRITE_REG(*pReg, ResetTrig);
3738 }
3739
3740 /**
3741 * @brief Get actual reset trigger of a timer counter.
3742 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
3743 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
3744 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
3745 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
3746 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
3747 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
3748 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
3749 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
3750 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
3751 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
3752 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
3753 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
3754 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
3755 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
3756 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
3757 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
3758 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
3759 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
3760 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
3761 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
3762 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
3763 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
3764 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
3765 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
3766 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
3767 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
3768 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
3769 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
3770 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
3771 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
3772 * @param HRTIMx High Resolution Timer instance
3773 * @param Timer This parameter can be one of the following values:
3774 * @arg @ref LL_HRTIM_TIMER_A
3775 * @arg @ref LL_HRTIM_TIMER_B
3776 * @arg @ref LL_HRTIM_TIMER_C
3777 * @arg @ref LL_HRTIM_TIMER_D
3778 * @arg @ref LL_HRTIM_TIMER_E
3779 * @retval ResetTrig Returned value can be one of the following values:
3780 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3781 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3782 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3783 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3784 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3785 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3786 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3787 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3788 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3789 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3790 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3791 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3792 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3793 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3794 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3795 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3796 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3797 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3798 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3799 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3800 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3801 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3802 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3803 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3804 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3805 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3806 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3807 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3808 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3809 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3810 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3811 */
LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3812 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3813 {
3814 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3815 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3816 REG_OFFSET_TAB_TIMER[iTimer]));
3817 return (READ_REG(*pReg));
3818 }
3819
3820 /**
3821 * @brief Get captured value for capture unit 1.
3822 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
3823 * @param HRTIMx High Resolution Timer instance
3824 * @param Timer This parameter can be one of the following values:
3825 * @arg @ref LL_HRTIM_TIMER_A
3826 * @arg @ref LL_HRTIM_TIMER_B
3827 * @arg @ref LL_HRTIM_TIMER_C
3828 * @arg @ref LL_HRTIM_TIMER_D
3829 * @arg @ref LL_HRTIM_TIMER_E
3830 * @retval Captured value
3831 */
LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3832 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3833 {
3834 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3835 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
3836 REG_OFFSET_TAB_TIMER[iTimer]));
3837 return (READ_REG(*pReg));
3838 }
3839
3840 /**
3841 * @brief Get captured value for capture unit 2.
3842 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
3843 * @param HRTIMx High Resolution Timer instance
3844 * @param Timer This parameter can be one of the following values:
3845 * @arg @ref LL_HRTIM_TIMER_A
3846 * @arg @ref LL_HRTIM_TIMER_B
3847 * @arg @ref LL_HRTIM_TIMER_C
3848 * @arg @ref LL_HRTIM_TIMER_D
3849 * @arg @ref LL_HRTIM_TIMER_E
3850 * @retval Captured value
3851 */
LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3852 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3853 {
3854 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3855 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
3856 REG_OFFSET_TAB_TIMER[iTimer]));
3857 return (READ_REG(*pReg));
3858 }
3859
3860 /**
3861 * @brief Set the trigger of a capture unit for a given timer.
3862 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
3863 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
3864 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
3865 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
3866 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
3867 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
3868 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
3869 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
3870 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
3871 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
3872 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
3873 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
3874 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
3875 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
3876 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3877 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3878 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
3879 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
3880 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3881 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3882 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
3883 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
3884 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3885 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3886 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
3887 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
3888 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3889 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3890 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
3891 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
3892 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3893 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
3894 * @param HRTIMx High Resolution Timer instance
3895 * @param Timer This parameter can be one of the following values:
3896 * @arg @ref LL_HRTIM_TIMER_A
3897 * @arg @ref LL_HRTIM_TIMER_B
3898 * @arg @ref LL_HRTIM_TIMER_C
3899 * @arg @ref LL_HRTIM_TIMER_D
3900 * @arg @ref LL_HRTIM_TIMER_E
3901 * @param CaptureUnit This parameter can be one of the following values:
3902 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3903 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3904 * @param CaptureTrig This parameter can be a combination of the following values:
3905 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3906 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3907 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3908 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3909 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3910 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3911 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
3912 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
3913 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
3914 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
3915 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
3916 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
3917 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
3918 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
3919 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
3920 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
3921 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
3922 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
3923 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
3924 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
3925 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
3926 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
3927 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
3928 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
3929 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
3930 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
3931 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
3932 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
3933 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
3934 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
3935 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
3936 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
3937 * @retval None
3938 */
LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit,uint32_t CaptureTrig)3939 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
3940 uint32_t CaptureTrig)
3941 {
3942 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3943 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
3944 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
3945 WRITE_REG(*pReg, CaptureTrig);
3946 }
3947
3948 /**
3949 * @brief Get actual trigger of a capture unit for a given timer.
3950 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
3951 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
3952 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
3953 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
3954 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
3955 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
3956 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
3957 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
3958 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
3959 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
3960 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
3961 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
3962 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
3963 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
3964 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3965 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3966 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
3967 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
3968 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3969 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3970 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
3971 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
3972 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3973 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3974 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
3975 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
3976 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3977 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3978 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
3979 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
3980 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3981 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
3982 * @param HRTIMx High Resolution Timer instance
3983 * @param Timer This parameter can be one of the following values:
3984 * @arg @ref LL_HRTIM_TIMER_A
3985 * @arg @ref LL_HRTIM_TIMER_B
3986 * @arg @ref LL_HRTIM_TIMER_C
3987 * @arg @ref LL_HRTIM_TIMER_D
3988 * @arg @ref LL_HRTIM_TIMER_E
3989 * @param CaptureUnit This parameter can be one of the following values:
3990 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3991 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3992 * @retval CaptureTrig This parameter can be a combination of the following values:
3993 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3994 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3995 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3996 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3997 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3998 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3999 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
4000 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
4001 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
4002 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
4003 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
4004 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
4005 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
4006 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
4007 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
4008 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
4009 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
4010 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
4011 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
4012 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
4013 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
4014 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
4015 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
4016 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
4017 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
4018 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
4019 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
4020 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
4021 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
4022 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
4023 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
4024 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
4025 */
LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit)4026 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
4027 {
4028 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4029 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
4030 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
4031 return (READ_REG(*pReg));
4032 }
4033
4034 /**
4035 * @brief Enable deadtime insertion for a given timer.
4036 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
4037 * @param HRTIMx High Resolution Timer instance
4038 * @param Timer This parameter can be one of the following values:
4039 * @arg @ref LL_HRTIM_TIMER_A
4040 * @arg @ref LL_HRTIM_TIMER_B
4041 * @arg @ref LL_HRTIM_TIMER_C
4042 * @arg @ref LL_HRTIM_TIMER_D
4043 * @arg @ref LL_HRTIM_TIMER_E
4044 * @retval None
4045 */
LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4046 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4047 {
4048 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4049 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4050 REG_OFFSET_TAB_TIMER[iTimer]));
4051 SET_BIT(*pReg, HRTIM_OUTR_DTEN);
4052 }
4053
4054 /**
4055 * @brief Disable deadtime insertion for a given timer.
4056 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
4057 * @param HRTIMx High Resolution Timer instance
4058 * @param Timer This parameter can be one of the following values:
4059 * @arg @ref LL_HRTIM_TIMER_A
4060 * @arg @ref LL_HRTIM_TIMER_B
4061 * @arg @ref LL_HRTIM_TIMER_C
4062 * @arg @ref LL_HRTIM_TIMER_D
4063 * @arg @ref LL_HRTIM_TIMER_E
4064 * @retval None
4065 */
LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4066 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4067 {
4068 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4069 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4070 REG_OFFSET_TAB_TIMER[iTimer]));
4071 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
4072 }
4073
4074 /**
4075 * @brief Indicate whether deadtime insertion is enabled for a given timer.
4076 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
4077 * @param HRTIMx High Resolution Timer instance
4078 * @param Timer This parameter can be one of the following values:
4079 * @arg @ref LL_HRTIM_TIMER_A
4080 * @arg @ref LL_HRTIM_TIMER_B
4081 * @arg @ref LL_HRTIM_TIMER_C
4082 * @arg @ref LL_HRTIM_TIMER_D
4083 * @arg @ref LL_HRTIM_TIMER_E
4084 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
4085 */
LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4086 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4087 {
4088 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4089 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4090 REG_OFFSET_TAB_TIMER[iTimer]));
4091
4092 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
4093 }
4094
4095 /**
4096 * @brief Set the delayed protection (DLYPRT) mode.
4097 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
4098 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
4099 * @note This function must be called prior enabling the delayed protection
4100 * @note Balanced Idle mode is only available in push-pull mode
4101 * @param HRTIMx High Resolution Timer instance
4102 * @param Timer This parameter can be one of the following values:
4103 * @arg @ref LL_HRTIM_TIMER_A
4104 * @arg @ref LL_HRTIM_TIMER_B
4105 * @arg @ref LL_HRTIM_TIMER_C
4106 * @arg @ref LL_HRTIM_TIMER_D
4107 * @arg @ref LL_HRTIM_TIMER_E
4108 * @param DLYPRTMode Delayed protection (DLYPRT) mode
4109 *
4110 * For timers A, B and C this parameter can be one of the following values:
4111 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4112 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4113 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4114 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4115 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4116 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4117 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4118 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4119 *
4120 * For timers D and E this parameter can be one of the following values:
4121 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4122 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4123 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4124 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4125 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4126 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4127 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4128 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4129 * @retval None
4130 */
LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DLYPRTMode)4131 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
4132 {
4133 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4134 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4135 REG_OFFSET_TAB_TIMER[iTimer]));
4136 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
4137 }
4138
4139 /**
4140 * @brief Get the delayed protection (DLYPRT) mode.
4141 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
4142 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
4143 * @param HRTIMx High Resolution Timer instance
4144 * @param Timer This parameter can be one of the following values:
4145 * @arg @ref LL_HRTIM_TIMER_A
4146 * @arg @ref LL_HRTIM_TIMER_B
4147 * @arg @ref LL_HRTIM_TIMER_C
4148 * @arg @ref LL_HRTIM_TIMER_D
4149 * @arg @ref LL_HRTIM_TIMER_E
4150 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
4151 *
4152 * For timers A, B and C this parameter can be one of the following values:
4153 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4154 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4155 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4156 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4157 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4158 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4159 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4160 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4161 *
4162 * For timers D and E this parameter can be one of the following values:
4163 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4164 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4165 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4166 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4167 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4168 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4169 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4170 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4171 */
LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4172 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4173 {
4174 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4175 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4176 REG_OFFSET_TAB_TIMER[iTimer]));
4177 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
4178 }
4179
4180 /**
4181 * @brief Enable delayed protection (DLYPRT) for a given timer.
4182 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
4183 * @note This function must not be called once the concerned timer is enabled
4184 * @param HRTIMx High Resolution Timer instance
4185 * @param Timer This parameter can be one of the following values:
4186 * @arg @ref LL_HRTIM_TIMER_A
4187 * @arg @ref LL_HRTIM_TIMER_B
4188 * @arg @ref LL_HRTIM_TIMER_C
4189 * @arg @ref LL_HRTIM_TIMER_D
4190 * @arg @ref LL_HRTIM_TIMER_E
4191 * @retval None
4192 */
LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4193 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4194 {
4195 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4196 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4197 REG_OFFSET_TAB_TIMER[iTimer]));
4198 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
4199 }
4200
4201 /**
4202 * @brief Disable delayed protection (DLYPRT) for a given timer.
4203 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
4204 * @note This function must not be called once the concerned timer is enabled
4205 * @param HRTIMx High Resolution Timer instance
4206 * @param Timer This parameter can be one of the following values:
4207 * @arg @ref LL_HRTIM_TIMER_A
4208 * @arg @ref LL_HRTIM_TIMER_B
4209 * @arg @ref LL_HRTIM_TIMER_C
4210 * @arg @ref LL_HRTIM_TIMER_D
4211 * @arg @ref LL_HRTIM_TIMER_E
4212 * @retval None
4213 */
LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4214 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4215 {
4216 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4217 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4218 REG_OFFSET_TAB_TIMER[iTimer]));
4219 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
4220 }
4221
4222 /**
4223 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
4224 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
4225 * @param HRTIMx High Resolution Timer instance
4226 * @param Timer This parameter can be one of the following values:
4227 * @arg @ref LL_HRTIM_TIMER_A
4228 * @arg @ref LL_HRTIM_TIMER_B
4229 * @arg @ref LL_HRTIM_TIMER_C
4230 * @arg @ref LL_HRTIM_TIMER_D
4231 * @arg @ref LL_HRTIM_TIMER_E
4232 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
4233 */
LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4234 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4235 {
4236 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4237 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4238 REG_OFFSET_TAB_TIMER[iTimer]));
4239 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
4240 }
4241
4242 /**
4243 * @brief Enable the fault channel(s) for a given timer.
4244 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
4245 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
4246 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
4247 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
4248 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
4249 * @param HRTIMx High Resolution Timer instance
4250 * @param Timer This parameter can be one of the following values:
4251 * @arg @ref LL_HRTIM_TIMER_A
4252 * @arg @ref LL_HRTIM_TIMER_B
4253 * @arg @ref LL_HRTIM_TIMER_C
4254 * @arg @ref LL_HRTIM_TIMER_D
4255 * @arg @ref LL_HRTIM_TIMER_E
4256 * @param Faults This parameter can be a combination of the following values:
4257 * @arg @ref LL_HRTIM_FAULT_1
4258 * @arg @ref LL_HRTIM_FAULT_2
4259 * @arg @ref LL_HRTIM_FAULT_3
4260 * @arg @ref LL_HRTIM_FAULT_4
4261 * @arg @ref LL_HRTIM_FAULT_5
4262 * @retval None
4263 */
LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)4264 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4265 {
4266 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4267 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4268 REG_OFFSET_TAB_TIMER[iTimer]));
4269 SET_BIT(*pReg, Faults);
4270 }
4271
4272 /**
4273 * @brief Disable the fault channel(s) for a given timer.
4274 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
4275 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
4276 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
4277 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
4278 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
4279 * @param HRTIMx High Resolution Timer instance
4280 * @param Timer This parameter can be one of the following values:
4281 * @arg @ref LL_HRTIM_TIMER_A
4282 * @arg @ref LL_HRTIM_TIMER_B
4283 * @arg @ref LL_HRTIM_TIMER_C
4284 * @arg @ref LL_HRTIM_TIMER_D
4285 * @arg @ref LL_HRTIM_TIMER_E
4286 * @param Faults This parameter can be a combination of the following values:
4287 * @arg @ref LL_HRTIM_FAULT_1
4288 * @arg @ref LL_HRTIM_FAULT_2
4289 * @arg @ref LL_HRTIM_FAULT_3
4290 * @arg @ref LL_HRTIM_FAULT_4
4291 * @arg @ref LL_HRTIM_FAULT_5
4292 * @retval None
4293 */
LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)4294 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4295 {
4296 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4297 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4298 REG_OFFSET_TAB_TIMER[iTimer]));
4299 CLEAR_BIT(*pReg, Faults);
4300 }
4301
4302 /**
4303 * @brief Indicate whether the fault channel is enabled for a given timer.
4304 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
4305 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
4306 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
4307 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
4308 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
4309 * @param HRTIMx High Resolution Timer instance
4310 * @param Timer This parameter can be one of the following values:
4311 * @arg @ref LL_HRTIM_TIMER_A
4312 * @arg @ref LL_HRTIM_TIMER_B
4313 * @arg @ref LL_HRTIM_TIMER_C
4314 * @arg @ref LL_HRTIM_TIMER_D
4315 * @arg @ref LL_HRTIM_TIMER_E
4316 * @param Fault This parameter can be one of the following values:
4317 * @arg @ref LL_HRTIM_FAULT_1
4318 * @arg @ref LL_HRTIM_FAULT_2
4319 * @arg @ref LL_HRTIM_FAULT_3
4320 * @arg @ref LL_HRTIM_FAULT_4
4321 * @arg @ref LL_HRTIM_FAULT_5
4322 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
4323 */
LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Fault)4324 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
4325 {
4326 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4327 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4328 REG_OFFSET_TAB_TIMER[iTimer]));
4329
4330 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
4331 }
4332
4333 /**
4334 * @brief Lock the fault conditioning set-up for a given timer.
4335 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
4336 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
4337 * @param HRTIMx High Resolution Timer instance
4338 * @param Timer This parameter can be one of the following values:
4339 * @arg @ref LL_HRTIM_TIMER_A
4340 * @arg @ref LL_HRTIM_TIMER_B
4341 * @arg @ref LL_HRTIM_TIMER_C
4342 * @arg @ref LL_HRTIM_TIMER_D
4343 * @arg @ref LL_HRTIM_TIMER_E
4344 * @retval None
4345 */
LL_HRTIM_TIM_LockFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4346 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4347 {
4348 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4349 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4350 REG_OFFSET_TAB_TIMER[iTimer]));
4351 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
4352 }
4353
4354 /**
4355 * @brief Define how the timer behaves during a burst mode operation.
4356 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
4357 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
4358 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
4359 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
4360 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
4361 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
4362 * @note This function must not be called when the burst mode is enabled
4363 * @param HRTIMx High Resolution Timer instance
4364 * @param Timer This parameter can be one of the following values:
4365 * @arg @ref LL_HRTIM_TIMER_MASTER
4366 * @arg @ref LL_HRTIM_TIMER_A
4367 * @arg @ref LL_HRTIM_TIMER_B
4368 * @arg @ref LL_HRTIM_TIMER_C
4369 * @arg @ref LL_HRTIM_TIMER_D
4370 * @arg @ref LL_HRTIM_TIMER_E
4371 * @param BurtsModeOption This parameter can be one of the following values:
4372 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4373 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4374 * @retval None
4375 */
LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t BurtsModeOption)4376 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
4377 {
4378 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
4379 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
4380 }
4381
4382 /**
4383 * @brief Retrieve how the timer behaves during a burst mode operation.
4384 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
4385 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
4386 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
4387 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
4388 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
4389 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
4390 * @param HRTIMx High Resolution Timer instance
4391 * @param Timer This parameter can be one of the following values:
4392 * @arg @ref LL_HRTIM_TIMER_MASTER
4393 * @arg @ref LL_HRTIM_TIMER_A
4394 * @arg @ref LL_HRTIM_TIMER_B
4395 * @arg @ref LL_HRTIM_TIMER_C
4396 * @arg @ref LL_HRTIM_TIMER_D
4397 * @arg @ref LL_HRTIM_TIMER_E
4398 * @retval BurtsMode This parameter can be one of the following values:
4399 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4400 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4401 */
LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4402 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4403 {
4404 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
4405 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
4406 }
4407
4408 /**
4409 * @brief Program which registers are to be written by Burst DMA transfers.
4410 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
4411 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
4412 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4413 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4414 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
4415 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
4416 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4417 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4418 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4419 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4420 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
4421 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
4422 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4423 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4424 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
4425 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
4426 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4427 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4428 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4429 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4430 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
4431 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
4432 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
4433 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
4434 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
4435 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
4436 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
4437 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
4438 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
4439 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
4440 * @param HRTIMx High Resolution Timer instance
4441 * @param Timer This parameter can be one of the following values:
4442 * @arg @ref LL_HRTIM_TIMER_MASTER
4443 * @arg @ref LL_HRTIM_TIMER_A
4444 * @arg @ref LL_HRTIM_TIMER_B
4445 * @arg @ref LL_HRTIM_TIMER_C
4446 * @arg @ref LL_HRTIM_TIMER_D
4447 * @arg @ref LL_HRTIM_TIMER_E
4448 * @param Registers Registers to be updated by the DMA request
4449 *
4450 * For Master timer this parameter can be can be a combination of the following values:
4451 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4452 * @arg @ref LL_HRTIM_BURSTDMA_MCR
4453 * @arg @ref LL_HRTIM_BURSTDMA_MICR
4454 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
4455 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
4456 * @arg @ref LL_HRTIM_BURSTDMA_MPER
4457 * @arg @ref LL_HRTIM_BURSTDMA_MREP
4458 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
4459 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
4460 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
4461 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
4462 *
4463 * For Timers A..E this parameter can be can be a combination of the following values:
4464 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4465 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
4466 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
4467 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
4468 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
4469 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
4470 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
4471 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
4472 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
4473 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
4474 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
4475 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
4476 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
4477 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
4478 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
4479 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
4480 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
4481 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
4482 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
4483 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
4484 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
4485 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
4486 * @retval None
4487 */
LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Registers)4488 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
4489 {
4490
4491 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4492 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
4493 WRITE_REG(*pReg, Registers);
4494 }
4495
4496 /**
4497 * @brief Indicate on which output the signal is currently applied.
4498 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
4499 * @note Only significant when the timer operates in push-pull mode.
4500 * @param HRTIMx High Resolution Timer instance
4501 * @param Timer This parameter can be one of the following values:
4502 * @arg @ref LL_HRTIM_TIMER_A
4503 * @arg @ref LL_HRTIM_TIMER_B
4504 * @arg @ref LL_HRTIM_TIMER_C
4505 * @arg @ref LL_HRTIM_TIMER_D
4506 * @arg @ref LL_HRTIM_TIMER_E
4507 * @retval CPPSTAT This parameter can be one of the following values:
4508 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
4509 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
4510 */
LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4511 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4512 {
4513 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4514 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4515 REG_OFFSET_TAB_TIMER[iTimer]));
4516 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
4517 }
4518
4519 /**
4520 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
4521 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
4522 * @param HRTIMx High Resolution Timer instance
4523 * @param Timer This parameter can be one of the following values:
4524 * @arg @ref LL_HRTIM_TIMER_A
4525 * @arg @ref LL_HRTIM_TIMER_B
4526 * @arg @ref LL_HRTIM_TIMER_C
4527 * @arg @ref LL_HRTIM_TIMER_D
4528 * @arg @ref LL_HRTIM_TIMER_E
4529 * @retval IPPSTAT This parameter can be one of the following values:
4530 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
4531 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
4532 */
LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4533 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4534 {
4535 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4536 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4537 REG_OFFSET_TAB_TIMER[iTimer]));
4538 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
4539 }
4540
4541 /**
4542 * @brief Set the event filter for a given timer.
4543 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
4544 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
4545 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
4546 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
4547 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
4548 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
4549 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
4550 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
4551 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
4552 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
4553 * @note This function must not be called when the timer counter is enabled.
4554 * @param HRTIMx High Resolution Timer instance
4555 * @param Timer This parameter can be one of the following values:
4556 * @arg @ref LL_HRTIM_TIMER_A
4557 * @arg @ref LL_HRTIM_TIMER_B
4558 * @arg @ref LL_HRTIM_TIMER_C
4559 * @arg @ref LL_HRTIM_TIMER_D
4560 * @arg @ref LL_HRTIM_TIMER_E
4561 * @param Event This parameter can be one of the following values:
4562 * @arg @ref LL_HRTIM_EVENT_1
4563 * @arg @ref LL_HRTIM_EVENT_2
4564 * @arg @ref LL_HRTIM_EVENT_3
4565 * @arg @ref LL_HRTIM_EVENT_4
4566 * @arg @ref LL_HRTIM_EVENT_5
4567 * @arg @ref LL_HRTIM_EVENT_6
4568 * @arg @ref LL_HRTIM_EVENT_7
4569 * @arg @ref LL_HRTIM_EVENT_8
4570 * @arg @ref LL_HRTIM_EVENT_9
4571 * @arg @ref LL_HRTIM_EVENT_10
4572 * @param Filter This parameter can be one of the following values:
4573 * @arg @ref LL_HRTIM_EEFLTR_NONE
4574 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4575 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4576 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4577 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4578 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4579 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4580 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4581 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4582 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4583 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4584 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4585 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4586 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4587 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4588 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4589
4590 * @retval None
4591 */
LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t Filter)4592 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
4593 {
4594 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4595 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4596 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4597 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4598 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
4599 }
4600
4601 /**
4602 * @brief Get actual event filter settings for a given timer.
4603 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
4604 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
4605 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
4606 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
4607 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
4608 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
4609 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
4610 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
4611 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
4612 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
4613 * @param HRTIMx High Resolution Timer instance
4614 * @param Timer This parameter can be one of the following values:
4615 * @arg @ref LL_HRTIM_TIMER_A
4616 * @arg @ref LL_HRTIM_TIMER_B
4617 * @arg @ref LL_HRTIM_TIMER_C
4618 * @arg @ref LL_HRTIM_TIMER_D
4619 * @arg @ref LL_HRTIM_TIMER_E
4620 * @param Event This parameter can be one of the following values:
4621 * @arg @ref LL_HRTIM_EVENT_1
4622 * @arg @ref LL_HRTIM_EVENT_2
4623 * @arg @ref LL_HRTIM_EVENT_3
4624 * @arg @ref LL_HRTIM_EVENT_4
4625 * @arg @ref LL_HRTIM_EVENT_5
4626 * @arg @ref LL_HRTIM_EVENT_6
4627 * @arg @ref LL_HRTIM_EVENT_7
4628 * @arg @ref LL_HRTIM_EVENT_8
4629 * @arg @ref LL_HRTIM_EVENT_9
4630 * @arg @ref LL_HRTIM_EVENT_10
4631 * @retval Filter This parameter can be one of the following values:
4632 * @arg @ref LL_HRTIM_EEFLTR_NONE
4633 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4634 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4635 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4636 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4637 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4638 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4639 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4640 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4641 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4642 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4643 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4644 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4645 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4646 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4647 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4648 */
LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)4649 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4650 {
4651 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4652 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4653 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4654 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4655 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4656 }
4657
4658 /**
4659 * @brief Enable or disable event latch mechanism for a given timer.
4660 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4661 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4662 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4663 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4664 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4665 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4666 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4667 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4668 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4669 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
4670 * @note This function must not be called when the timer counter is enabled.
4671 * @param HRTIMx High Resolution Timer instance
4672 * @param Timer This parameter can be one of the following values:
4673 * @arg @ref LL_HRTIM_TIMER_A
4674 * @arg @ref LL_HRTIM_TIMER_B
4675 * @arg @ref LL_HRTIM_TIMER_C
4676 * @arg @ref LL_HRTIM_TIMER_D
4677 * @arg @ref LL_HRTIM_TIMER_E
4678 * @param Event This parameter can be one of the following values:
4679 * @arg @ref LL_HRTIM_EVENT_1
4680 * @arg @ref LL_HRTIM_EVENT_2
4681 * @arg @ref LL_HRTIM_EVENT_3
4682 * @arg @ref LL_HRTIM_EVENT_4
4683 * @arg @ref LL_HRTIM_EVENT_5
4684 * @arg @ref LL_HRTIM_EVENT_6
4685 * @arg @ref LL_HRTIM_EVENT_7
4686 * @arg @ref LL_HRTIM_EVENT_8
4687 * @arg @ref LL_HRTIM_EVENT_9
4688 * @arg @ref LL_HRTIM_EVENT_10
4689 * @param LatchStatus This parameter can be one of the following values:
4690 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4691 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4692 * @retval None
4693 */
LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t LatchStatus)4694 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
4695 uint32_t LatchStatus)
4696 {
4697 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4698 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4699 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4700 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4701 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
4702 }
4703
4704 /**
4705 * @brief Get actual event latch status for a given timer.
4706 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4707 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4708 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4709 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4710 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4711 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4712 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4713 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4714 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4715 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
4716 * @param HRTIMx High Resolution Timer instance
4717 * @param Timer This parameter can be one of the following values:
4718 * @arg @ref LL_HRTIM_TIMER_A
4719 * @arg @ref LL_HRTIM_TIMER_B
4720 * @arg @ref LL_HRTIM_TIMER_C
4721 * @arg @ref LL_HRTIM_TIMER_D
4722 * @arg @ref LL_HRTIM_TIMER_E
4723 * @param Event This parameter can be one of the following values:
4724 * @arg @ref LL_HRTIM_EVENT_1
4725 * @arg @ref LL_HRTIM_EVENT_2
4726 * @arg @ref LL_HRTIM_EVENT_3
4727 * @arg @ref LL_HRTIM_EVENT_4
4728 * @arg @ref LL_HRTIM_EVENT_5
4729 * @arg @ref LL_HRTIM_EVENT_6
4730 * @arg @ref LL_HRTIM_EVENT_7
4731 * @arg @ref LL_HRTIM_EVENT_8
4732 * @arg @ref LL_HRTIM_EVENT_9
4733 * @arg @ref LL_HRTIM_EVENT_10
4734 * @retval LatchStatus This parameter can be one of the following values:
4735 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4736 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4737 */
LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)4738 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4739 {
4740 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4741 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4742 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4743 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4744 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4745 }
4746
4747 /**
4748 * @}
4749 */
4750
4751 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
4752 * @{
4753 */
4754
4755 /**
4756 * @brief Configure the dead time insertion feature for a given timer.
4757 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
4758 * DTxR SDTF LL_HRTIM_DT_Config\n
4759 * DTxR SDRT LL_HRTIM_DT_Config
4760 * @param HRTIMx High Resolution Timer instance
4761 * @param Timer This parameter can be one of the following values:
4762 * @arg @ref LL_HRTIM_TIMER_A
4763 * @arg @ref LL_HRTIM_TIMER_B
4764 * @arg @ref LL_HRTIM_TIMER_C
4765 * @arg @ref LL_HRTIM_TIMER_D
4766 * @arg @ref LL_HRTIM_TIMER_E
4767 * @param Configuration This parameter must be a combination of all the following values:
4768 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
4769 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
4770 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
4771 * @retval None
4772 */
LL_HRTIM_DT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)4773 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
4774 {
4775 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4776 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4777 REG_OFFSET_TAB_TIMER[iTimer]));
4778 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
4779 }
4780
4781 /**
4782 * @brief Set the deadtime prescaler value.
4783 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
4784 * @param HRTIMx High Resolution Timer instance
4785 * @param Timer This parameter can be one of the following values:
4786 * @arg @ref LL_HRTIM_TIMER_A
4787 * @arg @ref LL_HRTIM_TIMER_B
4788 * @arg @ref LL_HRTIM_TIMER_C
4789 * @arg @ref LL_HRTIM_TIMER_D
4790 * @arg @ref LL_HRTIM_TIMER_E
4791 * @param Prescaler This parameter can be one of the following values:
4792 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4793 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4794 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4795 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4796 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4797 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4798 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4799 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4800 * @retval None
4801 */
LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)4802 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
4803 {
4804 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4805 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4806 REG_OFFSET_TAB_TIMER[iTimer]));
4807 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
4808 }
4809
4810 /**
4811 * @brief Get actual deadtime prescaler value.
4812 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
4813 * @param HRTIMx High Resolution Timer instance
4814 * @param Timer This parameter can be one of the following values:
4815 * @arg @ref LL_HRTIM_TIMER_A
4816 * @arg @ref LL_HRTIM_TIMER_B
4817 * @arg @ref LL_HRTIM_TIMER_C
4818 * @arg @ref LL_HRTIM_TIMER_D
4819 * @arg @ref LL_HRTIM_TIMER_E
4820 * @retval Prescaler This parameter can be one of the following values:
4821 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4822 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4823 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4824 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4825 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4826 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4827 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4828 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4829 */
LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4830 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4831 {
4832 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4833 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4834 REG_OFFSET_TAB_TIMER[iTimer]));
4835 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
4836 }
4837
4838 /**
4839 * @brief Set the deadtime rising value.
4840 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
4841 * @param HRTIMx High Resolution Timer instance
4842 * @param Timer This parameter can be one of the following values:
4843 * @arg @ref LL_HRTIM_TIMER_A
4844 * @arg @ref LL_HRTIM_TIMER_B
4845 * @arg @ref LL_HRTIM_TIMER_C
4846 * @arg @ref LL_HRTIM_TIMER_D
4847 * @arg @ref LL_HRTIM_TIMER_E
4848 * @param RisingValue Value between 0 and 0x1FF
4849 * @retval None
4850 */
LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingValue)4851 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
4852 {
4853 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4854 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4855 REG_OFFSET_TAB_TIMER[iTimer]));
4856 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
4857 }
4858
4859 /**
4860 * @brief Get actual deadtime rising value.
4861 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
4862 * @param HRTIMx High Resolution Timer instance
4863 * @param Timer This parameter can be one of the following values:
4864 * @arg @ref LL_HRTIM_TIMER_A
4865 * @arg @ref LL_HRTIM_TIMER_B
4866 * @arg @ref LL_HRTIM_TIMER_C
4867 * @arg @ref LL_HRTIM_TIMER_D
4868 * @arg @ref LL_HRTIM_TIMER_E
4869 * @retval RisingValue Value between 0 and 0x1FF
4870 */
LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4871 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4872 {
4873 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4874 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4875 REG_OFFSET_TAB_TIMER[iTimer]));
4876 return (READ_BIT(*pReg, HRTIM_DTR_DTR));
4877 }
4878
4879 /**
4880 * @brief Set the deadtime sign on rising edge.
4881 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
4882 * @param HRTIMx High Resolution Timer instance
4883 * @param Timer This parameter can be one of the following values:
4884 * @arg @ref LL_HRTIM_TIMER_A
4885 * @arg @ref LL_HRTIM_TIMER_B
4886 * @arg @ref LL_HRTIM_TIMER_C
4887 * @arg @ref LL_HRTIM_TIMER_D
4888 * @arg @ref LL_HRTIM_TIMER_E
4889 * @param RisingSign This parameter can be one of the following values:
4890 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4891 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4892 * @retval None
4893 */
LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingSign)4894 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
4895 {
4896 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4897 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4898 REG_OFFSET_TAB_TIMER[iTimer]));
4899 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
4900 }
4901
4902 /**
4903 * @brief Get actual deadtime sign on rising edge.
4904 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
4905 * @param HRTIMx High Resolution Timer instance
4906 * @param Timer This parameter can be one of the following values:
4907 * @arg @ref LL_HRTIM_TIMER_A
4908 * @arg @ref LL_HRTIM_TIMER_B
4909 * @arg @ref LL_HRTIM_TIMER_C
4910 * @arg @ref LL_HRTIM_TIMER_D
4911 * @arg @ref LL_HRTIM_TIMER_E
4912 * @retval RisingSign This parameter can be one of the following values:
4913 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4914 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4915 */
LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4916 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4917 {
4918 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4919 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4920 REG_OFFSET_TAB_TIMER[iTimer]));
4921 return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
4922 }
4923
4924 /**
4925 * @brief Set the deadime falling value.
4926 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
4927 * @param HRTIMx High Resolution Timer instance
4928 * @param Timer This parameter can be one of the following values:
4929 * @arg @ref LL_HRTIM_TIMER_A
4930 * @arg @ref LL_HRTIM_TIMER_B
4931 * @arg @ref LL_HRTIM_TIMER_C
4932 * @arg @ref LL_HRTIM_TIMER_D
4933 * @arg @ref LL_HRTIM_TIMER_E
4934 * @param FallingValue Value between 0 and 0x1FF
4935 * @retval None
4936 */
LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingValue)4937 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
4938 {
4939 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4941 REG_OFFSET_TAB_TIMER[iTimer]));
4942 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
4943 }
4944
4945 /**
4946 * @brief Get actual deadtime falling value
4947 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
4948 * @param HRTIMx High Resolution Timer instance
4949 * @param Timer This parameter can be one of the following values:
4950 * @arg @ref LL_HRTIM_TIMER_A
4951 * @arg @ref LL_HRTIM_TIMER_B
4952 * @arg @ref LL_HRTIM_TIMER_C
4953 * @arg @ref LL_HRTIM_TIMER_D
4954 * @arg @ref LL_HRTIM_TIMER_E
4955 * @retval FallingValue Value between 0 and 0x1FF
4956 */
LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4957 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4958 {
4959 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4960 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4961 REG_OFFSET_TAB_TIMER[iTimer]));
4962 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
4963 }
4964
4965 /**
4966 * @brief Set the deadtime sign on falling edge.
4967 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
4968 * @param HRTIMx High Resolution Timer instance
4969 * @param Timer This parameter can be one of the following values:
4970 * @arg @ref LL_HRTIM_TIMER_A
4971 * @arg @ref LL_HRTIM_TIMER_B
4972 * @arg @ref LL_HRTIM_TIMER_C
4973 * @arg @ref LL_HRTIM_TIMER_D
4974 * @arg @ref LL_HRTIM_TIMER_E
4975 * @param FallingSign This parameter can be one of the following values:
4976 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
4977 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
4978 * @retval None
4979 */
LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingSign)4980 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
4981 {
4982 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4983 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4984 REG_OFFSET_TAB_TIMER[iTimer]));
4985 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
4986 }
4987
4988 /**
4989 * @brief Get actual deadtime sign on falling edge.
4990 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
4991 * @param HRTIMx High Resolution Timer instance
4992 * @param Timer This parameter can be one of the following values:
4993 * @arg @ref LL_HRTIM_TIMER_A
4994 * @arg @ref LL_HRTIM_TIMER_B
4995 * @arg @ref LL_HRTIM_TIMER_C
4996 * @arg @ref LL_HRTIM_TIMER_D
4997 * @arg @ref LL_HRTIM_TIMER_E
4998 * @retval FallingSign This parameter can be one of the following values:
4999 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
5000 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
5001 */
LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5002 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5003 {
5004 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5005 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5006 REG_OFFSET_TAB_TIMER[iTimer]));
5007 return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
5008 }
5009
5010 /**
5011 * @brief Lock the deadtime value and sign on rising edge.
5012 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
5013 * @param HRTIMx High Resolution Timer instance
5014 * @param Timer This parameter can be one of the following values:
5015 * @arg @ref LL_HRTIM_TIMER_A
5016 * @arg @ref LL_HRTIM_TIMER_B
5017 * @arg @ref LL_HRTIM_TIMER_C
5018 * @arg @ref LL_HRTIM_TIMER_D
5019 * @arg @ref LL_HRTIM_TIMER_E
5020 * @retval None
5021 */
LL_HRTIM_DT_LockRising(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5022 __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5023 {
5024 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5025 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5026 REG_OFFSET_TAB_TIMER[iTimer]));
5027 SET_BIT(*pReg, HRTIM_DTR_DTRLK);
5028 }
5029
5030 /**
5031 * @brief Lock the deadtime sign on rising edge.
5032 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
5033 * @param HRTIMx High Resolution Timer instance
5034 * @param Timer This parameter can be one of the following values:
5035 * @arg @ref LL_HRTIM_TIMER_A
5036 * @arg @ref LL_HRTIM_TIMER_B
5037 * @arg @ref LL_HRTIM_TIMER_C
5038 * @arg @ref LL_HRTIM_TIMER_D
5039 * @arg @ref LL_HRTIM_TIMER_E
5040 * @retval None
5041 */
LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5042 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5043 {
5044 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5045 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5046 REG_OFFSET_TAB_TIMER[iTimer]));
5047 SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
5048 }
5049
5050 /**
5051 * @brief Lock the deadtime value and sign on falling edge.
5052 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
5053 * @param HRTIMx High Resolution Timer instance
5054 * @param Timer This parameter can be one of the following values:
5055 * @arg @ref LL_HRTIM_TIMER_A
5056 * @arg @ref LL_HRTIM_TIMER_B
5057 * @arg @ref LL_HRTIM_TIMER_C
5058 * @arg @ref LL_HRTIM_TIMER_D
5059 * @arg @ref LL_HRTIM_TIMER_E
5060 * @retval None
5061 */
LL_HRTIM_DT_LockFalling(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5062 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5063 {
5064 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5065 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5066 REG_OFFSET_TAB_TIMER[iTimer]));
5067 SET_BIT(*pReg, HRTIM_DTR_DTFLK);
5068 }
5069
5070 /**
5071 * @brief Lock the deadtime sign on falling edge.
5072 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
5073 * @param HRTIMx High Resolution Timer instance
5074 * @param Timer This parameter can be one of the following values:
5075 * @arg @ref LL_HRTIM_TIMER_A
5076 * @arg @ref LL_HRTIM_TIMER_B
5077 * @arg @ref LL_HRTIM_TIMER_C
5078 * @arg @ref LL_HRTIM_TIMER_D
5079 * @arg @ref LL_HRTIM_TIMER_E
5080 * @retval None
5081 */
LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5082 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5083 {
5084 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5085 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5086 REG_OFFSET_TAB_TIMER[iTimer]));
5087 SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
5088 }
5089
5090 /**
5091 * @}
5092 */
5093
5094 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
5095 * @{
5096 */
5097
5098 /**
5099 * @brief Configure the chopper stage for a given timer.
5100 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
5101 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
5102 * CHPxR STRTPW LL_HRTIM_CHP_Config
5103 * @note This function must not be called if the chopper mode is already
5104 * enabled for one of the timer outputs.
5105 * @param HRTIMx High Resolution Timer instance
5106 * @param Timer This parameter can be one of the following values:
5107 * @arg @ref LL_HRTIM_TIMER_A
5108 * @arg @ref LL_HRTIM_TIMER_B
5109 * @arg @ref LL_HRTIM_TIMER_C
5110 * @arg @ref LL_HRTIM_TIMER_D
5111 * @arg @ref LL_HRTIM_TIMER_E
5112 * @param Configuration This parameter must be a combination of all the following values:
5113 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
5114 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
5115 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
5116 * @retval None
5117 */
LL_HRTIM_CHP_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)5118 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
5119 {
5120 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5121 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5122 REG_OFFSET_TAB_TIMER[iTimer]));
5123 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
5124 }
5125
5126 /**
5127 * @brief Set prescaler determining the carrier frequency to be added on top
5128 * of the timer output signals when chopper mode is enabled.
5129 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
5130 * @note This function must not be called if the chopper mode is already
5131 * enabled for one of the timer outputs.
5132 * @param HRTIMx High Resolution Timer instance
5133 * @param Timer This parameter can be one of the following values:
5134 * @arg @ref LL_HRTIM_TIMER_A
5135 * @arg @ref LL_HRTIM_TIMER_B
5136 * @arg @ref LL_HRTIM_TIMER_C
5137 * @arg @ref LL_HRTIM_TIMER_D
5138 * @arg @ref LL_HRTIM_TIMER_E
5139 * @param Prescaler This parameter can be one of the following values:
5140 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5141 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5142 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5143 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5144 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5145 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5146 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5147 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5148 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5149 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5150 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5151 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5152 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5153 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5154 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5155 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5156 * @retval None
5157 */
LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)5158 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
5159 {
5160 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5161 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5162 REG_OFFSET_TAB_TIMER[iTimer]));
5163 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
5164 }
5165
5166 /**
5167 * @brief Get actual chopper stage prescaler value.
5168 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
5169 * @param HRTIMx High Resolution Timer instance
5170 * @param Timer This parameter can be one of the following values:
5171 * @arg @ref LL_HRTIM_TIMER_A
5172 * @arg @ref LL_HRTIM_TIMER_B
5173 * @arg @ref LL_HRTIM_TIMER_C
5174 * @arg @ref LL_HRTIM_TIMER_D
5175 * @arg @ref LL_HRTIM_TIMER_E
5176 * @retval Prescaler This parameter can be one of the following values:
5177 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5178 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5179 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5180 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5181 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5182 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5183 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5184 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5185 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5186 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5187 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5188 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5189 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5190 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5191 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5192 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5193 */
LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5194 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5195 {
5196 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5197 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5198 REG_OFFSET_TAB_TIMER[iTimer]));
5199 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
5200 }
5201
5202 /**
5203 * @brief Set the chopper duty cycle.
5204 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
5205 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
5206 * @note This function must not be called if the chopper mode is already
5207 * enabled for one of the timer outputs.
5208 * @param HRTIMx High Resolution Timer instance
5209 * @param Timer This parameter can be one of the following values:
5210 * @arg @ref LL_HRTIM_TIMER_A
5211 * @arg @ref LL_HRTIM_TIMER_B
5212 * @arg @ref LL_HRTIM_TIMER_C
5213 * @arg @ref LL_HRTIM_TIMER_D
5214 * @arg @ref LL_HRTIM_TIMER_E
5215 * @param DutyCycle This parameter can be one of the following values:
5216 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5217 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5218 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5219 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5220 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5221 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5222 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5223 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5224 * @retval None
5225 */
LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DutyCycle)5226 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
5227 {
5228 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5229 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5230 REG_OFFSET_TAB_TIMER[iTimer]));
5231 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
5232 }
5233
5234 /**
5235 * @brief Get actual chopper duty cycle.
5236 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
5237 * @param HRTIMx High Resolution Timer instance
5238 * @param Timer This parameter can be one of the following values:
5239 * @arg @ref LL_HRTIM_TIMER_A
5240 * @arg @ref LL_HRTIM_TIMER_B
5241 * @arg @ref LL_HRTIM_TIMER_C
5242 * @arg @ref LL_HRTIM_TIMER_D
5243 * @arg @ref LL_HRTIM_TIMER_E
5244 * @retval DutyCycle This parameter can be one of the following values:
5245 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5246 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5247 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5248 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5249 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5250 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5251 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5252 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5253 */
LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5254 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5255 {
5256 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5257 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5258 REG_OFFSET_TAB_TIMER[iTimer]));
5259 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
5260 }
5261
5262 /**
5263 * @brief Set the start pulse width.
5264 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
5265 * @note This function must not be called if the chopper mode is already
5266 * enabled for one of the timer outputs.
5267 * @param HRTIMx High Resolution Timer instance
5268 * @param Timer This parameter can be one of the following values:
5269 * @arg @ref LL_HRTIM_TIMER_A
5270 * @arg @ref LL_HRTIM_TIMER_B
5271 * @arg @ref LL_HRTIM_TIMER_C
5272 * @arg @ref LL_HRTIM_TIMER_D
5273 * @arg @ref LL_HRTIM_TIMER_E
5274 * @param PulseWidth This parameter can be one of the following values:
5275 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5276 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5277 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5278 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5279 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5280 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5281 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5282 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5283 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5284 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5285 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5286 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5287 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5288 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5289 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5290 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5291 * @retval None
5292 */
LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t PulseWidth)5293 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
5294 {
5295 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5296 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5297 REG_OFFSET_TAB_TIMER[iTimer]));
5298 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
5299 }
5300
5301 /**
5302 * @brief Get actual start pulse width.
5303 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
5304 * @param HRTIMx High Resolution Timer instance
5305 * @param Timer This parameter can be one of the following values:
5306 * @arg @ref LL_HRTIM_TIMER_A
5307 * @arg @ref LL_HRTIM_TIMER_B
5308 * @arg @ref LL_HRTIM_TIMER_C
5309 * @arg @ref LL_HRTIM_TIMER_D
5310 * @arg @ref LL_HRTIM_TIMER_E
5311 * @retval PulseWidth This parameter can be one of the following values:
5312 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5313 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5314 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5315 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5316 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5317 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5318 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5319 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5320 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5321 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5322 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5323 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5324 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5325 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5326 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5327 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5328 */
LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5329 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5330 {
5331 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5332 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5333 REG_OFFSET_TAB_TIMER[iTimer]));
5334 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
5335 }
5336
5337 /**
5338 * @}
5339 */
5340
5341 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
5342 * @{
5343 */
5344
5345 /**
5346 * @brief Set the timer output set source.
5347 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5348 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5349 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5350 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5351 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5352 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5353 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5354 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5355 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5356 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5357 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5358 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5359 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5360 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5361 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5362 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5363 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5364 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5365 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5366 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5367 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5368 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5369 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5370 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5371 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5372 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5373 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5374 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5375 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5376 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5377 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5378 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
5379 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5380 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5381 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5382 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5383 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5384 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5385 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5386 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5387 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5388 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5389 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5390 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5391 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5392 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5393 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5394 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5395 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5396 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5397 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5398 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5399 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5400 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5401 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5402 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5403 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5404 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5405 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5406 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5407 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5408 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5409 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5410 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
5411 * @param HRTIMx High Resolution Timer instance
5412 * @param Output This parameter can be one of the following values:
5413 * @arg @ref LL_HRTIM_OUTPUT_TA1
5414 * @arg @ref LL_HRTIM_OUTPUT_TA2
5415 * @arg @ref LL_HRTIM_OUTPUT_TB1
5416 * @arg @ref LL_HRTIM_OUTPUT_TB2
5417 * @arg @ref LL_HRTIM_OUTPUT_TC1
5418 * @arg @ref LL_HRTIM_OUTPUT_TC2
5419 * @arg @ref LL_HRTIM_OUTPUT_TD1
5420 * @arg @ref LL_HRTIM_OUTPUT_TD2
5421 * @arg @ref LL_HRTIM_OUTPUT_TE1
5422 * @arg @ref LL_HRTIM_OUTPUT_TE2
5423 * @param SetSrc This parameter can be a combination of the following values:
5424 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5425 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5426 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5427 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5428 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5429 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5430 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5431 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5432 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5433 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5434 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5435 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5436 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5437 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5438 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5439 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5440 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5441 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5442 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5443 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5444 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5445 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5446 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5447 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5448 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5449 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5450 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5451 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5452 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5453 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5454 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5455 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5456 * @retval None
5457 */
LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t SetSrc)5458 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
5459 {
5460 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5461 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5462 REG_OFFSET_TAB_SETxR[iOutput]));
5463 WRITE_REG(*pReg, SetSrc);
5464 }
5465
5466 /**
5467 * @brief Get the timer output set source.
5468 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5469 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5470 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5471 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5472 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5473 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5474 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5475 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5476 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5477 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5478 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5479 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5480 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5481 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5482 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5483 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5484 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5485 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5486 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5487 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5488 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5489 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5490 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5491 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5492 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5493 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5494 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5495 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5496 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5497 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5498 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5499 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
5500 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5501 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5502 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5503 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5504 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5505 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5506 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5507 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5508 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5509 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5510 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5511 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5512 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5513 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5514 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5515 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5516 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5517 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5518 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5519 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5520 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5521 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5522 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5523 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5524 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5525 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5526 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5527 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5528 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5529 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5530 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5531 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
5532 * @param HRTIMx High Resolution Timer instance
5533 * @param Output This parameter can be one of the following values:
5534 * @arg @ref LL_HRTIM_OUTPUT_TA1
5535 * @arg @ref LL_HRTIM_OUTPUT_TA2
5536 * @arg @ref LL_HRTIM_OUTPUT_TB1
5537 * @arg @ref LL_HRTIM_OUTPUT_TB2
5538 * @arg @ref LL_HRTIM_OUTPUT_TC1
5539 * @arg @ref LL_HRTIM_OUTPUT_TC2
5540 * @arg @ref LL_HRTIM_OUTPUT_TD1
5541 * @arg @ref LL_HRTIM_OUTPUT_TD2
5542 * @arg @ref LL_HRTIM_OUTPUT_TE1
5543 * @arg @ref LL_HRTIM_OUTPUT_TE2
5544 * @retval SetSrc This parameter can be a combination of the following values:
5545 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5546 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5547 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5548 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5549 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5550 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5551 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5552 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5553 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5554 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5555 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5556 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5557 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5558 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5559 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5560 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5561 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5562 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5563 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5564 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5565 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5566 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5567 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5568 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5569 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5570 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5571 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5572 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5573 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5574 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5575 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5576 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5577 */
LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5578 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5579 {
5580 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5581 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5582 REG_OFFSET_TAB_SETxR[iOutput]));
5583 return (uint32_t) READ_REG(*pReg);
5584 }
5585
5586 /**
5587 * @brief Set the timer output reset source.
5588 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5589 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5590 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5591 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5592 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5593 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5594 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5595 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5596 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5597 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5598 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5599 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5600 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5601 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5602 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5603 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5604 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5605 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5606 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5607 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5608 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5609 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5610 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5611 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5612 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5613 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5614 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5615 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5616 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5617 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5618 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5619 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
5620 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5621 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5622 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5623 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5624 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5625 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5626 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5627 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5628 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5629 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5630 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5631 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5632 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5633 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5634 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5635 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5636 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5637 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5638 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5639 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5640 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5641 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5642 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5643 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5644 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5645 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5646 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5647 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5648 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5649 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5650 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5651 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
5652 * @param HRTIMx High Resolution Timer instance
5653 * @param Output This parameter can be one of the following values:
5654 * @arg @ref LL_HRTIM_OUTPUT_TA1
5655 * @arg @ref LL_HRTIM_OUTPUT_TA2
5656 * @arg @ref LL_HRTIM_OUTPUT_TB1
5657 * @arg @ref LL_HRTIM_OUTPUT_TB2
5658 * @arg @ref LL_HRTIM_OUTPUT_TC1
5659 * @arg @ref LL_HRTIM_OUTPUT_TC2
5660 * @arg @ref LL_HRTIM_OUTPUT_TD1
5661 * @arg @ref LL_HRTIM_OUTPUT_TD2
5662 * @arg @ref LL_HRTIM_OUTPUT_TE1
5663 * @arg @ref LL_HRTIM_OUTPUT_TE2
5664 * @param ResetSrc This parameter can be a combination of the following values:
5665 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5666 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5667 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5668 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5669 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5670 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5671 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5672 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5673 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5674 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5675 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5676 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5677 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5678 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5679 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5680 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5681 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5682 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5683 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5684 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5685 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5686 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5687 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5688 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5689 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5690 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5691 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5692 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5693 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5694 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5695 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5696 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5697 * @retval None
5698 */
LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ResetSrc)5699 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
5700 {
5701 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5702 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5703 REG_OFFSET_TAB_SETxR[iOutput]));
5704 WRITE_REG(*pReg, ResetSrc);
5705 }
5706
5707 /**
5708 * @brief Get the timer output set source.
5709 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5710 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5711 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5712 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5713 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5714 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5715 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5716 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5717 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5718 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5719 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5720 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5721 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5722 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5723 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5724 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5725 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5726 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5727 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5728 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5729 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5730 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5731 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5732 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5733 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5734 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5735 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5736 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5737 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5738 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5739 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5740 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
5741 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5742 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5743 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5744 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5745 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5746 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5747 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5748 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5749 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5750 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5751 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5752 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5753 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5754 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5755 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5756 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5757 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5758 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5759 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5760 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5761 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5762 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5763 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5764 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5765 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5766 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5767 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5768 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5769 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5770 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5771 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5772 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
5773 * @param HRTIMx High Resolution Timer instance
5774 * @param Output This parameter can be one of the following values:
5775 * @arg @ref LL_HRTIM_OUTPUT_TA1
5776 * @arg @ref LL_HRTIM_OUTPUT_TA2
5777 * @arg @ref LL_HRTIM_OUTPUT_TB1
5778 * @arg @ref LL_HRTIM_OUTPUT_TB2
5779 * @arg @ref LL_HRTIM_OUTPUT_TC1
5780 * @arg @ref LL_HRTIM_OUTPUT_TC2
5781 * @arg @ref LL_HRTIM_OUTPUT_TD1
5782 * @arg @ref LL_HRTIM_OUTPUT_TD2
5783 * @arg @ref LL_HRTIM_OUTPUT_TE1
5784 * @arg @ref LL_HRTIM_OUTPUT_TE2
5785 * @retval ResetSrc This parameter can be a combination of the following values:
5786 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5787 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5788 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5789 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5790 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5791 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5792 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5793 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5794 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5795 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5796 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5797 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5798 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5799 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5800 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5801 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5802 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5803 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5804 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5805 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5806 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5807 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5808 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5809 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5810 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5811 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5812 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5813 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5814 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5815 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5816 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5817 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5818 */
LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5819 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5820 {
5821 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5822 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5823 REG_OFFSET_TAB_SETxR[iOutput]));
5824 return (uint32_t) READ_REG(*pReg);
5825 }
5826
5827 /**
5828 * @brief Configure a timer output.
5829 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
5830 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
5831 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
5832 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
5833 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
5834 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
5835 * OUTxR POL2 LL_HRTIM_OUT_Config\n
5836 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
5837 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
5838 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
5839 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
5840 * OUTxR DIDL2 LL_HRTIM_OUT_Config
5841 * @param HRTIMx High Resolution Timer instance
5842 * @param Output This parameter can be one of the following values:
5843 * @arg @ref LL_HRTIM_OUTPUT_TA1
5844 * @arg @ref LL_HRTIM_OUTPUT_TA2
5845 * @arg @ref LL_HRTIM_OUTPUT_TB1
5846 * @arg @ref LL_HRTIM_OUTPUT_TB2
5847 * @arg @ref LL_HRTIM_OUTPUT_TC1
5848 * @arg @ref LL_HRTIM_OUTPUT_TC2
5849 * @arg @ref LL_HRTIM_OUTPUT_TD1
5850 * @arg @ref LL_HRTIM_OUTPUT_TD2
5851 * @arg @ref LL_HRTIM_OUTPUT_TE1
5852 * @arg @ref LL_HRTIM_OUTPUT_TE2
5853 * @param Configuration This parameter must be a combination of all the following values:
5854 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5855 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5856 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5857 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
5858 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
5859 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
5860 * @retval None
5861 */
LL_HRTIM_OUT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Configuration)5862 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
5863 {
5864 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5865 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5866 REG_OFFSET_TAB_OUTxR[iOutput]));
5867 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
5868 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
5869 }
5870
5871 /**
5872 * @brief Set the polarity of a timer output.
5873 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
5874 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
5875 * @param HRTIMx High Resolution Timer instance
5876 * @param Output This parameter can be one of the following values:
5877 * @arg @ref LL_HRTIM_OUTPUT_TA1
5878 * @arg @ref LL_HRTIM_OUTPUT_TA2
5879 * @arg @ref LL_HRTIM_OUTPUT_TB1
5880 * @arg @ref LL_HRTIM_OUTPUT_TB2
5881 * @arg @ref LL_HRTIM_OUTPUT_TC1
5882 * @arg @ref LL_HRTIM_OUTPUT_TC2
5883 * @arg @ref LL_HRTIM_OUTPUT_TD1
5884 * @arg @ref LL_HRTIM_OUTPUT_TD2
5885 * @arg @ref LL_HRTIM_OUTPUT_TE1
5886 * @arg @ref LL_HRTIM_OUTPUT_TE2
5887 * @param Polarity This parameter can be one of the following values:
5888 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5889 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5890 * @retval None
5891 */
LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Polarity)5892 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
5893 {
5894 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5895 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5896 REG_OFFSET_TAB_OUTxR[iOutput]));
5897 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
5898 }
5899
5900 /**
5901 * @brief Get actual polarity of the timer output.
5902 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
5903 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
5904 * @param HRTIMx High Resolution Timer instance
5905 * @param Output This parameter can be one of the following values:
5906 * @arg @ref LL_HRTIM_OUTPUT_TA1
5907 * @arg @ref LL_HRTIM_OUTPUT_TA2
5908 * @arg @ref LL_HRTIM_OUTPUT_TB1
5909 * @arg @ref LL_HRTIM_OUTPUT_TB2
5910 * @arg @ref LL_HRTIM_OUTPUT_TC1
5911 * @arg @ref LL_HRTIM_OUTPUT_TC2
5912 * @arg @ref LL_HRTIM_OUTPUT_TD1
5913 * @arg @ref LL_HRTIM_OUTPUT_TD2
5914 * @arg @ref LL_HRTIM_OUTPUT_TE1
5915 * @arg @ref LL_HRTIM_OUTPUT_TE2
5916 * @retval Polarity This parameter can be one of the following values:
5917 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5918 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5919 */
LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5920 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5921 {
5922 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5923 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5924 REG_OFFSET_TAB_OUTxR[iOutput]));
5925 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5926 }
5927
5928 /**
5929 * @brief Set the output IDLE mode.
5930 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
5931 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
5932 * @note This function must not be called when the burst mode is active
5933 * @param HRTIMx High Resolution Timer instance
5934 * @param Output This parameter can be one of the following values:
5935 * @arg @ref LL_HRTIM_OUTPUT_TA1
5936 * @arg @ref LL_HRTIM_OUTPUT_TA2
5937 * @arg @ref LL_HRTIM_OUTPUT_TB1
5938 * @arg @ref LL_HRTIM_OUTPUT_TB2
5939 * @arg @ref LL_HRTIM_OUTPUT_TC1
5940 * @arg @ref LL_HRTIM_OUTPUT_TC2
5941 * @arg @ref LL_HRTIM_OUTPUT_TD1
5942 * @arg @ref LL_HRTIM_OUTPUT_TD2
5943 * @arg @ref LL_HRTIM_OUTPUT_TE1
5944 * @arg @ref LL_HRTIM_OUTPUT_TE2
5945 * @param IdleMode This parameter can be one of the following values:
5946 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5947 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5948 * @retval None
5949 */
LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleMode)5950 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
5951 {
5952 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5953 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5954 REG_OFFSET_TAB_OUTxR[iOutput]));
5955 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
5956 }
5957
5958 /**
5959 * @brief Get actual output IDLE mode.
5960 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
5961 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
5962 * @param HRTIMx High Resolution Timer instance
5963 * @param Output This parameter can be one of the following values:
5964 * @arg @ref LL_HRTIM_OUTPUT_TA1
5965 * @arg @ref LL_HRTIM_OUTPUT_TA2
5966 * @arg @ref LL_HRTIM_OUTPUT_TB1
5967 * @arg @ref LL_HRTIM_OUTPUT_TB2
5968 * @arg @ref LL_HRTIM_OUTPUT_TC1
5969 * @arg @ref LL_HRTIM_OUTPUT_TC2
5970 * @arg @ref LL_HRTIM_OUTPUT_TD1
5971 * @arg @ref LL_HRTIM_OUTPUT_TD2
5972 * @arg @ref LL_HRTIM_OUTPUT_TE1
5973 * @arg @ref LL_HRTIM_OUTPUT_TE2
5974 * @retval IdleMode This parameter can be one of the following values:
5975 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5976 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5977 */
LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5978 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5979 {
5980 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5981 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5982 REG_OFFSET_TAB_OUTxR[iOutput]));
5983 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5984 }
5985
5986 /**
5987 * @brief Set the output IDLE level.
5988 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
5989 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
5990 * @note This function must be called prior enabling the timer.
5991 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
5992 * @param HRTIMx High Resolution Timer instance
5993 * @param Output This parameter can be one of the following values:
5994 * @arg @ref LL_HRTIM_OUTPUT_TA1
5995 * @arg @ref LL_HRTIM_OUTPUT_TA2
5996 * @arg @ref LL_HRTIM_OUTPUT_TB1
5997 * @arg @ref LL_HRTIM_OUTPUT_TB2
5998 * @arg @ref LL_HRTIM_OUTPUT_TC1
5999 * @arg @ref LL_HRTIM_OUTPUT_TC2
6000 * @arg @ref LL_HRTIM_OUTPUT_TD1
6001 * @arg @ref LL_HRTIM_OUTPUT_TD2
6002 * @arg @ref LL_HRTIM_OUTPUT_TE1
6003 * @arg @ref LL_HRTIM_OUTPUT_TE2
6004 * @param IdleLevel This parameter can be one of the following values:
6005 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
6006 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
6007 * @retval None
6008 */
LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleLevel)6009 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
6010 {
6011 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6012 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6013 REG_OFFSET_TAB_OUTxR[iOutput]));
6014 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
6015 }
6016
6017 /**
6018 * @brief Get actual output IDLE level.
6019 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
6020 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
6021 * @param HRTIMx High Resolution Timer instance
6022 * @param Output This parameter can be one of the following values:
6023 * @arg @ref LL_HRTIM_OUTPUT_TA1
6024 * @arg @ref LL_HRTIM_OUTPUT_TA2
6025 * @arg @ref LL_HRTIM_OUTPUT_TB1
6026 * @arg @ref LL_HRTIM_OUTPUT_TB2
6027 * @arg @ref LL_HRTIM_OUTPUT_TC1
6028 * @arg @ref LL_HRTIM_OUTPUT_TC2
6029 * @arg @ref LL_HRTIM_OUTPUT_TD1
6030 * @arg @ref LL_HRTIM_OUTPUT_TD2
6031 * @arg @ref LL_HRTIM_OUTPUT_TE1
6032 * @arg @ref LL_HRTIM_OUTPUT_TE2
6033 * @retval IdleLevel This parameter can be one of the following values:
6034 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
6035 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
6036 */
LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6037 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6038 {
6039 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6040 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6041 REG_OFFSET_TAB_OUTxR[iOutput]));
6042 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6043 }
6044
6045 /**
6046 * @brief Set the output FAULT state.
6047 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
6048 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
6049 * @note This function must not called when the timer is enabled and a fault
6050 * channel is enabled at timer level.
6051 * @param HRTIMx High Resolution Timer instance
6052 * @param Output This parameter can be one of the following values:
6053 * @arg @ref LL_HRTIM_OUTPUT_TA1
6054 * @arg @ref LL_HRTIM_OUTPUT_TA2
6055 * @arg @ref LL_HRTIM_OUTPUT_TB1
6056 * @arg @ref LL_HRTIM_OUTPUT_TB2
6057 * @arg @ref LL_HRTIM_OUTPUT_TC1
6058 * @arg @ref LL_HRTIM_OUTPUT_TC2
6059 * @arg @ref LL_HRTIM_OUTPUT_TD1
6060 * @arg @ref LL_HRTIM_OUTPUT_TD2
6061 * @arg @ref LL_HRTIM_OUTPUT_TE1
6062 * @arg @ref LL_HRTIM_OUTPUT_TE2
6063 * @param FaultState This parameter can be one of the following values:
6064 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
6065 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
6066 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
6067 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
6068 * @retval None
6069 */
LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t FaultState)6070 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
6071 {
6072 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6073 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6074 REG_OFFSET_TAB_OUTxR[iOutput]));
6075 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
6076 }
6077
6078 /**
6079 * @brief Get actual FAULT state.
6080 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
6081 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
6082 * @param HRTIMx High Resolution Timer instance
6083 * @param Output This parameter can be one of the following values:
6084 * @arg @ref LL_HRTIM_OUTPUT_TA1
6085 * @arg @ref LL_HRTIM_OUTPUT_TA2
6086 * @arg @ref LL_HRTIM_OUTPUT_TB1
6087 * @arg @ref LL_HRTIM_OUTPUT_TB2
6088 * @arg @ref LL_HRTIM_OUTPUT_TC1
6089 * @arg @ref LL_HRTIM_OUTPUT_TC2
6090 * @arg @ref LL_HRTIM_OUTPUT_TD1
6091 * @arg @ref LL_HRTIM_OUTPUT_TD2
6092 * @arg @ref LL_HRTIM_OUTPUT_TE1
6093 * @arg @ref LL_HRTIM_OUTPUT_TE2
6094 * @retval FaultState This parameter can be one of the following values:
6095 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
6096 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
6097 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
6098 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
6099 */
LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6100 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6101 {
6102 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6103 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6104 REG_OFFSET_TAB_OUTxR[iOutput]));
6105 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6106 }
6107
6108 /**
6109 * @brief Set the output chopper mode.
6110 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
6111 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
6112 * @note This function must not called when the timer is enabled.
6113 * @param HRTIMx High Resolution Timer instance
6114 * @param Output This parameter can be one of the following values:
6115 * @arg @ref LL_HRTIM_OUTPUT_TA1
6116 * @arg @ref LL_HRTIM_OUTPUT_TA2
6117 * @arg @ref LL_HRTIM_OUTPUT_TB1
6118 * @arg @ref LL_HRTIM_OUTPUT_TB2
6119 * @arg @ref LL_HRTIM_OUTPUT_TC1
6120 * @arg @ref LL_HRTIM_OUTPUT_TC2
6121 * @arg @ref LL_HRTIM_OUTPUT_TD1
6122 * @arg @ref LL_HRTIM_OUTPUT_TD2
6123 * @arg @ref LL_HRTIM_OUTPUT_TE1
6124 * @arg @ref LL_HRTIM_OUTPUT_TE2
6125 * @param ChopperMode This parameter can be one of the following values:
6126 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6127 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6128 * @retval None
6129 */
LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ChopperMode)6130 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
6131 {
6132 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6133 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6134 REG_OFFSET_TAB_OUTxR[iOutput]));
6135 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6136 }
6137
6138 /**
6139 * @brief Get actual output chopper mode
6140 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
6141 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
6142 * @param HRTIMx High Resolution Timer instance
6143 * @param Output This parameter can be one of the following values:
6144 * @arg @ref LL_HRTIM_OUTPUT_TA1
6145 * @arg @ref LL_HRTIM_OUTPUT_TA2
6146 * @arg @ref LL_HRTIM_OUTPUT_TB1
6147 * @arg @ref LL_HRTIM_OUTPUT_TB2
6148 * @arg @ref LL_HRTIM_OUTPUT_TC1
6149 * @arg @ref LL_HRTIM_OUTPUT_TC2
6150 * @arg @ref LL_HRTIM_OUTPUT_TD1
6151 * @arg @ref LL_HRTIM_OUTPUT_TD2
6152 * @arg @ref LL_HRTIM_OUTPUT_TE1
6153 * @arg @ref LL_HRTIM_OUTPUT_TE2
6154 * @retval ChopperMode This parameter can be one of the following values:
6155 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6156 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6157 */
LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6158 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6159 {
6160 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6161 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6162 REG_OFFSET_TAB_OUTxR[iOutput]));
6163 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6164 }
6165
6166 /**
6167 * @brief Set the output burst mode entry mode.
6168 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
6169 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
6170 * @note This function must not called when the timer is enabled.
6171 * @param HRTIMx High Resolution Timer instance
6172 * @param Output This parameter can be one of the following values:
6173 * @arg @ref LL_HRTIM_OUTPUT_TA1
6174 * @arg @ref LL_HRTIM_OUTPUT_TA2
6175 * @arg @ref LL_HRTIM_OUTPUT_TB1
6176 * @arg @ref LL_HRTIM_OUTPUT_TB2
6177 * @arg @ref LL_HRTIM_OUTPUT_TC1
6178 * @arg @ref LL_HRTIM_OUTPUT_TC2
6179 * @arg @ref LL_HRTIM_OUTPUT_TD1
6180 * @arg @ref LL_HRTIM_OUTPUT_TD2
6181 * @arg @ref LL_HRTIM_OUTPUT_TE1
6182 * @arg @ref LL_HRTIM_OUTPUT_TE2
6183 * @param BMEntryMode This parameter can be one of the following values:
6184 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6185 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6186 * @retval None
6187 */
LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t BMEntryMode)6188 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
6189 {
6190 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6191 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6192 REG_OFFSET_TAB_OUTxR[iOutput]));
6193 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6194 }
6195
6196 /**
6197 * @brief Get actual output burst mode entry mode.
6198 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
6199 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
6200 * @param HRTIMx High Resolution Timer instance
6201 * @param Output This parameter can be one of the following values:
6202 * @arg @ref LL_HRTIM_OUTPUT_TA1
6203 * @arg @ref LL_HRTIM_OUTPUT_TA2
6204 * @arg @ref LL_HRTIM_OUTPUT_TB1
6205 * @arg @ref LL_HRTIM_OUTPUT_TB2
6206 * @arg @ref LL_HRTIM_OUTPUT_TC1
6207 * @arg @ref LL_HRTIM_OUTPUT_TC2
6208 * @arg @ref LL_HRTIM_OUTPUT_TD1
6209 * @arg @ref LL_HRTIM_OUTPUT_TD2
6210 * @arg @ref LL_HRTIM_OUTPUT_TE1
6211 * @arg @ref LL_HRTIM_OUTPUT_TE2
6212 * @retval BMEntryMode This parameter can be one of the following values:
6213 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6214 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6215 */
LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6216 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6217 {
6218 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6219 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6220 REG_OFFSET_TAB_OUTxR[iOutput]));
6221 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6222 }
6223
6224 /**
6225 * @brief Get the level (active or inactive) of the designated output when the
6226 * delayed protection was triggered.
6227 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
6228 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
6229 * @param HRTIMx High Resolution Timer instance
6230 * @param Output This parameter can be one of the following values:
6231 * @arg @ref LL_HRTIM_OUTPUT_TA1
6232 * @arg @ref LL_HRTIM_OUTPUT_TA2
6233 * @arg @ref LL_HRTIM_OUTPUT_TB1
6234 * @arg @ref LL_HRTIM_OUTPUT_TB2
6235 * @arg @ref LL_HRTIM_OUTPUT_TC1
6236 * @arg @ref LL_HRTIM_OUTPUT_TC2
6237 * @arg @ref LL_HRTIM_OUTPUT_TD1
6238 * @arg @ref LL_HRTIM_OUTPUT_TD2
6239 * @arg @ref LL_HRTIM_OUTPUT_TE1
6240 * @arg @ref LL_HRTIM_OUTPUT_TE2
6241 * @retval OutputLevel This parameter can be one of the following values:
6242 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6243 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6244 */
LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6245 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6246 {
6247 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6248 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6249 REG_OFFSET_TAB_OUTxR[iOutput]));
6250 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6251 HRTIM_TIMISR_O1STAT_Pos);
6252 }
6253
6254 /**
6255 * @brief Force the timer output to its active or inactive level.
6256 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
6257 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
6258 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
6259 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
6260 * @param HRTIMx High Resolution Timer instance
6261 * @param Output This parameter can be one of the following values:
6262 * @arg @ref LL_HRTIM_OUTPUT_TA1
6263 * @arg @ref LL_HRTIM_OUTPUT_TA2
6264 * @arg @ref LL_HRTIM_OUTPUT_TB1
6265 * @arg @ref LL_HRTIM_OUTPUT_TB2
6266 * @arg @ref LL_HRTIM_OUTPUT_TC1
6267 * @arg @ref LL_HRTIM_OUTPUT_TC2
6268 * @arg @ref LL_HRTIM_OUTPUT_TD1
6269 * @arg @ref LL_HRTIM_OUTPUT_TD2
6270 * @arg @ref LL_HRTIM_OUTPUT_TE1
6271 * @arg @ref LL_HRTIM_OUTPUT_TE2
6272 * @param OutputLevel This parameter can be one of the following values:
6273 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6274 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6275 * @retval None
6276 */
LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t OutputLevel)6277 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
6278 {
6279 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
6280 {
6281 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
6282 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
6283 };
6284
6285 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6286 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
6287 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
6288 SET_BIT(*pReg, HRTIM_SET1R_SST);
6289 }
6290
6291 /**
6292 * @brief Get actual output level, before the output stage (chopper, polarity).
6293 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
6294 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
6295 * @param HRTIMx High Resolution Timer instance
6296 * @param Output This parameter can be one of the following values:
6297 * @arg @ref LL_HRTIM_OUTPUT_TA1
6298 * @arg @ref LL_HRTIM_OUTPUT_TA2
6299 * @arg @ref LL_HRTIM_OUTPUT_TB1
6300 * @arg @ref LL_HRTIM_OUTPUT_TB2
6301 * @arg @ref LL_HRTIM_OUTPUT_TC1
6302 * @arg @ref LL_HRTIM_OUTPUT_TC2
6303 * @arg @ref LL_HRTIM_OUTPUT_TD1
6304 * @arg @ref LL_HRTIM_OUTPUT_TD2
6305 * @arg @ref LL_HRTIM_OUTPUT_TE1
6306 * @arg @ref LL_HRTIM_OUTPUT_TE2
6307 * @retval OutputLevel This parameter can be one of the following values:
6308 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6309 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6310 */
LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6311 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6312 {
6313 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6314 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6315 REG_OFFSET_TAB_OUTxR[iOutput]));
6316 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6317 HRTIM_TIMISR_O1CPY_Pos);
6318 }
6319
6320 /**
6321 * @}
6322 */
6323
6324 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
6325 * @{
6326 */
6327
6328 /**
6329 * @brief Configure external event conditioning.
6330 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
6331 * EECR1 EE1POL LL_HRTIM_EE_Config\n
6332 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
6333 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
6334 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
6335 * EECR1 EE2POL LL_HRTIM_EE_Config\n
6336 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
6337 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
6338 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
6339 * EECR1 EE3POL LL_HRTIM_EE_Config\n
6340 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
6341 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
6342 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
6343 * EECR1 EE4POL LL_HRTIM_EE_Config\n
6344 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
6345 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
6346 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
6347 * EECR1 EE5POL LL_HRTIM_EE_Config\n
6348 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
6349 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
6350 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
6351 * EECR2 EE6POL LL_HRTIM_EE_Config\n
6352 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
6353 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
6354 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
6355 * EECR2 EE7POL LL_HRTIM_EE_Config\n
6356 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
6357 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
6358 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
6359 * EECR2 EE8POL LL_HRTIM_EE_Config\n
6360 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
6361 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
6362 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
6363 * EECR2 EE9POL LL_HRTIM_EE_Config\n
6364 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
6365 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
6366 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
6367 * EECR2 EE10POL LL_HRTIM_EE_Config\n
6368 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
6369 * EECR2 EE10FAST LL_HRTIM_EE_Config
6370 * @note This function must not be called when the timer counter is enabled.
6371 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
6372 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
6373 * @param HRTIMx High Resolution Timer instance
6374 * @param Event This parameter can be one of the following values:
6375 * @arg @ref LL_HRTIM_EVENT_1
6376 * @arg @ref LL_HRTIM_EVENT_2
6377 * @arg @ref LL_HRTIM_EVENT_3
6378 * @arg @ref LL_HRTIM_EVENT_4
6379 * @arg @ref LL_HRTIM_EVENT_5
6380 * @arg @ref LL_HRTIM_EVENT_6
6381 * @arg @ref LL_HRTIM_EVENT_7
6382 * @arg @ref LL_HRTIM_EVENT_8
6383 * @arg @ref LL_HRTIM_EVENT_9
6384 * @arg @ref LL_HRTIM_EVENT_10
6385 * @param Configuration This parameter must be a combination of all the following values:
6386 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
6387 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
6388 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6389 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
6390 * @retval None
6391 */
LL_HRTIM_EE_Config(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Configuration)6392 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
6393 {
6394 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6395 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6396 REG_OFFSET_TAB_EECR[iEvent]));
6397 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
6398 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
6399 }
6400
6401 /**
6402 * @brief Set the external event source.
6403 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
6404 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
6405 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
6406 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
6407 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
6408 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
6409 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
6410 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
6411 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
6412 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
6413 * @param HRTIMx High Resolution Timer instance
6414 * @param Event This parameter can be one of the following values:
6415 * @arg @ref LL_HRTIM_EVENT_1
6416 * @arg @ref LL_HRTIM_EVENT_2
6417 * @arg @ref LL_HRTIM_EVENT_3
6418 * @arg @ref LL_HRTIM_EVENT_4
6419 * @arg @ref LL_HRTIM_EVENT_5
6420 * @arg @ref LL_HRTIM_EVENT_6
6421 * @arg @ref LL_HRTIM_EVENT_7
6422 * @arg @ref LL_HRTIM_EVENT_8
6423 * @arg @ref LL_HRTIM_EVENT_9
6424 * @arg @ref LL_HRTIM_EVENT_10
6425 * @param Src This parameter can be one of the following values:
6426 * @arg External event source 1
6427 * @arg External event source 2
6428 * @arg External event source 3
6429 * @arg External event source 4
6430 * @retval None
6431 */
LL_HRTIM_EE_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Src)6432 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
6433 {
6434 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6435 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6436 REG_OFFSET_TAB_EECR[iEvent]));
6437 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
6438 }
6439
6440 /**
6441 * @brief Get actual external event source.
6442 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
6443 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
6444 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
6445 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
6446 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
6447 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
6448 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
6449 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
6450 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
6451 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
6452 * @param HRTIMx High Resolution Timer instance
6453 * @param Event This parameter can be one of the following values:
6454 * @arg @ref LL_HRTIM_EVENT_1
6455 * @arg @ref LL_HRTIM_EVENT_2
6456 * @arg @ref LL_HRTIM_EVENT_3
6457 * @arg @ref LL_HRTIM_EVENT_4
6458 * @arg @ref LL_HRTIM_EVENT_5
6459 * @arg @ref LL_HRTIM_EVENT_6
6460 * @arg @ref LL_HRTIM_EVENT_7
6461 * @arg @ref LL_HRTIM_EVENT_8
6462 * @arg @ref LL_HRTIM_EVENT_9
6463 * @arg @ref LL_HRTIM_EVENT_10
6464 * @retval EventSrc This parameter can be one of the following values:
6465 * @arg External event source 1
6466 * @arg External event source 2
6467 * @arg External event source 3
6468 * @arg External event source 4
6469 */
LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6470 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6471 {
6472 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6473 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6474 REG_OFFSET_TAB_EECR[iEvent]));
6475 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6476 }
6477
6478 /**
6479 * @brief Set the polarity of an external event.
6480 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
6481 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
6482 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
6483 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
6484 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
6485 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
6486 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
6487 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
6488 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
6489 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
6490 * @note This function must not be called when the timer counter is enabled.
6491 * @note Event polarity is only significant when event detection is level-sensitive.
6492 * @param HRTIMx High Resolution Timer instance
6493 * @param Event This parameter can be one of the following values:
6494 * @arg @ref LL_HRTIM_EVENT_1
6495 * @arg @ref LL_HRTIM_EVENT_2
6496 * @arg @ref LL_HRTIM_EVENT_3
6497 * @arg @ref LL_HRTIM_EVENT_4
6498 * @arg @ref LL_HRTIM_EVENT_5
6499 * @arg @ref LL_HRTIM_EVENT_6
6500 * @arg @ref LL_HRTIM_EVENT_7
6501 * @arg @ref LL_HRTIM_EVENT_8
6502 * @arg @ref LL_HRTIM_EVENT_9
6503 * @arg @ref LL_HRTIM_EVENT_10
6504 * @param Polarity This parameter can be one of the following values:
6505 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6506 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6507 * @retval None
6508 */
LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Polarity)6509 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
6510 {
6511 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6512 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6513 REG_OFFSET_TAB_EECR[iEvent]));
6514 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
6515 }
6516
6517 /**
6518 * @brief Get actual polarity setting of an external event.
6519 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
6520 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
6521 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
6522 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
6523 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
6524 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
6525 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
6526 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
6527 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
6528 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
6529 * @param HRTIMx High Resolution Timer instance
6530 * @param Event This parameter can be one of the following values:
6531 * @arg @ref LL_HRTIM_EVENT_1
6532 * @arg @ref LL_HRTIM_EVENT_2
6533 * @arg @ref LL_HRTIM_EVENT_3
6534 * @arg @ref LL_HRTIM_EVENT_4
6535 * @arg @ref LL_HRTIM_EVENT_5
6536 * @arg @ref LL_HRTIM_EVENT_6
6537 * @arg @ref LL_HRTIM_EVENT_7
6538 * @arg @ref LL_HRTIM_EVENT_8
6539 * @arg @ref LL_HRTIM_EVENT_9
6540 * @arg @ref LL_HRTIM_EVENT_10
6541 * @retval Polarity This parameter can be one of the following values:
6542 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6543 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6544 */
LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6545 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6546 {
6547 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6548 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6549 REG_OFFSET_TAB_EECR[iEvent]));
6550 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6551 }
6552
6553 /**
6554 * @brief Set the sensitivity of an external event.
6555 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
6556 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
6557 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
6558 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
6559 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
6560 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
6561 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
6562 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
6563 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
6564 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
6565 * @param HRTIMx High Resolution Timer instance
6566 * @param Event This parameter can be one of the following values:
6567 * @arg @ref LL_HRTIM_EVENT_1
6568 * @arg @ref LL_HRTIM_EVENT_2
6569 * @arg @ref LL_HRTIM_EVENT_3
6570 * @arg @ref LL_HRTIM_EVENT_4
6571 * @arg @ref LL_HRTIM_EVENT_5
6572 * @arg @ref LL_HRTIM_EVENT_6
6573 * @arg @ref LL_HRTIM_EVENT_7
6574 * @arg @ref LL_HRTIM_EVENT_8
6575 * @arg @ref LL_HRTIM_EVENT_9
6576 * @arg @ref LL_HRTIM_EVENT_10
6577 * @param Sensitivity This parameter can be one of the following values:
6578 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6579 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6580 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6581 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6582 * @retval None
6583 */
6584
LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Sensitivity)6585 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
6586 {
6587 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6588 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6589 REG_OFFSET_TAB_EECR[iEvent]));
6590 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
6591 }
6592
6593 /**
6594 * @brief Get actual sensitivity setting of an external event.
6595 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
6596 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
6597 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
6598 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
6599 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
6600 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
6601 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
6602 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
6603 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
6604 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
6605 * @param HRTIMx High Resolution Timer instance
6606 * @param Event This parameter can be one of the following values:
6607 * @arg @ref LL_HRTIM_EVENT_1
6608 * @arg @ref LL_HRTIM_EVENT_2
6609 * @arg @ref LL_HRTIM_EVENT_3
6610 * @arg @ref LL_HRTIM_EVENT_4
6611 * @arg @ref LL_HRTIM_EVENT_5
6612 * @arg @ref LL_HRTIM_EVENT_6
6613 * @arg @ref LL_HRTIM_EVENT_7
6614 * @arg @ref LL_HRTIM_EVENT_8
6615 * @arg @ref LL_HRTIM_EVENT_9
6616 * @arg @ref LL_HRTIM_EVENT_10
6617 * @retval Polarity This parameter can be one of the following values:
6618 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6619 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6620 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6621 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6622 */
LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6623 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6624 {
6625 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6626 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6627 REG_OFFSET_TAB_EECR[iEvent]));
6628 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6629 }
6630
6631 /**
6632 * @brief Set the fast mode of an external event.
6633 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
6634 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
6635 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
6636 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
6637 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
6638 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
6639 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
6640 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
6641 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
6642 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
6643 * @note This function must not be called when the timer counter is enabled.
6644 * @param HRTIMx High Resolution Timer instance
6645 * @param Event This parameter can be one of the following values:
6646 * @arg @ref LL_HRTIM_EVENT_1
6647 * @arg @ref LL_HRTIM_EVENT_2
6648 * @arg @ref LL_HRTIM_EVENT_3
6649 * @arg @ref LL_HRTIM_EVENT_4
6650 * @arg @ref LL_HRTIM_EVENT_5
6651 * @param FastMode This parameter can be one of the following values:
6652 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6653 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6654 * @retval None
6655 */
LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t FastMode)6656 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
6657 {
6658 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6659 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6660 REG_OFFSET_TAB_EECR[iEvent]));
6661 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
6662 }
6663
6664 /**
6665 * @brief Get actual fast mode setting of an external event.
6666 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
6667 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
6668 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
6669 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
6670 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
6671 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
6672 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
6673 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
6674 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
6675 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
6676 * @param HRTIMx High Resolution Timer instance
6677 * @param Event This parameter can be one of the following values:
6678 * @arg @ref LL_HRTIM_EVENT_1
6679 * @arg @ref LL_HRTIM_EVENT_2
6680 * @arg @ref LL_HRTIM_EVENT_3
6681 * @arg @ref LL_HRTIM_EVENT_4
6682 * @arg @ref LL_HRTIM_EVENT_5
6683 * @retval FastMode This parameter can be one of the following values:
6684 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6685 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6686 */
LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6687 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6688 {
6689 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6690 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6691 REG_OFFSET_TAB_EECR[iEvent]));
6692 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6693 }
6694
6695 /**
6696 * @brief Set the digital noise filter of a external event.
6697 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
6698 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
6699 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
6700 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
6701 * EECR3 EE10F LL_HRTIM_EE_SetFilter
6702 * @param HRTIMx High Resolution Timer instance
6703 * @param Event This parameter can be one of the following values:
6704 * @arg @ref LL_HRTIM_EVENT_6
6705 * @arg @ref LL_HRTIM_EVENT_7
6706 * @arg @ref LL_HRTIM_EVENT_8
6707 * @arg @ref LL_HRTIM_EVENT_9
6708 * @arg @ref LL_HRTIM_EVENT_10
6709 * @param Filter This parameter can be one of the following values:
6710 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6711 * @arg @ref LL_HRTIM_EE_FILTER_1
6712 * @arg @ref LL_HRTIM_EE_FILTER_2
6713 * @arg @ref LL_HRTIM_EE_FILTER_3
6714 * @arg @ref LL_HRTIM_EE_FILTER_4
6715 * @arg @ref LL_HRTIM_EE_FILTER_5
6716 * @arg @ref LL_HRTIM_EE_FILTER_6
6717 * @arg @ref LL_HRTIM_EE_FILTER_7
6718 * @arg @ref LL_HRTIM_EE_FILTER_8
6719 * @arg @ref LL_HRTIM_EE_FILTER_9
6720 * @arg @ref LL_HRTIM_EE_FILTER_10
6721 * @arg @ref LL_HRTIM_EE_FILTER_11
6722 * @arg @ref LL_HRTIM_EE_FILTER_12
6723 * @arg @ref LL_HRTIM_EE_FILTER_13
6724 * @arg @ref LL_HRTIM_EE_FILTER_14
6725 * @arg @ref LL_HRTIM_EE_FILTER_15
6726 * @retval None
6727 */
LL_HRTIM_EE_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Filter)6728 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
6729 {
6730 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6731 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
6732 (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6733 }
6734
6735 /**
6736 * @brief Get actual digital noise filter setting of a external event.
6737 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
6738 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
6739 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
6740 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
6741 * EECR3 EE10F LL_HRTIM_EE_GetFilter
6742 * @param HRTIMx High Resolution Timer instance
6743 * @param Event This parameter can be one of the following values:
6744 * @arg @ref LL_HRTIM_EVENT_6
6745 * @arg @ref LL_HRTIM_EVENT_7
6746 * @arg @ref LL_HRTIM_EVENT_8
6747 * @arg @ref LL_HRTIM_EVENT_9
6748 * @arg @ref LL_HRTIM_EVENT_10
6749 * @retval Filter This parameter can be one of the following values:
6750 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6751 * @arg @ref LL_HRTIM_EE_FILTER_1
6752 * @arg @ref LL_HRTIM_EE_FILTER_2
6753 * @arg @ref LL_HRTIM_EE_FILTER_3
6754 * @arg @ref LL_HRTIM_EE_FILTER_4
6755 * @arg @ref LL_HRTIM_EE_FILTER_5
6756 * @arg @ref LL_HRTIM_EE_FILTER_6
6757 * @arg @ref LL_HRTIM_EE_FILTER_7
6758 * @arg @ref LL_HRTIM_EE_FILTER_8
6759 * @arg @ref LL_HRTIM_EE_FILTER_9
6760 * @arg @ref LL_HRTIM_EE_FILTER_10
6761 * @arg @ref LL_HRTIM_EE_FILTER_11
6762 * @arg @ref LL_HRTIM_EE_FILTER_12
6763 * @arg @ref LL_HRTIM_EE_FILTER_13
6764 * @arg @ref LL_HRTIM_EE_FILTER_14
6765 * @arg @ref LL_HRTIM_EE_FILTER_15
6766 */
LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6767 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6768 {
6769 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
6770 return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
6771 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6772 }
6773
6774 /**
6775 * @brief Set the external event prescaler.
6776 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
6777 * @param HRTIMx High Resolution Timer instance
6778 * @param Prescaler This parameter can be one of the following values:
6779 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6780 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6781 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6782 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6783 * @retval None
6784 */
6785
LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)6786 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
6787 {
6788 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
6789 }
6790
6791 /**
6792 * @brief Get actual external event prescaler setting.
6793 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
6794 * @param HRTIMx High Resolution Timer instance
6795 * @retval Prescaler This parameter can be one of the following values:
6796 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6797 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6798 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6799 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6800 */
6801
LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef * HRTIMx)6802 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
6803 {
6804 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
6805 }
6806
6807 /**
6808 * @}
6809 */
6810
6811 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
6812 * @{
6813 */
6814 /**
6815 * @brief Configure fault signal conditioning Polarity and Source.
6816 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
6817 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
6818 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
6819 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
6820 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
6821 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
6822 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
6823 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
6824 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
6825 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
6826 * @note This function must not be called when the fault channel is enabled.
6827 * @param HRTIMx High Resolution Timer instance
6828 * @param Fault This parameter can be one of the following values:
6829 * @arg @ref LL_HRTIM_FAULT_1
6830 * @arg @ref LL_HRTIM_FAULT_2
6831 * @arg @ref LL_HRTIM_FAULT_3
6832 * @arg @ref LL_HRTIM_FAULT_4
6833 * @arg @ref LL_HRTIM_FAULT_5
6834 * @param Configuration This parameter must be a combination of all the following values:
6835 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL
6836 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
6837 * @retval None
6838 */
LL_HRTIM_FLT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Configuration)6839 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
6840 {
6841 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6842 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6843 REG_OFFSET_TAB_FLTINR[iFault]));
6844 MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
6845 (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
6846 }
6847
6848 /**
6849 * @brief Set the source of a fault signal.
6850 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
6851 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
6852 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
6853 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
6854 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
6855 * @note This function must not be called when the fault channel is enabled.
6856 * @param HRTIMx High Resolution Timer instance
6857 * @param Fault This parameter can be one of the following values:
6858 * @arg @ref LL_HRTIM_FAULT_1
6859 * @arg @ref LL_HRTIM_FAULT_2
6860 * @arg @ref LL_HRTIM_FAULT_3
6861 * @arg @ref LL_HRTIM_FAULT_4
6862 * @arg @ref LL_HRTIM_FAULT_5
6863 * @param Src This parameter can be one of the following values:
6864 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6865 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6866 * @retval None
6867 */
LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Src)6868 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
6869 {
6870 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6871 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6872 REG_OFFSET_TAB_FLTINR[iFault]));
6873 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
6874 }
6875
6876 /**
6877 * @brief Get actual source of a fault signal.
6878 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
6879 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
6880 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
6881 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
6882 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
6883 * @param HRTIMx High Resolution Timer instance
6884 * @param Fault This parameter can be one of the following values:
6885 * @arg @ref LL_HRTIM_FAULT_1
6886 * @arg @ref LL_HRTIM_FAULT_2
6887 * @arg @ref LL_HRTIM_FAULT_3
6888 * @arg @ref LL_HRTIM_FAULT_4
6889 * @arg @ref LL_HRTIM_FAULT_5
6890 * @retval Source This parameter can be one of the following values:
6891 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6892 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6893 */
LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)6894 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
6895 {
6896 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6897 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6898 REG_OFFSET_TAB_FLTINR[iFault]));
6899 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6900 }
6901
6902 /**
6903 * @brief Set the polarity of a fault signal.
6904 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
6905 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
6906 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
6907 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
6908 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
6909 * @note This function must not be called when the fault channel is enabled.
6910 * @param HRTIMx High Resolution Timer instance
6911 * @param Fault This parameter can be one of the following values:
6912 * @arg @ref LL_HRTIM_FAULT_1
6913 * @arg @ref LL_HRTIM_FAULT_2
6914 * @arg @ref LL_HRTIM_FAULT_3
6915 * @arg @ref LL_HRTIM_FAULT_4
6916 * @arg @ref LL_HRTIM_FAULT_5
6917 * @param Polarity This parameter can be one of the following values:
6918 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6919 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6920 * @retval None
6921 */
LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Polarity)6922 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
6923 {
6924 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6925 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6926 REG_OFFSET_TAB_FLTINR[iFault]));
6927 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
6928 }
6929
6930 /**
6931 * @brief Get actual polarity of a fault signal.
6932 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
6933 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
6934 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
6935 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
6936 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
6937 * @param HRTIMx High Resolution Timer instance
6938 * @param Fault This parameter can be one of the following values:
6939 * @arg @ref LL_HRTIM_FAULT_1
6940 * @arg @ref LL_HRTIM_FAULT_2
6941 * @arg @ref LL_HRTIM_FAULT_3
6942 * @arg @ref LL_HRTIM_FAULT_4
6943 * @arg @ref LL_HRTIM_FAULT_5
6944 * @retval Polarity This parameter can be one of the following values:
6945 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6946 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6947 */
LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)6948 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
6949 {
6950 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6951 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6952 REG_OFFSET_TAB_FLTINR[iFault]));
6953 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6954 }
6955
6956 /**
6957 * @brief Set the digital noise filter of a fault signal.
6958 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
6959 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
6960 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
6961 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
6962 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
6963 * @note This function must not be called when the fault channel is enabled.
6964 * @param HRTIMx High Resolution Timer instance
6965 * @param Fault This parameter can be one of the following values:
6966 * @arg @ref LL_HRTIM_FAULT_1
6967 * @arg @ref LL_HRTIM_FAULT_2
6968 * @arg @ref LL_HRTIM_FAULT_3
6969 * @arg @ref LL_HRTIM_FAULT_4
6970 * @arg @ref LL_HRTIM_FAULT_5
6971 * @param Filter This parameter can be one of the following values:
6972 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
6973 * @arg @ref LL_HRTIM_FLT_FILTER_1
6974 * @arg @ref LL_HRTIM_FLT_FILTER_2
6975 * @arg @ref LL_HRTIM_FLT_FILTER_3
6976 * @arg @ref LL_HRTIM_FLT_FILTER_4
6977 * @arg @ref LL_HRTIM_FLT_FILTER_5
6978 * @arg @ref LL_HRTIM_FLT_FILTER_6
6979 * @arg @ref LL_HRTIM_FLT_FILTER_7
6980 * @arg @ref LL_HRTIM_FLT_FILTER_8
6981 * @arg @ref LL_HRTIM_FLT_FILTER_9
6982 * @arg @ref LL_HRTIM_FLT_FILTER_10
6983 * @arg @ref LL_HRTIM_FLT_FILTER_11
6984 * @arg @ref LL_HRTIM_FLT_FILTER_12
6985 * @arg @ref LL_HRTIM_FLT_FILTER_13
6986 * @arg @ref LL_HRTIM_FLT_FILTER_14
6987 * @arg @ref LL_HRTIM_FLT_FILTER_15
6988 * @retval None
6989 */
LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Filter)6990 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
6991 {
6992 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6993 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6994 REG_OFFSET_TAB_FLTINR[iFault]));
6995 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
6996 }
6997
6998 /**
6999 * @brief Get actual digital noise filter setting of a fault signal.
7000 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
7001 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
7002 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
7003 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
7004 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
7005 * @param HRTIMx High Resolution Timer instance
7006 * @param Fault This parameter can be one of the following values:
7007 * @arg @ref LL_HRTIM_FAULT_1
7008 * @arg @ref LL_HRTIM_FAULT_2
7009 * @arg @ref LL_HRTIM_FAULT_3
7010 * @arg @ref LL_HRTIM_FAULT_4
7011 * @arg @ref LL_HRTIM_FAULT_5
7012 * @retval Filter This parameter can be one of the following values:
7013 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
7014 * @arg @ref LL_HRTIM_FLT_FILTER_1
7015 * @arg @ref LL_HRTIM_FLT_FILTER_2
7016 * @arg @ref LL_HRTIM_FLT_FILTER_3
7017 * @arg @ref LL_HRTIM_FLT_FILTER_4
7018 * @arg @ref LL_HRTIM_FLT_FILTER_5
7019 * @arg @ref LL_HRTIM_FLT_FILTER_6
7020 * @arg @ref LL_HRTIM_FLT_FILTER_7
7021 * @arg @ref LL_HRTIM_FLT_FILTER_8
7022 * @arg @ref LL_HRTIM_FLT_FILTER_9
7023 * @arg @ref LL_HRTIM_FLT_FILTER_10
7024 * @arg @ref LL_HRTIM_FLT_FILTER_11
7025 * @arg @ref LL_HRTIM_FLT_FILTER_12
7026 * @arg @ref LL_HRTIM_FLT_FILTER_13
7027 * @arg @ref LL_HRTIM_FLT_FILTER_14
7028 * @arg @ref LL_HRTIM_FLT_FILTER_15
7029 */
LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)7030 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7031 {
7032 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7033 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7034 REG_OFFSET_TAB_FLTINR[iFault]));
7035 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
7036
7037 }
7038
7039 /**
7040 * @brief Set the fault circuitry prescaler.
7041 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
7042 * @param HRTIMx High Resolution Timer instance
7043 * @param Prescaler This parameter can be one of the following values:
7044 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
7045 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
7046 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
7047 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
7048 * @retval None
7049 */
LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)7050 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
7051 {
7052 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
7053 }
7054
7055 /**
7056 * @brief Get actual fault circuitry prescaler setting.
7057 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
7058 * @param HRTIMx High Resolution Timer instance
7059 * @retval Prescaler This parameter can be one of the following values:
7060 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
7061 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
7062 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
7063 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
7064 */
LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef * HRTIMx)7065 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
7066 {
7067 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
7068 }
7069
7070 /**
7071 * @brief Lock the fault signal conditioning settings.
7072 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
7073 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
7074 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
7075 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
7076 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
7077 * @param HRTIMx High Resolution Timer instance
7078 * @param Fault This parameter can be one of the following values:
7079 * @arg @ref LL_HRTIM_FAULT_1
7080 * @arg @ref LL_HRTIM_FAULT_2
7081 * @arg @ref LL_HRTIM_FAULT_3
7082 * @arg @ref LL_HRTIM_FAULT_4
7083 * @arg @ref LL_HRTIM_FAULT_5
7084 * @retval None
7085 */
LL_HRTIM_FLT_Lock(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7086 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7087 {
7088 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7089 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7090 REG_OFFSET_TAB_FLTINR[iFault]));
7091 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
7092 }
7093
7094 /**
7095 * @brief Enable the fault circuitry for the designated fault input.
7096 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
7097 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
7098 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
7099 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
7100 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable
7101 * @param HRTIMx High Resolution Timer instance
7102 * @param Fault This parameter can be one of the following values:
7103 * @arg @ref LL_HRTIM_FAULT_1
7104 * @arg @ref LL_HRTIM_FAULT_2
7105 * @arg @ref LL_HRTIM_FAULT_3
7106 * @arg @ref LL_HRTIM_FAULT_4
7107 * @arg @ref LL_HRTIM_FAULT_5
7108 * @retval None
7109 */
LL_HRTIM_FLT_Enable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7110 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7111 {
7112 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7113 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7114 REG_OFFSET_TAB_FLTINR[iFault]));
7115 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
7116 }
7117
7118 /**
7119 * @brief Disable the fault circuitry for for the designated fault input.
7120 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
7121 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
7122 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
7123 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
7124 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable
7125 * @param HRTIMx High Resolution Timer instance
7126 * @param Fault This parameter can be one of the following values:
7127 * @arg @ref LL_HRTIM_FAULT_1
7128 * @arg @ref LL_HRTIM_FAULT_2
7129 * @arg @ref LL_HRTIM_FAULT_3
7130 * @arg @ref LL_HRTIM_FAULT_4
7131 * @arg @ref LL_HRTIM_FAULT_5
7132 * @retval None
7133 */
LL_HRTIM_FLT_Disable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7134 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7135 {
7136 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7137 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7138 REG_OFFSET_TAB_FLTINR[iFault]));
7139 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
7140 }
7141
7142 /**
7143 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
7144 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
7145 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
7146 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
7147 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
7148 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
7149 * @param HRTIMx High Resolution Timer instance
7150 * @param Fault This parameter can be one of the following values:
7151 * @arg @ref LL_HRTIM_FAULT_1
7152 * @arg @ref LL_HRTIM_FAULT_2
7153 * @arg @ref LL_HRTIM_FAULT_3
7154 * @arg @ref LL_HRTIM_FAULT_4
7155 * @arg @ref LL_HRTIM_FAULT_5
7156 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
7157 */
LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)7158 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7159 {
7160 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7161 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7162 REG_OFFSET_TAB_FLTINR[iFault]));
7163 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
7164 (HRTIM_IER_FLT1)) ? 1UL : 0UL);
7165 }
7166
7167 /**
7168 * @}
7169 */
7170
7171 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
7172 * @{
7173 */
7174
7175 /**
7176 * @brief Configure the burst mode controller.
7177 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
7178 * BMCR BMCLK LL_HRTIM_BM_Config\n
7179 * BMCR BMPRSC LL_HRTIM_BM_Config
7180 * @param HRTIMx High Resolution Timer instance
7181 * @param Configuration This parameter must be a combination of all the following values:
7182 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
7183 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7184 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
7185 * @retval None
7186 */
LL_HRTIM_BM_Config(HRTIM_TypeDef * HRTIMx,uint32_t Configuration)7187 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
7188 {
7189 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
7190 }
7191
7192 /**
7193 * @brief Set the burst mode controller operating mode.
7194 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
7195 * @param HRTIMx High Resolution Timer instance
7196 * @param Mode This parameter can be one of the following values:
7197 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7198 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7199 * @retval None
7200 */
LL_HRTIM_BM_SetMode(HRTIM_TypeDef * HRTIMx,uint32_t Mode)7201 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
7202 {
7203 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
7204 }
7205
7206 /**
7207 * @brief Get actual burst mode controller operating mode.
7208 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
7209 * @param HRTIMx High Resolution Timer instance
7210 * @retval Mode This parameter can be one of the following values:
7211 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7212 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7213 */
LL_HRTIM_BM_GetMode(const HRTIM_TypeDef * HRTIMx)7214 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
7215 {
7216 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
7217 }
7218
7219 /**
7220 * @brief Set the burst mode controller clock source.
7221 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
7222 * @param HRTIMx High Resolution Timer instance
7223 * @param ClockSrc This parameter can be one of the following values:
7224 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7225 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7226 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7227 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7228 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7229 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7230 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7231 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7232 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7233 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7234 * @retval None
7235 */
LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef * HRTIMx,uint32_t ClockSrc)7236 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
7237 {
7238 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
7239 }
7240
7241 /**
7242 * @brief Get actual burst mode controller clock source.
7243 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
7244 * @param HRTIMx High Resolution Timer instance
7245 * @retval ClockSrc This parameter can be one of the following values:
7246 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7247 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7248 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7249 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7250 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7251 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7252 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7253 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7254 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7255 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7256 * @retval ClockSrc This parameter can be one of the following values:
7257 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7258 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7259 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7260 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7261 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7262 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7263 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7264 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7265 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7266 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7267 */
LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef * HRTIMx)7268 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
7269 {
7270 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
7271 }
7272
7273 /**
7274 * @brief Set the burst mode controller prescaler.
7275 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
7276 * @param HRTIMx High Resolution Timer instance
7277 * @param Prescaler This parameter can be one of the following values:
7278 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7279 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7280 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7281 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7282 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7283 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7284 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7285 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7286 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7287 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7288 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7289 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7290 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7291 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7292 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7293 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7294 * @retval None
7295 */
LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)7296 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
7297 {
7298 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
7299 }
7300
7301 /**
7302 * @brief Get actual burst mode controller prescaler setting.
7303 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
7304 * @param HRTIMx High Resolution Timer instance
7305 * @retval Prescaler This parameter can be one of the following values:
7306 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7307 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7308 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7309 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7310 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7311 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7312 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7313 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7314 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7315 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7316 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7317 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7318 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7319 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7320 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7321 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7322 */
LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef * HRTIMx)7323 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
7324 {
7325 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
7326 }
7327
7328 /**
7329 * @brief Enable burst mode compare and period registers preload.
7330 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
7331 * @param HRTIMx High Resolution Timer instance
7332 * @retval None
7333 */
LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef * HRTIMx)7334 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
7335 {
7336 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7337 }
7338
7339 /**
7340 * @brief Disable burst mode compare and period registers preload.
7341 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
7342 * @param HRTIMx High Resolution Timer instance
7343 * @retval None
7344 */
LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef * HRTIMx)7345 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
7346 {
7347 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7348 }
7349
7350 /**
7351 * @brief Indicate whether burst mode compare and period registers are preloaded.
7352 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
7353 * @param HRTIMx High Resolution Timer instance
7354 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
7355 */
LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx)7356 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
7357 {
7358 uint32_t temp; /* MISRAC-2012 compliance */
7359 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7360
7361 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
7362 }
7363
7364 /**
7365 * @brief Set the burst mode controller trigger
7366 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
7367 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
7368 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
7369 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
7370 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
7371 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
7372 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
7373 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
7374 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
7375 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
7376 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
7377 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
7378 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
7379 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
7380 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
7381 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
7382 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
7383 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
7384 * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
7385 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
7386 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
7387 * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
7388 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
7389 * BMTRGR TERST LL_HRTIM_BM_SetTrig\n
7390 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
7391 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
7392 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
7393 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
7394 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
7395 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
7396 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
7397 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
7398 * @param HRTIMx High Resolution Timer instance
7399 * @param Trig This parameter can be a combination of the following values:
7400 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7401 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7402 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7403 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7404 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7405 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7406 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7407 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7408 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7409 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7410 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7411 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7412 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7413 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7414 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7415 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7416 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7417 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7418 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7419 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7420 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7421 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7422 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7423 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7424 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7425 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7426 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7427 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7428 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7429 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7430 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7431 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7432 * @retval None
7433 */
LL_HRTIM_BM_SetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Trig)7434 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
7435 {
7436 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
7437 }
7438
7439 /**
7440 * @brief Get actual burst mode controller trigger.
7441 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
7442 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
7443 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
7444 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
7445 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
7446 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
7447 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
7448 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
7449 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
7450 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
7451 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
7452 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
7453 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
7454 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
7455 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
7456 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
7457 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
7458 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
7459 * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
7460 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
7461 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
7462 * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
7463 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
7464 * BMTRGR TERST LL_HRTIM_BM_GetTrig\n
7465 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
7466 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
7467 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
7468 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
7469 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
7470 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
7471 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
7472 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
7473 * @param HRTIMx High Resolution Timer instance
7474 * @retval Trig This parameter can be a combination of the following values:
7475 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7476 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7477 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7478 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7479 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7480 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7481 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7482 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7483 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7484 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7485 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7486 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7487 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7488 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7489 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7490 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7491 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7492 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7493 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7494 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7495 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7496 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7497 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7498 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7499 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7500 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7501 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7502 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7503 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7504 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7505 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7506 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7507 */
LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef * HRTIMx)7508 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
7509 {
7510 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
7511 }
7512
7513 /**
7514 * @brief Set the burst mode controller compare value.
7515 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
7516 * @param HRTIMx High Resolution Timer instance
7517 * @param CompareValue Compare value must be above or equal to 3
7518 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7519 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7520 * @retval None
7521 */
LL_HRTIM_BM_SetCompare(HRTIM_TypeDef * HRTIMx,uint32_t CompareValue)7522 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
7523 {
7524 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
7525 }
7526
7527 /**
7528 * @brief Get actual burst mode controller compare value.
7529 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
7530 * @param HRTIMx High Resolution Timer instance
7531 * @retval CompareValue Compare value must be above or equal to 3
7532 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7533 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7534 */
LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef * HRTIMx)7535 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
7536 {
7537 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
7538 }
7539
7540 /**
7541 * @brief Set the burst mode controller period.
7542 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
7543 * @param HRTIMx High Resolution Timer instance
7544 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
7545 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7546 * The maximum value is 0x0000 FFDF.
7547 * @retval None
7548 */
LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Period)7549 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
7550 {
7551 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
7552 }
7553
7554 /**
7555 * @brief Get actual burst mode controller period.
7556 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
7557 * @param HRTIMx High Resolution Timer instance
7558 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
7559 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7560 * The maximum value is 0x0000 FFDF.
7561 */
LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef * HRTIMx)7562 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
7563 {
7564 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
7565 }
7566
7567 /**
7568 * @brief Enable the burst mode controller
7569 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
7570 * @param HRTIMx High Resolution Timer instance
7571 * @retval None
7572 */
LL_HRTIM_BM_Enable(HRTIM_TypeDef * HRTIMx)7573 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
7574 {
7575 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
7576 }
7577
7578 /**
7579 * @brief Disable the burst mode controller
7580 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
7581 * @param HRTIMx High Resolution Timer instance
7582 * @retval None
7583 */
LL_HRTIM_BM_Disable(HRTIM_TypeDef * HRTIMx)7584 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
7585 {
7586 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
7587 }
7588
7589 /**
7590 * @brief Indicate whether the burst mode controller is enabled.
7591 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
7592 * @param HRTIMx High Resolution Timer instance
7593 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
7594 */
LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef * HRTIMx)7595 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
7596 {
7597 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
7598 }
7599
7600 /**
7601 * @brief Trigger the burst operation (software trigger)
7602 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
7603 * @param HRTIMx High Resolution Timer instance
7604 * @retval None
7605 */
LL_HRTIM_BM_Start(HRTIM_TypeDef * HRTIMx)7606 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
7607 {
7608 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
7609 }
7610
7611 /**
7612 * @brief Stop the burst mode operation.
7613 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
7614 * @note Causes a burst mode early termination.
7615 * @param HRTIMx High Resolution Timer instance
7616 * @retval None
7617 */
LL_HRTIM_BM_Stop(HRTIM_TypeDef * HRTIMx)7618 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
7619 {
7620 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
7621 }
7622
7623 /**
7624 * @brief Get actual burst mode status
7625 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
7626 * @param HRTIMx High Resolution Timer instance
7627 * @retval Status This parameter can be one of the following values:
7628 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
7629 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
7630 */
LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef * HRTIMx)7631 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
7632 {
7633 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
7634 }
7635
7636 /**
7637 * @}
7638 */
7639
7640 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
7641 * @{
7642 */
7643
7644 /**
7645 * @brief Clear the Fault 1 interrupt flag.
7646 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
7647 * @param HRTIMx High Resolution Timer instance
7648 * @retval None
7649 */
LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef * HRTIMx)7650 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
7651 {
7652 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
7653 }
7654
7655 /**
7656 * @brief Indicate whether Fault 1 interrupt occurred.
7657 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
7658 * @param HRTIMx High Resolution Timer instance
7659 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
7660 */
LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef * HRTIMx)7661 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
7662 {
7663 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
7664 }
7665
7666 /**
7667 * @brief Clear the Fault 2 interrupt flag.
7668 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
7669 * @param HRTIMx High Resolution Timer instance
7670 * @retval None
7671 */
LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef * HRTIMx)7672 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
7673 {
7674 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
7675 }
7676
7677 /**
7678 * @brief Indicate whether Fault 2 interrupt occurred.
7679 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
7680 * @param HRTIMx High Resolution Timer instance
7681 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
7682 */
LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef * HRTIMx)7683 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
7684 {
7685 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
7686 }
7687
7688 /**
7689 * @brief Clear the Fault 3 interrupt flag.
7690 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
7691 * @param HRTIMx High Resolution Timer instance
7692 * @retval None
7693 */
LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef * HRTIMx)7694 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
7695 {
7696 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
7697 }
7698
7699 /**
7700 * @brief Indicate whether Fault 3 interrupt occurred.
7701 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
7702 * @param HRTIMx High Resolution Timer instance
7703 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
7704 */
LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef * HRTIMx)7705 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
7706 {
7707 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
7708 }
7709
7710 /**
7711 * @brief Clear the Fault 4 interrupt flag.
7712 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
7713 * @param HRTIMx High Resolution Timer instance
7714 * @retval None
7715 */
LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef * HRTIMx)7716 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
7717 {
7718 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
7719 }
7720
7721 /**
7722 * @brief Indicate whether Fault 4 interrupt occurred.
7723 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
7724 * @param HRTIMx High Resolution Timer instance
7725 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
7726 */
LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef * HRTIMx)7727 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
7728 {
7729 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
7730 }
7731
7732 /**
7733 * @brief Clear the Fault 5 interrupt flag.
7734 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
7735 * @param HRTIMx High Resolution Timer instance
7736 * @retval None
7737 */
LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef * HRTIMx)7738 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
7739 {
7740 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
7741 }
7742
7743 /**
7744 * @brief Indicate whether Fault 5 interrupt occurred.
7745 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
7746 * @param HRTIMx High Resolution Timer instance
7747 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
7748 */
LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef * HRTIMx)7749 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
7750 {
7751 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
7752 }
7753
7754 /**
7755 * @brief Clear the System Fault interrupt flag.
7756 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
7757 * @param HRTIMx High Resolution Timer instance
7758 * @retval None
7759 */
LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)7760 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
7761 {
7762 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
7763 }
7764
7765 /**
7766 * @brief Indicate whether System Fault interrupt occurred.
7767 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
7768 * @param HRTIMx High Resolution Timer instance
7769 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
7770 */
LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef * HRTIMx)7771 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
7772 {
7773 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
7774 }
7775
7776 /**
7777 * @brief Clear the DLL ready interrupt flag.
7778 * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
7779 * @param HRTIMx High Resolution Timer instance
7780 * @retval None
7781 */
LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)7782 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
7783 {
7784 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
7785 }
7786
7787 /**
7788 * @brief Indicate whether DLL ready interrupt occurred.
7789 * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
7790 * @param HRTIMx High Resolution Timer instance
7791 * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
7792 */
LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef * HRTIMx)7793 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef *HRTIMx)
7794 {
7795 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
7796 }
7797
7798 /**
7799 * @brief Clear the Burst Mode period interrupt flag.
7800 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
7801 * @param HRTIMx High Resolution Timer instance
7802 * @retval None
7803 */
LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef * HRTIMx)7804 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
7805 {
7806 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
7807 }
7808
7809 /**
7810 * @brief Indicate whether Burst Mode period interrupt occurred.
7811 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
7812 * @param HRTIMx High Resolution Timer instance
7813 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
7814 */
LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef * HRTIMx)7815 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
7816 {
7817 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
7818 }
7819
7820 /**
7821 * @brief Clear the Synchronization Input interrupt flag.
7822 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
7823 * @param HRTIMx High Resolution Timer instance
7824 * @retval None
7825 */
LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef * HRTIMx)7826 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
7827 {
7828 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
7829 }
7830
7831 /**
7832 * @brief Indicate whether the Synchronization Input interrupt occurred.
7833 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
7834 * @param HRTIMx High Resolution Timer instance
7835 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
7836 */
LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef * HRTIMx)7837 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
7838 {
7839 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
7840 }
7841
7842 /**
7843 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
7844 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
7845 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
7846 * @param HRTIMx High Resolution Timer instance
7847 * @param Timer This parameter can be one of the following values:
7848 * @arg @ref LL_HRTIM_TIMER_MASTER
7849 * @arg @ref LL_HRTIM_TIMER_A
7850 * @arg @ref LL_HRTIM_TIMER_B
7851 * @arg @ref LL_HRTIM_TIMER_C
7852 * @arg @ref LL_HRTIM_TIMER_D
7853 * @arg @ref LL_HRTIM_TIMER_E
7854 * @retval None
7855 */
LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7856 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7857 {
7858 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7859 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7860 REG_OFFSET_TAB_TIMER[iTimer]));
7861 SET_BIT(*pReg, HRTIM_MICR_MUPD);
7862 }
7863
7864 /**
7865 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
7866 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
7867 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
7868 * @param HRTIMx High Resolution Timer instance
7869 * @param Timer This parameter can be one of the following values:
7870 * @arg @ref LL_HRTIM_TIMER_MASTER
7871 * @arg @ref LL_HRTIM_TIMER_A
7872 * @arg @ref LL_HRTIM_TIMER_B
7873 * @arg @ref LL_HRTIM_TIMER_C
7874 * @arg @ref LL_HRTIM_TIMER_D
7875 * @arg @ref LL_HRTIM_TIMER_E
7876 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7877 */
LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7878 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7879 {
7880 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7881 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7882 REG_OFFSET_TAB_TIMER[iTimer]));
7883
7884 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
7885 }
7886
7887 /**
7888 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
7889 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
7890 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
7891 * @param HRTIMx High Resolution Timer instance
7892 * @param Timer This parameter can be one of the following values:
7893 * @arg @ref LL_HRTIM_TIMER_MASTER
7894 * @arg @ref LL_HRTIM_TIMER_A
7895 * @arg @ref LL_HRTIM_TIMER_B
7896 * @arg @ref LL_HRTIM_TIMER_C
7897 * @arg @ref LL_HRTIM_TIMER_D
7898 * @arg @ref LL_HRTIM_TIMER_E
7899 * @retval None
7900 */
LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7901 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7902 {
7903 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7904 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7905 REG_OFFSET_TAB_TIMER[iTimer]));
7906 SET_BIT(*pReg, HRTIM_MICR_MREP);
7907
7908 }
7909
7910 /**
7911 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
7912 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
7913 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
7914 * @param HRTIMx High Resolution Timer instance
7915 * @param Timer This parameter can be one of the following values:
7916 * @arg @ref LL_HRTIM_TIMER_MASTER
7917 * @arg @ref LL_HRTIM_TIMER_A
7918 * @arg @ref LL_HRTIM_TIMER_B
7919 * @arg @ref LL_HRTIM_TIMER_C
7920 * @arg @ref LL_HRTIM_TIMER_D
7921 * @arg @ref LL_HRTIM_TIMER_E
7922 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7923 */
LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7924 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7925 {
7926 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7927 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7928 REG_OFFSET_TAB_TIMER[iTimer]));
7929
7930 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
7931 }
7932
7933 /**
7934 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
7935 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
7936 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
7937 * @param HRTIMx High Resolution Timer instance
7938 * @param Timer This parameter can be one of the following values:
7939 * @arg @ref LL_HRTIM_TIMER_MASTER
7940 * @arg @ref LL_HRTIM_TIMER_A
7941 * @arg @ref LL_HRTIM_TIMER_B
7942 * @arg @ref LL_HRTIM_TIMER_C
7943 * @arg @ref LL_HRTIM_TIMER_D
7944 * @arg @ref LL_HRTIM_TIMER_E
7945 * @retval None
7946 */
LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7947 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7948 {
7949 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7950 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7951 REG_OFFSET_TAB_TIMER[iTimer]));
7952 SET_BIT(*pReg, HRTIM_MICR_MCMP1);
7953 }
7954
7955 /**
7956 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
7957 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
7958 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
7959 * @param HRTIMx High Resolution Timer instance
7960 * @param Timer This parameter can be one of the following values:
7961 * @arg @ref LL_HRTIM_TIMER_MASTER
7962 * @arg @ref LL_HRTIM_TIMER_A
7963 * @arg @ref LL_HRTIM_TIMER_B
7964 * @arg @ref LL_HRTIM_TIMER_C
7965 * @arg @ref LL_HRTIM_TIMER_D
7966 * @arg @ref LL_HRTIM_TIMER_E
7967 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7968 */
LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7969 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7970 {
7971 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7972 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7973 REG_OFFSET_TAB_TIMER[iTimer]));
7974
7975 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
7976 }
7977
7978 /**
7979 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
7980 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
7981 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
7982 * @param HRTIMx High Resolution Timer instance
7983 * @param Timer This parameter can be one of the following values:
7984 * @arg @ref LL_HRTIM_TIMER_MASTER
7985 * @arg @ref LL_HRTIM_TIMER_A
7986 * @arg @ref LL_HRTIM_TIMER_B
7987 * @arg @ref LL_HRTIM_TIMER_C
7988 * @arg @ref LL_HRTIM_TIMER_D
7989 * @arg @ref LL_HRTIM_TIMER_E
7990 * @retval None
7991 */
LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7992 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7993 {
7994 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7995 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7996 REG_OFFSET_TAB_TIMER[iTimer]));
7997 SET_BIT(*pReg, HRTIM_MICR_MCMP2);
7998 }
7999
8000 /**
8001 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
8002 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
8003 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
8004 * @param HRTIMx High Resolution Timer instance
8005 * @param Timer This parameter can be one of the following values:
8006 * @arg @ref LL_HRTIM_TIMER_MASTER
8007 * @arg @ref LL_HRTIM_TIMER_A
8008 * @arg @ref LL_HRTIM_TIMER_B
8009 * @arg @ref LL_HRTIM_TIMER_C
8010 * @arg @ref LL_HRTIM_TIMER_D
8011 * @arg @ref LL_HRTIM_TIMER_E
8012 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
8013 */
LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8014 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8015 {
8016 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8017 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8018 REG_OFFSET_TAB_TIMER[iTimer]));
8019
8020 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
8021 }
8022
8023 /**
8024 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
8025 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
8026 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
8027 * @param HRTIMx High Resolution Timer instance
8028 * @param Timer This parameter can be one of the following values:
8029 * @arg @ref LL_HRTIM_TIMER_MASTER
8030 * @arg @ref LL_HRTIM_TIMER_A
8031 * @arg @ref LL_HRTIM_TIMER_B
8032 * @arg @ref LL_HRTIM_TIMER_C
8033 * @arg @ref LL_HRTIM_TIMER_D
8034 * @arg @ref LL_HRTIM_TIMER_E
8035 * @retval None
8036 */
LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8037 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8038 {
8039 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8040 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8041 REG_OFFSET_TAB_TIMER[iTimer]));
8042 SET_BIT(*pReg, HRTIM_MICR_MCMP3);
8043 }
8044
8045 /**
8046 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
8047 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
8048 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
8049 * @param HRTIMx High Resolution Timer instance
8050 * @param Timer This parameter can be one of the following values:
8051 * @arg @ref LL_HRTIM_TIMER_MASTER
8052 * @arg @ref LL_HRTIM_TIMER_A
8053 * @arg @ref LL_HRTIM_TIMER_B
8054 * @arg @ref LL_HRTIM_TIMER_C
8055 * @arg @ref LL_HRTIM_TIMER_D
8056 * @arg @ref LL_HRTIM_TIMER_E
8057 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
8058 */
LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8059 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8060 {
8061 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8062 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8063 REG_OFFSET_TAB_TIMER[iTimer]));
8064
8065 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
8066 }
8067
8068 /**
8069 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
8070 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
8071 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
8072 * @param HRTIMx High Resolution Timer instance
8073 * @param Timer This parameter can be one of the following values:
8074 * @arg @ref LL_HRTIM_TIMER_MASTER
8075 * @arg @ref LL_HRTIM_TIMER_A
8076 * @arg @ref LL_HRTIM_TIMER_B
8077 * @arg @ref LL_HRTIM_TIMER_C
8078 * @arg @ref LL_HRTIM_TIMER_D
8079 * @arg @ref LL_HRTIM_TIMER_E
8080 * @retval None
8081 */
LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8082 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8083 {
8084 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8085 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8086 REG_OFFSET_TAB_TIMER[iTimer]));
8087 SET_BIT(*pReg, HRTIM_MICR_MCMP4);
8088 }
8089
8090 /**
8091 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
8092 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
8093 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
8094 * @param HRTIMx High Resolution Timer instance
8095 * @param Timer This parameter can be one of the following values:
8096 * @arg @ref LL_HRTIM_TIMER_MASTER
8097 * @arg @ref LL_HRTIM_TIMER_A
8098 * @arg @ref LL_HRTIM_TIMER_B
8099 * @arg @ref LL_HRTIM_TIMER_C
8100 * @arg @ref LL_HRTIM_TIMER_D
8101 * @arg @ref LL_HRTIM_TIMER_E
8102 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
8103 */
LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8104 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8105 {
8106 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8107 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8108 REG_OFFSET_TAB_TIMER[iTimer]));
8109
8110 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
8111 }
8112
8113 /**
8114 * @brief Clear the capture 1 interrupt flag for a given timer.
8115 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
8116 * @param HRTIMx High Resolution Timer instance
8117 * @param Timer This parameter can be one of the following values:
8118 * @arg @ref LL_HRTIM_TIMER_A
8119 * @arg @ref LL_HRTIM_TIMER_B
8120 * @arg @ref LL_HRTIM_TIMER_C
8121 * @arg @ref LL_HRTIM_TIMER_D
8122 * @arg @ref LL_HRTIM_TIMER_E
8123 * @retval None
8124 */
LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8125 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8126 {
8127 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8128 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8129 REG_OFFSET_TAB_TIMER[iTimer]));
8130 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
8131 }
8132
8133 /**
8134 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
8135 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
8136 * @param HRTIMx High Resolution Timer instance
8137 * @param Timer This parameter can be one of the following values:
8138 * @arg @ref LL_HRTIM_TIMER_A
8139 * @arg @ref LL_HRTIM_TIMER_B
8140 * @arg @ref LL_HRTIM_TIMER_C
8141 * @arg @ref LL_HRTIM_TIMER_D
8142 * @arg @ref LL_HRTIM_TIMER_E
8143 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
8144 */
LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8145 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8146 {
8147 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8148 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8149 REG_OFFSET_TAB_TIMER[iTimer]));
8150
8151 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
8152 }
8153
8154 /**
8155 * @brief Clear the capture 2 interrupt flag for a given timer.
8156 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
8157 * @param HRTIMx High Resolution Timer instance
8158 * @param Timer This parameter can be one of the following values:
8159 * @arg @ref LL_HRTIM_TIMER_A
8160 * @arg @ref LL_HRTIM_TIMER_B
8161 * @arg @ref LL_HRTIM_TIMER_C
8162 * @arg @ref LL_HRTIM_TIMER_D
8163 * @arg @ref LL_HRTIM_TIMER_E
8164 * @retval None
8165 */
LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8166 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8167 {
8168 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8169 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8170 REG_OFFSET_TAB_TIMER[iTimer]));
8171 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
8172 }
8173
8174 /**
8175 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
8176 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
8177 * @param HRTIMx High Resolution Timer instance
8178 * @param Timer This parameter can be one of the following values:
8179 * @arg @ref LL_HRTIM_TIMER_A
8180 * @arg @ref LL_HRTIM_TIMER_B
8181 * @arg @ref LL_HRTIM_TIMER_C
8182 * @arg @ref LL_HRTIM_TIMER_D
8183 * @arg @ref LL_HRTIM_TIMER_E
8184 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
8185 */
LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8186 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8187 {
8188 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8189 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8190 REG_OFFSET_TAB_TIMER[iTimer]));
8191
8192 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
8193 }
8194
8195 /**
8196 * @brief Clear the output 1 set interrupt flag for a given timer.
8197 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
8198 * @param HRTIMx High Resolution Timer instance
8199 * @param Timer This parameter can be one of the following values:
8200 * @arg @ref LL_HRTIM_TIMER_A
8201 * @arg @ref LL_HRTIM_TIMER_B
8202 * @arg @ref LL_HRTIM_TIMER_C
8203 * @arg @ref LL_HRTIM_TIMER_D
8204 * @arg @ref LL_HRTIM_TIMER_E
8205 * @retval None
8206 */
LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8207 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8208 {
8209 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8210 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8211 REG_OFFSET_TAB_TIMER[iTimer]));
8212 SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
8213 }
8214
8215 /**
8216 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
8217 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
8218 * @param HRTIMx High Resolution Timer instance
8219 * @param Timer This parameter can be one of the following values:
8220 * @arg @ref LL_HRTIM_TIMER_A
8221 * @arg @ref LL_HRTIM_TIMER_B
8222 * @arg @ref LL_HRTIM_TIMER_C
8223 * @arg @ref LL_HRTIM_TIMER_D
8224 * @arg @ref LL_HRTIM_TIMER_E
8225 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
8226 */
LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8227 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8228 {
8229 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8230 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8231 REG_OFFSET_TAB_TIMER[iTimer]));
8232
8233 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
8234 }
8235
8236 /**
8237 * @brief Clear the output 1 reset interrupt flag for a given timer.
8238 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
8239 * @param HRTIMx High Resolution Timer instance
8240 * @param Timer This parameter can be one of the following values:
8241 * @arg @ref LL_HRTIM_TIMER_A
8242 * @arg @ref LL_HRTIM_TIMER_B
8243 * @arg @ref LL_HRTIM_TIMER_C
8244 * @arg @ref LL_HRTIM_TIMER_D
8245 * @arg @ref LL_HRTIM_TIMER_E
8246 * @retval None
8247 */
LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8248 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8249 {
8250 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8251 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8252 REG_OFFSET_TAB_TIMER[iTimer]));
8253 SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
8254 }
8255
8256 /**
8257 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
8258 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
8259 * @param HRTIMx High Resolution Timer instance
8260 * @param Timer This parameter can be one of the following values:
8261 * @arg @ref LL_HRTIM_TIMER_A
8262 * @arg @ref LL_HRTIM_TIMER_B
8263 * @arg @ref LL_HRTIM_TIMER_C
8264 * @arg @ref LL_HRTIM_TIMER_D
8265 * @arg @ref LL_HRTIM_TIMER_E
8266 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
8267 */
LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8268 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8269 {
8270 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8271 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8272 REG_OFFSET_TAB_TIMER[iTimer]));
8273
8274 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
8275 }
8276
8277 /**
8278 * @brief Clear the output 2 set interrupt flag for a given timer.
8279 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
8280 * @param HRTIMx High Resolution Timer instance
8281 * @param Timer This parameter can be one of the following values:
8282 * @arg @ref LL_HRTIM_TIMER_A
8283 * @arg @ref LL_HRTIM_TIMER_B
8284 * @arg @ref LL_HRTIM_TIMER_C
8285 * @arg @ref LL_HRTIM_TIMER_D
8286 * @arg @ref LL_HRTIM_TIMER_E
8287 * @retval None
8288 */
LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8289 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8290 {
8291 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8292 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8293 REG_OFFSET_TAB_TIMER[iTimer]));
8294 SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
8295 }
8296
8297 /**
8298 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
8299 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
8300 * @param HRTIMx High Resolution Timer instance
8301 * @param Timer This parameter can be one of the following values:
8302 * @arg @ref LL_HRTIM_TIMER_A
8303 * @arg @ref LL_HRTIM_TIMER_B
8304 * @arg @ref LL_HRTIM_TIMER_C
8305 * @arg @ref LL_HRTIM_TIMER_D
8306 * @arg @ref LL_HRTIM_TIMER_E
8307 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
8308 */
LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8309 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8310 {
8311 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8312 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8313 REG_OFFSET_TAB_TIMER[iTimer]));
8314
8315 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
8316 }
8317
8318 /**
8319 * @brief Clear the output 2reset interrupt flag for a given timer.
8320 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
8321 * @param HRTIMx High Resolution Timer instance
8322 * @param Timer This parameter can be one of the following values:
8323 * @arg @ref LL_HRTIM_TIMER_A
8324 * @arg @ref LL_HRTIM_TIMER_B
8325 * @arg @ref LL_HRTIM_TIMER_C
8326 * @arg @ref LL_HRTIM_TIMER_D
8327 * @arg @ref LL_HRTIM_TIMER_E
8328 * @retval None
8329 */
LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8330 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8331 {
8332 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8333 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8334 REG_OFFSET_TAB_TIMER[iTimer]));
8335 SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
8336 }
8337
8338 /**
8339 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
8340 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
8341 * @param HRTIMx High Resolution Timer instance
8342 * @param Timer This parameter can be one of the following values:
8343 * @arg @ref LL_HRTIM_TIMER_A
8344 * @arg @ref LL_HRTIM_TIMER_B
8345 * @arg @ref LL_HRTIM_TIMER_C
8346 * @arg @ref LL_HRTIM_TIMER_D
8347 * @arg @ref LL_HRTIM_TIMER_E
8348 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
8349 */
LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8350 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8351 {
8352 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8353 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8354 REG_OFFSET_TAB_TIMER[iTimer]));
8355
8356 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
8357 }
8358
8359 /**
8360 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
8361 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
8362 * @param HRTIMx High Resolution Timer instance
8363 * @param Timer This parameter can be one of the following values:
8364 * @arg @ref LL_HRTIM_TIMER_A
8365 * @arg @ref LL_HRTIM_TIMER_B
8366 * @arg @ref LL_HRTIM_TIMER_C
8367 * @arg @ref LL_HRTIM_TIMER_D
8368 * @arg @ref LL_HRTIM_TIMER_E
8369 * @retval None
8370 */
LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8371 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8372 {
8373 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8374 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8375 REG_OFFSET_TAB_TIMER[iTimer]));
8376 SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
8377 }
8378
8379 /**
8380 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
8381 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
8382 * @param HRTIMx High Resolution Timer instance
8383 * @param Timer This parameter can be one of the following values:
8384 * @arg @ref LL_HRTIM_TIMER_A
8385 * @arg @ref LL_HRTIM_TIMER_B
8386 * @arg @ref LL_HRTIM_TIMER_C
8387 * @arg @ref LL_HRTIM_TIMER_D
8388 * @arg @ref LL_HRTIM_TIMER_E
8389 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
8390 */
LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8391 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8392 {
8393 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8394 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8395 REG_OFFSET_TAB_TIMER[iTimer]));
8396
8397 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
8398 }
8399
8400 /**
8401 * @brief Clear the delayed protection interrupt flag for a given timer.
8402 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
8403 * @param HRTIMx High Resolution Timer instance
8404 * @param Timer This parameter can be one of the following values:
8405 * @arg @ref LL_HRTIM_TIMER_A
8406 * @arg @ref LL_HRTIM_TIMER_B
8407 * @arg @ref LL_HRTIM_TIMER_C
8408 * @arg @ref LL_HRTIM_TIMER_D
8409 * @arg @ref LL_HRTIM_TIMER_E
8410 * @retval None
8411 */
LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8412 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8413 {
8414 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8415 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8416 REG_OFFSET_TAB_TIMER[iTimer]));
8417 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
8418 }
8419
8420 /**
8421 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
8422 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
8423 * @param HRTIMx High Resolution Timer instance
8424 * @param Timer This parameter can be one of the following values:
8425 * @arg @ref LL_HRTIM_TIMER_A
8426 * @arg @ref LL_HRTIM_TIMER_B
8427 * @arg @ref LL_HRTIM_TIMER_C
8428 * @arg @ref LL_HRTIM_TIMER_D
8429 * @arg @ref LL_HRTIM_TIMER_E
8430 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
8431 */
LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8432 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8433 {
8434 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8435 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8436 REG_OFFSET_TAB_TIMER[iTimer]));
8437
8438 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
8439 }
8440
8441 /**
8442 * @}
8443 */
8444
8445 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
8446 * @{
8447 */
8448
8449 /**
8450 * @brief Enable the fault 1 interrupt.
8451 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
8452 * @param HRTIMx High Resolution Timer instance
8453 * @retval None
8454 */
LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef * HRTIMx)8455 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
8456 {
8457 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
8458 }
8459
8460 /**
8461 * @brief Disable the fault 1 interrupt.
8462 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
8463 * @param HRTIMx High Resolution Timer instance
8464 * @retval None
8465 */
LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef * HRTIMx)8466 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
8467 {
8468 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
8469 }
8470
8471 /**
8472 * @brief Indicate whether the fault 1 interrupt is enabled.
8473 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
8474 * @param HRTIMx High Resolution Timer instance
8475 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
8476 */
LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef * HRTIMx)8477 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
8478 {
8479 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
8480 }
8481
8482 /**
8483 * @brief Enable the fault 2 interrupt.
8484 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
8485 * @param HRTIMx High Resolution Timer instance
8486 * @retval None
8487 */
LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef * HRTIMx)8488 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
8489 {
8490 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
8491 }
8492
8493 /**
8494 * @brief Disable the fault 2 interrupt.
8495 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
8496 * @param HRTIMx High Resolution Timer instance
8497 * @retval None
8498 */
LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef * HRTIMx)8499 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
8500 {
8501 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
8502 }
8503
8504 /**
8505 * @brief Indicate whether the fault 2 interrupt is enabled.
8506 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
8507 * @param HRTIMx High Resolution Timer instance
8508 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
8509 */
LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef * HRTIMx)8510 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
8511 {
8512 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
8513 }
8514
8515 /**
8516 * @brief Enable the fault 3 interrupt.
8517 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
8518 * @param HRTIMx High Resolution Timer instance
8519 * @retval None
8520 */
LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef * HRTIMx)8521 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
8522 {
8523 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
8524 }
8525
8526 /**
8527 * @brief Disable the fault 3 interrupt.
8528 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
8529 * @param HRTIMx High Resolution Timer instance
8530 * @retval None
8531 */
LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef * HRTIMx)8532 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
8533 {
8534 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
8535 }
8536
8537 /**
8538 * @brief Indicate whether the fault 3 interrupt is enabled.
8539 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
8540 * @param HRTIMx High Resolution Timer instance
8541 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
8542 */
LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef * HRTIMx)8543 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
8544 {
8545 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
8546 }
8547
8548 /**
8549 * @brief Enable the fault 4 interrupt.
8550 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
8551 * @param HRTIMx High Resolution Timer instance
8552 * @retval None
8553 */
LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef * HRTIMx)8554 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
8555 {
8556 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
8557 }
8558
8559 /**
8560 * @brief Disable the fault 4 interrupt.
8561 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
8562 * @param HRTIMx High Resolution Timer instance
8563 * @retval None
8564 */
LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef * HRTIMx)8565 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
8566 {
8567 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
8568 }
8569
8570 /**
8571 * @brief Indicate whether the fault 4 interrupt is enabled.
8572 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
8573 * @param HRTIMx High Resolution Timer instance
8574 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
8575 */
LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef * HRTIMx)8576 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
8577 {
8578 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
8579 }
8580
8581 /**
8582 * @brief Enable the fault 5 interrupt.
8583 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
8584 * @param HRTIMx High Resolution Timer instance
8585 * @retval None
8586 */
LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef * HRTIMx)8587 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
8588 {
8589 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
8590 }
8591
8592 /**
8593 * @brief Disable the fault 5 interrupt.
8594 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
8595 * @param HRTIMx High Resolution Timer instance
8596 * @retval None
8597 */
LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef * HRTIMx)8598 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
8599 {
8600 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
8601 }
8602
8603 /**
8604 * @brief Indicate whether the fault 5 interrupt is enabled.
8605 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
8606 * @param HRTIMx High Resolution Timer instance
8607 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
8608 */
LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef * HRTIMx)8609 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
8610 {
8611 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
8612 }
8613
8614 /**
8615 * @brief Enable the system fault interrupt.
8616 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
8617 * @param HRTIMx High Resolution Timer instance
8618 * @retval None
8619 */
LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)8620 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
8621 {
8622 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
8623 }
8624
8625 /**
8626 * @brief Disable the system fault interrupt.
8627 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
8628 * @param HRTIMx High Resolution Timer instance
8629 * @retval None
8630 */
LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)8631 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
8632 {
8633 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
8634 }
8635
8636 /**
8637 * @brief Indicate whether the system fault interrupt is enabled.
8638 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
8639 * @param HRTIMx High Resolution Timer instance
8640 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
8641 */
LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef * HRTIMx)8642 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
8643 {
8644 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
8645 }
8646
8647 /**
8648 * @brief Enable the DLL ready interrupt.
8649 * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
8650 * @param HRTIMx High Resolution Timer instance
8651 * @retval None
8652 */
LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)8653 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
8654 {
8655 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
8656 }
8657
8658 /**
8659 * @brief Disable the DLL ready interrupt.
8660 * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
8661 * @param HRTIMx High Resolution Timer instance
8662 * @retval None
8663 */
LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)8664 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
8665 {
8666 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
8667 }
8668
8669 /**
8670 * @brief Indicate whether the DLL ready interrupt is enabled.
8671 * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
8672 * @param HRTIMx High Resolution Timer instance
8673 * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
8674 */
LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef * HRTIMx)8675 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef *HRTIMx)
8676 {
8677 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
8678 }
8679
8680 /**
8681 * @brief Enable the burst mode period interrupt.
8682 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
8683 * @param HRTIMx High Resolution Timer instance
8684 * @retval None
8685 */
LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef * HRTIMx)8686 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
8687 {
8688 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
8689 }
8690
8691 /**
8692 * @brief Disable the burst mode period interrupt.
8693 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
8694 * @param HRTIMx High Resolution Timer instance
8695 * @retval None
8696 */
LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef * HRTIMx)8697 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
8698 {
8699 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
8700 }
8701
8702 /**
8703 * @brief Indicate whether the burst mode period interrupt is enabled.
8704 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
8705 * @param HRTIMx High Resolution Timer instance
8706 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
8707 */
LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef * HRTIMx)8708 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
8709 {
8710 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
8711 }
8712
8713 /**
8714 * @brief Enable the synchronization input interrupt.
8715 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
8716 * @param HRTIMx High Resolution Timer instance
8717 * @retval None
8718 */
LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef * HRTIMx)8719 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
8720 {
8721 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
8722 }
8723
8724 /**
8725 * @brief Disable the synchronization input interrupt.
8726 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
8727 * @param HRTIMx High Resolution Timer instance
8728 * @retval None
8729 */
LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef * HRTIMx)8730 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
8731 {
8732 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
8733 }
8734
8735 /**
8736 * @brief Indicate whether the synchronization input interrupt is enabled.
8737 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
8738 * @param HRTIMx High Resolution Timer instance
8739 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
8740 */
LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef * HRTIMx)8741 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
8742 {
8743 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
8744 }
8745
8746 /**
8747 * @brief Enable the update interrupt for a given timer.
8748 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
8749 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
8750 * @param HRTIMx High Resolution Timer instance
8751 * @param Timer This parameter can be one of the following values:
8752 * @arg @ref LL_HRTIM_TIMER_MASTER
8753 * @arg @ref LL_HRTIM_TIMER_A
8754 * @arg @ref LL_HRTIM_TIMER_B
8755 * @arg @ref LL_HRTIM_TIMER_C
8756 * @arg @ref LL_HRTIM_TIMER_D
8757 * @arg @ref LL_HRTIM_TIMER_E
8758 * @retval None
8759 */
LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8760 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8761 {
8762 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8763 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8764 REG_OFFSET_TAB_TIMER[iTimer]));
8765 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
8766 }
8767
8768 /**
8769 * @brief Disable the update interrupt for a given timer.
8770 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
8771 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
8772 * @param HRTIMx High Resolution Timer instance
8773 * @param Timer This parameter can be one of the following values:
8774 * @arg @ref LL_HRTIM_TIMER_MASTER
8775 * @arg @ref LL_HRTIM_TIMER_A
8776 * @arg @ref LL_HRTIM_TIMER_B
8777 * @arg @ref LL_HRTIM_TIMER_C
8778 * @arg @ref LL_HRTIM_TIMER_D
8779 * @arg @ref LL_HRTIM_TIMER_E
8780 * @retval None
8781 */
LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8782 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8783 {
8784 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8785 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8786 REG_OFFSET_TAB_TIMER[iTimer]));
8787 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
8788 }
8789
8790 /**
8791 * @brief Indicate whether the update interrupt is enabled for a given timer.
8792 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
8793 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
8794 * @param HRTIMx High Resolution Timer instance
8795 * @param Timer This parameter can be one of the following values:
8796 * @arg @ref LL_HRTIM_TIMER_MASTER
8797 * @arg @ref LL_HRTIM_TIMER_A
8798 * @arg @ref LL_HRTIM_TIMER_B
8799 * @arg @ref LL_HRTIM_TIMER_C
8800 * @arg @ref LL_HRTIM_TIMER_D
8801 * @arg @ref LL_HRTIM_TIMER_E
8802 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8803 */
LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8804 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8805 {
8806 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8807 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8808 REG_OFFSET_TAB_TIMER[iTimer]));
8809
8810 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
8811 }
8812
8813 /**
8814 * @brief Enable the repetition interrupt for a given timer.
8815 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
8816 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
8817 * @param HRTIMx High Resolution Timer instance
8818 * @param Timer This parameter can be one of the following values:
8819 * @arg @ref LL_HRTIM_TIMER_MASTER
8820 * @arg @ref LL_HRTIM_TIMER_A
8821 * @arg @ref LL_HRTIM_TIMER_B
8822 * @arg @ref LL_HRTIM_TIMER_C
8823 * @arg @ref LL_HRTIM_TIMER_D
8824 * @arg @ref LL_HRTIM_TIMER_E
8825 * @retval None
8826 */
LL_HRTIM_EnableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8827 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8828 {
8829 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8830 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8831 REG_OFFSET_TAB_TIMER[iTimer]));
8832 SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
8833 }
8834
8835 /**
8836 * @brief Disable the repetition interrupt for a given timer.
8837 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
8838 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
8839 * @param HRTIMx High Resolution Timer instance
8840 * @param Timer This parameter can be one of the following values:
8841 * @arg @ref LL_HRTIM_TIMER_MASTER
8842 * @arg @ref LL_HRTIM_TIMER_A
8843 * @arg @ref LL_HRTIM_TIMER_B
8844 * @arg @ref LL_HRTIM_TIMER_C
8845 * @arg @ref LL_HRTIM_TIMER_D
8846 * @arg @ref LL_HRTIM_TIMER_E
8847 * @retval None
8848 */
LL_HRTIM_DisableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8849 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8850 {
8851 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8852 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8853 REG_OFFSET_TAB_TIMER[iTimer]));
8854 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
8855 }
8856
8857 /**
8858 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
8859 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
8860 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
8861 * @param HRTIMx High Resolution Timer instance
8862 * @param Timer This parameter can be one of the following values:
8863 * @arg @ref LL_HRTIM_TIMER_MASTER
8864 * @arg @ref LL_HRTIM_TIMER_A
8865 * @arg @ref LL_HRTIM_TIMER_B
8866 * @arg @ref LL_HRTIM_TIMER_C
8867 * @arg @ref LL_HRTIM_TIMER_D
8868 * @arg @ref LL_HRTIM_TIMER_E
8869 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8870 */
LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8871 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8872 {
8873 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8874 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8875 REG_OFFSET_TAB_TIMER[iTimer]));
8876
8877 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
8878 }
8879
8880 /**
8881 * @brief Enable the compare 1 interrupt for a given timer.
8882 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
8883 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
8884 * @param HRTIMx High Resolution Timer instance
8885 * @param Timer This parameter can be one of the following values:
8886 * @arg @ref LL_HRTIM_TIMER_MASTER
8887 * @arg @ref LL_HRTIM_TIMER_A
8888 * @arg @ref LL_HRTIM_TIMER_B
8889 * @arg @ref LL_HRTIM_TIMER_C
8890 * @arg @ref LL_HRTIM_TIMER_D
8891 * @arg @ref LL_HRTIM_TIMER_E
8892 * @retval None
8893 */
LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8894 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8895 {
8896 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8897 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8898 REG_OFFSET_TAB_TIMER[iTimer]));
8899 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
8900 }
8901
8902 /**
8903 * @brief Disable the compare 1 interrupt for a given timer.
8904 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
8905 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
8906 * @param HRTIMx High Resolution Timer instance
8907 * @param Timer This parameter can be one of the following values:
8908 * @arg @ref LL_HRTIM_TIMER_MASTER
8909 * @arg @ref LL_HRTIM_TIMER_A
8910 * @arg @ref LL_HRTIM_TIMER_B
8911 * @arg @ref LL_HRTIM_TIMER_C
8912 * @arg @ref LL_HRTIM_TIMER_D
8913 * @arg @ref LL_HRTIM_TIMER_E
8914 * @retval None
8915 */
LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8916 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8917 {
8918 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8919 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8920 REG_OFFSET_TAB_TIMER[iTimer]));
8921 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
8922 }
8923
8924 /**
8925 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
8926 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
8927 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
8928 * @param HRTIMx High Resolution Timer instance
8929 * @param Timer This parameter can be one of the following values:
8930 * @arg @ref LL_HRTIM_TIMER_MASTER
8931 * @arg @ref LL_HRTIM_TIMER_A
8932 * @arg @ref LL_HRTIM_TIMER_B
8933 * @arg @ref LL_HRTIM_TIMER_C
8934 * @arg @ref LL_HRTIM_TIMER_D
8935 * @arg @ref LL_HRTIM_TIMER_E
8936 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8937 */
LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8938 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8939 {
8940 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8941 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8942 REG_OFFSET_TAB_TIMER[iTimer]));
8943
8944 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
8945 }
8946
8947 /**
8948 * @brief Enable the compare 2 interrupt for a given timer.
8949 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
8950 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
8951 * @param HRTIMx High Resolution Timer instance
8952 * @param Timer This parameter can be one of the following values:
8953 * @arg @ref LL_HRTIM_TIMER_MASTER
8954 * @arg @ref LL_HRTIM_TIMER_A
8955 * @arg @ref LL_HRTIM_TIMER_B
8956 * @arg @ref LL_HRTIM_TIMER_C
8957 * @arg @ref LL_HRTIM_TIMER_D
8958 * @arg @ref LL_HRTIM_TIMER_E
8959 * @retval None
8960 */
LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8961 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8962 {
8963 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8964 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8965 REG_OFFSET_TAB_TIMER[iTimer]));
8966 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
8967 }
8968
8969 /**
8970 * @brief Disable the compare 2 interrupt for a given timer.
8971 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
8972 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
8973 * @param HRTIMx High Resolution Timer instance
8974 * @param Timer This parameter can be one of the following values:
8975 * @arg @ref LL_HRTIM_TIMER_MASTER
8976 * @arg @ref LL_HRTIM_TIMER_A
8977 * @arg @ref LL_HRTIM_TIMER_B
8978 * @arg @ref LL_HRTIM_TIMER_C
8979 * @arg @ref LL_HRTIM_TIMER_D
8980 * @arg @ref LL_HRTIM_TIMER_E
8981 * @retval None
8982 */
LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8983 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8984 {
8985 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8986 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8987 REG_OFFSET_TAB_TIMER[iTimer]));
8988 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
8989 }
8990
8991 /**
8992 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
8993 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
8994 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
8995 * @param HRTIMx High Resolution Timer instance
8996 * @param Timer This parameter can be one of the following values:
8997 * @arg @ref LL_HRTIM_TIMER_MASTER
8998 * @arg @ref LL_HRTIM_TIMER_A
8999 * @arg @ref LL_HRTIM_TIMER_B
9000 * @arg @ref LL_HRTIM_TIMER_C
9001 * @arg @ref LL_HRTIM_TIMER_D
9002 * @arg @ref LL_HRTIM_TIMER_E
9003 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9004 */
LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9005 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9006 {
9007 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9008 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9009 REG_OFFSET_TAB_TIMER[iTimer]));
9010
9011 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
9012 }
9013
9014 /**
9015 * @brief Enable the compare 3 interrupt for a given timer.
9016 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
9017 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
9018 * @param HRTIMx High Resolution Timer instance
9019 * @param Timer This parameter can be one of the following values:
9020 * @arg @ref LL_HRTIM_TIMER_MASTER
9021 * @arg @ref LL_HRTIM_TIMER_A
9022 * @arg @ref LL_HRTIM_TIMER_B
9023 * @arg @ref LL_HRTIM_TIMER_C
9024 * @arg @ref LL_HRTIM_TIMER_D
9025 * @arg @ref LL_HRTIM_TIMER_E
9026 * @retval None
9027 */
LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9028 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9029 {
9030 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9031 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9032 REG_OFFSET_TAB_TIMER[iTimer]));
9033 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
9034 }
9035
9036 /**
9037 * @brief Disable the compare 3 interrupt for a given timer.
9038 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
9039 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
9040 * @param HRTIMx High Resolution Timer instance
9041 * @param Timer This parameter can be one of the following values:
9042 * @arg @ref LL_HRTIM_TIMER_MASTER
9043 * @arg @ref LL_HRTIM_TIMER_A
9044 * @arg @ref LL_HRTIM_TIMER_B
9045 * @arg @ref LL_HRTIM_TIMER_C
9046 * @arg @ref LL_HRTIM_TIMER_D
9047 * @arg @ref LL_HRTIM_TIMER_E
9048 * @retval None
9049 */
LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9050 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9051 {
9052 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9053 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9054 REG_OFFSET_TAB_TIMER[iTimer]));
9055 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
9056 }
9057
9058 /**
9059 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
9060 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
9061 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
9062 * @param HRTIMx High Resolution Timer instance
9063 * @param Timer This parameter can be one of the following values:
9064 * @arg @ref LL_HRTIM_TIMER_MASTER
9065 * @arg @ref LL_HRTIM_TIMER_A
9066 * @arg @ref LL_HRTIM_TIMER_B
9067 * @arg @ref LL_HRTIM_TIMER_C
9068 * @arg @ref LL_HRTIM_TIMER_D
9069 * @arg @ref LL_HRTIM_TIMER_E
9070 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9071 */
LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9072 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9073 {
9074 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9075 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9076 REG_OFFSET_TAB_TIMER[iTimer]));
9077
9078 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
9079 }
9080
9081 /**
9082 * @brief Enable the compare 4 interrupt for a given timer.
9083 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
9084 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
9085 * @param HRTIMx High Resolution Timer instance
9086 * @param Timer This parameter can be one of the following values:
9087 * @arg @ref LL_HRTIM_TIMER_MASTER
9088 * @arg @ref LL_HRTIM_TIMER_A
9089 * @arg @ref LL_HRTIM_TIMER_B
9090 * @arg @ref LL_HRTIM_TIMER_C
9091 * @arg @ref LL_HRTIM_TIMER_D
9092 * @arg @ref LL_HRTIM_TIMER_E
9093 * @retval None
9094 */
LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9095 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9096 {
9097 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9098 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9099 REG_OFFSET_TAB_TIMER[iTimer]));
9100 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
9101 }
9102
9103 /**
9104 * @brief Disable the compare 4 interrupt for a given timer.
9105 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
9106 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
9107 * @param HRTIMx High Resolution Timer instance
9108 * @param Timer This parameter can be one of the following values:
9109 * @arg @ref LL_HRTIM_TIMER_MASTER
9110 * @arg @ref LL_HRTIM_TIMER_A
9111 * @arg @ref LL_HRTIM_TIMER_B
9112 * @arg @ref LL_HRTIM_TIMER_C
9113 * @arg @ref LL_HRTIM_TIMER_D
9114 * @arg @ref LL_HRTIM_TIMER_E
9115 * @retval None
9116 */
LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9117 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9118 {
9119 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9120 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9121 REG_OFFSET_TAB_TIMER[iTimer]));
9122 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
9123 }
9124
9125 /**
9126 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
9127 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
9128 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
9129 * @param HRTIMx High Resolution Timer instance
9130 * @param Timer This parameter can be one of the following values:
9131 * @arg @ref LL_HRTIM_TIMER_MASTER
9132 * @arg @ref LL_HRTIM_TIMER_A
9133 * @arg @ref LL_HRTIM_TIMER_B
9134 * @arg @ref LL_HRTIM_TIMER_C
9135 * @arg @ref LL_HRTIM_TIMER_D
9136 * @arg @ref LL_HRTIM_TIMER_E
9137 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9138 */
LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9139 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9140 {
9141 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9142 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9143 REG_OFFSET_TAB_TIMER[iTimer]));
9144
9145 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
9146 }
9147
9148 /**
9149 * @brief Enable the capture 1 interrupt for a given timer.
9150 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
9151 * @param HRTIMx High Resolution Timer instance
9152 * @param Timer This parameter can be one of the following values:
9153 * @arg @ref LL_HRTIM_TIMER_A
9154 * @arg @ref LL_HRTIM_TIMER_B
9155 * @arg @ref LL_HRTIM_TIMER_C
9156 * @arg @ref LL_HRTIM_TIMER_D
9157 * @arg @ref LL_HRTIM_TIMER_E
9158 * @retval None
9159 */
LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9160 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9161 {
9162 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9163 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9164 REG_OFFSET_TAB_TIMER[iTimer]));
9165 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
9166 }
9167
9168 /**
9169 * @brief Enable the capture 1 interrupt for a given timer.
9170 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
9171 * @param HRTIMx High Resolution Timer instance
9172 * @param Timer This parameter can be one of the following values:
9173 * @arg @ref LL_HRTIM_TIMER_A
9174 * @arg @ref LL_HRTIM_TIMER_B
9175 * @arg @ref LL_HRTIM_TIMER_C
9176 * @arg @ref LL_HRTIM_TIMER_D
9177 * @arg @ref LL_HRTIM_TIMER_E
9178 * @retval None
9179 */
LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9180 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9181 {
9182 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9183 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9184 REG_OFFSET_TAB_TIMER[iTimer]));
9185 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
9186 }
9187
9188 /**
9189 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
9190 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
9191 * @param HRTIMx High Resolution Timer instance
9192 * @param Timer This parameter can be one of the following values:
9193 * @arg @ref LL_HRTIM_TIMER_A
9194 * @arg @ref LL_HRTIM_TIMER_B
9195 * @arg @ref LL_HRTIM_TIMER_C
9196 * @arg @ref LL_HRTIM_TIMER_D
9197 * @arg @ref LL_HRTIM_TIMER_E
9198 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
9199 */
LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9200 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9201 {
9202 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9203 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9204 REG_OFFSET_TAB_TIMER[iTimer]));
9205
9206 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
9207 }
9208
9209 /**
9210 * @brief Enable the capture 2 interrupt for a given timer.
9211 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
9212 * @param HRTIMx High Resolution Timer instance
9213 * @param Timer This parameter can be one of the following values:
9214 * @arg @ref LL_HRTIM_TIMER_A
9215 * @arg @ref LL_HRTIM_TIMER_B
9216 * @arg @ref LL_HRTIM_TIMER_C
9217 * @arg @ref LL_HRTIM_TIMER_D
9218 * @arg @ref LL_HRTIM_TIMER_E
9219 * @retval None
9220 */
LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9221 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9222 {
9223 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9224 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9225 REG_OFFSET_TAB_TIMER[iTimer]));
9226 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
9227 }
9228
9229 /**
9230 * @brief Enable the capture 2 interrupt for a given timer.
9231 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
9232 * @param HRTIMx High Resolution Timer instance
9233 * @param Timer This parameter can be one of the following values:
9234 * @arg @ref LL_HRTIM_TIMER_A
9235 * @arg @ref LL_HRTIM_TIMER_B
9236 * @arg @ref LL_HRTIM_TIMER_C
9237 * @arg @ref LL_HRTIM_TIMER_D
9238 * @arg @ref LL_HRTIM_TIMER_E
9239 * @retval None
9240 */
LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9241 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9242 {
9243 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9244 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9245 REG_OFFSET_TAB_TIMER[iTimer]));
9246 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
9247 }
9248
9249 /**
9250 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
9251 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
9252 * @param HRTIMx High Resolution Timer instance
9253 * @param Timer This parameter can be one of the following values:
9254 * @arg @ref LL_HRTIM_TIMER_A
9255 * @arg @ref LL_HRTIM_TIMER_B
9256 * @arg @ref LL_HRTIM_TIMER_C
9257 * @arg @ref LL_HRTIM_TIMER_D
9258 * @arg @ref LL_HRTIM_TIMER_E
9259 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
9260 */
LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9261 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9262 {
9263 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9264 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9265 REG_OFFSET_TAB_TIMER[iTimer]));
9266
9267 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
9268 }
9269
9270 /**
9271 * @brief Enable the output 1 set interrupt for a given timer.
9272 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
9273 * @param HRTIMx High Resolution Timer instance
9274 * @param Timer This parameter can be one of the following values:
9275 * @arg @ref LL_HRTIM_TIMER_A
9276 * @arg @ref LL_HRTIM_TIMER_B
9277 * @arg @ref LL_HRTIM_TIMER_C
9278 * @arg @ref LL_HRTIM_TIMER_D
9279 * @arg @ref LL_HRTIM_TIMER_E
9280 * @retval None
9281 */
LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9282 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9283 {
9284 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9285 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9286 REG_OFFSET_TAB_TIMER[iTimer]));
9287 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
9288 }
9289
9290 /**
9291 * @brief Disable the output 1 set interrupt for a given timer.
9292 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
9293 * @param HRTIMx High Resolution Timer instance
9294 * @param Timer This parameter can be one of the following values:
9295 * @arg @ref LL_HRTIM_TIMER_A
9296 * @arg @ref LL_HRTIM_TIMER_B
9297 * @arg @ref LL_HRTIM_TIMER_C
9298 * @arg @ref LL_HRTIM_TIMER_D
9299 * @arg @ref LL_HRTIM_TIMER_E
9300 * @retval None
9301 */
LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9302 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9303 {
9304 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9305 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9306 REG_OFFSET_TAB_TIMER[iTimer]));
9307 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
9308 }
9309
9310 /**
9311 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
9312 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
9313 * @param HRTIMx High Resolution Timer instance
9314 * @param Timer This parameter can be one of the following values:
9315 * @arg @ref LL_HRTIM_TIMER_A
9316 * @arg @ref LL_HRTIM_TIMER_B
9317 * @arg @ref LL_HRTIM_TIMER_C
9318 * @arg @ref LL_HRTIM_TIMER_D
9319 * @arg @ref LL_HRTIM_TIMER_E
9320 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9321 */
LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9322 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9323 {
9324 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9325 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9326 REG_OFFSET_TAB_TIMER[iTimer]));
9327
9328 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
9329 }
9330
9331 /**
9332 * @brief Enable the output 1 reset interrupt for a given timer.
9333 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
9334 * @param HRTIMx High Resolution Timer instance
9335 * @param Timer This parameter can be one of the following values:
9336 * @arg @ref LL_HRTIM_TIMER_A
9337 * @arg @ref LL_HRTIM_TIMER_B
9338 * @arg @ref LL_HRTIM_TIMER_C
9339 * @arg @ref LL_HRTIM_TIMER_D
9340 * @arg @ref LL_HRTIM_TIMER_E
9341 * @retval None
9342 */
LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9343 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9344 {
9345 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9346 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9347 REG_OFFSET_TAB_TIMER[iTimer]));
9348 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
9349 }
9350
9351 /**
9352 * @brief Disable the output 1 reset interrupt for a given timer.
9353 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
9354 * @param HRTIMx High Resolution Timer instance
9355 * @param Timer This parameter can be one of the following values:
9356 * @arg @ref LL_HRTIM_TIMER_A
9357 * @arg @ref LL_HRTIM_TIMER_B
9358 * @arg @ref LL_HRTIM_TIMER_C
9359 * @arg @ref LL_HRTIM_TIMER_D
9360 * @arg @ref LL_HRTIM_TIMER_E
9361 * @retval None
9362 */
LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9363 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9364 {
9365 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9366 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9367 REG_OFFSET_TAB_TIMER[iTimer]));
9368 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
9369 }
9370
9371 /**
9372 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
9373 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
9374 * @param HRTIMx High Resolution Timer instance
9375 * @param Timer This parameter can be one of the following values:
9376 * @arg @ref LL_HRTIM_TIMER_A
9377 * @arg @ref LL_HRTIM_TIMER_B
9378 * @arg @ref LL_HRTIM_TIMER_C
9379 * @arg @ref LL_HRTIM_TIMER_D
9380 * @arg @ref LL_HRTIM_TIMER_E
9381 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9382 */
LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9383 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9384 {
9385 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9386 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9387 REG_OFFSET_TAB_TIMER[iTimer]));
9388
9389 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
9390 }
9391
9392 /**
9393 * @brief Enable the output 2 set interrupt for a given timer.
9394 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
9395 * @param HRTIMx High Resolution Timer instance
9396 * @param Timer This parameter can be one of the following values:
9397 * @arg @ref LL_HRTIM_TIMER_A
9398 * @arg @ref LL_HRTIM_TIMER_B
9399 * @arg @ref LL_HRTIM_TIMER_C
9400 * @arg @ref LL_HRTIM_TIMER_D
9401 * @arg @ref LL_HRTIM_TIMER_E
9402 * @retval None
9403 */
LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9404 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9405 {
9406 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9407 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9408 REG_OFFSET_TAB_TIMER[iTimer]));
9409 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
9410 }
9411
9412 /**
9413 * @brief Disable the output 2 set interrupt for a given timer.
9414 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
9415 * @param HRTIMx High Resolution Timer instance
9416 * @param Timer This parameter can be one of the following values:
9417 * @arg @ref LL_HRTIM_TIMER_A
9418 * @arg @ref LL_HRTIM_TIMER_B
9419 * @arg @ref LL_HRTIM_TIMER_C
9420 * @arg @ref LL_HRTIM_TIMER_D
9421 * @arg @ref LL_HRTIM_TIMER_E
9422 * @retval None
9423 */
LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9424 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9425 {
9426 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9427 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9428 REG_OFFSET_TAB_TIMER[iTimer]));
9429 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
9430 }
9431
9432 /**
9433 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
9434 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
9435 * @param HRTIMx High Resolution Timer instance
9436 * @param Timer This parameter can be one of the following values:
9437 * @arg @ref LL_HRTIM_TIMER_A
9438 * @arg @ref LL_HRTIM_TIMER_B
9439 * @arg @ref LL_HRTIM_TIMER_C
9440 * @arg @ref LL_HRTIM_TIMER_D
9441 * @arg @ref LL_HRTIM_TIMER_E
9442 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9443 */
LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9444 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9445 {
9446 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9447 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9448 REG_OFFSET_TAB_TIMER[iTimer]));
9449
9450 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
9451 }
9452
9453 /**
9454 * @brief Enable the output 2 reset interrupt for a given timer.
9455 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
9456 * @param HRTIMx High Resolution Timer instance
9457 * @param Timer This parameter can be one of the following values:
9458 * @arg @ref LL_HRTIM_TIMER_A
9459 * @arg @ref LL_HRTIM_TIMER_B
9460 * @arg @ref LL_HRTIM_TIMER_C
9461 * @arg @ref LL_HRTIM_TIMER_D
9462 * @arg @ref LL_HRTIM_TIMER_E
9463 * @retval None
9464 */
LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9465 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9466 {
9467 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9468 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9469 REG_OFFSET_TAB_TIMER[iTimer]));
9470 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
9471 }
9472
9473 /**
9474 * @brief Disable the output 2 reset interrupt for a given timer.
9475 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9476 * @param HRTIMx High Resolution Timer instance
9477 * @param Timer This parameter can be one of the following values:
9478 * @arg @ref LL_HRTIM_TIMER_A
9479 * @arg @ref LL_HRTIM_TIMER_B
9480 * @arg @ref LL_HRTIM_TIMER_C
9481 * @arg @ref LL_HRTIM_TIMER_D
9482 * @arg @ref LL_HRTIM_TIMER_E
9483 * @retval None
9484 */
LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9485 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9486 {
9487 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9488 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9489 REG_OFFSET_TAB_TIMER[iTimer]));
9490 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
9491 }
9492
9493 /**
9494 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
9495 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9496 * @param HRTIMx High Resolution Timer instance
9497 * @param Timer This parameter can be one of the following values:
9498 * @arg @ref LL_HRTIM_TIMER_A
9499 * @arg @ref LL_HRTIM_TIMER_B
9500 * @arg @ref LL_HRTIM_TIMER_C
9501 * @arg @ref LL_HRTIM_TIMER_D
9502 * @arg @ref LL_HRTIM_TIMER_E
9503 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9504 */
LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9505 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9506 {
9507 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9508 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9509 REG_OFFSET_TAB_TIMER[iTimer]));
9510
9511 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
9512 }
9513
9514 /**
9515 * @brief Enable the reset/roll-over interrupt for a given timer.
9516 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
9517 * @param HRTIMx High Resolution Timer instance
9518 * @param Timer This parameter can be one of the following values:
9519 * @arg @ref LL_HRTIM_TIMER_A
9520 * @arg @ref LL_HRTIM_TIMER_B
9521 * @arg @ref LL_HRTIM_TIMER_C
9522 * @arg @ref LL_HRTIM_TIMER_D
9523 * @arg @ref LL_HRTIM_TIMER_E
9524 * @retval None
9525 */
LL_HRTIM_EnableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9526 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9527 {
9528 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9529 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9530 REG_OFFSET_TAB_TIMER[iTimer]));
9531 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
9532 }
9533
9534 /**
9535 * @brief Disable the reset/roll-over interrupt for a given timer.
9536 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
9537 * @param HRTIMx High Resolution Timer instance
9538 * @param Timer This parameter can be one of the following values:
9539 * @arg @ref LL_HRTIM_TIMER_A
9540 * @arg @ref LL_HRTIM_TIMER_B
9541 * @arg @ref LL_HRTIM_TIMER_C
9542 * @arg @ref LL_HRTIM_TIMER_D
9543 * @arg @ref LL_HRTIM_TIMER_E
9544 * @retval None
9545 */
LL_HRTIM_DisableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9546 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9547 {
9548 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9549 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9550 REG_OFFSET_TAB_TIMER[iTimer]));
9551 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
9552 }
9553
9554 /**
9555 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
9556 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
9557 * @param HRTIMx High Resolution Timer instance
9558 * @param Timer This parameter can be one of the following values:
9559 * @arg @ref LL_HRTIM_TIMER_A
9560 * @arg @ref LL_HRTIM_TIMER_B
9561 * @arg @ref LL_HRTIM_TIMER_C
9562 * @arg @ref LL_HRTIM_TIMER_D
9563 * @arg @ref LL_HRTIM_TIMER_E
9564 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
9565 */
LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9566 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9567 {
9568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9569 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9570 REG_OFFSET_TAB_TIMER[iTimer]));
9571
9572 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
9573 }
9574
9575 /**
9576 * @brief Enable the delayed protection interrupt for a given timer.
9577 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
9578 * @param HRTIMx High Resolution Timer instance
9579 * @param Timer This parameter can be one of the following values:
9580 * @arg @ref LL_HRTIM_TIMER_A
9581 * @arg @ref LL_HRTIM_TIMER_B
9582 * @arg @ref LL_HRTIM_TIMER_C
9583 * @arg @ref LL_HRTIM_TIMER_D
9584 * @arg @ref LL_HRTIM_TIMER_E
9585 * @retval None
9586 */
LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9587 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9588 {
9589 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9590 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9591 REG_OFFSET_TAB_TIMER[iTimer]));
9592 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
9593 }
9594
9595 /**
9596 * @brief Disable the delayed protection interrupt for a given timer.
9597 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
9598 * @param HRTIMx High Resolution Timer instance
9599 * @param Timer This parameter can be one of the following values:
9600 * @arg @ref LL_HRTIM_TIMER_A
9601 * @arg @ref LL_HRTIM_TIMER_B
9602 * @arg @ref LL_HRTIM_TIMER_C
9603 * @arg @ref LL_HRTIM_TIMER_D
9604 * @arg @ref LL_HRTIM_TIMER_E
9605 * @retval None
9606 */
LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9607 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9608 {
9609 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9610 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9611 REG_OFFSET_TAB_TIMER[iTimer]));
9612 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
9613 }
9614
9615 /**
9616 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
9617 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
9618 * @param HRTIMx High Resolution Timer instance
9619 * @param Timer This parameter can be one of the following values:
9620 * @arg @ref LL_HRTIM_TIMER_A
9621 * @arg @ref LL_HRTIM_TIMER_B
9622 * @arg @ref LL_HRTIM_TIMER_C
9623 * @arg @ref LL_HRTIM_TIMER_D
9624 * @arg @ref LL_HRTIM_TIMER_E
9625 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
9626 */
LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9627 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9628 {
9629 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9630 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9631 REG_OFFSET_TAB_TIMER[iTimer]));
9632
9633 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
9634 }
9635
9636 /**
9637 * @}
9638 */
9639
9640 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
9641 * @{
9642 */
9643
9644 /**
9645 * @brief Enable the synchronization input DMA request.
9646 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
9647 * @param HRTIMx High Resolution Timer instance
9648 * @retval None
9649 */
LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)9650 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
9651 {
9652 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
9653 }
9654
9655 /**
9656 * @brief Disable the synchronization input DMA request
9657 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
9658 * @param HRTIMx High Resolution Timer instance
9659 * @retval None
9660 */
LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)9661 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
9662 {
9663 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
9664 }
9665
9666 /**
9667 * @brief Indicate whether the synchronization input DMA request is enabled.
9668 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
9669 * @param HRTIMx High Resolution Timer instance
9670 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
9671 */
LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef * HRTIMx)9672 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
9673 {
9674 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
9675 }
9676
9677 /**
9678 * @brief Enable the update DMA request for a given timer.
9679 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
9680 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
9681 * @param HRTIMx High Resolution Timer instance
9682 * @param Timer This parameter can be one of the following values:
9683 * @arg @ref LL_HRTIM_TIMER_MASTER
9684 * @arg @ref LL_HRTIM_TIMER_A
9685 * @arg @ref LL_HRTIM_TIMER_B
9686 * @arg @ref LL_HRTIM_TIMER_C
9687 * @arg @ref LL_HRTIM_TIMER_D
9688 * @arg @ref LL_HRTIM_TIMER_E
9689 * @retval None
9690 */
LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9691 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9692 {
9693 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9694 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9695 REG_OFFSET_TAB_TIMER[iTimer]));
9696 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
9697 }
9698
9699 /**
9700 * @brief Disable the update DMA request for a given timer.
9701 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
9702 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
9703 * @param HRTIMx High Resolution Timer instance
9704 * @param Timer This parameter can be one of the following values:
9705 * @arg @ref LL_HRTIM_TIMER_MASTER
9706 * @arg @ref LL_HRTIM_TIMER_A
9707 * @arg @ref LL_HRTIM_TIMER_B
9708 * @arg @ref LL_HRTIM_TIMER_C
9709 * @arg @ref LL_HRTIM_TIMER_D
9710 * @arg @ref LL_HRTIM_TIMER_E
9711 * @retval None
9712 */
LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9713 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9714 {
9715 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9716 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9717 REG_OFFSET_TAB_TIMER[iTimer]));
9718 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
9719 }
9720
9721 /**
9722 * @brief Indicate whether the update DMA request is enabled for a given timer.
9723 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
9724 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
9725 * @param HRTIMx High Resolution Timer instance
9726 * @param Timer This parameter can be one of the following values:
9727 * @arg @ref LL_HRTIM_TIMER_MASTER
9728 * @arg @ref LL_HRTIM_TIMER_A
9729 * @arg @ref LL_HRTIM_TIMER_B
9730 * @arg @ref LL_HRTIM_TIMER_C
9731 * @arg @ref LL_HRTIM_TIMER_D
9732 * @arg @ref LL_HRTIM_TIMER_E
9733 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9734 */
LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9735 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9736 {
9737 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9738 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9739 REG_OFFSET_TAB_TIMER[iTimer]));
9740
9741 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
9742 }
9743
9744 /**
9745 * @brief Enable the repetition DMA request for a given timer.
9746 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
9747 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
9748 * @param HRTIMx High Resolution Timer instance
9749 * @param Timer This parameter can be one of the following values:
9750 * @arg @ref LL_HRTIM_TIMER_MASTER
9751 * @arg @ref LL_HRTIM_TIMER_A
9752 * @arg @ref LL_HRTIM_TIMER_B
9753 * @arg @ref LL_HRTIM_TIMER_C
9754 * @arg @ref LL_HRTIM_TIMER_D
9755 * @arg @ref LL_HRTIM_TIMER_E
9756 * @retval None
9757 */
LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9758 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9759 {
9760 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9761 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9762 REG_OFFSET_TAB_TIMER[iTimer]));
9763 SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
9764 }
9765
9766 /**
9767 * @brief Disable the repetition DMA request for a given timer.
9768 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
9769 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
9770 * @param HRTIMx High Resolution Timer instance
9771 * @param Timer This parameter can be one of the following values:
9772 * @arg @ref LL_HRTIM_TIMER_MASTER
9773 * @arg @ref LL_HRTIM_TIMER_A
9774 * @arg @ref LL_HRTIM_TIMER_B
9775 * @arg @ref LL_HRTIM_TIMER_C
9776 * @arg @ref LL_HRTIM_TIMER_D
9777 * @arg @ref LL_HRTIM_TIMER_E
9778 * @retval None
9779 */
LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9780 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9781 {
9782 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9783 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9784 REG_OFFSET_TAB_TIMER[iTimer]));
9785 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
9786 }
9787
9788 /**
9789 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
9790 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
9791 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
9792 * @param HRTIMx High Resolution Timer instance
9793 * @param Timer This parameter can be one of the following values:
9794 * @arg @ref LL_HRTIM_TIMER_MASTER
9795 * @arg @ref LL_HRTIM_TIMER_A
9796 * @arg @ref LL_HRTIM_TIMER_B
9797 * @arg @ref LL_HRTIM_TIMER_C
9798 * @arg @ref LL_HRTIM_TIMER_D
9799 * @arg @ref LL_HRTIM_TIMER_E
9800 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9801 */
LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9802 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9803 {
9804 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9805 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9806 REG_OFFSET_TAB_TIMER[iTimer]));
9807
9808 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
9809 }
9810
9811 /**
9812 * @brief Enable the compare 1 DMA request for a given timer.
9813 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
9814 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
9815 * @param HRTIMx High Resolution Timer instance
9816 * @param Timer This parameter can be one of the following values:
9817 * @arg @ref LL_HRTIM_TIMER_MASTER
9818 * @arg @ref LL_HRTIM_TIMER_A
9819 * @arg @ref LL_HRTIM_TIMER_B
9820 * @arg @ref LL_HRTIM_TIMER_C
9821 * @arg @ref LL_HRTIM_TIMER_D
9822 * @arg @ref LL_HRTIM_TIMER_E
9823 * @retval None
9824 */
LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9825 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9826 {
9827 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9828 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9829 REG_OFFSET_TAB_TIMER[iTimer]));
9830 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
9831 }
9832
9833 /**
9834 * @brief Disable the compare 1 DMA request for a given timer.
9835 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
9836 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
9837 * @param HRTIMx High Resolution Timer instance
9838 * @param Timer This parameter can be one of the following values:
9839 * @arg @ref LL_HRTIM_TIMER_MASTER
9840 * @arg @ref LL_HRTIM_TIMER_A
9841 * @arg @ref LL_HRTIM_TIMER_B
9842 * @arg @ref LL_HRTIM_TIMER_C
9843 * @arg @ref LL_HRTIM_TIMER_D
9844 * @arg @ref LL_HRTIM_TIMER_E
9845 * @retval None
9846 */
LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9847 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9848 {
9849 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9850 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9851 REG_OFFSET_TAB_TIMER[iTimer]));
9852 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
9853 }
9854
9855 /**
9856 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
9857 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
9858 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
9859 * @param HRTIMx High Resolution Timer instance
9860 * @param Timer This parameter can be one of the following values:
9861 * @arg @ref LL_HRTIM_TIMER_MASTER
9862 * @arg @ref LL_HRTIM_TIMER_A
9863 * @arg @ref LL_HRTIM_TIMER_B
9864 * @arg @ref LL_HRTIM_TIMER_C
9865 * @arg @ref LL_HRTIM_TIMER_D
9866 * @arg @ref LL_HRTIM_TIMER_E
9867 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9868 */
LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9869 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9870 {
9871 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9872 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9873 REG_OFFSET_TAB_TIMER[iTimer]));
9874
9875 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
9876 }
9877
9878 /**
9879 * @brief Enable the compare 2 DMA request for a given timer.
9880 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
9881 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
9882 * @param HRTIMx High Resolution Timer instance
9883 * @param Timer This parameter can be one of the following values:
9884 * @arg @ref LL_HRTIM_TIMER_MASTER
9885 * @arg @ref LL_HRTIM_TIMER_A
9886 * @arg @ref LL_HRTIM_TIMER_B
9887 * @arg @ref LL_HRTIM_TIMER_C
9888 * @arg @ref LL_HRTIM_TIMER_D
9889 * @arg @ref LL_HRTIM_TIMER_E
9890 * @retval None
9891 */
LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9892 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9893 {
9894 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9895 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9896 REG_OFFSET_TAB_TIMER[iTimer]));
9897 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
9898 }
9899
9900 /**
9901 * @brief Disable the compare 2 DMA request for a given timer.
9902 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
9903 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
9904 * @param HRTIMx High Resolution Timer instance
9905 * @param Timer This parameter can be one of the following values:
9906 * @arg @ref LL_HRTIM_TIMER_MASTER
9907 * @arg @ref LL_HRTIM_TIMER_A
9908 * @arg @ref LL_HRTIM_TIMER_B
9909 * @arg @ref LL_HRTIM_TIMER_C
9910 * @arg @ref LL_HRTIM_TIMER_D
9911 * @arg @ref LL_HRTIM_TIMER_E
9912 * @retval None
9913 */
LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9914 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9915 {
9916 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9917 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9918 REG_OFFSET_TAB_TIMER[iTimer]));
9919 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
9920 }
9921
9922 /**
9923 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
9924 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
9925 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
9926 * @param HRTIMx High Resolution Timer instance
9927 * @param Timer This parameter can be one of the following values:
9928 * @arg @ref LL_HRTIM_TIMER_MASTER
9929 * @arg @ref LL_HRTIM_TIMER_A
9930 * @arg @ref LL_HRTIM_TIMER_B
9931 * @arg @ref LL_HRTIM_TIMER_C
9932 * @arg @ref LL_HRTIM_TIMER_D
9933 * @arg @ref LL_HRTIM_TIMER_E
9934 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9935 */
LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9936 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9937 {
9938 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9939 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9940 REG_OFFSET_TAB_TIMER[iTimer]));
9941
9942 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
9943 }
9944
9945 /**
9946 * @brief Enable the compare 3 DMA request for a given timer.
9947 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
9948 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
9949 * @param HRTIMx High Resolution Timer instance
9950 * @param Timer This parameter can be one of the following values:
9951 * @arg @ref LL_HRTIM_TIMER_MASTER
9952 * @arg @ref LL_HRTIM_TIMER_A
9953 * @arg @ref LL_HRTIM_TIMER_B
9954 * @arg @ref LL_HRTIM_TIMER_C
9955 * @arg @ref LL_HRTIM_TIMER_D
9956 * @arg @ref LL_HRTIM_TIMER_E
9957 * @retval None
9958 */
LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9959 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9960 {
9961 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9962 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9963 REG_OFFSET_TAB_TIMER[iTimer]));
9964 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
9965 }
9966
9967 /**
9968 * @brief Disable the compare 3 DMA request for a given timer.
9969 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
9970 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
9971 * @param HRTIMx High Resolution Timer instance
9972 * @param Timer This parameter can be one of the following values:
9973 * @arg @ref LL_HRTIM_TIMER_MASTER
9974 * @arg @ref LL_HRTIM_TIMER_A
9975 * @arg @ref LL_HRTIM_TIMER_B
9976 * @arg @ref LL_HRTIM_TIMER_C
9977 * @arg @ref LL_HRTIM_TIMER_D
9978 * @arg @ref LL_HRTIM_TIMER_E
9979 * @retval None
9980 */
LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9981 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9982 {
9983 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9984 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9985 REG_OFFSET_TAB_TIMER[iTimer]));
9986 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
9987 }
9988
9989 /**
9990 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
9991 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
9992 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
9993 * @param HRTIMx High Resolution Timer instance
9994 * @param Timer This parameter can be one of the following values:
9995 * @arg @ref LL_HRTIM_TIMER_MASTER
9996 * @arg @ref LL_HRTIM_TIMER_A
9997 * @arg @ref LL_HRTIM_TIMER_B
9998 * @arg @ref LL_HRTIM_TIMER_C
9999 * @arg @ref LL_HRTIM_TIMER_D
10000 * @arg @ref LL_HRTIM_TIMER_E
10001 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
10002 */
LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10003 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10004 {
10005 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10006 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10007 REG_OFFSET_TAB_TIMER[iTimer]));
10008
10009 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
10010 }
10011
10012 /**
10013 * @brief Enable the compare 4 DMA request for a given timer.
10014 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
10015 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
10016 * @param HRTIMx High Resolution Timer instance
10017 * @param Timer This parameter can be one of the following values:
10018 * @arg @ref LL_HRTIM_TIMER_MASTER
10019 * @arg @ref LL_HRTIM_TIMER_A
10020 * @arg @ref LL_HRTIM_TIMER_B
10021 * @arg @ref LL_HRTIM_TIMER_C
10022 * @arg @ref LL_HRTIM_TIMER_D
10023 * @arg @ref LL_HRTIM_TIMER_E
10024 * @retval None
10025 */
LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10026 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10027 {
10028 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10029 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10030 REG_OFFSET_TAB_TIMER[iTimer]));
10031 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
10032 }
10033
10034 /**
10035 * @brief Disable the compare 4 DMA request for a given timer.
10036 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
10037 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
10038 * @param HRTIMx High Resolution Timer instance
10039 * @param Timer This parameter can be one of the following values:
10040 * @arg @ref LL_HRTIM_TIMER_MASTER
10041 * @arg @ref LL_HRTIM_TIMER_A
10042 * @arg @ref LL_HRTIM_TIMER_B
10043 * @arg @ref LL_HRTIM_TIMER_C
10044 * @arg @ref LL_HRTIM_TIMER_D
10045 * @arg @ref LL_HRTIM_TIMER_E
10046 * @retval None
10047 */
LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10048 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10049 {
10050 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10052 REG_OFFSET_TAB_TIMER[iTimer]));
10053 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
10054 }
10055
10056 /**
10057 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
10058 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
10059 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
10060 * @param HRTIMx High Resolution Timer instance
10061 * @param Timer This parameter can be one of the following values:
10062 * @arg @ref LL_HRTIM_TIMER_MASTER
10063 * @arg @ref LL_HRTIM_TIMER_A
10064 * @arg @ref LL_HRTIM_TIMER_B
10065 * @arg @ref LL_HRTIM_TIMER_C
10066 * @arg @ref LL_HRTIM_TIMER_D
10067 * @arg @ref LL_HRTIM_TIMER_E
10068 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
10069 */
LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10070 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10071 {
10072 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10073 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10074 REG_OFFSET_TAB_TIMER[iTimer]));
10075
10076 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
10077 }
10078
10079 /**
10080 * @brief Enable the capture 1 DMA request for a given timer.
10081 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
10082 * @param HRTIMx High Resolution Timer instance
10083 * @param Timer This parameter can be one of the following values:
10084 * @arg @ref LL_HRTIM_TIMER_A
10085 * @arg @ref LL_HRTIM_TIMER_B
10086 * @arg @ref LL_HRTIM_TIMER_C
10087 * @arg @ref LL_HRTIM_TIMER_D
10088 * @arg @ref LL_HRTIM_TIMER_E
10089 * @retval None
10090 */
LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10091 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10092 {
10093 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10094 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10095 REG_OFFSET_TAB_TIMER[iTimer]));
10096 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
10097 }
10098
10099 /**
10100 * @brief Disable the capture 1 DMA request for a given timer.
10101 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
10102 * @param HRTIMx High Resolution Timer instance
10103 * @param Timer This parameter can be one of the following values:
10104 * @arg @ref LL_HRTIM_TIMER_A
10105 * @arg @ref LL_HRTIM_TIMER_B
10106 * @arg @ref LL_HRTIM_TIMER_C
10107 * @arg @ref LL_HRTIM_TIMER_D
10108 * @arg @ref LL_HRTIM_TIMER_E
10109 * @retval None
10110 */
LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10111 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10112 {
10113 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10114 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10115 REG_OFFSET_TAB_TIMER[iTimer]));
10116 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
10117 }
10118
10119 /**
10120 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
10121 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
10122 * @param HRTIMx High Resolution Timer instance
10123 * @param Timer This parameter can be one of the following values:
10124 * @arg @ref LL_HRTIM_TIMER_A
10125 * @arg @ref LL_HRTIM_TIMER_B
10126 * @arg @ref LL_HRTIM_TIMER_C
10127 * @arg @ref LL_HRTIM_TIMER_D
10128 * @arg @ref LL_HRTIM_TIMER_E
10129 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
10130 */
LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10131 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10132 {
10133 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10134 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10135 REG_OFFSET_TAB_TIMER[iTimer]));
10136
10137 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
10138 }
10139
10140 /**
10141 * @brief Enable the capture 2 DMA request for a given timer.
10142 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
10143 * @param HRTIMx High Resolution Timer instance
10144 * @param Timer This parameter can be one of the following values:
10145 * @arg @ref LL_HRTIM_TIMER_A
10146 * @arg @ref LL_HRTIM_TIMER_B
10147 * @arg @ref LL_HRTIM_TIMER_C
10148 * @arg @ref LL_HRTIM_TIMER_D
10149 * @arg @ref LL_HRTIM_TIMER_E
10150 * @retval None
10151 */
LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10152 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10153 {
10154 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10155 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10156 REG_OFFSET_TAB_TIMER[iTimer]));
10157 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10158 }
10159
10160 /**
10161 * @brief Disable the capture 2 DMA request for a given timer.
10162 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
10163 * @param HRTIMx High Resolution Timer instance
10164 * @param Timer This parameter can be one of the following values:
10165 * @arg @ref LL_HRTIM_TIMER_A
10166 * @arg @ref LL_HRTIM_TIMER_B
10167 * @arg @ref LL_HRTIM_TIMER_C
10168 * @arg @ref LL_HRTIM_TIMER_D
10169 * @arg @ref LL_HRTIM_TIMER_E
10170 * @retval None
10171 */
LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10172 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10173 {
10174 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10175 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10176 REG_OFFSET_TAB_TIMER[iTimer]));
10177 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10178 }
10179
10180 /**
10181 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
10182 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
10183 * @param HRTIMx High Resolution Timer instance
10184 * @param Timer This parameter can be one of the following values:
10185 * @arg @ref LL_HRTIM_TIMER_A
10186 * @arg @ref LL_HRTIM_TIMER_B
10187 * @arg @ref LL_HRTIM_TIMER_C
10188 * @arg @ref LL_HRTIM_TIMER_D
10189 * @arg @ref LL_HRTIM_TIMER_E
10190 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
10191 */
LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10192 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10193 {
10194 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10195 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10196 REG_OFFSET_TAB_TIMER[iTimer]));
10197
10198 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
10199 }
10200
10201 /**
10202 * @brief Enable the output 1 set DMA request for a given timer.
10203 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
10204 * @param HRTIMx High Resolution Timer instance
10205 * @param Timer This parameter can be one of the following values:
10206 * @arg @ref LL_HRTIM_TIMER_A
10207 * @arg @ref LL_HRTIM_TIMER_B
10208 * @arg @ref LL_HRTIM_TIMER_C
10209 * @arg @ref LL_HRTIM_TIMER_D
10210 * @arg @ref LL_HRTIM_TIMER_E
10211 * @retval None
10212 */
LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10213 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10214 {
10215 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10216 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10217 REG_OFFSET_TAB_TIMER[iTimer]));
10218 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10219 }
10220
10221 /**
10222 * @brief Disable the output 1 set DMA request for a given timer.
10223 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
10224 * @param HRTIMx High Resolution Timer instance
10225 * @param Timer This parameter can be one of the following values:
10226 * @arg @ref LL_HRTIM_TIMER_A
10227 * @arg @ref LL_HRTIM_TIMER_B
10228 * @arg @ref LL_HRTIM_TIMER_C
10229 * @arg @ref LL_HRTIM_TIMER_D
10230 * @arg @ref LL_HRTIM_TIMER_E
10231 * @retval None
10232 */
LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10233 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10234 {
10235 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10236 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10237 REG_OFFSET_TAB_TIMER[iTimer]));
10238 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10239 }
10240
10241 /**
10242 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
10243 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
10244 * @param HRTIMx High Resolution Timer instance
10245 * @param Timer This parameter can be one of the following values:
10246 * @arg @ref LL_HRTIM_TIMER_A
10247 * @arg @ref LL_HRTIM_TIMER_B
10248 * @arg @ref LL_HRTIM_TIMER_C
10249 * @arg @ref LL_HRTIM_TIMER_D
10250 * @arg @ref LL_HRTIM_TIMER_E
10251 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10252 */
LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10253 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10254 {
10255 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10256 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10257 REG_OFFSET_TAB_TIMER[iTimer]));
10258
10259 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
10260 }
10261
10262 /**
10263 * @brief Enable the output 1 reset DMA request for a given timer.
10264 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
10265 * @param HRTIMx High Resolution Timer instance
10266 * @param Timer This parameter can be one of the following values:
10267 * @arg @ref LL_HRTIM_TIMER_A
10268 * @arg @ref LL_HRTIM_TIMER_B
10269 * @arg @ref LL_HRTIM_TIMER_C
10270 * @arg @ref LL_HRTIM_TIMER_D
10271 * @arg @ref LL_HRTIM_TIMER_E
10272 * @retval None
10273 */
LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10274 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10275 {
10276 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10277 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10278 REG_OFFSET_TAB_TIMER[iTimer]));
10279 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10280 }
10281
10282 /**
10283 * @brief Disable the output 1 reset DMA request for a given timer.
10284 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
10285 * @param HRTIMx High Resolution Timer instance
10286 * @param Timer This parameter can be one of the following values:
10287 * @arg @ref LL_HRTIM_TIMER_A
10288 * @arg @ref LL_HRTIM_TIMER_B
10289 * @arg @ref LL_HRTIM_TIMER_C
10290 * @arg @ref LL_HRTIM_TIMER_D
10291 * @arg @ref LL_HRTIM_TIMER_E
10292 * @retval None
10293 */
LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10294 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10295 {
10296 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10297 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10298 REG_OFFSET_TAB_TIMER[iTimer]));
10299 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10300 }
10301
10302 /**
10303 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
10304 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
10305 * @param HRTIMx High Resolution Timer instance
10306 * @param Timer This parameter can be one of the following values:
10307 * @arg @ref LL_HRTIM_TIMER_A
10308 * @arg @ref LL_HRTIM_TIMER_B
10309 * @arg @ref LL_HRTIM_TIMER_C
10310 * @arg @ref LL_HRTIM_TIMER_D
10311 * @arg @ref LL_HRTIM_TIMER_E
10312 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10313 */
LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10314 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10315 {
10316 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10317 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10318 REG_OFFSET_TAB_TIMER[iTimer]));
10319
10320 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
10321 }
10322
10323 /**
10324 * @brief Enable the output 2 set DMA request for a given timer.
10325 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
10326 * @param HRTIMx High Resolution Timer instance
10327 * @param Timer This parameter can be one of the following values:
10328 * @arg @ref LL_HRTIM_TIMER_A
10329 * @arg @ref LL_HRTIM_TIMER_B
10330 * @arg @ref LL_HRTIM_TIMER_C
10331 * @arg @ref LL_HRTIM_TIMER_D
10332 * @arg @ref LL_HRTIM_TIMER_E
10333 * @retval None
10334 */
LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10335 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10336 {
10337 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10338 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10339 REG_OFFSET_TAB_TIMER[iTimer]));
10340 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10341 }
10342
10343 /**
10344 * @brief Disable the output 2 set DMA request for a given timer.
10345 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
10346 * @param HRTIMx High Resolution Timer instance
10347 * @param Timer This parameter can be one of the following values:
10348 * @arg @ref LL_HRTIM_TIMER_A
10349 * @arg @ref LL_HRTIM_TIMER_B
10350 * @arg @ref LL_HRTIM_TIMER_C
10351 * @arg @ref LL_HRTIM_TIMER_D
10352 * @arg @ref LL_HRTIM_TIMER_E
10353 * @retval None
10354 */
LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10355 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10356 {
10357 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10358 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10359 REG_OFFSET_TAB_TIMER[iTimer]));
10360 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10361 }
10362
10363 /**
10364 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
10365 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
10366 * @param HRTIMx High Resolution Timer instance
10367 * @param Timer This parameter can be one of the following values:
10368 * @arg @ref LL_HRTIM_TIMER_A
10369 * @arg @ref LL_HRTIM_TIMER_B
10370 * @arg @ref LL_HRTIM_TIMER_C
10371 * @arg @ref LL_HRTIM_TIMER_D
10372 * @arg @ref LL_HRTIM_TIMER_E
10373 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10374 */
LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10375 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10376 {
10377 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10378 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10379 REG_OFFSET_TAB_TIMER[iTimer]));
10380
10381 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
10382 }
10383
10384 /**
10385 * @brief Enable the output 2 reset DMA request for a given timer.
10386 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
10387 * @param HRTIMx High Resolution Timer instance
10388 * @param Timer This parameter can be one of the following values:
10389 * @arg @ref LL_HRTIM_TIMER_A
10390 * @arg @ref LL_HRTIM_TIMER_B
10391 * @arg @ref LL_HRTIM_TIMER_C
10392 * @arg @ref LL_HRTIM_TIMER_D
10393 * @arg @ref LL_HRTIM_TIMER_E
10394 * @retval None
10395 */
LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10396 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10397 {
10398 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10399 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10400 REG_OFFSET_TAB_TIMER[iTimer]));
10401 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10402 }
10403
10404 /**
10405 * @brief Disable the output 2 reset DMA request for a given timer.
10406 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
10407 * @param HRTIMx High Resolution Timer instance
10408 * @param Timer This parameter can be one of the following values:
10409 * @arg @ref LL_HRTIM_TIMER_A
10410 * @arg @ref LL_HRTIM_TIMER_B
10411 * @arg @ref LL_HRTIM_TIMER_C
10412 * @arg @ref LL_HRTIM_TIMER_D
10413 * @arg @ref LL_HRTIM_TIMER_E
10414 * @retval None
10415 */
LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10416 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10417 {
10418 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10419 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10420 REG_OFFSET_TAB_TIMER[iTimer]));
10421 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10422 }
10423
10424 /**
10425 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
10426 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
10427 * @param HRTIMx High Resolution Timer instance
10428 * @param Timer This parameter can be one of the following values:
10429 * @arg @ref LL_HRTIM_TIMER_A
10430 * @arg @ref LL_HRTIM_TIMER_B
10431 * @arg @ref LL_HRTIM_TIMER_C
10432 * @arg @ref LL_HRTIM_TIMER_D
10433 * @arg @ref LL_HRTIM_TIMER_E
10434 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10435 */
LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10436 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10437 {
10438 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10439 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10440 REG_OFFSET_TAB_TIMER[iTimer]));
10441
10442 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
10443 }
10444
10445 /**
10446 * @brief Enable the reset/roll-over DMA request for a given timer.
10447 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
10448 * @param HRTIMx High Resolution Timer instance
10449 * @param Timer This parameter can be one of the following values:
10450 * @arg @ref LL_HRTIM_TIMER_A
10451 * @arg @ref LL_HRTIM_TIMER_B
10452 * @arg @ref LL_HRTIM_TIMER_C
10453 * @arg @ref LL_HRTIM_TIMER_D
10454 * @arg @ref LL_HRTIM_TIMER_E
10455 * @retval None
10456 */
LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10457 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10458 {
10459 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10460 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10461 REG_OFFSET_TAB_TIMER[iTimer]));
10462 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10463 }
10464
10465 /**
10466 * @brief Disable the reset/roll-over DMA request for a given timer.
10467 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
10468 * @param HRTIMx High Resolution Timer instance
10469 * @param Timer This parameter can be one of the following values:
10470 * @arg @ref LL_HRTIM_TIMER_A
10471 * @arg @ref LL_HRTIM_TIMER_B
10472 * @arg @ref LL_HRTIM_TIMER_C
10473 * @arg @ref LL_HRTIM_TIMER_D
10474 * @arg @ref LL_HRTIM_TIMER_E
10475 * @retval None
10476 */
LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10477 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10478 {
10479 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10480 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10481 REG_OFFSET_TAB_TIMER[iTimer]));
10482 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10483 }
10484
10485 /**
10486 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
10487 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
10488 * @param HRTIMx High Resolution Timer instance
10489 * @param Timer This parameter can be one of the following values:
10490 * @arg @ref LL_HRTIM_TIMER_A
10491 * @arg @ref LL_HRTIM_TIMER_B
10492 * @arg @ref LL_HRTIM_TIMER_C
10493 * @arg @ref LL_HRTIM_TIMER_D
10494 * @arg @ref LL_HRTIM_TIMER_E
10495 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
10496 */
LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10497 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10498 {
10499 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10500 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10501 REG_OFFSET_TAB_TIMER[iTimer]));
10502
10503 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
10504 }
10505
10506 /**
10507 * @brief Enable the delayed protection DMA request for a given timer.
10508 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
10509 * @param HRTIMx High Resolution Timer instance
10510 * @param Timer This parameter can be one of the following values:
10511 * @arg @ref LL_HRTIM_TIMER_A
10512 * @arg @ref LL_HRTIM_TIMER_B
10513 * @arg @ref LL_HRTIM_TIMER_C
10514 * @arg @ref LL_HRTIM_TIMER_D
10515 * @arg @ref LL_HRTIM_TIMER_E
10516 * @retval None
10517 */
LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10518 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10519 {
10520 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10521 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10522 REG_OFFSET_TAB_TIMER[iTimer]));
10523 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10524 }
10525
10526 /**
10527 * @brief Disable the delayed protection DMA request for a given timer.
10528 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
10529 * @param HRTIMx High Resolution Timer instance
10530 * @param Timer This parameter can be one of the following values:
10531 * @arg @ref LL_HRTIM_TIMER_A
10532 * @arg @ref LL_HRTIM_TIMER_B
10533 * @arg @ref LL_HRTIM_TIMER_C
10534 * @arg @ref LL_HRTIM_TIMER_D
10535 * @arg @ref LL_HRTIM_TIMER_E
10536 * @retval None
10537 */
LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10538 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10539 {
10540 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10541 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10542 REG_OFFSET_TAB_TIMER[iTimer]));
10543 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10544 }
10545
10546 /**
10547 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
10548 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
10549 * @param HRTIMx High Resolution Timer instance
10550 * @param Timer This parameter can be one of the following values:
10551 * @arg @ref LL_HRTIM_TIMER_A
10552 * @arg @ref LL_HRTIM_TIMER_B
10553 * @arg @ref LL_HRTIM_TIMER_C
10554 * @arg @ref LL_HRTIM_TIMER_D
10555 * @arg @ref LL_HRTIM_TIMER_E
10556 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
10557 */
LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10558 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10559 {
10560 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10561 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10562 REG_OFFSET_TAB_TIMER[iTimer]));
10563
10564 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
10565 }
10566
10567 /**
10568 * @}
10569 */
10570
10571 #if defined(USE_FULL_LL_DRIVER)
10572 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
10573 * @{
10574 */
10575 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
10576 /**
10577 * @}
10578 */
10579 #endif /* USE_FULL_LL_DRIVER */
10580
10581 /**
10582 * @}
10583 */
10584
10585 /**
10586 * @}
10587 */
10588
10589 #endif /* HRTIM1 */
10590
10591 /**
10592 * @}
10593 */
10594
10595 #ifdef __cplusplus
10596 }
10597 #endif
10598
10599 #endif /* STM32F3xx_LL_HRTIM_H */
10600
10601
