1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_DMA_H
21 #define __STM32F3xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
46 static const uint8_t CHANNEL_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
55 };
56 /**
57 * @}
58 */
59
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
64 * @{
65 */
66 /**
67 * @}
68 */
69 #endif /*USE_FULL_LL_DRIVER*/
70
71 /* Exported types ------------------------------------------------------------*/
72 #if defined(USE_FULL_LL_DRIVER)
73 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
74 * @{
75 */
76 typedef struct
77 {
78 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
79 or as Source base address in case of memory to memory transfer direction.
80
81 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
82
83 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
84 or as Destination base address in case of memory to memory transfer direction.
85
86 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
87
88 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
89 from memory to memory or from peripheral to memory.
90 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
91
92 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
93
94 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
95 This parameter can be a value of @ref DMA_LL_EC_MODE
96 @note: The circular buffer mode cannot be used if the memory to memory
97 data transfer direction is configured on the selected Channel
98
99 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
100
101 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
102 is incremented or not.
103 This parameter can be a value of @ref DMA_LL_EC_PERIPH
104
105 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
106
107 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
108 is incremented or not.
109 This parameter can be a value of @ref DMA_LL_EC_MEMORY
110
111 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
112
113 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
114 in case of memory to memory transfer direction.
115 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
118
119 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
120 in case of memory to memory transfer direction.
121 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
122
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
124
125 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
126 The data unit is equal to the source buffer configuration set in PeripheralSize
127 or MemorySize parameters depending in the transfer direction.
128 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
129
130 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
131
132 uint32_t Priority; /*!< Specifies the channel priority level.
133 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
136
137 } LL_DMA_InitTypeDef;
138 /**
139 * @}
140 */
141 #endif /*USE_FULL_LL_DRIVER*/
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
145 * @{
146 */
147 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
148 * @brief Flags defines which can be used with LL_DMA_WriteReg function
149 * @{
150 */
151 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
152 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
153 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
154 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
155 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
156 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
157 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
158 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
159 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
160 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
161 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
162 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
163 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
164 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
165 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
166 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
167 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
168 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
169 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
170 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
171 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
172 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
173 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
174 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
175 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
176 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
177 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
178 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
179 /**
180 * @}
181 */
182
183 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
184 * @brief Flags defines which can be used with LL_DMA_ReadReg function
185 * @{
186 */
187 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
188 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
189 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
190 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
191 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
192 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
193 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
194 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
195 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
196 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
197 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
198 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
199 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
200 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
201 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
202 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
203 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
204 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
205 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
206 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
207 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
208 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
209 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
210 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
211 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
212 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
213 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
214 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
215 /**
216 * @}
217 */
218
219 /** @defgroup DMA_LL_EC_IT IT Defines
220 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
221 * @{
222 */
223 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
224 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
225 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
226 /**
227 * @}
228 */
229
230 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
231 * @{
232 */
233 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
234 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
235 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
236 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
237 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
238 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
239 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
240 #if defined(USE_FULL_LL_DRIVER)
241 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
242 #endif /*USE_FULL_LL_DRIVER*/
243 /**
244 * @}
245 */
246
247 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
248 * @{
249 */
250 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
251 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
252 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
253 /**
254 * @}
255 */
256
257 /** @defgroup DMA_LL_EC_MODE Transfer mode
258 * @{
259 */
260 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
261 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
262 /**
263 * @}
264 */
265
266 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
267 * @{
268 */
269 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
270 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
271 /**
272 * @}
273 */
274
275 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
276 * @{
277 */
278 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
279 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
280 /**
281 * @}
282 */
283
284 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
285 * @{
286 */
287 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
288 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
289 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
290 /**
291 * @}
292 */
293
294 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
295 * @{
296 */
297 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
298 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
299 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
300 /**
301 * @}
302 */
303
304 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
305 * @{
306 */
307 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
308 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
309 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
310 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
311 /**
312 * @}
313 */
314
315
316 /**
317 * @}
318 */
319
320 /* Exported macro ------------------------------------------------------------*/
321 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
322 * @{
323 */
324
325 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
326 * @{
327 */
328 /**
329 * @brief Write a value in DMA register
330 * @param __INSTANCE__ DMA Instance
331 * @param __REG__ Register to be written
332 * @param __VALUE__ Value to be written in the register
333 * @retval None
334 */
335 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
336
337 /**
338 * @brief Read a value in DMA register
339 * @param __INSTANCE__ DMA Instance
340 * @param __REG__ Register to be read
341 * @retval Register value
342 */
343 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
344 /**
345 * @}
346 */
347
348 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
349 * @{
350 */
351 /**
352 * @brief Convert DMAx_Channely into DMAx
353 * @param __CHANNEL_INSTANCE__ DMAx_Channely
354 * @retval DMAx
355 */
356 #if defined(DMA2)
357 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
358 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
359 #else
360 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
361 #endif
362
363 /**
364 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
365 * @param __CHANNEL_INSTANCE__ DMAx_Channely
366 * @retval LL_DMA_CHANNEL_y
367 */
368 #if defined (DMA2)
369 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
370 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
371 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
383 LL_DMA_CHANNEL_7)
384 #else
385 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
386 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
397 LL_DMA_CHANNEL_7)
398 #endif
399 #else
400 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
401 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
407 LL_DMA_CHANNEL_7)
408 #endif
409
410 /**
411 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
412 * @param __DMA_INSTANCE__ DMAx
413 * @param __CHANNEL__ LL_DMA_CHANNEL_y
414 * @retval DMAx_Channely
415 */
416 #if defined (DMA2)
417 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
418 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
419 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
432 DMA2_Channel7)
433 #else
434 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
435 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
446 DMA1_Channel7)
447 #endif
448 #else
449 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
450 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
456 DMA1_Channel7)
457 #endif
458
459 /**
460 * @}
461 */
462
463 /**
464 * @}
465 */
466
467 /* Exported functions --------------------------------------------------------*/
468 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
469 * @{
470 */
471
472 /** @defgroup DMA_LL_EF_Configuration Configuration
473 * @{
474 */
475 /**
476 * @brief Enable DMA channel.
477 * @rmtoll CCR EN LL_DMA_EnableChannel
478 * @param DMAx DMAx Instance
479 * @param Channel This parameter can be one of the following values:
480 * @arg @ref LL_DMA_CHANNEL_1
481 * @arg @ref LL_DMA_CHANNEL_2
482 * @arg @ref LL_DMA_CHANNEL_3
483 * @arg @ref LL_DMA_CHANNEL_4
484 * @arg @ref LL_DMA_CHANNEL_5
485 * @arg @ref LL_DMA_CHANNEL_6
486 * @arg @ref LL_DMA_CHANNEL_7
487 * @retval None
488 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)489 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
490 {
491 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
492 }
493
494 /**
495 * @brief Disable DMA channel.
496 * @rmtoll CCR EN LL_DMA_DisableChannel
497 * @param DMAx DMAx Instance
498 * @param Channel This parameter can be one of the following values:
499 * @arg @ref LL_DMA_CHANNEL_1
500 * @arg @ref LL_DMA_CHANNEL_2
501 * @arg @ref LL_DMA_CHANNEL_3
502 * @arg @ref LL_DMA_CHANNEL_4
503 * @arg @ref LL_DMA_CHANNEL_5
504 * @arg @ref LL_DMA_CHANNEL_6
505 * @arg @ref LL_DMA_CHANNEL_7
506 * @retval None
507 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)508 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
509 {
510 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
511 }
512
513 /**
514 * @brief Check if DMA channel is enabled or disabled.
515 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
516 * @param DMAx DMAx Instance
517 * @param Channel This parameter can be one of the following values:
518 * @arg @ref LL_DMA_CHANNEL_1
519 * @arg @ref LL_DMA_CHANNEL_2
520 * @arg @ref LL_DMA_CHANNEL_3
521 * @arg @ref LL_DMA_CHANNEL_4
522 * @arg @ref LL_DMA_CHANNEL_5
523 * @arg @ref LL_DMA_CHANNEL_6
524 * @arg @ref LL_DMA_CHANNEL_7
525 * @retval State of bit (1 or 0).
526 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)527 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
528 {
529 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
530 DMA_CCR_EN) == (DMA_CCR_EN));
531 }
532
533 /**
534 * @brief Configure all parameters link to DMA transfer.
535 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
536 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
537 * CCR CIRC LL_DMA_ConfigTransfer\n
538 * CCR PINC LL_DMA_ConfigTransfer\n
539 * CCR MINC LL_DMA_ConfigTransfer\n
540 * CCR PSIZE LL_DMA_ConfigTransfer\n
541 * CCR MSIZE LL_DMA_ConfigTransfer\n
542 * CCR PL LL_DMA_ConfigTransfer
543 * @param DMAx DMAx Instance
544 * @param Channel This parameter can be one of the following values:
545 * @arg @ref LL_DMA_CHANNEL_1
546 * @arg @ref LL_DMA_CHANNEL_2
547 * @arg @ref LL_DMA_CHANNEL_3
548 * @arg @ref LL_DMA_CHANNEL_4
549 * @arg @ref LL_DMA_CHANNEL_5
550 * @arg @ref LL_DMA_CHANNEL_6
551 * @arg @ref LL_DMA_CHANNEL_7
552 * @param Configuration This parameter must be a combination of all the following values:
553 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
554 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
555 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
556 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
557 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
558 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
559 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
560 * @retval None
561 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)562 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
563 {
564 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
565 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
566 Configuration);
567 }
568
569 /**
570 * @brief Set Data transfer direction (read from peripheral or from memory).
571 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
572 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
573 * @param DMAx DMAx Instance
574 * @param Channel This parameter can be one of the following values:
575 * @arg @ref LL_DMA_CHANNEL_1
576 * @arg @ref LL_DMA_CHANNEL_2
577 * @arg @ref LL_DMA_CHANNEL_3
578 * @arg @ref LL_DMA_CHANNEL_4
579 * @arg @ref LL_DMA_CHANNEL_5
580 * @arg @ref LL_DMA_CHANNEL_6
581 * @arg @ref LL_DMA_CHANNEL_7
582 * @param Direction This parameter can be one of the following values:
583 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
584 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
585 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
586 * @retval None
587 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)588 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
589 {
590 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
591 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
592 }
593
594 /**
595 * @brief Get Data transfer direction (read from peripheral or from memory).
596 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
597 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
598 * @param DMAx DMAx Instance
599 * @param Channel This parameter can be one of the following values:
600 * @arg @ref LL_DMA_CHANNEL_1
601 * @arg @ref LL_DMA_CHANNEL_2
602 * @arg @ref LL_DMA_CHANNEL_3
603 * @arg @ref LL_DMA_CHANNEL_4
604 * @arg @ref LL_DMA_CHANNEL_5
605 * @arg @ref LL_DMA_CHANNEL_6
606 * @arg @ref LL_DMA_CHANNEL_7
607 * @retval Returned value can be one of the following values:
608 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
609 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
610 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
611 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)612 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
613 {
614 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
615 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
616 }
617
618 /**
619 * @brief Set DMA mode circular or normal.
620 * @note The circular buffer mode cannot be used if the memory-to-memory
621 * data transfer is configured on the selected Channel.
622 * @rmtoll CCR CIRC LL_DMA_SetMode
623 * @param DMAx DMAx Instance
624 * @param Channel This parameter can be one of the following values:
625 * @arg @ref LL_DMA_CHANNEL_1
626 * @arg @ref LL_DMA_CHANNEL_2
627 * @arg @ref LL_DMA_CHANNEL_3
628 * @arg @ref LL_DMA_CHANNEL_4
629 * @arg @ref LL_DMA_CHANNEL_5
630 * @arg @ref LL_DMA_CHANNEL_6
631 * @arg @ref LL_DMA_CHANNEL_7
632 * @param Mode This parameter can be one of the following values:
633 * @arg @ref LL_DMA_MODE_NORMAL
634 * @arg @ref LL_DMA_MODE_CIRCULAR
635 * @retval None
636 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)637 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
638 {
639 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
640 Mode);
641 }
642
643 /**
644 * @brief Get DMA mode circular or normal.
645 * @rmtoll CCR CIRC LL_DMA_GetMode
646 * @param DMAx DMAx Instance
647 * @param Channel This parameter can be one of the following values:
648 * @arg @ref LL_DMA_CHANNEL_1
649 * @arg @ref LL_DMA_CHANNEL_2
650 * @arg @ref LL_DMA_CHANNEL_3
651 * @arg @ref LL_DMA_CHANNEL_4
652 * @arg @ref LL_DMA_CHANNEL_5
653 * @arg @ref LL_DMA_CHANNEL_6
654 * @arg @ref LL_DMA_CHANNEL_7
655 * @retval Returned value can be one of the following values:
656 * @arg @ref LL_DMA_MODE_NORMAL
657 * @arg @ref LL_DMA_MODE_CIRCULAR
658 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)659 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
660 {
661 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
662 DMA_CCR_CIRC));
663 }
664
665 /**
666 * @brief Set Peripheral increment mode.
667 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
668 * @param DMAx DMAx Instance
669 * @param Channel This parameter can be one of the following values:
670 * @arg @ref LL_DMA_CHANNEL_1
671 * @arg @ref LL_DMA_CHANNEL_2
672 * @arg @ref LL_DMA_CHANNEL_3
673 * @arg @ref LL_DMA_CHANNEL_4
674 * @arg @ref LL_DMA_CHANNEL_5
675 * @arg @ref LL_DMA_CHANNEL_6
676 * @arg @ref LL_DMA_CHANNEL_7
677 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
678 * @arg @ref LL_DMA_PERIPH_INCREMENT
679 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
680 * @retval None
681 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)682 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
683 {
684 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
685 PeriphOrM2MSrcIncMode);
686 }
687
688 /**
689 * @brief Get Peripheral increment mode.
690 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
691 * @param DMAx DMAx Instance
692 * @param Channel This parameter can be one of the following values:
693 * @arg @ref LL_DMA_CHANNEL_1
694 * @arg @ref LL_DMA_CHANNEL_2
695 * @arg @ref LL_DMA_CHANNEL_3
696 * @arg @ref LL_DMA_CHANNEL_4
697 * @arg @ref LL_DMA_CHANNEL_5
698 * @arg @ref LL_DMA_CHANNEL_6
699 * @arg @ref LL_DMA_CHANNEL_7
700 * @retval Returned value can be one of the following values:
701 * @arg @ref LL_DMA_PERIPH_INCREMENT
702 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
703 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)704 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
705 {
706 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
707 DMA_CCR_PINC));
708 }
709
710 /**
711 * @brief Set Memory increment mode.
712 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
713 * @param DMAx DMAx Instance
714 * @param Channel This parameter can be one of the following values:
715 * @arg @ref LL_DMA_CHANNEL_1
716 * @arg @ref LL_DMA_CHANNEL_2
717 * @arg @ref LL_DMA_CHANNEL_3
718 * @arg @ref LL_DMA_CHANNEL_4
719 * @arg @ref LL_DMA_CHANNEL_5
720 * @arg @ref LL_DMA_CHANNEL_6
721 * @arg @ref LL_DMA_CHANNEL_7
722 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
723 * @arg @ref LL_DMA_MEMORY_INCREMENT
724 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
725 * @retval None
726 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)727 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
728 {
729 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
730 MemoryOrM2MDstIncMode);
731 }
732
733 /**
734 * @brief Get Memory increment mode.
735 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
736 * @param DMAx DMAx Instance
737 * @param Channel This parameter can be one of the following values:
738 * @arg @ref LL_DMA_CHANNEL_1
739 * @arg @ref LL_DMA_CHANNEL_2
740 * @arg @ref LL_DMA_CHANNEL_3
741 * @arg @ref LL_DMA_CHANNEL_4
742 * @arg @ref LL_DMA_CHANNEL_5
743 * @arg @ref LL_DMA_CHANNEL_6
744 * @arg @ref LL_DMA_CHANNEL_7
745 * @retval Returned value can be one of the following values:
746 * @arg @ref LL_DMA_MEMORY_INCREMENT
747 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
748 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)749 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
750 {
751 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
752 DMA_CCR_MINC));
753 }
754
755 /**
756 * @brief Set Peripheral size.
757 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
758 * @param DMAx DMAx Instance
759 * @param Channel This parameter can be one of the following values:
760 * @arg @ref LL_DMA_CHANNEL_1
761 * @arg @ref LL_DMA_CHANNEL_2
762 * @arg @ref LL_DMA_CHANNEL_3
763 * @arg @ref LL_DMA_CHANNEL_4
764 * @arg @ref LL_DMA_CHANNEL_5
765 * @arg @ref LL_DMA_CHANNEL_6
766 * @arg @ref LL_DMA_CHANNEL_7
767 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
768 * @arg @ref LL_DMA_PDATAALIGN_BYTE
769 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
770 * @arg @ref LL_DMA_PDATAALIGN_WORD
771 * @retval None
772 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)773 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
774 {
775 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
776 PeriphOrM2MSrcDataSize);
777 }
778
779 /**
780 * @brief Get Peripheral size.
781 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
782 * @param DMAx DMAx Instance
783 * @param Channel This parameter can be one of the following values:
784 * @arg @ref LL_DMA_CHANNEL_1
785 * @arg @ref LL_DMA_CHANNEL_2
786 * @arg @ref LL_DMA_CHANNEL_3
787 * @arg @ref LL_DMA_CHANNEL_4
788 * @arg @ref LL_DMA_CHANNEL_5
789 * @arg @ref LL_DMA_CHANNEL_6
790 * @arg @ref LL_DMA_CHANNEL_7
791 * @retval Returned value can be one of the following values:
792 * @arg @ref LL_DMA_PDATAALIGN_BYTE
793 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
794 * @arg @ref LL_DMA_PDATAALIGN_WORD
795 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)796 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
797 {
798 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
799 DMA_CCR_PSIZE));
800 }
801
802 /**
803 * @brief Set Memory size.
804 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
805 * @param DMAx DMAx Instance
806 * @param Channel This parameter can be one of the following values:
807 * @arg @ref LL_DMA_CHANNEL_1
808 * @arg @ref LL_DMA_CHANNEL_2
809 * @arg @ref LL_DMA_CHANNEL_3
810 * @arg @ref LL_DMA_CHANNEL_4
811 * @arg @ref LL_DMA_CHANNEL_5
812 * @arg @ref LL_DMA_CHANNEL_6
813 * @arg @ref LL_DMA_CHANNEL_7
814 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
815 * @arg @ref LL_DMA_MDATAALIGN_BYTE
816 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
817 * @arg @ref LL_DMA_MDATAALIGN_WORD
818 * @retval None
819 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)820 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
821 {
822 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
823 MemoryOrM2MDstDataSize);
824 }
825
826 /**
827 * @brief Get Memory size.
828 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
829 * @param DMAx DMAx Instance
830 * @param Channel This parameter can be one of the following values:
831 * @arg @ref LL_DMA_CHANNEL_1
832 * @arg @ref LL_DMA_CHANNEL_2
833 * @arg @ref LL_DMA_CHANNEL_3
834 * @arg @ref LL_DMA_CHANNEL_4
835 * @arg @ref LL_DMA_CHANNEL_5
836 * @arg @ref LL_DMA_CHANNEL_6
837 * @arg @ref LL_DMA_CHANNEL_7
838 * @retval Returned value can be one of the following values:
839 * @arg @ref LL_DMA_MDATAALIGN_BYTE
840 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
841 * @arg @ref LL_DMA_MDATAALIGN_WORD
842 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)843 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
844 {
845 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
846 DMA_CCR_MSIZE));
847 }
848
849 /**
850 * @brief Set Channel priority level.
851 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
852 * @param DMAx DMAx Instance
853 * @param Channel This parameter can be one of the following values:
854 * @arg @ref LL_DMA_CHANNEL_1
855 * @arg @ref LL_DMA_CHANNEL_2
856 * @arg @ref LL_DMA_CHANNEL_3
857 * @arg @ref LL_DMA_CHANNEL_4
858 * @arg @ref LL_DMA_CHANNEL_5
859 * @arg @ref LL_DMA_CHANNEL_6
860 * @arg @ref LL_DMA_CHANNEL_7
861 * @param Priority This parameter can be one of the following values:
862 * @arg @ref LL_DMA_PRIORITY_LOW
863 * @arg @ref LL_DMA_PRIORITY_MEDIUM
864 * @arg @ref LL_DMA_PRIORITY_HIGH
865 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
866 * @retval None
867 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)868 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
869 {
870 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
871 Priority);
872 }
873
874 /**
875 * @brief Get Channel priority level.
876 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
877 * @param DMAx DMAx Instance
878 * @param Channel This parameter can be one of the following values:
879 * @arg @ref LL_DMA_CHANNEL_1
880 * @arg @ref LL_DMA_CHANNEL_2
881 * @arg @ref LL_DMA_CHANNEL_3
882 * @arg @ref LL_DMA_CHANNEL_4
883 * @arg @ref LL_DMA_CHANNEL_5
884 * @arg @ref LL_DMA_CHANNEL_6
885 * @arg @ref LL_DMA_CHANNEL_7
886 * @retval Returned value can be one of the following values:
887 * @arg @ref LL_DMA_PRIORITY_LOW
888 * @arg @ref LL_DMA_PRIORITY_MEDIUM
889 * @arg @ref LL_DMA_PRIORITY_HIGH
890 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
891 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)892 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
893 {
894 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
895 DMA_CCR_PL));
896 }
897
898 /**
899 * @brief Set Number of data to transfer.
900 * @note This action has no effect if
901 * channel is enabled.
902 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
903 * @param DMAx DMAx Instance
904 * @param Channel This parameter can be one of the following values:
905 * @arg @ref LL_DMA_CHANNEL_1
906 * @arg @ref LL_DMA_CHANNEL_2
907 * @arg @ref LL_DMA_CHANNEL_3
908 * @arg @ref LL_DMA_CHANNEL_4
909 * @arg @ref LL_DMA_CHANNEL_5
910 * @arg @ref LL_DMA_CHANNEL_6
911 * @arg @ref LL_DMA_CHANNEL_7
912 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
913 * @retval None
914 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)915 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
916 {
917 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
918 DMA_CNDTR_NDT, NbData);
919 }
920
921 /**
922 * @brief Get Number of data to transfer.
923 * @note Once the channel is enabled, the return value indicate the
924 * remaining bytes to be transmitted.
925 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
926 * @param DMAx DMAx Instance
927 * @param Channel This parameter can be one of the following values:
928 * @arg @ref LL_DMA_CHANNEL_1
929 * @arg @ref LL_DMA_CHANNEL_2
930 * @arg @ref LL_DMA_CHANNEL_3
931 * @arg @ref LL_DMA_CHANNEL_4
932 * @arg @ref LL_DMA_CHANNEL_5
933 * @arg @ref LL_DMA_CHANNEL_6
934 * @arg @ref LL_DMA_CHANNEL_7
935 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
936 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)937 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
938 {
939 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
940 DMA_CNDTR_NDT));
941 }
942
943 /**
944 * @brief Configure the Source and Destination addresses.
945 * @note This API must not be called when the DMA channel is enabled.
946 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
947 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
948 * CMAR MA LL_DMA_ConfigAddresses
949 * @param DMAx DMAx Instance
950 * @param Channel This parameter can be one of the following values:
951 * @arg @ref LL_DMA_CHANNEL_1
952 * @arg @ref LL_DMA_CHANNEL_2
953 * @arg @ref LL_DMA_CHANNEL_3
954 * @arg @ref LL_DMA_CHANNEL_4
955 * @arg @ref LL_DMA_CHANNEL_5
956 * @arg @ref LL_DMA_CHANNEL_6
957 * @arg @ref LL_DMA_CHANNEL_7
958 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
959 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
960 * @param Direction This parameter can be one of the following values:
961 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
962 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
963 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
964 * @retval None
965 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)966 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
967 uint32_t DstAddress, uint32_t Direction)
968 {
969 /* Direction Memory to Periph */
970 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
971 {
972 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
973 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
974 }
975 /* Direction Periph to Memory and Memory to Memory */
976 else
977 {
978 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
979 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
980 }
981 }
982
983 /**
984 * @brief Set the Memory address.
985 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
986 * @note This API must not be called when the DMA channel is enabled.
987 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
988 * @param DMAx DMAx Instance
989 * @param Channel This parameter can be one of the following values:
990 * @arg @ref LL_DMA_CHANNEL_1
991 * @arg @ref LL_DMA_CHANNEL_2
992 * @arg @ref LL_DMA_CHANNEL_3
993 * @arg @ref LL_DMA_CHANNEL_4
994 * @arg @ref LL_DMA_CHANNEL_5
995 * @arg @ref LL_DMA_CHANNEL_6
996 * @arg @ref LL_DMA_CHANNEL_7
997 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
998 * @retval None
999 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1000 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1001 {
1002 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1003 }
1004
1005 /**
1006 * @brief Set the Peripheral address.
1007 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1008 * @note This API must not be called when the DMA channel is enabled.
1009 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1010 * @param DMAx DMAx Instance
1011 * @param Channel This parameter can be one of the following values:
1012 * @arg @ref LL_DMA_CHANNEL_1
1013 * @arg @ref LL_DMA_CHANNEL_2
1014 * @arg @ref LL_DMA_CHANNEL_3
1015 * @arg @ref LL_DMA_CHANNEL_4
1016 * @arg @ref LL_DMA_CHANNEL_5
1017 * @arg @ref LL_DMA_CHANNEL_6
1018 * @arg @ref LL_DMA_CHANNEL_7
1019 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1020 * @retval None
1021 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1022 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1023 {
1024 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1025 }
1026
1027 /**
1028 * @brief Get Memory address.
1029 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1030 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1031 * @param DMAx DMAx Instance
1032 * @param Channel This parameter can be one of the following values:
1033 * @arg @ref LL_DMA_CHANNEL_1
1034 * @arg @ref LL_DMA_CHANNEL_2
1035 * @arg @ref LL_DMA_CHANNEL_3
1036 * @arg @ref LL_DMA_CHANNEL_4
1037 * @arg @ref LL_DMA_CHANNEL_5
1038 * @arg @ref LL_DMA_CHANNEL_6
1039 * @arg @ref LL_DMA_CHANNEL_7
1040 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1041 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1042 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1043 {
1044 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1045 }
1046
1047 /**
1048 * @brief Get Peripheral address.
1049 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1050 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1051 * @param DMAx DMAx Instance
1052 * @param Channel This parameter can be one of the following values:
1053 * @arg @ref LL_DMA_CHANNEL_1
1054 * @arg @ref LL_DMA_CHANNEL_2
1055 * @arg @ref LL_DMA_CHANNEL_3
1056 * @arg @ref LL_DMA_CHANNEL_4
1057 * @arg @ref LL_DMA_CHANNEL_5
1058 * @arg @ref LL_DMA_CHANNEL_6
1059 * @arg @ref LL_DMA_CHANNEL_7
1060 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1061 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1062 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1063 {
1064 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1065 }
1066
1067 /**
1068 * @brief Set the Memory to Memory Source address.
1069 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1070 * @note This API must not be called when the DMA channel is enabled.
1071 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1072 * @param DMAx DMAx Instance
1073 * @param Channel This parameter can be one of the following values:
1074 * @arg @ref LL_DMA_CHANNEL_1
1075 * @arg @ref LL_DMA_CHANNEL_2
1076 * @arg @ref LL_DMA_CHANNEL_3
1077 * @arg @ref LL_DMA_CHANNEL_4
1078 * @arg @ref LL_DMA_CHANNEL_5
1079 * @arg @ref LL_DMA_CHANNEL_6
1080 * @arg @ref LL_DMA_CHANNEL_7
1081 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1082 * @retval None
1083 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1084 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1085 {
1086 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1087 }
1088
1089 /**
1090 * @brief Set the Memory to Memory Destination address.
1091 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1092 * @note This API must not be called when the DMA channel is enabled.
1093 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1094 * @param DMAx DMAx Instance
1095 * @param Channel This parameter can be one of the following values:
1096 * @arg @ref LL_DMA_CHANNEL_1
1097 * @arg @ref LL_DMA_CHANNEL_2
1098 * @arg @ref LL_DMA_CHANNEL_3
1099 * @arg @ref LL_DMA_CHANNEL_4
1100 * @arg @ref LL_DMA_CHANNEL_5
1101 * @arg @ref LL_DMA_CHANNEL_6
1102 * @arg @ref LL_DMA_CHANNEL_7
1103 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1104 * @retval None
1105 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1106 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1107 {
1108 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1109 }
1110
1111 /**
1112 * @brief Get the Memory to Memory Source address.
1113 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1114 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1115 * @param DMAx DMAx Instance
1116 * @param Channel This parameter can be one of the following values:
1117 * @arg @ref LL_DMA_CHANNEL_1
1118 * @arg @ref LL_DMA_CHANNEL_2
1119 * @arg @ref LL_DMA_CHANNEL_3
1120 * @arg @ref LL_DMA_CHANNEL_4
1121 * @arg @ref LL_DMA_CHANNEL_5
1122 * @arg @ref LL_DMA_CHANNEL_6
1123 * @arg @ref LL_DMA_CHANNEL_7
1124 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1125 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1126 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1127 {
1128 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1129 }
1130
1131 /**
1132 * @brief Get the Memory to Memory Destination address.
1133 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1134 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1135 * @param DMAx DMAx Instance
1136 * @param Channel This parameter can be one of the following values:
1137 * @arg @ref LL_DMA_CHANNEL_1
1138 * @arg @ref LL_DMA_CHANNEL_2
1139 * @arg @ref LL_DMA_CHANNEL_3
1140 * @arg @ref LL_DMA_CHANNEL_4
1141 * @arg @ref LL_DMA_CHANNEL_5
1142 * @arg @ref LL_DMA_CHANNEL_6
1143 * @arg @ref LL_DMA_CHANNEL_7
1144 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1145 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1146 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1147 {
1148 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1149 }
1150
1151
1152 /**
1153 * @}
1154 */
1155
1156 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1157 * @{
1158 */
1159
1160 /**
1161 * @brief Get Channel 1 global interrupt flag.
1162 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1163 * @param DMAx DMAx Instance
1164 * @retval State of bit (1 or 0).
1165 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1166 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1167 {
1168 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1169 }
1170
1171 /**
1172 * @brief Get Channel 2 global interrupt flag.
1173 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1174 * @param DMAx DMAx Instance
1175 * @retval State of bit (1 or 0).
1176 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1177 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1178 {
1179 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1180 }
1181
1182 /**
1183 * @brief Get Channel 3 global interrupt flag.
1184 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1185 * @param DMAx DMAx Instance
1186 * @retval State of bit (1 or 0).
1187 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1188 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1189 {
1190 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1191 }
1192
1193 /**
1194 * @brief Get Channel 4 global interrupt flag.
1195 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1196 * @param DMAx DMAx Instance
1197 * @retval State of bit (1 or 0).
1198 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1199 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1200 {
1201 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1202 }
1203
1204 /**
1205 * @brief Get Channel 5 global interrupt flag.
1206 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1207 * @param DMAx DMAx Instance
1208 * @retval State of bit (1 or 0).
1209 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1210 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1211 {
1212 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1213 }
1214
1215 /**
1216 * @brief Get Channel 6 global interrupt flag.
1217 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1218 * @param DMAx DMAx Instance
1219 * @retval State of bit (1 or 0).
1220 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1221 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1222 {
1223 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1224 }
1225
1226 /**
1227 * @brief Get Channel 7 global interrupt flag.
1228 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1229 * @param DMAx DMAx Instance
1230 * @retval State of bit (1 or 0).
1231 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1232 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1233 {
1234 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1235 }
1236
1237 /**
1238 * @brief Get Channel 1 transfer complete flag.
1239 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1240 * @param DMAx DMAx Instance
1241 * @retval State of bit (1 or 0).
1242 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1243 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1244 {
1245 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1246 }
1247
1248 /**
1249 * @brief Get Channel 2 transfer complete flag.
1250 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1251 * @param DMAx DMAx Instance
1252 * @retval State of bit (1 or 0).
1253 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1254 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1255 {
1256 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1257 }
1258
1259 /**
1260 * @brief Get Channel 3 transfer complete flag.
1261 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1262 * @param DMAx DMAx Instance
1263 * @retval State of bit (1 or 0).
1264 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1265 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1266 {
1267 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1268 }
1269
1270 /**
1271 * @brief Get Channel 4 transfer complete flag.
1272 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1273 * @param DMAx DMAx Instance
1274 * @retval State of bit (1 or 0).
1275 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1276 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1277 {
1278 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1279 }
1280
1281 /**
1282 * @brief Get Channel 5 transfer complete flag.
1283 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1284 * @param DMAx DMAx Instance
1285 * @retval State of bit (1 or 0).
1286 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1287 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1288 {
1289 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1290 }
1291
1292 /**
1293 * @brief Get Channel 6 transfer complete flag.
1294 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1295 * @param DMAx DMAx Instance
1296 * @retval State of bit (1 or 0).
1297 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1298 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1299 {
1300 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1301 }
1302
1303 /**
1304 * @brief Get Channel 7 transfer complete flag.
1305 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1306 * @param DMAx DMAx Instance
1307 * @retval State of bit (1 or 0).
1308 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1309 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1310 {
1311 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1312 }
1313
1314 /**
1315 * @brief Get Channel 1 half transfer flag.
1316 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1317 * @param DMAx DMAx Instance
1318 * @retval State of bit (1 or 0).
1319 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1320 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1321 {
1322 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1323 }
1324
1325 /**
1326 * @brief Get Channel 2 half transfer flag.
1327 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1328 * @param DMAx DMAx Instance
1329 * @retval State of bit (1 or 0).
1330 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1331 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1332 {
1333 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1334 }
1335
1336 /**
1337 * @brief Get Channel 3 half transfer flag.
1338 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1339 * @param DMAx DMAx Instance
1340 * @retval State of bit (1 or 0).
1341 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1342 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1343 {
1344 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1345 }
1346
1347 /**
1348 * @brief Get Channel 4 half transfer flag.
1349 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1350 * @param DMAx DMAx Instance
1351 * @retval State of bit (1 or 0).
1352 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1353 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1354 {
1355 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1356 }
1357
1358 /**
1359 * @brief Get Channel 5 half transfer flag.
1360 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1361 * @param DMAx DMAx Instance
1362 * @retval State of bit (1 or 0).
1363 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1364 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1365 {
1366 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1367 }
1368
1369 /**
1370 * @brief Get Channel 6 half transfer flag.
1371 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1372 * @param DMAx DMAx Instance
1373 * @retval State of bit (1 or 0).
1374 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1375 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1376 {
1377 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1378 }
1379
1380 /**
1381 * @brief Get Channel 7 half transfer flag.
1382 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1383 * @param DMAx DMAx Instance
1384 * @retval State of bit (1 or 0).
1385 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1386 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1387 {
1388 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1389 }
1390
1391 /**
1392 * @brief Get Channel 1 transfer error flag.
1393 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1394 * @param DMAx DMAx Instance
1395 * @retval State of bit (1 or 0).
1396 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1397 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1398 {
1399 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1400 }
1401
1402 /**
1403 * @brief Get Channel 2 transfer error flag.
1404 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1405 * @param DMAx DMAx Instance
1406 * @retval State of bit (1 or 0).
1407 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1408 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1409 {
1410 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1411 }
1412
1413 /**
1414 * @brief Get Channel 3 transfer error flag.
1415 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1416 * @param DMAx DMAx Instance
1417 * @retval State of bit (1 or 0).
1418 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1419 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1420 {
1421 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1422 }
1423
1424 /**
1425 * @brief Get Channel 4 transfer error flag.
1426 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1427 * @param DMAx DMAx Instance
1428 * @retval State of bit (1 or 0).
1429 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1430 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1431 {
1432 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1433 }
1434
1435 /**
1436 * @brief Get Channel 5 transfer error flag.
1437 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1438 * @param DMAx DMAx Instance
1439 * @retval State of bit (1 or 0).
1440 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1441 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1442 {
1443 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1444 }
1445
1446 /**
1447 * @brief Get Channel 6 transfer error flag.
1448 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1449 * @param DMAx DMAx Instance
1450 * @retval State of bit (1 or 0).
1451 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1452 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1453 {
1454 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1455 }
1456
1457 /**
1458 * @brief Get Channel 7 transfer error flag.
1459 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1460 * @param DMAx DMAx Instance
1461 * @retval State of bit (1 or 0).
1462 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1463 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1464 {
1465 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1466 }
1467
1468 /**
1469 * @brief Clear Channel 1 global interrupt flag.
1470 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1471 * @param DMAx DMAx Instance
1472 * @retval None
1473 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1474 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1475 {
1476 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1477 }
1478
1479 /**
1480 * @brief Clear Channel 2 global interrupt flag.
1481 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1482 * @param DMAx DMAx Instance
1483 * @retval None
1484 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1485 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1486 {
1487 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1488 }
1489
1490 /**
1491 * @brief Clear Channel 3 global interrupt flag.
1492 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1493 * @param DMAx DMAx Instance
1494 * @retval None
1495 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1496 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1497 {
1498 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1499 }
1500
1501 /**
1502 * @brief Clear Channel 4 global interrupt flag.
1503 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1504 * @param DMAx DMAx Instance
1505 * @retval None
1506 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1507 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1508 {
1509 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1510 }
1511
1512 /**
1513 * @brief Clear Channel 5 global interrupt flag.
1514 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1515 * @param DMAx DMAx Instance
1516 * @retval None
1517 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1518 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1519 {
1520 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1521 }
1522
1523 /**
1524 * @brief Clear Channel 6 global interrupt flag.
1525 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1526 * @param DMAx DMAx Instance
1527 * @retval None
1528 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1529 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1530 {
1531 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1532 }
1533
1534 /**
1535 * @brief Clear Channel 7 global interrupt flag.
1536 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1537 * @param DMAx DMAx Instance
1538 * @retval None
1539 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1540 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1541 {
1542 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1543 }
1544
1545 /**
1546 * @brief Clear Channel 1 transfer complete flag.
1547 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1548 * @param DMAx DMAx Instance
1549 * @retval None
1550 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1551 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1552 {
1553 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1554 }
1555
1556 /**
1557 * @brief Clear Channel 2 transfer complete flag.
1558 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1559 * @param DMAx DMAx Instance
1560 * @retval None
1561 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1562 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1563 {
1564 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1565 }
1566
1567 /**
1568 * @brief Clear Channel 3 transfer complete flag.
1569 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1570 * @param DMAx DMAx Instance
1571 * @retval None
1572 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1573 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1574 {
1575 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1576 }
1577
1578 /**
1579 * @brief Clear Channel 4 transfer complete flag.
1580 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1581 * @param DMAx DMAx Instance
1582 * @retval None
1583 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1584 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1585 {
1586 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1587 }
1588
1589 /**
1590 * @brief Clear Channel 5 transfer complete flag.
1591 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1592 * @param DMAx DMAx Instance
1593 * @retval None
1594 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1595 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1596 {
1597 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1598 }
1599
1600 /**
1601 * @brief Clear Channel 6 transfer complete flag.
1602 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1603 * @param DMAx DMAx Instance
1604 * @retval None
1605 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1606 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1607 {
1608 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1609 }
1610
1611 /**
1612 * @brief Clear Channel 7 transfer complete flag.
1613 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1614 * @param DMAx DMAx Instance
1615 * @retval None
1616 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1617 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1618 {
1619 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1620 }
1621
1622 /**
1623 * @brief Clear Channel 1 half transfer flag.
1624 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1625 * @param DMAx DMAx Instance
1626 * @retval None
1627 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1628 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1629 {
1630 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1631 }
1632
1633 /**
1634 * @brief Clear Channel 2 half transfer flag.
1635 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1636 * @param DMAx DMAx Instance
1637 * @retval None
1638 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1639 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1640 {
1641 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1642 }
1643
1644 /**
1645 * @brief Clear Channel 3 half transfer flag.
1646 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1647 * @param DMAx DMAx Instance
1648 * @retval None
1649 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1650 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1651 {
1652 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1653 }
1654
1655 /**
1656 * @brief Clear Channel 4 half transfer flag.
1657 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1658 * @param DMAx DMAx Instance
1659 * @retval None
1660 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1661 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1662 {
1663 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1664 }
1665
1666 /**
1667 * @brief Clear Channel 5 half transfer flag.
1668 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1669 * @param DMAx DMAx Instance
1670 * @retval None
1671 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1672 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1673 {
1674 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1675 }
1676
1677 /**
1678 * @brief Clear Channel 6 half transfer flag.
1679 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1680 * @param DMAx DMAx Instance
1681 * @retval None
1682 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1683 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1684 {
1685 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1686 }
1687
1688 /**
1689 * @brief Clear Channel 7 half transfer flag.
1690 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1691 * @param DMAx DMAx Instance
1692 * @retval None
1693 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1694 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1695 {
1696 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1697 }
1698
1699 /**
1700 * @brief Clear Channel 1 transfer error flag.
1701 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1702 * @param DMAx DMAx Instance
1703 * @retval None
1704 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1705 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1706 {
1707 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1708 }
1709
1710 /**
1711 * @brief Clear Channel 2 transfer error flag.
1712 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1713 * @param DMAx DMAx Instance
1714 * @retval None
1715 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1716 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1717 {
1718 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1719 }
1720
1721 /**
1722 * @brief Clear Channel 3 transfer error flag.
1723 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1724 * @param DMAx DMAx Instance
1725 * @retval None
1726 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1727 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1728 {
1729 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1730 }
1731
1732 /**
1733 * @brief Clear Channel 4 transfer error flag.
1734 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1735 * @param DMAx DMAx Instance
1736 * @retval None
1737 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1738 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1739 {
1740 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1741 }
1742
1743 /**
1744 * @brief Clear Channel 5 transfer error flag.
1745 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1746 * @param DMAx DMAx Instance
1747 * @retval None
1748 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1749 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1750 {
1751 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1752 }
1753
1754 /**
1755 * @brief Clear Channel 6 transfer error flag.
1756 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1757 * @param DMAx DMAx Instance
1758 * @retval None
1759 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1760 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1761 {
1762 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1763 }
1764
1765 /**
1766 * @brief Clear Channel 7 transfer error flag.
1767 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1768 * @param DMAx DMAx Instance
1769 * @retval None
1770 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1771 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1772 {
1773 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1774 }
1775
1776 /**
1777 * @}
1778 */
1779
1780 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1781 * @{
1782 */
1783 /**
1784 * @brief Enable Transfer complete interrupt.
1785 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1786 * @param DMAx DMAx Instance
1787 * @param Channel This parameter can be one of the following values:
1788 * @arg @ref LL_DMA_CHANNEL_1
1789 * @arg @ref LL_DMA_CHANNEL_2
1790 * @arg @ref LL_DMA_CHANNEL_3
1791 * @arg @ref LL_DMA_CHANNEL_4
1792 * @arg @ref LL_DMA_CHANNEL_5
1793 * @arg @ref LL_DMA_CHANNEL_6
1794 * @arg @ref LL_DMA_CHANNEL_7
1795 * @retval None
1796 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1797 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1798 {
1799 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1800 }
1801
1802 /**
1803 * @brief Enable Half transfer interrupt.
1804 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1805 * @param DMAx DMAx Instance
1806 * @param Channel This parameter can be one of the following values:
1807 * @arg @ref LL_DMA_CHANNEL_1
1808 * @arg @ref LL_DMA_CHANNEL_2
1809 * @arg @ref LL_DMA_CHANNEL_3
1810 * @arg @ref LL_DMA_CHANNEL_4
1811 * @arg @ref LL_DMA_CHANNEL_5
1812 * @arg @ref LL_DMA_CHANNEL_6
1813 * @arg @ref LL_DMA_CHANNEL_7
1814 * @retval None
1815 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1816 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1817 {
1818 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1819 }
1820
1821 /**
1822 * @brief Enable Transfer error interrupt.
1823 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1824 * @param DMAx DMAx Instance
1825 * @param Channel This parameter can be one of the following values:
1826 * @arg @ref LL_DMA_CHANNEL_1
1827 * @arg @ref LL_DMA_CHANNEL_2
1828 * @arg @ref LL_DMA_CHANNEL_3
1829 * @arg @ref LL_DMA_CHANNEL_4
1830 * @arg @ref LL_DMA_CHANNEL_5
1831 * @arg @ref LL_DMA_CHANNEL_6
1832 * @arg @ref LL_DMA_CHANNEL_7
1833 * @retval None
1834 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1835 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1836 {
1837 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1838 }
1839
1840 /**
1841 * @brief Disable Transfer complete interrupt.
1842 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1843 * @param DMAx DMAx Instance
1844 * @param Channel This parameter can be one of the following values:
1845 * @arg @ref LL_DMA_CHANNEL_1
1846 * @arg @ref LL_DMA_CHANNEL_2
1847 * @arg @ref LL_DMA_CHANNEL_3
1848 * @arg @ref LL_DMA_CHANNEL_4
1849 * @arg @ref LL_DMA_CHANNEL_5
1850 * @arg @ref LL_DMA_CHANNEL_6
1851 * @arg @ref LL_DMA_CHANNEL_7
1852 * @retval None
1853 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1854 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1855 {
1856 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1857 }
1858
1859 /**
1860 * @brief Disable Half transfer interrupt.
1861 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1862 * @param DMAx DMAx Instance
1863 * @param Channel This parameter can be one of the following values:
1864 * @arg @ref LL_DMA_CHANNEL_1
1865 * @arg @ref LL_DMA_CHANNEL_2
1866 * @arg @ref LL_DMA_CHANNEL_3
1867 * @arg @ref LL_DMA_CHANNEL_4
1868 * @arg @ref LL_DMA_CHANNEL_5
1869 * @arg @ref LL_DMA_CHANNEL_6
1870 * @arg @ref LL_DMA_CHANNEL_7
1871 * @retval None
1872 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1873 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1874 {
1875 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1876 }
1877
1878 /**
1879 * @brief Disable Transfer error interrupt.
1880 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1881 * @param DMAx DMAx Instance
1882 * @param Channel This parameter can be one of the following values:
1883 * @arg @ref LL_DMA_CHANNEL_1
1884 * @arg @ref LL_DMA_CHANNEL_2
1885 * @arg @ref LL_DMA_CHANNEL_3
1886 * @arg @ref LL_DMA_CHANNEL_4
1887 * @arg @ref LL_DMA_CHANNEL_5
1888 * @arg @ref LL_DMA_CHANNEL_6
1889 * @arg @ref LL_DMA_CHANNEL_7
1890 * @retval None
1891 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1892 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1893 {
1894 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1895 }
1896
1897 /**
1898 * @brief Check if Transfer complete Interrupt is enabled.
1899 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1900 * @param DMAx DMAx Instance
1901 * @param Channel This parameter can be one of the following values:
1902 * @arg @ref LL_DMA_CHANNEL_1
1903 * @arg @ref LL_DMA_CHANNEL_2
1904 * @arg @ref LL_DMA_CHANNEL_3
1905 * @arg @ref LL_DMA_CHANNEL_4
1906 * @arg @ref LL_DMA_CHANNEL_5
1907 * @arg @ref LL_DMA_CHANNEL_6
1908 * @arg @ref LL_DMA_CHANNEL_7
1909 * @retval State of bit (1 or 0).
1910 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1911 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1912 {
1913 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1914 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1915 }
1916
1917 /**
1918 * @brief Check if Half transfer Interrupt is enabled.
1919 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1920 * @param DMAx DMAx Instance
1921 * @param Channel This parameter can be one of the following values:
1922 * @arg @ref LL_DMA_CHANNEL_1
1923 * @arg @ref LL_DMA_CHANNEL_2
1924 * @arg @ref LL_DMA_CHANNEL_3
1925 * @arg @ref LL_DMA_CHANNEL_4
1926 * @arg @ref LL_DMA_CHANNEL_5
1927 * @arg @ref LL_DMA_CHANNEL_6
1928 * @arg @ref LL_DMA_CHANNEL_7
1929 * @retval State of bit (1 or 0).
1930 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1931 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1932 {
1933 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1934 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1935 }
1936
1937 /**
1938 * @brief Check if Transfer error Interrupt is enabled.
1939 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1940 * @param DMAx DMAx Instance
1941 * @param Channel This parameter can be one of the following values:
1942 * @arg @ref LL_DMA_CHANNEL_1
1943 * @arg @ref LL_DMA_CHANNEL_2
1944 * @arg @ref LL_DMA_CHANNEL_3
1945 * @arg @ref LL_DMA_CHANNEL_4
1946 * @arg @ref LL_DMA_CHANNEL_5
1947 * @arg @ref LL_DMA_CHANNEL_6
1948 * @arg @ref LL_DMA_CHANNEL_7
1949 * @retval State of bit (1 or 0).
1950 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1951 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1952 {
1953 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1954 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1955 }
1956
1957 /**
1958 * @}
1959 */
1960
1961 #if defined(USE_FULL_LL_DRIVER)
1962 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1963 * @{
1964 */
1965
1966 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1967 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1968 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1969
1970 /**
1971 * @}
1972 */
1973 #endif /* USE_FULL_LL_DRIVER */
1974
1975 /**
1976 * @}
1977 */
1978
1979 /**
1980 * @}
1981 */
1982
1983 #endif /* DMA1 || DMA2 */
1984
1985 /**
1986 * @}
1987 */
1988
1989 #ifdef __cplusplus
1990 }
1991 #endif
1992
1993 #endif /* __STM32F3xx_LL_DMA_H */
1994
1995
