1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_ADC_H
21 #define __STM32F3xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 /* Note: Devices of STM32F3 series embed 1 out of 2 different ADC IP. */
35 /* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
36 /* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
37 /* features (refer to reference manual). */
38 /* - STM32F37x: */
39 /* ADC IP 1Msamples/sec, 1 ADC instance */
40 /* This file contains the drivers of these ADC IP, located in 2 area */
41 /* delimited by compilation switches. */
42
43 #if defined(ADC5_V1_1)
44
45 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
46
47 /** @defgroup ADC_LL ADC
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
56 * @{
57 */
58
59 /* Internal mask for ADC group regular sequencer: */
60 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
61 /* - sequencer register offset */
62 /* - sequencer rank bits position into the selected register */
63
64 /* Internal register offset for ADC group regular sequencer configuration */
65 /* (offset placed into a spare area of literal definition) */
66 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
67 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
68 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
69 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
70
71 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
72 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
73
74 /* Definition of ADC group regular sequencer bits information to be inserted */
75 /* into ADC group regular sequencer ranks literals definition. */
76 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
77 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
78 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
79 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
80 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
81 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
82 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
83 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
84 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
85 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
86 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
87 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
88 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
89 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
90 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
91 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
92
93
94
95 /* Internal mask for ADC group injected sequencer: */
96 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
97 /* - data register offset */
98 /* - sequencer rank bits position into the selected register */
99
100 /* Internal register offset for ADC group injected data register */
101 /* (offset placed into a spare area of literal definition) */
102 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
103 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
104 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
105 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
106
107 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
108 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
109
110 /* Definition of ADC group injected sequencer bits information to be inserted */
111 /* into ADC group injected sequencer ranks literals definition. */
112 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
113 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
114 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
115 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
116
117
118
119 /* Internal mask for ADC group regular trigger: */
120 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
121 /* - regular trigger source */
122 /* - regular trigger edge */
123 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
124
125 /* Mask containing trigger source masks for each of possible */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
128 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
129 ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \
130 ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \
131 ((ADC_CFGR_EXTSEL) << (4U * 3U)) )
132
133 /* Mask containing trigger edge masks for each of possible */
134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
136 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
137 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
138 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
139 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
140
141 /* Definition of ADC group regular trigger bits information. */
142 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
143 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
144
145
146
147 /* Internal definitions for ADC group regular trigger sources: */
148 /* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources */
149 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
150 /* available on the selected device). */
151
152 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
153 /* Internal mask offset for ADC group injected trigger sources */
154 /* available only on specific ADC instances. */
155 /* (offset placed into a spare area of literal definition) */
156 #define ADC_REG_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
157 #define ADC_REG_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
158 #endif
159
160 /* Internal mask for ADC group injected trigger: */
161 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
162 /* - injected trigger source */
163 /* - injected trigger edge */
164 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
165
166 /* Mask containing trigger source masks for each of possible */
167 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
168 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
169 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
170 ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \
171 ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \
172 ((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
173
174 /* Mask containing trigger edge masks for each of possible */
175 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
176 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
177 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
178 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
179 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
180 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
181
182 /* Definition of ADC group injected trigger bits information. */
183 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
184 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
185
186
187
188 /* Internal definitions for ADC group injected trigger sources: */
189 /* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources */
190 /* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
191 /* available on the selected device). */
192
193 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
194 /* Internal mask offset for ADC group injected trigger sources */
195 /* available only on specific ADC instances. */
196 /* (offset placed into a spare area of literal definition) */
197 #define ADC_INJ_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
198 #define ADC_INJ_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
199 #endif
200
201
202
203
204 /* Internal mask for ADC channel: */
205 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
206 /* - channel identifier defined by number */
207 /* - channel identifier defined by bitfield */
208 /* - channel differentiation between external channels (connected to */
209 /* GPIO pins) and internal channels (connected to internal paths) */
210 /* - channel sampling time defined by SMPRx register offset */
211 /* and SMPx bits positions into SMPRx register */
212 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
213 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
214 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
215 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
216 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
217 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
218
219 /* Channel differentiation between external and internal channels */
220 #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
221 #define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
222 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
223
224 /* Internal register offset for ADC channel sampling time configuration */
225 /* (offset placed into a spare area of literal definition) */
226 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
227 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
228 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
229
230 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
231 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
232
233 /* Definition of channels ID number information to be inserted into */
234 /* channels literals definition. */
235 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
236 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
237 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
238 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
239 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
240 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
241 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
242 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
243 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
244 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
245 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
246 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
247 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
248 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
249 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
250 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
251 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
252 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
253 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
254
255 /* Definition of channels ID bitfield information to be inserted into */
256 /* channels literals definition. */
257 #define ADC_CHANNEL_0_BITFIELD 0x00000001UL
258 #define ADC_CHANNEL_1_BITFIELD 0x00000002UL
259 #define ADC_CHANNEL_2_BITFIELD 0x00000004UL
260 #define ADC_CHANNEL_3_BITFIELD 0x00000008UL
261 #define ADC_CHANNEL_4_BITFIELD 0x00000010UL
262 #define ADC_CHANNEL_5_BITFIELD 0x00000020UL
263 #define ADC_CHANNEL_6_BITFIELD 0x00000040UL
264 #define ADC_CHANNEL_7_BITFIELD 0x00000080UL
265 #define ADC_CHANNEL_8_BITFIELD 0x00000100UL
266 #define ADC_CHANNEL_9_BITFIELD 0x00000200UL
267 #define ADC_CHANNEL_10_BITFIELD 0x00000400UL
268 #define ADC_CHANNEL_11_BITFIELD 0x00000800UL
269 #define ADC_CHANNEL_12_BITFIELD 0x00001000UL
270 #define ADC_CHANNEL_13_BITFIELD 0x00002000UL
271 #define ADC_CHANNEL_14_BITFIELD 0x00004000UL
272 #define ADC_CHANNEL_15_BITFIELD 0x00008000UL
273 #define ADC_CHANNEL_16_BITFIELD 0x00010000UL
274 #define ADC_CHANNEL_17_BITFIELD 0x00020000UL
275 #define ADC_CHANNEL_18_BITFIELD 0x00040000UL
276
277 /* Definition of channels sampling time information to be inserted into */
278 /* channels literals definition. */
279 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
280 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
281 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
282 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
283 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
284 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
285 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
286 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
287 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
288 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
289 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
290 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
291 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
292 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
293 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
294 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
295 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
296 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
297 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
298
299
300 /* Internal mask for ADC mode single or differential ended: */
301 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
302 /* the relevant bits for: */
303 /* (concatenation of multiple bits used in different registers) */
304 /* - ADC calibration: calibration start, calibration factor get or set */
305 /* - ADC channels: set each ADC channel ending mode */
306 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
307 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
308 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
309 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
310
311
312 /* Internal mask for ADC analog watchdog: */
313 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
314 /* (concatenation of multiple bits used in different analog watchdogs, */
315 /* (feature of several watchdogs not available on all STM32 families)). */
316 /* - analog watchdog 1: monitored channel defined by number, */
317 /* selection of ADC group (ADC groups regular and-or injected). */
318 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
319 /* selection on groups. */
320
321 /* Internal register offset for ADC analog watchdog channel configuration */
322 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
323 #define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
324 #define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
325
326 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
327 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
328 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
329 #define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
330
331 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
332
333 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
334 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
335 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
336
337 /* Internal register offset for ADC analog watchdog threshold configuration */
338 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
339 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
340 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
341 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
342
343
344 /* Internal mask for ADC offset: */
345 /* Internal register offset for ADC offset number configuration */
346 #define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
347 #define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
348 #define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
349 #define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
350 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
351
352
353 /* ADC registers bits positions */
354 #define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
355 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
356 #define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
357 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
358 #define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
359
360
361 /* ADC registers bits groups */
362 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
363
364
365 /* ADC internal channels related definitions */
366 /* Internal voltage reference VrefInt */
367 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
368 #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
369 /* Temperature sensor */
370 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
371 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
372 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
373 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
374 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
375
376
377 /**
378 * @}
379 */
380
381
382 /* Private macros ------------------------------------------------------------*/
383 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
384 * @{
385 */
386
387 /**
388 * @brief Driver macro reserved for internal use: isolate bits with the
389 * selected mask and shift them to the register LSB
390 * (shift mask on register position bit 0).
391 * @param __BITS__ Bits in register 32 bits
392 * @param __MASK__ Mask in register 32 bits
393 * @retval Bits in register 32 bits
394 */
395 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
396 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
397
398 /**
399 * @brief Driver macro reserved for internal use: set a pointer to
400 * a register from a register basis from which an offset
401 * is applied.
402 * @param __REG__ Register basis from which the offset is applied.
403 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
404 * @retval Pointer to register address
405 */
406 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
407 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
408
409 /**
410 * @}
411 */
412
413
414 /* Exported types ------------------------------------------------------------*/
415 #if defined(USE_FULL_LL_DRIVER)
416 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
417 * @{
418 */
419
420 /**
421 * @brief Structure definition of some features of ADC common parameters
422 * and multimode
423 * (all ADC instances belonging to the same ADC common instance).
424 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
425 * is conditioned to ADC instances state (all ADC instances
426 * sharing the same ADC common instance):
427 * All ADC instances sharing the same ADC common instance must be
428 * disabled.
429 */
430 typedef struct
431 {
432 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
433 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
434 @note On this STM32 series, if ADC group injected is used, some
435 clock ratio constraints between ADC clock and AHB clock
436 must be respected. Refer to reference manual.
437
438 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
439
440 #if defined(ADC_MULTIMODE_SUPPORT)
441 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
442 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
443
444 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
445
446 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
447 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
448
449 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
450
451 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
452 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
453
454 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
455 #endif /* ADC_MULTIMODE_SUPPORT */
456
457 } LL_ADC_CommonInitTypeDef;
458
459 /**
460 * @brief Structure definition of some features of ADC instance.
461 * @note These parameters have an impact on ADC scope: ADC instance.
462 * Affects both group regular and group injected (availability
463 * of ADC group injected depends on STM32 families).
464 * Refer to corresponding unitary functions into
465 * @ref ADC_LL_EF_Configuration_ADC_Instance .
466 * @note The setting of these parameters by function @ref LL_ADC_Init()
467 * is conditioned to ADC state:
468 * ADC instance must be disabled.
469 * This condition is applied to all ADC features, for efficiency
470 * and compatibility over all STM32 families. However, the different
471 * features can be set under different ADC state conditions
472 * (setting possible with ADC enabled without conversion on going,
473 * ADC enabled with conversion on going, ...)
474 * Each feature can be updated afterwards with a unitary function
475 * and potentially with ADC in a different state than disabled,
476 * refer to description of each function for setting
477 * conditioned to ADC state.
478 */
479 typedef struct
480 {
481 uint32_t Resolution; /*!< Set ADC resolution.
482 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
483
484 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
485
486 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
487 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
488
489 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
490
491 uint32_t LowPowerMode; /*!< Set ADC low power mode.
492 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
493
494 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
495
496 } LL_ADC_InitTypeDef;
497
498 /**
499 * @brief Structure definition of some features of ADC group regular.
500 * @note These parameters have an impact on ADC scope: ADC group regular.
501 * Refer to corresponding unitary functions into
502 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
503 * (functions with prefix "REG").
504 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
505 * is conditioned to ADC state:
506 * ADC instance must be disabled.
507 * This condition is applied to all ADC features, for efficiency
508 * and compatibility over all STM32 families. However, the different
509 * features can be set under different ADC state conditions
510 * (setting possible with ADC enabled without conversion on going,
511 * ADC enabled with conversion on going, ...)
512 * Each feature can be updated afterwards with a unitary function
513 * and potentially with ADC in a different state than disabled,
514 * refer to description of each function for setting
515 * conditioned to ADC state.
516 */
517 typedef struct
518 {
519 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
520 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
521 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
522 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
523 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
524
525 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
526
527 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
528 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
529
530 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
531
532 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
533 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
534 @note This parameter has an effect only if group regular sequencer is enabled
535 (scan length of 2 ranks or more).
536
537 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
538
539 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
540 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
541 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
542
543 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
544
545 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
546 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
547
548 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
549
550 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
551 data preserved or overwritten.
552 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
553
554 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
555
556 } LL_ADC_REG_InitTypeDef;
557
558 /**
559 * @brief Structure definition of some features of ADC group injected.
560 * @note These parameters have an impact on ADC scope: ADC group injected.
561 * Refer to corresponding unitary functions into
562 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
563 * (functions with prefix "INJ").
564 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
565 * is conditioned to ADC state:
566 * ADC instance must be disabled.
567 * This condition is applied to all ADC features, for efficiency
568 * and compatibility over all STM32 families. However, the different
569 * features can be set under different ADC state conditions
570 * (setting possible with ADC enabled without conversion on going,
571 * ADC enabled with conversion on going, ...)
572 * Each feature can be updated afterwards with a unitary function
573 * and potentially with ADC in a different state than disabled,
574 * refer to description of each function for setting
575 * conditioned to ADC state.
576 */
577 typedef struct
578 {
579 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
580 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
581 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
582 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
583 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
584
585 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
586
587 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
588 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
589
590 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
591
592 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
593 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
594 @note This parameter has an effect only if group injected sequencer is enabled
595 (scan length of 2 ranks or more).
596
597 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
598
599 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
600 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
601 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
602
603 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
604
605 } LL_ADC_INJ_InitTypeDef;
606
607 /**
608 * @}
609 */
610 #endif /* USE_FULL_LL_DRIVER */
611
612 /* Exported constants --------------------------------------------------------*/
613 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
614 * @{
615 */
616
617 /** @defgroup ADC_LL_EC_FLAG ADC flags
618 * @brief Flags defines which can be used with LL_ADC_ReadReg function
619 * @{
620 */
621 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
622 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
623 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
624 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
625 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
626 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
627 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
628 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
629 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
630 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
631 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
632 #if defined(ADC_MULTIMODE_SUPPORT)
633 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
634 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
635 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
636 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
637 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
638 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
639 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
640 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
641 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
642 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
643 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
644 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
645 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
646 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
647 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
648 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
649 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
650 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
651 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
652 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
653 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
654 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
655 #endif
656 /**
657 * @}
658 */
659
660 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
661 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
662 * @{
663 */
664 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
665 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
666 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
667 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
668 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
669 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
670 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
671 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
672 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
673 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
674 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
675 /**
676 * @}
677 */
678
679 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
680 * @{
681 */
682 /* List of ADC registers intended to be used (most commonly) with */
683 /* DMA transfer. */
684 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
685 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
686 #if defined(ADC_MULTIMODE_SUPPORT)
687 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
688 #endif
689 /**
690 * @}
691 */
692
693 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
694 * @{
695 */
696 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
697 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
698 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
699 #define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
700 /**
701 * @}
702 */
703
704 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
705 * @{
706 */
707 /* Note: Other measurement paths to internal channels may be available */
708 /* (connections to other peripherals). */
709 /* If they are not listed below, they do not require any specific */
710 /* path enable. In this case, Access to measurement path is done */
711 /* only by selecting the corresponding ADC internal channel. */
712 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement paths all disabled */
713 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
714 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
715 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
716 /**
717 * @}
718 */
719
720 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
721 * @{
722 */
723 #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
724 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
725 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
726 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
727 /**
728 * @}
729 */
730
731 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
732 * @{
733 */
734 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
735 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
736 /**
737 * @}
738 */
739
740 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
741 * @{
742 */
743 #define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */
744 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
745 /**
746 * @}
747 */
748
749 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
750 * @{
751 */
752 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
753 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
754 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
755 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
756 /**
757 * @}
758 */
759
760 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
761 * @{
762 */
763 #define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
764 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
765 /**
766 * @}
767 */
768
769 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
770 * @{
771 */
772 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
773 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
774 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
775 /**
776 * @}
777 */
778
779 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
780 * @{
781 */
782 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
783 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
784 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
785 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
786 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
787 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
788 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
789 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
790 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
791 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
792 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
793 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
794 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
795 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
796 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
797 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
798 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
799 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
800 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
801 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
802 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
803 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
804 #if defined(OPAMP1_CSR_OPAMP1EN)
805 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
806 #endif
807 #if defined(OPAMP2_CSR_OPAMP2EN)
808 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
809 #endif
810 #if defined(OPAMP3_CSR_OPAMP3EN)
811 #define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
812 #endif
813 #if defined(OPAMP4_CSR_OPAMP4EN)
814 #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
815 #endif
816 /**
817 * @}
818 */
819
820 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
821 * @{
822 */
823 #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
824 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
825 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for */
826 /* ADC instances ADCx available on the selected device) */
827 /* Note: Literal without suffix "ADCxy" means that external trigger */
828 /* is available on all ADC instances. */
829 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
830 /* register SYSCFG_CFGR4. Refer to reference manual. */
831 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
832 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
833 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
834 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
835 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
836 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
837 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
838 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
839 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
840 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
841 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
842 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
843 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
844 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
845 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
846 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
847 #if defined(STM32F303xE) || defined(STM32F398xx)
848 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
849 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
850 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
851 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
852 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
853 #endif /* STM32F303xE || STM32F398xx */
854
855 /* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for */
856 /* ADC instances ADCx available on the selected device) */
857 /* Note: Literal without suffix "ADCxy" means that external trigger */
858 /* is available on all ADC instances. */
859 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
860 /* register SYSCFG_CFGR4. Refer to reference manual. */
861 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
862 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
863 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
864 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
865 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
866 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
867 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
868 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
869 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
870 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
871 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
872 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
873 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
874 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
875 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
876 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
877 #if defined(STM32F303xE) || defined(STM32F398xx)
878 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
879 #define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
880 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
881 #endif /* STM32F303xE || STM32F398xx */
882
883 #elif defined(STM32F303x8) || defined(STM32F328xx)
884 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
885 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
886 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
887 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
888 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
889 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
890 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
891 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
892 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
893 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
894 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
895 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
896 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
897 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
898 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
899
900 #elif defined(STM32F334x8)
901 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
902 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
903 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
904 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
905 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
906 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
907 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
908 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
909 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
910 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
911 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
912 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
913 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
914 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
915
916 #elif defined(STM32F302xC) || defined(STM32F302xE)
917 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
918 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
919 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
920 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
921 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
922 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
923 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
924 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
925 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
926 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
927 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
928 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
929 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
930 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
931
932 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
933 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
934 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
935 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
936 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
937 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
938 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
939 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
940 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
941 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
942 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
943 #endif
944 /**
945 * @}
946 */
947
948 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
949 * @{
950 */
951 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
952 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
953 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
954 /**
955 * @}
956 */
957
958 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
959 * @{
960 */
961 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
962 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
963 /**
964 * @}
965 */
966
967 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
968 * @{
969 */
970 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
971 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
972 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
973 /**
974 * @}
975 */
976
977 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
978 * @{
979 */
980 #define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
981 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
982 /**
983 * @}
984 */
985
986 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
987 * @{
988 */
989 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
990 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
991 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
992 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
993 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
994 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
995 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
996 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
997 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
998 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
999 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1000 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1001 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1002 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1003 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1004 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1005 /**
1006 * @}
1007 */
1008
1009 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1010 * @{
1011 */
1012 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
1013 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1014 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1015 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1016 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1017 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1018 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1019 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1020 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1026 * @{
1027 */
1028 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1029 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1030 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1031 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1032 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1033 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1034 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1035 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1036 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1037 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1038 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1039 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1040 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1041 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1042 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1043 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1049 * @{
1050 */
1051 #define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
1052 #if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
1053 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for */
1054 /* ADC instances ADCx available on the selected device) */
1055 /* Note: Literal without suffix "ADCxy" means that external trigger */
1056 /* is available on all ADC instances. */
1057 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
1058 /* register SYSCFG_CFGR4. Refer to reference manual. */
1059 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1060 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1061 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1062 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1063 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1064 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1065 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1066 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1067 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1068 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1069 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1070 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1071 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1072 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1073 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1074 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1075 #if defined(STM32F303xE) || defined(STM32F398xx)
1076 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
1077 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
1078 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1079 #endif /* STM32F303xE || STM32F398xx */
1080
1081 /* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for */
1082 /* ADC instances ADCx available on the selected device) */
1083 /* Note: Literal without suffix "ADCxy" means that external trigger */
1084 /* is available on all ADC instances. */
1085 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event). */
1086 /* JEXT2 is the main trigger, JEXT5 is kept as spare trigger for */
1087 /* future devices. */
1088 /* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
1089 /* register SYSCFG_CFGR4. Refer to reference manual. */
1090 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1091 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1092 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1093 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1094 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1095 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1096 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1097 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1098 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1099 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1100 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1101 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1102 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1103 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
1104 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1105 #if defined(STM32F303xE) || defined(STM32F398xx)
1106 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
1107 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
1108 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1109 #endif /* STM32F303xE || STM32F398xx */
1110
1111 #elif defined(STM32F303x8) || defined(STM32F328xx)
1112 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1113 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1114 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1115 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1116 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1117 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1118 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1119 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1120 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1121 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
1122 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
1123 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1124 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1125 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1126 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1127 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1128
1129 #elif defined(STM32F334x8)
1130 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1131 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1132 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1133 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1134 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1135 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1136 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1137 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
1138 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
1139 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1140 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1141 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1142 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1143 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1144
1145 #elif defined(STM32F302xC) || defined(STM32F302xE)
1146 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1147 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1148 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
1149 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1150 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1151 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
1152 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1153 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1154 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1155 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
1156 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1157 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1158 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1159
1160 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1161 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
1162 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1163 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1164 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
1165 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
1166 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
1167 #endif
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1173 * @{
1174 */
1175 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1176 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1177 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1178 /**
1179 * @}
1180 */
1181
1182 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1183 * @{
1184 */
1185 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1186 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1187 /**
1188 * @}
1189 */
1190
1191 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1192 * @{
1193 */
1194 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1195 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1201 * @{
1202 */
1203 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1204 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1205 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1206 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1212 * @{
1213 */
1214 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
1215 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1216 /**
1217 * @}
1218 */
1219
1220 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1221 * @{
1222 */
1223 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1224 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1225 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1226 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1232 * @{
1233 */
1234 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
1235 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1236 #define LL_ADC_SAMPLINGTIME_4CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 4.5 ADC clock cycles */
1237 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
1238 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 19.5 ADC clock cycles */
1239 #define LL_ADC_SAMPLINGTIME_61CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
1240 #define LL_ADC_SAMPLINGTIME_181CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 181.5 ADC clock cycles */
1241 #define LL_ADC_SAMPLINGTIME_601CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1247 * @{
1248 */
1249 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1250 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1251 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1257 * @{
1258 */
1259 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1260 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1261 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1262 /**
1263 * @}
1264 */
1265
1266 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1267 * @{
1268 */
1269 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
1270 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1271 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1272 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1273 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1274 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1275 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1276 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1277 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1278 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1279 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1280 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1281 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1282 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1283 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1284 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1285 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1286 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1287 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1288 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1289 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1290 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1291 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1292 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1293 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1294 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1295 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1296 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1297 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1298 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1299 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1300 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1301 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1302 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1303 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1304 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1305 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1306 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1307 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1308 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1309 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1310 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1311 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1312 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1313 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1314 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1315 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1316 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1317 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1318 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1319 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1320 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1321 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1322 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1323 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1324 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1325 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1326 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1327 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1328 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1329 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1330 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1331 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1332 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1333 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1334 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1335 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1336 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1337 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1338 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1339 #if defined(OPAMP1_CSR_OPAMP1EN)
1340 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1341 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1342 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1343 #endif
1344 #if defined(OPAMP2_CSR_OPAMP2EN)
1345 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1346 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1347 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1348 #endif
1349 #if defined(OPAMP3_CSR_OPAMP3EN)
1350 #define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1351 #define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1352 #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1353 #endif
1354 #if defined(OPAMP4_CSR_OPAMP4EN)
1355 #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1356 #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1357 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1358 #endif
1359 /**
1360 * @}
1361 */
1362
1363 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1364 * @{
1365 */
1366 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1367 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1368 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1369 /**
1370 * @}
1371 */
1372
1373 #if defined(ADC_MULTIMODE_SUPPORT)
1374 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1375 * @{
1376 */
1377 #define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */
1378 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1379 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1380 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1381 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1382 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1383 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1384 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1390 * @{
1391 */
1392 #define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1393 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1394 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1395 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1396 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1402 * @{
1403 */
1404 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1405 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1406 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1407 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1408 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1409 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1410 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1411 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1412 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1413 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1414 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1415 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1416 /**
1417 * @}
1418 */
1419
1420 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1421 * @{
1422 */
1423 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1424 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1425 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1426 /**
1427 * @}
1428 */
1429
1430 #endif /* ADC_MULTIMODE_SUPPORT */
1431
1432
1433 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1434 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1435 * not timeout values.
1436 * For details on delays values, refer to descriptions in source code
1437 * above each literal definition.
1438 * @{
1439 */
1440
1441 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1442 /* not timeout values. */
1443 /* Timeout values for ADC operations are dependent to device clock */
1444 /* configuration (system clock versus ADC clock), */
1445 /* and therefore must be defined in user application. */
1446 /* Indications for estimation of ADC timeout delays, for this */
1447 /* STM32 series: */
1448 /* - ADC calibration time: maximum delay is 112/fADC. */
1449 /* (refer to device datasheet, parameter "tCAL") */
1450 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1451 /* (refer to device datasheet, parameter "tSTAB") */
1452 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1453 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1454 /* cycles */
1455 /* - ADC conversion time: duration depending on ADC clock and ADC */
1456 /* configuration. */
1457 /* (refer to device reference manual, section "Timing") */
1458
1459 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1460 /* Delay set to maximum value (refer to device datasheet, */
1461 /* parameter "tADCVREG_STUP"). */
1462 /* Unit: us */
1463 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1464
1465 /* Delay for internal voltage reference stabilization time. */
1466 /* Delay set to maximum value (refer to device datasheet, */
1467 /* parameter "tstart_vrefint"). */
1468 /* Unit: us */
1469 #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */
1470
1471 /* Delay for temperature sensor stabilization time. */
1472 /* Literal set to maximum value (refer to device datasheet, */
1473 /* parameter "tSTART"). */
1474 /* Unit: us */
1475 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
1476
1477 /* Delay required between ADC end of calibration and ADC enable. */
1478 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1479 /* are required between ADC end of calibration and ADC enable. */
1480 /* Wait time can be computed in user application by waiting for the */
1481 /* equivalent number of CPU cycles, by taking into account */
1482 /* ratio of CPU clock versus ADC clock prescalers. */
1483 /* Unit: ADC clock cycles. */
1484 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */
1485
1486 /**
1487 * @}
1488 */
1489
1490 /**
1491 * @}
1492 */
1493
1494
1495 /* Exported macro ------------------------------------------------------------*/
1496 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1497 * @{
1498 */
1499
1500 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1501 * @{
1502 */
1503
1504 /**
1505 * @brief Write a value in ADC register
1506 * @param __INSTANCE__ ADC Instance
1507 * @param __REG__ Register to be written
1508 * @param __VALUE__ Value to be written in the register
1509 * @retval None
1510 */
1511 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1512
1513 /**
1514 * @brief Read a value in ADC register
1515 * @param __INSTANCE__ ADC Instance
1516 * @param __REG__ Register to be read
1517 * @retval Register value
1518 */
1519 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1525 * @{
1526 */
1527
1528 /**
1529 * @brief Helper macro to get ADC channel number in decimal format
1530 * from literals LL_ADC_CHANNEL_x.
1531 * @note Example:
1532 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1533 * will return decimal number "4".
1534 * @note The input can be a value from functions where a channel
1535 * number is returned, either defined with number
1536 * or with bitfield (only one bit must be set).
1537 * @param __CHANNEL__ This parameter can be one of the following values:
1538 * @arg @ref LL_ADC_CHANNEL_0
1539 * @arg @ref LL_ADC_CHANNEL_1
1540 * @arg @ref LL_ADC_CHANNEL_2
1541 * @arg @ref LL_ADC_CHANNEL_3
1542 * @arg @ref LL_ADC_CHANNEL_4
1543 * @arg @ref LL_ADC_CHANNEL_5
1544 * @arg @ref LL_ADC_CHANNEL_6
1545 * @arg @ref LL_ADC_CHANNEL_7
1546 * @arg @ref LL_ADC_CHANNEL_8
1547 * @arg @ref LL_ADC_CHANNEL_9
1548 * @arg @ref LL_ADC_CHANNEL_10
1549 * @arg @ref LL_ADC_CHANNEL_11
1550 * @arg @ref LL_ADC_CHANNEL_12
1551 * @arg @ref LL_ADC_CHANNEL_13
1552 * @arg @ref LL_ADC_CHANNEL_14
1553 * @arg @ref LL_ADC_CHANNEL_15
1554 * @arg @ref LL_ADC_CHANNEL_16
1555 * @arg @ref LL_ADC_CHANNEL_17
1556 * @arg @ref LL_ADC_CHANNEL_18
1557 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1558 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1559 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1560 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1561 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1562 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1563 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1564 *
1565 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1566 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1567 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1568 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1569 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1570 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1571 * @retval Value between Min_Data=0 and Max_Data=18
1572 */
1573 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1574 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
1575 ? ( \
1576 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1577 ) \
1578 : \
1579 ( \
1580 POSITION_VAL((__CHANNEL__)) \
1581 ) \
1582 )
1583
1584 /**
1585 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1586 * from number in decimal format.
1587 * @note Example:
1588 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1589 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1590 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1591 * @retval Returned value can be one of the following values:
1592 * @arg @ref LL_ADC_CHANNEL_0
1593 * @arg @ref LL_ADC_CHANNEL_1
1594 * @arg @ref LL_ADC_CHANNEL_2
1595 * @arg @ref LL_ADC_CHANNEL_3
1596 * @arg @ref LL_ADC_CHANNEL_4
1597 * @arg @ref LL_ADC_CHANNEL_5
1598 * @arg @ref LL_ADC_CHANNEL_6
1599 * @arg @ref LL_ADC_CHANNEL_7
1600 * @arg @ref LL_ADC_CHANNEL_8
1601 * @arg @ref LL_ADC_CHANNEL_9
1602 * @arg @ref LL_ADC_CHANNEL_10
1603 * @arg @ref LL_ADC_CHANNEL_11
1604 * @arg @ref LL_ADC_CHANNEL_12
1605 * @arg @ref LL_ADC_CHANNEL_13
1606 * @arg @ref LL_ADC_CHANNEL_14
1607 * @arg @ref LL_ADC_CHANNEL_15
1608 * @arg @ref LL_ADC_CHANNEL_16
1609 * @arg @ref LL_ADC_CHANNEL_17
1610 * @arg @ref LL_ADC_CHANNEL_18
1611 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1612 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1613 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1614 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1615 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1616 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1617 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1618 *
1619 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1620 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1621 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1622 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1623 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1624 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
1625 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
1626 * comparison with internal channel parameter to be done
1627 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1628 */
1629 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1630 (((__DECIMAL_NB__) <= 9U) \
1631 ? ( \
1632 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1633 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1634 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1635 ) \
1636 : \
1637 ( \
1638 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1639 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1640 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1641 ) \
1642 )
1643
1644 /**
1645 * @brief Helper macro to determine whether the selected channel
1646 * corresponds to literal definitions of driver.
1647 * @note The different literal definitions of ADC channels are:
1648 * - ADC internal channel:
1649 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1650 * - ADC external channel (channel connected to a GPIO pin):
1651 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1652 * @note The channel parameter must be a value defined from literal
1653 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1654 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1655 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1656 * must not be a value from functions where a channel number is
1657 * returned from ADC registers,
1658 * because internal and external channels share the same channel
1659 * number in ADC registers. The differentiation is made only with
1660 * parameters definitions of driver.
1661 * @param __CHANNEL__ This parameter can be one of the following values:
1662 * @arg @ref LL_ADC_CHANNEL_0
1663 * @arg @ref LL_ADC_CHANNEL_1
1664 * @arg @ref LL_ADC_CHANNEL_2
1665 * @arg @ref LL_ADC_CHANNEL_3
1666 * @arg @ref LL_ADC_CHANNEL_4
1667 * @arg @ref LL_ADC_CHANNEL_5
1668 * @arg @ref LL_ADC_CHANNEL_6
1669 * @arg @ref LL_ADC_CHANNEL_7
1670 * @arg @ref LL_ADC_CHANNEL_8
1671 * @arg @ref LL_ADC_CHANNEL_9
1672 * @arg @ref LL_ADC_CHANNEL_10
1673 * @arg @ref LL_ADC_CHANNEL_11
1674 * @arg @ref LL_ADC_CHANNEL_12
1675 * @arg @ref LL_ADC_CHANNEL_13
1676 * @arg @ref LL_ADC_CHANNEL_14
1677 * @arg @ref LL_ADC_CHANNEL_15
1678 * @arg @ref LL_ADC_CHANNEL_16
1679 * @arg @ref LL_ADC_CHANNEL_17
1680 * @arg @ref LL_ADC_CHANNEL_18
1681 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1682 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1683 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1684 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1685 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1686 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1687 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1688 *
1689 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1690 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1691 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1692 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1693 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1694 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1695 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1696 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1697 */
1698 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1699 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1700
1701 /**
1702 * @brief Helper macro to convert a channel defined from parameter
1703 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1704 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1705 * to its equivalent parameter definition of a ADC external channel
1706 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1707 * @note The channel parameter can be, additionally to a value
1708 * defined from parameter definition of a ADC internal channel
1709 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1710 * a value defined from parameter definition of
1711 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1712 * or a value from functions where a channel number is returned
1713 * from ADC registers.
1714 * @param __CHANNEL__ This parameter can be one of the following values:
1715 * @arg @ref LL_ADC_CHANNEL_0
1716 * @arg @ref LL_ADC_CHANNEL_1
1717 * @arg @ref LL_ADC_CHANNEL_2
1718 * @arg @ref LL_ADC_CHANNEL_3
1719 * @arg @ref LL_ADC_CHANNEL_4
1720 * @arg @ref LL_ADC_CHANNEL_5
1721 * @arg @ref LL_ADC_CHANNEL_6
1722 * @arg @ref LL_ADC_CHANNEL_7
1723 * @arg @ref LL_ADC_CHANNEL_8
1724 * @arg @ref LL_ADC_CHANNEL_9
1725 * @arg @ref LL_ADC_CHANNEL_10
1726 * @arg @ref LL_ADC_CHANNEL_11
1727 * @arg @ref LL_ADC_CHANNEL_12
1728 * @arg @ref LL_ADC_CHANNEL_13
1729 * @arg @ref LL_ADC_CHANNEL_14
1730 * @arg @ref LL_ADC_CHANNEL_15
1731 * @arg @ref LL_ADC_CHANNEL_16
1732 * @arg @ref LL_ADC_CHANNEL_17
1733 * @arg @ref LL_ADC_CHANNEL_18
1734 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1735 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1736 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1737 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1738 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1739 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1740 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1741 *
1742 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1743 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1744 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1745 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1746 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1747 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1748 * @retval Returned value can be one of the following values:
1749 * @arg @ref LL_ADC_CHANNEL_0
1750 * @arg @ref LL_ADC_CHANNEL_1
1751 * @arg @ref LL_ADC_CHANNEL_2
1752 * @arg @ref LL_ADC_CHANNEL_3
1753 * @arg @ref LL_ADC_CHANNEL_4
1754 * @arg @ref LL_ADC_CHANNEL_5
1755 * @arg @ref LL_ADC_CHANNEL_6
1756 * @arg @ref LL_ADC_CHANNEL_7
1757 * @arg @ref LL_ADC_CHANNEL_8
1758 * @arg @ref LL_ADC_CHANNEL_9
1759 * @arg @ref LL_ADC_CHANNEL_10
1760 * @arg @ref LL_ADC_CHANNEL_11
1761 * @arg @ref LL_ADC_CHANNEL_12
1762 * @arg @ref LL_ADC_CHANNEL_13
1763 * @arg @ref LL_ADC_CHANNEL_14
1764 * @arg @ref LL_ADC_CHANNEL_15
1765 * @arg @ref LL_ADC_CHANNEL_16
1766 * @arg @ref LL_ADC_CHANNEL_17
1767 * @arg @ref LL_ADC_CHANNEL_18
1768 */
1769 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1770 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1771
1772 /**
1773 * @brief Helper macro to determine whether the internal channel
1774 * selected is available on the ADC instance selected.
1775 * @note The channel parameter must be a value defined from parameter
1776 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1777 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1778 * must not be a value defined from parameter definition of
1779 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1780 * or a value from functions where a channel number is
1781 * returned from ADC registers,
1782 * because internal and external channels share the same channel
1783 * number in ADC registers. The differentiation is made only with
1784 * parameters definitions of driver.
1785 * @param __ADC_INSTANCE__ ADC instance
1786 * @param __CHANNEL__ This parameter can be one of the following values:
1787 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1788 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1789 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1790 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1791 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1792 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1793 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1794 *
1795 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1796 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1797 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1798 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1799 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1800 * only one ADC instance is allowed to be connected to VrefInt at the same time.
1801 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1802 * Value "1" if the internal channel selected is available on the ADC instance selected.
1803 */
1804 #if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
1805 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1806 (((__ADC_INSTANCE__) == ADC1) \
1807 ? ( \
1808 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1809 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1810 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1811 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1812 ) \
1813 : \
1814 ((__ADC_INSTANCE__) == ADC2) \
1815 ? ( \
1816 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1817 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1818 ) \
1819 : \
1820 ((__ADC_INSTANCE__) == ADC3) \
1821 ? ( \
1822 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1823 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
1824 ) \
1825 : \
1826 ((__ADC_INSTANCE__) == ADC4) \
1827 ? ( \
1828 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1829 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) \
1830 ) \
1831 : \
1832 (0U) \
1833 )
1834 #elif defined (ADC1) && defined (ADC2)
1835 #if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
1836 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1837 (((__ADC_INSTANCE__) == ADC1) \
1838 ? ( \
1839 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1840 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1841 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1842 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1843 ) \
1844 : \
1845 ((__ADC_INSTANCE__) == ADC2) \
1846 ? ( \
1847 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1848 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1849 ) \
1850 : \
1851 (0U) \
1852 )
1853 #elif defined(OPAMP2_CSR_OPAMP2EN)
1854 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1855 (((__ADC_INSTANCE__) == ADC1) \
1856 ? ( \
1857 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1858 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1859 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1860 ) \
1861 : \
1862 ((__ADC_INSTANCE__) == ADC2) \
1863 ? ( \
1864 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1865 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1866 ) \
1867 : \
1868 (0U) \
1869 )
1870 #else
1871 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1872 (((__ADC_INSTANCE__) == ADC1) \
1873 ? ( \
1874 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1875 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1876 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1877 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1878 ) \
1879 : \
1880 ((__ADC_INSTANCE__) == ADC2) \
1881 ? ( \
1882 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1883 ) \
1884 : \
1885 (0U) \
1886 )
1887 #endif
1888 #elif defined (ADC1)
1889 #if defined(OPAMP1_CSR_OPAMP1EN)
1890 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1891 ( \
1892 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1893 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1894 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1895 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
1896 )
1897 #else
1898 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1899 ( \
1900 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1901 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1902 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1903 )
1904 #endif
1905 #endif
1906
1907 /**
1908 * @brief Helper macro to define ADC analog watchdog parameter:
1909 * define a single channel to monitor with analog watchdog
1910 * from sequencer channel and groups definition.
1911 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1912 * Example:
1913 * LL_ADC_SetAnalogWDMonitChannels(
1914 * ADC1, LL_ADC_AWD1,
1915 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1916 * @param __CHANNEL__ This parameter can be one of the following values:
1917 * @arg @ref LL_ADC_CHANNEL_0
1918 * @arg @ref LL_ADC_CHANNEL_1
1919 * @arg @ref LL_ADC_CHANNEL_2
1920 * @arg @ref LL_ADC_CHANNEL_3
1921 * @arg @ref LL_ADC_CHANNEL_4
1922 * @arg @ref LL_ADC_CHANNEL_5
1923 * @arg @ref LL_ADC_CHANNEL_6
1924 * @arg @ref LL_ADC_CHANNEL_7
1925 * @arg @ref LL_ADC_CHANNEL_8
1926 * @arg @ref LL_ADC_CHANNEL_9
1927 * @arg @ref LL_ADC_CHANNEL_10
1928 * @arg @ref LL_ADC_CHANNEL_11
1929 * @arg @ref LL_ADC_CHANNEL_12
1930 * @arg @ref LL_ADC_CHANNEL_13
1931 * @arg @ref LL_ADC_CHANNEL_14
1932 * @arg @ref LL_ADC_CHANNEL_15
1933 * @arg @ref LL_ADC_CHANNEL_16
1934 * @arg @ref LL_ADC_CHANNEL_17
1935 * @arg @ref LL_ADC_CHANNEL_18
1936 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
1937 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1938 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1939 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1940 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1941 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
1942 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
1943 *
1944 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
1945 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
1946 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
1947 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
1948 * (5) On STM32F3, ADC channel available only on all ADC instances, but
1949 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
1950 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
1951 * comparison with internal channel parameter to be done
1952 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1953 * @param __GROUP__ This parameter can be one of the following values:
1954 * @arg @ref LL_ADC_GROUP_REGULAR
1955 * @arg @ref LL_ADC_GROUP_INJECTED
1956 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1957 * @retval Returned value can be one of the following values:
1958 * @arg @ref LL_ADC_AWD_DISABLE
1959 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1960 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1961 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1962 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1963 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1964 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1965 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1966 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1967 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1968 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1969 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1970 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1971 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1972 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1973 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1974 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1975 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1976 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1977 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1978 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1979 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1980 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1981 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1982 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1983 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1984 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1985 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1986 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1987 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1988 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1989 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1990 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
1991 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1992 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1993 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
1994 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1995 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1996 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
1997 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1998 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1999 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2000 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2001 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2002 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2003 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2004 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2005 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2006 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2007 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2008 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2009 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2010 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2011 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2012 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2013 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2014 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2015 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2016 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2017 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2018 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2019 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
2020 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
2021 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
2022 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2023 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2024 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2025 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2026 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2027 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2028 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
2029 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
2030 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
2031 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
2032 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
2033 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
2034 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
2035 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
2036 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
2037 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
2038 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
2039 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
2040 *
2041 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
2042 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
2043 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
2044 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
2045 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
2046 * (5) On STM32F3, ADC channel available only on all ADC instances, but
2047 * only one ADC instance is allowed to be connected to VrefInt at the same time.
2048 */
2049 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2050 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2051 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2052 : \
2053 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2054 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2055 : \
2056 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2057 )
2058
2059 /**
2060 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2061 * or low in function of ADC resolution, when ADC resolution is
2062 * different of 12 bits.
2063 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2064 * or @ref LL_ADC_SetAnalogWDThresholds().
2065 * Example, with a ADC resolution of 8 bits, to set the value of
2066 * analog watchdog threshold high (on 8 bits):
2067 * LL_ADC_SetAnalogWDThresholds
2068 * (< ADCx param >,
2069 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2070 * );
2071 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2072 * @arg @ref LL_ADC_RESOLUTION_12B
2073 * @arg @ref LL_ADC_RESOLUTION_10B
2074 * @arg @ref LL_ADC_RESOLUTION_8B
2075 * @arg @ref LL_ADC_RESOLUTION_6B
2076 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2077 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2078 */
2079 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2080 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2081
2082 /**
2083 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2084 * or low in function of ADC resolution, when ADC resolution is
2085 * different of 12 bits.
2086 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2087 * Example, with a ADC resolution of 8 bits, to get the value of
2088 * analog watchdog threshold high (on 8 bits):
2089 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2090 * (LL_ADC_RESOLUTION_8B,
2091 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2092 * );
2093 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2094 * @arg @ref LL_ADC_RESOLUTION_12B
2095 * @arg @ref LL_ADC_RESOLUTION_10B
2096 * @arg @ref LL_ADC_RESOLUTION_8B
2097 * @arg @ref LL_ADC_RESOLUTION_6B
2098 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2099 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2100 */
2101 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2102 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2103
2104 /**
2105 * @brief Helper macro to get the ADC analog watchdog threshold high
2106 * or low from raw value containing both thresholds concatenated.
2107 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2108 * Example, to get analog watchdog threshold high from the register raw value:
2109 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2110 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2111 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2112 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2113 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2114 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2115 */
2116 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2117 (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
2118
2119 /**
2120 * @brief Helper macro to set the ADC calibration value with both single ended
2121 * and differential modes calibration factors concatenated.
2122 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2123 * Example, to set calibration factors single ended to 0x55
2124 * and differential ended to 0x2A:
2125 * LL_ADC_SetCalibrationFactor(
2126 * ADC1,
2127 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2128 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2129 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2130 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2131 */
2132 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2133 (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
2134
2135 #if defined(ADC_MULTIMODE_SUPPORT)
2136 /**
2137 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2138 * or ADC slave from raw value with both ADC conversion data concatenated.
2139 * @note This macro is intended to be used when multimode transfer by DMA
2140 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2141 * In this case the transferred data need to processed with this macro
2142 * to separate the conversion data of ADC master and ADC slave.
2143 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2144 * @arg @ref LL_ADC_MULTI_MASTER
2145 * @arg @ref LL_ADC_MULTI_SLAVE
2146 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2147 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2148 */
2149 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2150 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2151 #endif
2152
2153 /**
2154 * @brief Helper macro to select the ADC common instance
2155 * to which is belonging the selected ADC instance.
2156 * @note ADC common register instance can be used for:
2157 * - Set parameters common to several ADC instances
2158 * - Multimode (for devices with several ADC instances)
2159 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2160 * @param __ADCx__ ADC instance
2161 * @retval ADC common register instance
2162 */
2163 #if defined(ADC3) && defined(ADC4)
2164 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2165 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2166 ? ( \
2167 (ADC12_COMMON) \
2168 ) \
2169 : \
2170 ( \
2171 (ADC34_COMMON) \
2172 ) \
2173 )
2174 #elif defined(ADC1) && defined(ADC2)
2175 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2176 (ADC12_COMMON)
2177 #else
2178 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2179 (ADC1_COMMON)
2180 #endif
2181
2182 /**
2183 * @brief Helper macro to check if all ADC instances sharing the same
2184 * ADC common instance are disabled.
2185 * @note This check is required by functions with setting conditioned to
2186 * ADC state:
2187 * All ADC instances of the ADC common group must be disabled.
2188 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2189 * @note On devices with only 1 ADC common instance, parameter of this macro
2190 * is useless and can be ignored (parameter kept for compatibility
2191 * with devices featuring several ADC common instances).
2192 * @param __ADCXY_COMMON__ ADC common instance
2193 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2194 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2195 * are disabled.
2196 * Value "1" if at least one ADC instance sharing the same ADC common instance
2197 * is enabled.
2198 */
2199 #if defined(ADC3) && defined(ADC4)
2200 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2201 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2202 ? ( \
2203 (LL_ADC_IsEnabled(ADC1) | \
2204 LL_ADC_IsEnabled(ADC2) ) \
2205 ) \
2206 : \
2207 ( \
2208 (LL_ADC_IsEnabled(ADC3) | \
2209 LL_ADC_IsEnabled(ADC4) ) \
2210 ) \
2211 )
2212 #elif defined(ADC1) && defined(ADC2)
2213 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2214 (LL_ADC_IsEnabled(ADC1) | \
2215 LL_ADC_IsEnabled(ADC2) )
2216 #else
2217 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2218 LL_ADC_IsEnabled(ADC1)
2219 #endif
2220
2221 /**
2222 * @brief Helper macro to define the ADC conversion data full-scale digital
2223 * value corresponding to the selected ADC resolution.
2224 * @note ADC conversion data full-scale corresponds to voltage range
2225 * determined by analog voltage references Vref+ and Vref-
2226 * (refer to reference manual).
2227 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2228 * @arg @ref LL_ADC_RESOLUTION_12B
2229 * @arg @ref LL_ADC_RESOLUTION_10B
2230 * @arg @ref LL_ADC_RESOLUTION_8B
2231 * @arg @ref LL_ADC_RESOLUTION_6B
2232 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2233 */
2234 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2235 (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
2236
2237 /**
2238 * @brief Helper macro to convert the ADC conversion data from
2239 * a resolution to another resolution.
2240 * @param __DATA__ ADC conversion data to be converted
2241 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
2242 * This parameter can be one of the following values:
2243 * @arg @ref LL_ADC_RESOLUTION_12B
2244 * @arg @ref LL_ADC_RESOLUTION_10B
2245 * @arg @ref LL_ADC_RESOLUTION_8B
2246 * @arg @ref LL_ADC_RESOLUTION_6B
2247 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2248 * This parameter can be one of the following values:
2249 * @arg @ref LL_ADC_RESOLUTION_12B
2250 * @arg @ref LL_ADC_RESOLUTION_10B
2251 * @arg @ref LL_ADC_RESOLUTION_8B
2252 * @arg @ref LL_ADC_RESOLUTION_6B
2253 * @retval ADC conversion data to the requested resolution
2254 */
2255 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2256 __ADC_RESOLUTION_CURRENT__,\
2257 __ADC_RESOLUTION_TARGET__) \
2258 (((__DATA__) \
2259 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \
2260 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \
2261 )
2262
2263 /**
2264 * @brief Helper macro to calculate the voltage (unit: mVolt)
2265 * corresponding to a ADC conversion data (unit: digital value).
2266 * @note Analog reference voltage (Vref+) must be either known from
2267 * user board environment or can be calculated using ADC measurement
2268 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2269 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2270 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2271 * (unit: digital value).
2272 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2273 * @arg @ref LL_ADC_RESOLUTION_12B
2274 * @arg @ref LL_ADC_RESOLUTION_10B
2275 * @arg @ref LL_ADC_RESOLUTION_8B
2276 * @arg @ref LL_ADC_RESOLUTION_6B
2277 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2278 */
2279 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2280 __ADC_DATA__,\
2281 __ADC_RESOLUTION__) \
2282 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2283 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2284 )
2285
2286 /**
2287 * @brief Helper macro to calculate analog reference voltage (Vref+)
2288 * (unit: mVolt) from ADC conversion data of internal voltage
2289 * reference VrefInt.
2290 * @note Computation is using VrefInt calibration value
2291 * stored in system memory for each device during production.
2292 * @note This voltage depends on user board environment: voltage level
2293 * connected to pin Vref+.
2294 * On devices with small package, the pin Vref+ is not present
2295 * and internally bonded to pin Vdda.
2296 * @note On this STM32 series, calibration data of internal voltage reference
2297 * VrefInt corresponds to a resolution of 12 bits,
2298 * this is the recommended ADC resolution to convert voltage of
2299 * internal voltage reference VrefInt.
2300 * Otherwise, this macro performs the processing to scale
2301 * ADC conversion data to 12 bits.
2302 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2303 * of internal voltage reference VrefInt (unit: digital value).
2304 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2305 * @arg @ref LL_ADC_RESOLUTION_12B
2306 * @arg @ref LL_ADC_RESOLUTION_10B
2307 * @arg @ref LL_ADC_RESOLUTION_8B
2308 * @arg @ref LL_ADC_RESOLUTION_6B
2309 * @retval Analog reference voltage (unit: mV)
2310 */
2311 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2312 __ADC_RESOLUTION__) \
2313 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2314 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2315 (__ADC_RESOLUTION__), \
2316 LL_ADC_RESOLUTION_12B) \
2317 )
2318
2319 /**
2320 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2321 * from ADC conversion data of internal temperature sensor.
2322 * @note Computation is using temperature sensor calibration values
2323 * stored in system memory for each device during production.
2324 * @note Calculation formula:
2325 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2326 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2327 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2328 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2329 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2330 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2331 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2332 * TEMP_DEGC_CAL1 (calibrated in factory)
2333 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2334 * TEMP_DEGC_CAL2 (calibrated in factory)
2335 * Caution: Calculation relevancy under reserve that calibration
2336 * parameters are correct (address and data).
2337 * To calculate temperature using temperature sensor
2338 * datasheet typical values (generic values less, therefore
2339 * less accurate than calibrated values),
2340 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2341 * @note As calculation input, the analog reference voltage (Vref+) must be
2342 * defined as it impacts the ADC LSB equivalent voltage.
2343 * @note Analog reference voltage (Vref+) must be either known from
2344 * user board environment or can be calculated using ADC measurement
2345 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2346 * @note On this STM32 series, calibration data of temperature sensor
2347 * corresponds to a resolution of 12 bits,
2348 * this is the recommended ADC resolution to convert voltage of
2349 * temperature sensor.
2350 * Otherwise, this macro performs the processing to scale
2351 * ADC conversion data to 12 bits.
2352 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2353 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2354 * temperature sensor (unit: digital value).
2355 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2356 * sensor voltage has been measured.
2357 * This parameter can be one of the following values:
2358 * @arg @ref LL_ADC_RESOLUTION_12B
2359 * @arg @ref LL_ADC_RESOLUTION_10B
2360 * @arg @ref LL_ADC_RESOLUTION_8B
2361 * @arg @ref LL_ADC_RESOLUTION_6B
2362 * @retval Temperature (unit: degree Celsius)
2363 */
2364 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2365 __TEMPSENSOR_ADC_DATA__,\
2366 __ADC_RESOLUTION__) \
2367 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2368 (__ADC_RESOLUTION__), \
2369 LL_ADC_RESOLUTION_12B) \
2370 * (__VREFANALOG_VOLTAGE__)) \
2371 / TEMPSENSOR_CAL_VREFANALOG) \
2372 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2373 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2374 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2375 ) + TEMPSENSOR_CAL1_TEMP \
2376 )
2377
2378 /**
2379 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2380 * from ADC conversion data of internal temperature sensor.
2381 * @note Computation is using temperature sensor typical values
2382 * (refer to device datasheet).
2383 * @note Calculation formula:
2384 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2385 * / Avg_Slope + CALx_TEMP
2386 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2387 * (unit: digital value)
2388 * Avg_Slope = temperature sensor slope
2389 * (unit: uV/Degree Celsius)
2390 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2391 * temperature CALx_TEMP (unit: mV)
2392 * Caution: Calculation relevancy under reserve the temperature sensor
2393 * of the current device has characteristics in line with
2394 * datasheet typical values.
2395 * If temperature sensor calibration values are available on
2396 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2397 * temperature calculation will be more accurate using
2398 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2399 * @note As calculation input, the analog reference voltage (Vref+) must be
2400 * defined as it impacts the ADC LSB equivalent voltage.
2401 * @note Analog reference voltage (Vref+) must be either known from
2402 * user board environment or can be calculated using ADC measurement
2403 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2404 * @note ADC measurement data must correspond to a resolution of 12bits
2405 * (full scale digital value 4095). If not the case, the data must be
2406 * preliminarily rescaled to an equivalent resolution of 12 bits.
2407 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2408 * On STM32F3, refer to device datasheet parameter "Avg_Slope".
2409 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2410 * On STM32F3, refer to device datasheet parameter "V25" (corresponding to TS_CAL1).
2411 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: DegC)
2412 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2413 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2414 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2415 * This parameter can be one of the following values:
2416 * @arg @ref LL_ADC_RESOLUTION_12B
2417 * @arg @ref LL_ADC_RESOLUTION_10B
2418 * @arg @ref LL_ADC_RESOLUTION_8B
2419 * @arg @ref LL_ADC_RESOLUTION_6B
2420 * @retval Temperature (unit: degree Celsius)
2421 */
2422 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2423 __TEMPSENSOR_TYP_CALX_V__,\
2424 __TEMPSENSOR_CALX_TEMP__,\
2425 __VREFANALOG_VOLTAGE__,\
2426 __TEMPSENSOR_ADC_DATA__,\
2427 __ADC_RESOLUTION__) \
2428 ((( ( \
2429 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2430 * 1000) \
2431 - \
2432 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2433 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2434 * 1000) \
2435 ) \
2436 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
2437 ) + (__TEMPSENSOR_CALX_TEMP__) \
2438 )
2439
2440 /**
2441 * @}
2442 */
2443
2444 /**
2445 * @}
2446 */
2447
2448
2449 /* Exported functions --------------------------------------------------------*/
2450 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2451 * @{
2452 */
2453
2454 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2455 * @{
2456 */
2457 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2458 /* configuration of ADC instance, groups and multimode (if available): */
2459 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2460
2461 /**
2462 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2463 * ADC register address from ADC instance and a list of ADC registers
2464 * intended to be used (most commonly) with DMA transfer.
2465 * @note These ADC registers are data registers:
2466 * when ADC conversion data is available in ADC data registers,
2467 * ADC generates a DMA transfer request.
2468 * @note This macro is intended to be used with LL DMA driver, refer to
2469 * function "LL_DMA_ConfigAddresses()".
2470 * Example:
2471 * LL_DMA_ConfigAddresses(DMA1,
2472 * LL_DMA_CHANNEL_1,
2473 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2474 * (uint32_t)&< array or variable >,
2475 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2476 * @note For devices with several ADC: in multimode, some devices
2477 * use a different data register outside of ADC instance scope
2478 * (common data register). This macro manages this register difference,
2479 * only ADC instance has to be set as parameter.
2480 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2481 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2482 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2483 * @param ADCx ADC instance
2484 * @param Register This parameter can be one of the following values:
2485 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2486 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2487 *
2488 * (1) Available on devices with several ADC instances.
2489 * @retval ADC register address
2490 */
2491 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2492 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2493 {
2494 uint32_t data_reg_addr = 0U;
2495
2496 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2497 {
2498 /* Retrieve address of register DR */
2499 data_reg_addr = (uint32_t)&(ADCx->DR);
2500 }
2501 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2502 {
2503 /* Retrieve address of register CDR */
2504 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2505 }
2506
2507 return data_reg_addr;
2508 }
2509 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2510 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2511 {
2512 /* Prevent unused argument compilation warning */
2513 (void)Register;
2514
2515 /* Retrieve address of register DR */
2516 return (uint32_t)&(ADCx->DR);
2517 }
2518 #endif
2519
2520 /**
2521 * @}
2522 */
2523
2524 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2525 * @{
2526 */
2527
2528 /**
2529 * @brief Set parameter common to several ADC: Clock source and prescaler.
2530 * @note On this STM32 series, if ADC group injected is used, some
2531 * clock ratio constraints between ADC clock and AHB clock
2532 * must be respected.
2533 * Refer to reference manual.
2534 * @note On this STM32 series, setting of this feature is conditioned to
2535 * ADC state:
2536 * All ADC instances of the ADC common group must be disabled.
2537 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2538 * ADC instance or by using helper macro helper macro
2539 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2540 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2541 * CCR PRESC LL_ADC_SetCommonClock
2542 * @param ADCxy_COMMON ADC common instance
2543 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2544 * @param CommonClock This parameter can be one of the following values:
2545 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2546 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2547 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2548 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2549 * @retval None
2550 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2551 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2552 {
2553 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE, CommonClock);
2554 }
2555
2556 /**
2557 * @brief Get parameter common to several ADC: Clock source and prescaler.
2558 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2559 * CCR PRESC LL_ADC_GetCommonClock
2560 * @param ADCxy_COMMON ADC common instance
2561 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2562 * @retval Returned value can be one of the following values:
2563 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2564 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2565 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2566 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2567 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2568 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2569 {
2570 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE));
2571 }
2572
2573 /**
2574 * @brief Set parameter common to several ADC: measurement path to internal
2575 * channels (VrefInt, temperature sensor, ...).
2576 * @note One or several values can be selected.
2577 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2578 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2579 * @note Stabilization time of measurement path to internal channel:
2580 * After enabling internal paths, before starting ADC conversion,
2581 * a delay is required for internal voltage reference and
2582 * temperature sensor stabilization time.
2583 * Refer to device datasheet.
2584 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2585 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2586 * @note ADC internal channel sampling time constraint:
2587 * For ADC conversion of internal channels,
2588 * a sampling time minimum value is required.
2589 * Refer to device datasheet.
2590 * @note On this STM32 series, setting of this feature is conditioned to
2591 * ADC state:
2592 * All ADC instances of the ADC common group must be disabled.
2593 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2594 * ADC instance or by using helper macro helper macro
2595 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2596 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2597 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2598 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2599 * @param ADCxy_COMMON ADC common instance
2600 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2601 * @param PathInternal This parameter can be a combination of the following values:
2602 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2603 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2604 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2605 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2606 * @retval None
2607 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2608 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2609 {
2610 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2611 }
2612
2613 /**
2614 * @brief Get parameter common to several ADC: measurement path to internal
2615 * channels (VrefInt, temperature sensor, ...).
2616 * @note One or several values can be selected.
2617 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2618 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2619 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2620 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2621 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2622 * @param ADCxy_COMMON ADC common instance
2623 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2624 * @retval Returned value can be a combination of the following values:
2625 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2626 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2627 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2628 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2629 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2630 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2631 {
2632 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2633 }
2634
2635 /**
2636 * @}
2637 */
2638
2639 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2640 * @{
2641 */
2642
2643 /**
2644 * @brief Set ADC calibration factor in the mode single-ended
2645 * or differential (for devices with differential mode available).
2646 * @note This function is intended to set calibration parameters
2647 * without having to perform a new calibration using
2648 * @ref LL_ADC_StartCalibration().
2649 * @note For devices with differential mode available:
2650 * Calibration of offset is specific to each of
2651 * single-ended and differential modes
2652 * (calibration factor must be specified for each of these
2653 * differential modes, if used afterwards and if the application
2654 * requires their calibration).
2655 * @note In case of setting calibration factors of both modes single ended
2656 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2657 * both calibration factors must be concatenated.
2658 * To perform this processing, use helper macro
2659 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2660 * @note On this STM32 series, setting of this feature is conditioned to
2661 * ADC state:
2662 * ADC must be enabled, without calibration on going, without conversion
2663 * on going on group regular.
2664 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2665 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2666 * @param ADCx ADC instance
2667 * @param SingleDiff This parameter can be one of the following values:
2668 * @arg @ref LL_ADC_SINGLE_ENDED
2669 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2670 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2671 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2672 * @retval None
2673 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2674 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2675 {
2676 MODIFY_REG(ADCx->CALFACT,
2677 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2678 CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
2679 }
2680
2681 /**
2682 * @brief Get ADC calibration factor in the mode single-ended
2683 * or differential (for devices with differential mode available).
2684 * @note Calibration factors are set by hardware after performing
2685 * a calibration run using function @ref LL_ADC_StartCalibration().
2686 * @note For devices with differential mode available:
2687 * Calibration of offset is specific to each of
2688 * single-ended and differential modes
2689 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2690 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2691 * @param ADCx ADC instance
2692 * @param SingleDiff This parameter can be one of the following values:
2693 * @arg @ref LL_ADC_SINGLE_ENDED
2694 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2695 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2696 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2697 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2698 {
2699 /* Retrieve bits with position in register depending on parameter */
2700 /* "SingleDiff". */
2701 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2702 /* containing other bits reserved for other purpose. */
2703 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
2704 }
2705
2706 /**
2707 * @brief Set ADC resolution.
2708 * Refer to reference manual for alignments formats
2709 * dependencies to ADC resolutions.
2710 * @note On this STM32 series, setting of this feature is conditioned to
2711 * ADC state:
2712 * ADC must be disabled or enabled without conversion on going
2713 * on either groups regular or injected.
2714 * @rmtoll CFGR RES LL_ADC_SetResolution
2715 * @param ADCx ADC instance
2716 * @param Resolution This parameter can be one of the following values:
2717 * @arg @ref LL_ADC_RESOLUTION_12B
2718 * @arg @ref LL_ADC_RESOLUTION_10B
2719 * @arg @ref LL_ADC_RESOLUTION_8B
2720 * @arg @ref LL_ADC_RESOLUTION_6B
2721 * @retval None
2722 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2723 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2724 {
2725 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2726 }
2727
2728 /**
2729 * @brief Get ADC resolution.
2730 * Refer to reference manual for alignments formats
2731 * dependencies to ADC resolutions.
2732 * @rmtoll CFGR RES LL_ADC_GetResolution
2733 * @param ADCx ADC instance
2734 * @retval Returned value can be one of the following values:
2735 * @arg @ref LL_ADC_RESOLUTION_12B
2736 * @arg @ref LL_ADC_RESOLUTION_10B
2737 * @arg @ref LL_ADC_RESOLUTION_8B
2738 * @arg @ref LL_ADC_RESOLUTION_6B
2739 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2740 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2741 {
2742 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2743 }
2744
2745 /**
2746 * @brief Set ADC conversion data alignment.
2747 * @note Refer to reference manual for alignments formats
2748 * dependencies to ADC resolutions.
2749 * @note On this STM32 series, setting of this feature is conditioned to
2750 * ADC state:
2751 * ADC must be disabled or enabled without conversion on going
2752 * on either groups regular or injected.
2753 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2754 * @param ADCx ADC instance
2755 * @param DataAlignment This parameter can be one of the following values:
2756 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2757 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2758 * @retval None
2759 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2760 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2761 {
2762 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2763 }
2764
2765 /**
2766 * @brief Get ADC conversion data alignment.
2767 * @note Refer to reference manual for alignments formats
2768 * dependencies to ADC resolutions.
2769 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2770 * @param ADCx ADC instance
2771 * @retval Returned value can be one of the following values:
2772 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2773 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2774 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2775 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2776 {
2777 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2778 }
2779
2780 /**
2781 * @brief Set ADC low power mode.
2782 * @note Description of ADC low power modes:
2783 * - ADC low power mode "auto wait": Dynamic low power mode,
2784 * ADC conversions occurrences are limited to the minimum necessary
2785 * in order to reduce power consumption.
2786 * New ADC conversion starts only when the previous
2787 * unitary conversion data (for ADC group regular)
2788 * or previous sequence conversions data (for ADC group injected)
2789 * has been retrieved by user software.
2790 * In the meantime, ADC remains idle: does not performs any
2791 * other conversion.
2792 * This mode allows to automatically adapt the ADC conversions
2793 * triggers to the speed of the software that reads the data.
2794 * Moreover, this avoids risk of overrun for low frequency
2795 * applications.
2796 * How to use this low power mode:
2797 * - It is not recommended to use with interruption or DMA
2798 * since these modes have to clear immediately the EOC flag
2799 * (by CPU to free the IRQ pending event or by DMA).
2800 * Auto wait will work but fort a very short time, discarding
2801 * its intended benefit (except specific case of high load of CPU
2802 * or DMA transfers which can justify usage of auto wait).
2803 * - Do use with polling: 1. Start conversion,
2804 * 2. Later on, when conversion data is needed: poll for end of
2805 * conversion to ensure that conversion is completed and
2806 * retrieve ADC conversion data. This will trig another
2807 * ADC conversion start.
2808 * - ADC low power mode "auto power-off" (feature available on
2809 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2810 * the ADC automatically powers-off after a conversion and
2811 * automatically wakes up when a new conversion is triggered
2812 * (with startup time between trigger and start of sampling).
2813 * This feature can be combined with low power mode "auto wait".
2814 * @note With ADC low power mode "auto wait", the ADC conversion data read
2815 * is corresponding to previous ADC conversion start, independently
2816 * of delay during which ADC was idle.
2817 * Therefore, the ADC conversion data may be outdated: does not
2818 * correspond to the current voltage level on the selected
2819 * ADC channel.
2820 * @note On this STM32 series, setting of this feature is conditioned to
2821 * ADC state:
2822 * ADC must be disabled or enabled without conversion on going
2823 * on either groups regular or injected.
2824 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2825 * @param ADCx ADC instance
2826 * @param LowPowerMode This parameter can be one of the following values:
2827 * @arg @ref LL_ADC_LP_MODE_NONE
2828 * @arg @ref LL_ADC_LP_AUTOWAIT
2829 * @retval None
2830 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2831 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2832 {
2833 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2834 }
2835
2836 /**
2837 * @brief Get ADC low power mode:
2838 * @note Description of ADC low power modes:
2839 * - ADC low power mode "auto wait": Dynamic low power mode,
2840 * ADC conversions occurrences are limited to the minimum necessary
2841 * in order to reduce power consumption.
2842 * New ADC conversion starts only when the previous
2843 * unitary conversion data (for ADC group regular)
2844 * or previous sequence conversions data (for ADC group injected)
2845 * has been retrieved by user software.
2846 * In the meantime, ADC remains idle: does not performs any
2847 * other conversion.
2848 * This mode allows to automatically adapt the ADC conversions
2849 * triggers to the speed of the software that reads the data.
2850 * Moreover, this avoids risk of overrun for low frequency
2851 * applications.
2852 * How to use this low power mode:
2853 * - It is not recommended to use with interruption or DMA
2854 * since these modes have to clear immediately the EOC flag
2855 * (by CPU to free the IRQ pending event or by DMA).
2856 * Auto wait will work but fort a very short time, discarding
2857 * its intended benefit (except specific case of high load of CPU
2858 * or DMA transfers which can justify usage of auto wait).
2859 * - Do use with polling: 1. Start conversion,
2860 * 2. Later on, when conversion data is needed: poll for end of
2861 * conversion to ensure that conversion is completed and
2862 * retrieve ADC conversion data. This will trig another
2863 * ADC conversion start.
2864 * - ADC low power mode "auto power-off" (feature available on
2865 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
2866 * the ADC automatically powers-off after a conversion and
2867 * automatically wakes up when a new conversion is triggered
2868 * (with startup time between trigger and start of sampling).
2869 * This feature can be combined with low power mode "auto wait".
2870 * @note With ADC low power mode "auto wait", the ADC conversion data read
2871 * is corresponding to previous ADC conversion start, independently
2872 * of delay during which ADC was idle.
2873 * Therefore, the ADC conversion data may be outdated: does not
2874 * correspond to the current voltage level on the selected
2875 * ADC channel.
2876 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2877 * @param ADCx ADC instance
2878 * @retval Returned value can be one of the following values:
2879 * @arg @ref LL_ADC_LP_MODE_NONE
2880 * @arg @ref LL_ADC_LP_AUTOWAIT
2881 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2882 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2883 {
2884 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2885 }
2886
2887 /**
2888 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2889 * @note This function set the 2 items of offset configuration:
2890 * - ADC channel to which the offset programmed will be applied
2891 * (independently of channel mapped on ADC group regular
2892 * or group injected)
2893 * - Offset level (offset to be subtracted from the raw
2894 * converted data).
2895 * @note Caution: Offset format is dependent to ADC resolution:
2896 * offset has to be left-aligned on bit 11, the LSB (right bits)
2897 * are set to 0.
2898 * @note This function enables the offset, by default. It can be forced
2899 * to disable state using function LL_ADC_SetOffsetState().
2900 * @note If a channel is mapped on several offsets numbers, only the offset
2901 * with the lowest value is considered for the subtraction.
2902 * @note On this STM32 series, setting of this feature is conditioned to
2903 * ADC state:
2904 * ADC must be disabled or enabled without conversion on going
2905 * on either groups regular or injected.
2906 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2907 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2908 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2909 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2910 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2911 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2912 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2913 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2914 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2915 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2916 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2917 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2918 * @param ADCx ADC instance
2919 * @param Offsety This parameter can be one of the following values:
2920 * @arg @ref LL_ADC_OFFSET_1
2921 * @arg @ref LL_ADC_OFFSET_2
2922 * @arg @ref LL_ADC_OFFSET_3
2923 * @arg @ref LL_ADC_OFFSET_4
2924 * @param Channel This parameter can be one of the following values:
2925 * @arg @ref LL_ADC_CHANNEL_0
2926 * @arg @ref LL_ADC_CHANNEL_1
2927 * @arg @ref LL_ADC_CHANNEL_2
2928 * @arg @ref LL_ADC_CHANNEL_3
2929 * @arg @ref LL_ADC_CHANNEL_4
2930 * @arg @ref LL_ADC_CHANNEL_5
2931 * @arg @ref LL_ADC_CHANNEL_6
2932 * @arg @ref LL_ADC_CHANNEL_7
2933 * @arg @ref LL_ADC_CHANNEL_8
2934 * @arg @ref LL_ADC_CHANNEL_9
2935 * @arg @ref LL_ADC_CHANNEL_10
2936 * @arg @ref LL_ADC_CHANNEL_11
2937 * @arg @ref LL_ADC_CHANNEL_12
2938 * @arg @ref LL_ADC_CHANNEL_13
2939 * @arg @ref LL_ADC_CHANNEL_14
2940 * @arg @ref LL_ADC_CHANNEL_15
2941 * @arg @ref LL_ADC_CHANNEL_16
2942 * @arg @ref LL_ADC_CHANNEL_17
2943 * @arg @ref LL_ADC_CHANNEL_18
2944 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
2945 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2946 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2947 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2948 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2949 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
2950 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
2951 *
2952 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
2953 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
2954 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
2955 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
2956 * (5) On STM32F3, ADC channel available only on all ADC instances, but
2957 * only one ADC instance is allowed to be connected to VrefInt at the same time.
2958 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2959 * @retval None
2960 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)2961 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2962 {
2963 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2964
2965 MODIFY_REG(*preg,
2966 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2967 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2968 }
2969
2970 /**
2971 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2972 * Channel to which the offset programmed will be applied
2973 * (independently of channel mapped on ADC group regular
2974 * or group injected)
2975 * @note Usage of the returned channel number:
2976 * - To reinject this channel into another function LL_ADC_xxx:
2977 * the returned channel number is only partly formatted on definition
2978 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2979 * with parts of literals LL_ADC_CHANNEL_x or using
2980 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2981 * Then the selected literal LL_ADC_CHANNEL_x can be used
2982 * as parameter for another function.
2983 * - To get the channel number in decimal format:
2984 * process the returned value with the helper macro
2985 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2986 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2987 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2988 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2989 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2990 * @param ADCx ADC instance
2991 * @param Offsety This parameter can be one of the following values:
2992 * @arg @ref LL_ADC_OFFSET_1
2993 * @arg @ref LL_ADC_OFFSET_2
2994 * @arg @ref LL_ADC_OFFSET_3
2995 * @arg @ref LL_ADC_OFFSET_4
2996 * @retval Returned value can be one of the following values:
2997 * @arg @ref LL_ADC_CHANNEL_0
2998 * @arg @ref LL_ADC_CHANNEL_1
2999 * @arg @ref LL_ADC_CHANNEL_2
3000 * @arg @ref LL_ADC_CHANNEL_3
3001 * @arg @ref LL_ADC_CHANNEL_4
3002 * @arg @ref LL_ADC_CHANNEL_5
3003 * @arg @ref LL_ADC_CHANNEL_6
3004 * @arg @ref LL_ADC_CHANNEL_7
3005 * @arg @ref LL_ADC_CHANNEL_8
3006 * @arg @ref LL_ADC_CHANNEL_9
3007 * @arg @ref LL_ADC_CHANNEL_10
3008 * @arg @ref LL_ADC_CHANNEL_11
3009 * @arg @ref LL_ADC_CHANNEL_12
3010 * @arg @ref LL_ADC_CHANNEL_13
3011 * @arg @ref LL_ADC_CHANNEL_14
3012 * @arg @ref LL_ADC_CHANNEL_15
3013 * @arg @ref LL_ADC_CHANNEL_16
3014 * @arg @ref LL_ADC_CHANNEL_17
3015 * @arg @ref LL_ADC_CHANNEL_18
3016 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3017 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3018 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3019 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3020 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3021 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3022 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3023 *
3024 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3025 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3026 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3027 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3028 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3029 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
3030 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
3031 * comparison with internal channel parameter to be done
3032 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3033 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)3034 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3035 {
3036 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3037
3038 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3039 }
3040
3041 /**
3042 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3043 * Offset level (offset to be subtracted from the raw
3044 * converted data).
3045 * @note Caution: Offset format is dependent to ADC resolution:
3046 * offset has to be left-aligned on bit 11, the LSB (right bits)
3047 * are set to 0.
3048 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3049 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3050 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3051 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3052 * @param ADCx ADC instance
3053 * @param Offsety This parameter can be one of the following values:
3054 * @arg @ref LL_ADC_OFFSET_1
3055 * @arg @ref LL_ADC_OFFSET_2
3056 * @arg @ref LL_ADC_OFFSET_3
3057 * @arg @ref LL_ADC_OFFSET_4
3058 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3059 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)3060 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3061 {
3062 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3063
3064 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3065 }
3066
3067 /**
3068 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3069 * force offset state disable or enable
3070 * without modifying offset channel or offset value.
3071 * @note This function should be needed only in case of offset to be
3072 * enabled-disabled dynamically, and should not be needed in other cases:
3073 * function LL_ADC_SetOffset() automatically enables the offset.
3074 * @note On this STM32 series, setting of this feature is conditioned to
3075 * ADC state:
3076 * ADC must be disabled or enabled without conversion on going
3077 * on either groups regular or injected.
3078 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3079 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3080 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3081 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3082 * @param ADCx ADC instance
3083 * @param Offsety This parameter can be one of the following values:
3084 * @arg @ref LL_ADC_OFFSET_1
3085 * @arg @ref LL_ADC_OFFSET_2
3086 * @arg @ref LL_ADC_OFFSET_3
3087 * @arg @ref LL_ADC_OFFSET_4
3088 * @param OffsetState This parameter can be one of the following values:
3089 * @arg @ref LL_ADC_OFFSET_DISABLE
3090 * @arg @ref LL_ADC_OFFSET_ENABLE
3091 * @retval None
3092 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3093 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3094 {
3095 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)
3096 ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
3097
3098 MODIFY_REG(*preg,
3099 ADC_OFR1_OFFSET1_EN,
3100 OffsetState);
3101 }
3102
3103 /**
3104 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3105 * offset state disabled or enabled.
3106 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3107 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3108 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3109 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3110 * @param ADCx ADC instance
3111 * @param Offsety This parameter can be one of the following values:
3112 * @arg @ref LL_ADC_OFFSET_1
3113 * @arg @ref LL_ADC_OFFSET_2
3114 * @arg @ref LL_ADC_OFFSET_3
3115 * @arg @ref LL_ADC_OFFSET_4
3116 * @retval Returned value can be one of the following values:
3117 * @arg @ref LL_ADC_OFFSET_DISABLE
3118 * @arg @ref LL_ADC_OFFSET_ENABLE
3119 */
LL_ADC_GetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety)3120 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3121 {
3122 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3123
3124 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3125 }
3126
3127 /**
3128 * @}
3129 */
3130
3131 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3132 * @{
3133 */
3134
3135 /**
3136 * @brief Set ADC group regular conversion trigger source:
3137 * internal (SW start) or from external IP (timer event,
3138 * external interrupt line).
3139 * @note On this STM32 series, setting trigger source to external trigger
3140 * also set trigger polarity to rising edge
3141 * (default setting for compatibility with some ADC on other
3142 * STM32 families having this setting set by HW default value).
3143 * In case of need to modify trigger edge, use
3144 * function @ref LL_ADC_REG_SetTriggerEdge().
3145 * @note Availability of parameters of trigger sources from timer
3146 * depends on timers availability on the selected device.
3147 * @note On this STM32 series, setting of this feature is conditioned to
3148 * ADC state:
3149 * ADC must be disabled or enabled without conversion on going
3150 * on group regular.
3151 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3152 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3153 * @param ADCx ADC instance
3154 * @param TriggerSource This parameter can be one of the following values:
3155 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3156 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3157 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3158 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
3159 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
3160 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
3161 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
3162 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3163 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
3164 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3165 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3166 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
3167 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
3168 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
3169 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
3170 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
3171 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
3172 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
3173 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
3175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
3176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
3177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
3178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
3179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
3180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
3182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
3183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
3187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3188 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
3189 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
3190 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
3191 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
3192 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
3193 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
3194 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
3195 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
3196 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
3197 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
3198 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
3199 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
3200 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
3201 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
3202 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
3203
3204 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3205 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3206 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3207 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3208 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3209 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3210 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3211 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3212 * @retval None
3213 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3214 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3215 {
3216 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3217 }
3218
3219 /**
3220 * @brief Get ADC group regular conversion trigger source:
3221 * internal (SW start) or from external IP (timer event,
3222 * external interrupt line).
3223 * @note To determine whether group regular trigger source is
3224 * internal (SW start) or external, without detail
3225 * of which peripheral is selected as external trigger,
3226 * (equivalent to
3227 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3228 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3229 * @note Availability of parameters of trigger sources from timer
3230 * depends on timers availability on the selected device.
3231 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3232 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3233 * @param ADCx ADC instance
3234 * @retval Returned value can be one of the following values:
3235 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3236 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3237 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3238 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
3239 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
3240 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
3241 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
3242 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3243 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
3244 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3245 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3246 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
3247 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
3248 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
3249 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
3250 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
3251 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
3252 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
3253 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3254 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
3255 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
3256 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
3257 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
3258 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
3259 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
3260 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3261 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
3262 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
3263 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3264 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3265 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3266 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
3267 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
3268 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
3269 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
3270 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
3271 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
3272 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
3273 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
3274 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
3275 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
3276 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
3277 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
3278 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
3279 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
3280 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
3281 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
3282 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
3283
3284 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3285 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3286 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3287 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3288 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3289 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3290 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3291 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3292 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3293 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3294 {
3295 uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3296
3297 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3298 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3299 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
3300
3301 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3302 /* to match with triggers literals definition. */
3303 return ((TriggerSource
3304 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3305 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3306 );
3307 }
3308
3309 /**
3310 * @brief Get ADC group regular conversion trigger source internal (SW start)
3311 or external.
3312 * @note In case of group regular trigger source set to external trigger,
3313 * to determine which peripheral is selected as external trigger,
3314 * use function @ref LL_ADC_REG_GetTriggerSource().
3315 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3316 * @param ADCx ADC instance
3317 * @retval Value "0" if trigger source external trigger
3318 * Value "1" if trigger source SW start.
3319 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3320 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3321 {
3322 return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
3323 }
3324
3325 /**
3326 * @brief Set ADC group regular conversion trigger polarity.
3327 * @note Applicable only for trigger source set to external trigger.
3328 * @note On this STM32 series, setting of this feature is conditioned to
3329 * ADC state:
3330 * ADC must be disabled or enabled without conversion on going
3331 * on group regular.
3332 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3333 * @param ADCx ADC instance
3334 * @param ExternalTriggerEdge This parameter can be one of the following values:
3335 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3336 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3337 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3338 * @retval None
3339 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3340 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3341 {
3342 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3343 }
3344
3345 /**
3346 * @brief Get ADC group regular conversion trigger polarity.
3347 * @note Applicable only for trigger source set to external trigger.
3348 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3349 * @param ADCx ADC instance
3350 * @retval Returned value can be one of the following values:
3351 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3352 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3353 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3354 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3355 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3356 {
3357 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3358 }
3359
3360
3361 /**
3362 * @brief Set ADC group regular sequencer length and scan direction.
3363 * @note Description of ADC group regular sequencer features:
3364 * - For devices with sequencer fully configurable
3365 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3366 * sequencer length and each rank affectation to a channel
3367 * are configurable.
3368 * This function performs configuration of:
3369 * - Sequence length: Number of ranks in the scan sequence.
3370 * - Sequence direction: Unless specified in parameters, sequencer
3371 * scan direction is forward (from rank 1 to rank n).
3372 * Sequencer ranks are selected using
3373 * function "LL_ADC_REG_SetSequencerRanks()".
3374 * - For devices with sequencer not fully configurable
3375 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3376 * sequencer length and each rank affectation to a channel
3377 * are defined by channel number.
3378 * This function performs configuration of:
3379 * - Sequence length: Number of ranks in the scan sequence is
3380 * defined by number of channels set in the sequence,
3381 * rank of each channel is fixed by channel HW number.
3382 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3383 * - Sequence direction: Unless specified in parameters, sequencer
3384 * scan direction is forward (from lowest channel number to
3385 * highest channel number).
3386 * Sequencer ranks are selected using
3387 * function "LL_ADC_REG_SetSequencerChannels()".
3388 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3389 * ADC conversion on only 1 channel.
3390 * @note On this STM32 series, setting of this feature is conditioned to
3391 * ADC state:
3392 * ADC must be disabled or enabled without conversion on going
3393 * on group regular.
3394 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3395 * @param ADCx ADC instance
3396 * @param SequencerNbRanks This parameter can be one of the following values:
3397 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3398 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3399 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3400 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3401 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3402 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3403 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3404 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3405 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3406 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3407 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3408 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3409 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3410 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3411 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3412 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3413 * @retval None
3414 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3415 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3416 {
3417 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3418 }
3419
3420 /**
3421 * @brief Get ADC group regular sequencer length and scan direction.
3422 * @note Description of ADC group regular sequencer features:
3423 * - For devices with sequencer fully configurable
3424 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3425 * sequencer length and each rank affectation to a channel
3426 * are configurable.
3427 * This function retrieves:
3428 * - Sequence length: Number of ranks in the scan sequence.
3429 * - Sequence direction: Unless specified in parameters, sequencer
3430 * scan direction is forward (from rank 1 to rank n).
3431 * Sequencer ranks are selected using
3432 * function "LL_ADC_REG_SetSequencerRanks()".
3433 * - For devices with sequencer not fully configurable
3434 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3435 * sequencer length and each rank affectation to a channel
3436 * are defined by channel number.
3437 * This function retrieves:
3438 * - Sequence length: Number of ranks in the scan sequence is
3439 * defined by number of channels set in the sequence,
3440 * rank of each channel is fixed by channel HW number.
3441 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3442 * - Sequence direction: Unless specified in parameters, sequencer
3443 * scan direction is forward (from lowest channel number to
3444 * highest channel number).
3445 * Sequencer ranks are selected using
3446 * function "LL_ADC_REG_SetSequencerChannels()".
3447 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3448 * ADC conversion on only 1 channel.
3449 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3450 * @param ADCx ADC instance
3451 * @retval Returned value can be one of the following values:
3452 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3453 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3454 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3455 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3456 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3457 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3458 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3459 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3460 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3461 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3462 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3463 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3464 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3465 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3466 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3467 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3468 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3469 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3470 {
3471 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3472 }
3473
3474 /**
3475 * @brief Set ADC group regular sequencer discontinuous mode:
3476 * sequence subdivided and scan conversions interrupted every selected
3477 * number of ranks.
3478 * @note It is not possible to enable both ADC group regular
3479 * continuous mode and sequencer discontinuous mode.
3480 * @note It is not possible to enable both ADC auto-injected mode
3481 * and ADC group regular sequencer discontinuous mode.
3482 * @note On this STM32 series, setting of this feature is conditioned to
3483 * ADC state:
3484 * ADC must be disabled or enabled without conversion on going
3485 * on group regular.
3486 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3487 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3488 * @param ADCx ADC instance
3489 * @param SeqDiscont This parameter can be one of the following values:
3490 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3491 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3492 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3493 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3494 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3495 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3496 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3497 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3498 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3499 * @retval None
3500 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3501 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3502 {
3503 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3504 }
3505
3506 /**
3507 * @brief Get ADC group regular sequencer discontinuous mode:
3508 * sequence subdivided and scan conversions interrupted every selected
3509 * number of ranks.
3510 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3511 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3512 * @param ADCx ADC instance
3513 * @retval Returned value can be one of the following values:
3514 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3515 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3516 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3517 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3518 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3519 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3520 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3521 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3522 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3523 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3524 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3525 {
3526 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3527 }
3528
3529 /**
3530 * @brief Set ADC group regular sequence: channel on the selected
3531 * scan sequence rank.
3532 * @note This function performs configuration of:
3533 * - Channels ordering into each rank of scan sequence:
3534 * whatever channel can be placed into whatever rank.
3535 * @note On this STM32 series, ADC group regular sequencer is
3536 * fully configurable: sequencer length and each rank
3537 * affectation to a channel are configurable.
3538 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3539 * @note Depending on devices and packages, some channels may not be available.
3540 * Refer to device datasheet for channels availability.
3541 * @note On this STM32 series, to measure internal channels (VrefInt,
3542 * TempSensor, ...), measurement paths to internal channels must be
3543 * enabled separately.
3544 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3545 * @note On this STM32 series, setting of this feature is conditioned to
3546 * ADC state:
3547 * ADC must be disabled or enabled without conversion on going
3548 * on group regular.
3549 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3550 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3551 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3552 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3553 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3554 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3555 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3556 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3557 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3558 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3559 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3560 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3561 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3562 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3563 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3564 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3565 * @param ADCx ADC instance
3566 * @param Rank This parameter can be one of the following values:
3567 * @arg @ref LL_ADC_REG_RANK_1
3568 * @arg @ref LL_ADC_REG_RANK_2
3569 * @arg @ref LL_ADC_REG_RANK_3
3570 * @arg @ref LL_ADC_REG_RANK_4
3571 * @arg @ref LL_ADC_REG_RANK_5
3572 * @arg @ref LL_ADC_REG_RANK_6
3573 * @arg @ref LL_ADC_REG_RANK_7
3574 * @arg @ref LL_ADC_REG_RANK_8
3575 * @arg @ref LL_ADC_REG_RANK_9
3576 * @arg @ref LL_ADC_REG_RANK_10
3577 * @arg @ref LL_ADC_REG_RANK_11
3578 * @arg @ref LL_ADC_REG_RANK_12
3579 * @arg @ref LL_ADC_REG_RANK_13
3580 * @arg @ref LL_ADC_REG_RANK_14
3581 * @arg @ref LL_ADC_REG_RANK_15
3582 * @arg @ref LL_ADC_REG_RANK_16
3583 * @param Channel This parameter can be one of the following values:
3584 * @arg @ref LL_ADC_CHANNEL_0
3585 * @arg @ref LL_ADC_CHANNEL_1
3586 * @arg @ref LL_ADC_CHANNEL_2
3587 * @arg @ref LL_ADC_CHANNEL_3
3588 * @arg @ref LL_ADC_CHANNEL_4
3589 * @arg @ref LL_ADC_CHANNEL_5
3590 * @arg @ref LL_ADC_CHANNEL_6
3591 * @arg @ref LL_ADC_CHANNEL_7
3592 * @arg @ref LL_ADC_CHANNEL_8
3593 * @arg @ref LL_ADC_CHANNEL_9
3594 * @arg @ref LL_ADC_CHANNEL_10
3595 * @arg @ref LL_ADC_CHANNEL_11
3596 * @arg @ref LL_ADC_CHANNEL_12
3597 * @arg @ref LL_ADC_CHANNEL_13
3598 * @arg @ref LL_ADC_CHANNEL_14
3599 * @arg @ref LL_ADC_CHANNEL_15
3600 * @arg @ref LL_ADC_CHANNEL_16
3601 * @arg @ref LL_ADC_CHANNEL_17
3602 * @arg @ref LL_ADC_CHANNEL_18
3603 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3604 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3605 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3606 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3607 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3608 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3609 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3610 *
3611 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3612 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3613 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3614 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3615 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3616 * only one ADC instance is allowed to be connected to VrefInt at the same time.
3617 * @retval None
3618 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3619 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3620 {
3621 /* Set bits with content of parameter "Channel" with bits position */
3622 /* in register and register position depending on parameter "Rank". */
3623 /* Parameters "Rank" and "Channel" are used with masks because containing */
3624 /* other bits reserved for other purpose. */
3625 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
3626
3627 MODIFY_REG(*preg,
3628 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3629 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3630 }
3631
3632 /**
3633 * @brief Get ADC group regular sequence: channel on the selected
3634 * scan sequence rank.
3635 * @note On this STM32 series, ADC group regular sequencer is
3636 * fully configurable: sequencer length and each rank
3637 * affectation to a channel are configurable.
3638 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3639 * @note Depending on devices and packages, some channels may not be available.
3640 * Refer to device datasheet for channels availability.
3641 * @note Usage of the returned channel number:
3642 * - To reinject this channel into another function LL_ADC_xxx:
3643 * the returned channel number is only partly formatted on definition
3644 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3645 * with parts of literals LL_ADC_CHANNEL_x or using
3646 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3647 * Then the selected literal LL_ADC_CHANNEL_x can be used
3648 * as parameter for another function.
3649 * - To get the channel number in decimal format:
3650 * process the returned value with the helper macro
3651 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3652 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3653 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3654 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3655 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3656 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3657 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3658 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3659 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3660 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3661 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3662 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3663 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3664 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3665 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3666 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3667 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3668 * @param ADCx ADC instance
3669 * @param Rank This parameter can be one of the following values:
3670 * @arg @ref LL_ADC_REG_RANK_1
3671 * @arg @ref LL_ADC_REG_RANK_2
3672 * @arg @ref LL_ADC_REG_RANK_3
3673 * @arg @ref LL_ADC_REG_RANK_4
3674 * @arg @ref LL_ADC_REG_RANK_5
3675 * @arg @ref LL_ADC_REG_RANK_6
3676 * @arg @ref LL_ADC_REG_RANK_7
3677 * @arg @ref LL_ADC_REG_RANK_8
3678 * @arg @ref LL_ADC_REG_RANK_9
3679 * @arg @ref LL_ADC_REG_RANK_10
3680 * @arg @ref LL_ADC_REG_RANK_11
3681 * @arg @ref LL_ADC_REG_RANK_12
3682 * @arg @ref LL_ADC_REG_RANK_13
3683 * @arg @ref LL_ADC_REG_RANK_14
3684 * @arg @ref LL_ADC_REG_RANK_15
3685 * @arg @ref LL_ADC_REG_RANK_16
3686 * @retval Returned value can be one of the following values:
3687 * @arg @ref LL_ADC_CHANNEL_0
3688 * @arg @ref LL_ADC_CHANNEL_1
3689 * @arg @ref LL_ADC_CHANNEL_2
3690 * @arg @ref LL_ADC_CHANNEL_3
3691 * @arg @ref LL_ADC_CHANNEL_4
3692 * @arg @ref LL_ADC_CHANNEL_5
3693 * @arg @ref LL_ADC_CHANNEL_6
3694 * @arg @ref LL_ADC_CHANNEL_7
3695 * @arg @ref LL_ADC_CHANNEL_8
3696 * @arg @ref LL_ADC_CHANNEL_9
3697 * @arg @ref LL_ADC_CHANNEL_10
3698 * @arg @ref LL_ADC_CHANNEL_11
3699 * @arg @ref LL_ADC_CHANNEL_12
3700 * @arg @ref LL_ADC_CHANNEL_13
3701 * @arg @ref LL_ADC_CHANNEL_14
3702 * @arg @ref LL_ADC_CHANNEL_15
3703 * @arg @ref LL_ADC_CHANNEL_16
3704 * @arg @ref LL_ADC_CHANNEL_17
3705 * @arg @ref LL_ADC_CHANNEL_18
3706 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
3707 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3708 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3709 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3710 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3711 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
3712 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
3713 *
3714 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
3715 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
3716 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
3717 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
3718 * (5) On STM32F3, ADC channel available only on all ADC instances, but
3719 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
3720 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
3721 * comparison with internal channel parameter to be done
3722 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3723 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3724 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3725 {
3726 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
3727
3728 return (uint32_t) ((READ_BIT(*preg,
3729 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3730 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3731 );
3732 }
3733
3734 /**
3735 * @brief Set ADC continuous conversion mode on ADC group regular.
3736 * @note Description of ADC continuous conversion mode:
3737 * - single mode: one conversion per trigger
3738 * - continuous mode: after the first trigger, following
3739 * conversions launched successively automatically.
3740 * @note It is not possible to enable both ADC group regular
3741 * continuous mode and sequencer discontinuous mode.
3742 * @note On this STM32 series, setting of this feature is conditioned to
3743 * ADC state:
3744 * ADC must be disabled or enabled without conversion on going
3745 * on group regular.
3746 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3747 * @param ADCx ADC instance
3748 * @param Continuous This parameter can be one of the following values:
3749 * @arg @ref LL_ADC_REG_CONV_SINGLE
3750 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3751 * @retval None
3752 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3753 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3754 {
3755 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3756 }
3757
3758 /**
3759 * @brief Get ADC continuous conversion mode on ADC group regular.
3760 * @note Description of ADC continuous conversion mode:
3761 * - single mode: one conversion per trigger
3762 * - continuous mode: after the first trigger, following
3763 * conversions launched successively automatically.
3764 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3765 * @param ADCx ADC instance
3766 * @retval Returned value can be one of the following values:
3767 * @arg @ref LL_ADC_REG_CONV_SINGLE
3768 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3769 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3770 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3771 {
3772 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3773 }
3774
3775 /**
3776 * @brief Set ADC group regular conversion data transfer: no transfer or
3777 * transfer by DMA, and DMA requests mode.
3778 * @note If transfer by DMA selected, specifies the DMA requests
3779 * mode:
3780 * - Limited mode (One shot mode): DMA transfer requests are stopped
3781 * when number of DMA data transfers (number of
3782 * ADC conversions) is reached.
3783 * This ADC mode is intended to be used with DMA mode non-circular.
3784 * - Unlimited mode: DMA transfer requests are unlimited,
3785 * whatever number of DMA data transfers (number of
3786 * ADC conversions).
3787 * This ADC mode is intended to be used with DMA mode circular.
3788 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3789 * mode non-circular:
3790 * when DMA transfers size will be reached, DMA will stop transfers of
3791 * ADC conversions data ADC will raise an overrun error
3792 * (overrun flag and interruption if enabled).
3793 * @note For devices with several ADC instances: ADC multimode DMA
3794 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
3795 * @note To configure DMA source address (peripheral address),
3796 * use function @ref LL_ADC_DMA_GetRegAddr().
3797 * @note On this STM32 series, setting of this feature is conditioned to
3798 * ADC state:
3799 * ADC must be disabled or enabled without conversion on going
3800 * on either groups regular or injected.
3801 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
3802 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
3803 * @param ADCx ADC instance
3804 * @param DMATransfer This parameter can be one of the following values:
3805 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3806 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3807 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3808 * @retval None
3809 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3810 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3811 {
3812 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
3813 }
3814
3815 /**
3816 * @brief Get ADC group regular conversion data transfer: no transfer or
3817 * transfer by DMA, and DMA requests mode.
3818 * @note If transfer by DMA selected, specifies the DMA requests
3819 * mode:
3820 * - Limited mode (One shot mode): DMA transfer requests are stopped
3821 * when number of DMA data transfers (number of
3822 * ADC conversions) is reached.
3823 * This ADC mode is intended to be used with DMA mode non-circular.
3824 * - Unlimited mode: DMA transfer requests are unlimited,
3825 * whatever number of DMA data transfers (number of
3826 * ADC conversions).
3827 * This ADC mode is intended to be used with DMA mode circular.
3828 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3829 * mode non-circular:
3830 * when DMA transfers size will be reached, DMA will stop transfers of
3831 * ADC conversions data ADC will raise an overrun error
3832 * (overrun flag and interruption if enabled).
3833 * @note For devices with several ADC instances: ADC multimode DMA
3834 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
3835 * @note To configure DMA source address (peripheral address),
3836 * use function @ref LL_ADC_DMA_GetRegAddr().
3837 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
3838 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
3839 * @param ADCx ADC instance
3840 * @retval Returned value can be one of the following values:
3841 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3842 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3843 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3844 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3845 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3846 {
3847 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
3848 }
3849
3850 /**
3851 * @brief Set ADC group regular behavior in case of overrun:
3852 * data preserved or overwritten.
3853 * @note Compatibility with devices without feature overrun:
3854 * other devices without this feature have a behavior
3855 * equivalent to data overwritten.
3856 * The default setting of overrun is data preserved.
3857 * Therefore, for compatibility with all devices, parameter
3858 * overrun should be set to data overwritten.
3859 * @note On this STM32 series, setting of this feature is conditioned to
3860 * ADC state:
3861 * ADC must be disabled or enabled without conversion on going
3862 * on group regular.
3863 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3864 * @param ADCx ADC instance
3865 * @param Overrun This parameter can be one of the following values:
3866 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3867 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3868 * @retval None
3869 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3870 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3871 {
3872 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3873 }
3874
3875 /**
3876 * @brief Get ADC group regular behavior in case of overrun:
3877 * data preserved or overwritten.
3878 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3879 * @param ADCx ADC instance
3880 * @retval Returned value can be one of the following values:
3881 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3882 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3883 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3884 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3885 {
3886 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3887 }
3888
3889 /**
3890 * @}
3891 */
3892
3893 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3894 * @{
3895 */
3896
3897 /**
3898 * @brief Set ADC group injected conversion trigger source:
3899 * internal (SW start) or from external IP (timer event,
3900 * external interrupt line).
3901 * @note On this STM32 series, setting trigger source to external trigger
3902 * also set trigger polarity to rising edge
3903 * (default setting for compatibility with some ADC on other
3904 * STM32 families having this setting set by HW default value).
3905 * In case of need to modify trigger edge, use
3906 * function @ref LL_ADC_INJ_SetTriggerEdge().
3907 * @note Caution to ADC group injected contexts queue: On this STM32 series,
3908 * using successively several times this function will appear has
3909 * having no effect.
3910 * This is due to ADC group injected contexts queue (this feature
3911 * cannot be disabled on this STM32 series).
3912 * To set several features of ADC group injected, use
3913 * function @ref LL_ADC_INJ_ConfigQueueContext().
3914 * @note Availability of parameters of trigger sources from timer
3915 * depends on timers availability on the selected device.
3916 * @note On this STM32 series, setting of this feature is conditioned to
3917 * ADC state:
3918 * ADC must not be disabled. Can be enabled with or without conversion
3919 * on going on either groups regular or injected.
3920 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3921 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3922 * @param ADCx ADC instance
3923 * @param TriggerSource This parameter can be one of the following values:
3924 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3925 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3926 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3927 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
3928 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3929 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
3930 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
3931 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
3932 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
3933 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
3934 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
3935 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
3936 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
3937 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
3938 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
3939 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
3940 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
3941 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
3942 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
3943 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
3944 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
3945 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
3946 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
3947 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
3948 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
3949 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
3950 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
3951 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
3952 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
3953 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
3954 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3955 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
3956 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
3957 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
3958 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
3959 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
3960 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
3961 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
3962 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
3963 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
3964 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
3965 *
3966 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
3967 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
3968 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
3969 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
3970 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
3971 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
3972 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
3973 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
3974 * @retval None
3975 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3976 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3977 {
3978 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3979 }
3980
3981 /**
3982 * @brief Get ADC group injected conversion trigger source:
3983 * internal (SW start) or from external IP (timer event,
3984 * external interrupt line).
3985 * @note To determine whether group injected trigger source is
3986 * internal (SW start) or external, without detail
3987 * of which peripheral is selected as external trigger,
3988 * (equivalent to
3989 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3990 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3991 * @note Availability of parameters of trigger sources from timer
3992 * depends on timers availability on the selected device.
3993 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3994 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
3995 * @param ADCx ADC instance
3996 * @retval Returned value can be one of the following values:
3997 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3998 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3999 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4000 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
4001 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4002 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
4003 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
4004 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
4005 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
4006 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
4007 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
4008 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
4009 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
4010 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
4011 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
4012 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
4013 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
4014 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
4015 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
4016 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
4017 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
4018 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
4019 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
4020 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
4021 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
4022 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
4023 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
4024 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
4025 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
4026 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
4027 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4028 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
4029 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
4030 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
4031 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
4032 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
4033 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
4034 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
4035 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
4036 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
4037 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
4038 *
4039 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
4040 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
4041 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
4042 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
4043 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
4044 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
4045 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
4046 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
4047 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)4048 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4049 {
4050 uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4051
4052 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4053 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4054 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
4055
4056 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4057 /* to match with triggers literals definition. */
4058 return ((TriggerSource
4059 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4060 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4061 );
4062 }
4063
4064 /**
4065 * @brief Get ADC group injected conversion trigger source internal (SW start)
4066 or external
4067 * @note In case of group injected trigger source set to external trigger,
4068 * to determine which peripheral is selected as external trigger,
4069 * use function @ref LL_ADC_INJ_GetTriggerSource.
4070 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4071 * @param ADCx ADC instance
4072 * @retval Value "0" if trigger source external trigger
4073 * Value "1" if trigger source SW start.
4074 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)4075 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4076 {
4077 return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
4078 }
4079
4080 /**
4081 * @brief Set ADC group injected conversion trigger polarity.
4082 * Applicable only for trigger source set to external trigger.
4083 * @note On this STM32 series, setting of this feature is conditioned to
4084 * ADC state:
4085 * ADC must not be disabled. Can be enabled with or without conversion
4086 * on going on either groups regular or injected.
4087 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4088 * @param ADCx ADC instance
4089 * @param ExternalTriggerEdge This parameter can be one of the following values:
4090 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4091 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4092 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4093 * @retval None
4094 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4095 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4096 {
4097 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4098 }
4099
4100 /**
4101 * @brief Get ADC group injected conversion trigger polarity.
4102 * Applicable only for trigger source set to external trigger.
4103 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4104 * @param ADCx ADC instance
4105 * @retval Returned value can be one of the following values:
4106 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4107 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4108 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4109 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)4110 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4111 {
4112 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4113 }
4114
4115 /**
4116 * @brief Set ADC group injected sequencer length and scan direction.
4117 * @note This function performs configuration of:
4118 * - Sequence length: Number of ranks in the scan sequence.
4119 * - Sequence direction: Unless specified in parameters, sequencer
4120 * scan direction is forward (from rank 1 to rank n).
4121 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4122 * ADC conversion on only 1 channel.
4123 * @note Caution to ADC group injected contexts queue: On this STM32 series,
4124 * using successively several times this function will appear has
4125 * having no effect.
4126 * This is due to ADC group injected contexts queue (this feature
4127 * cannot be disabled on this STM32 series).
4128 * To set several features of ADC group injected, use
4129 * function @ref LL_ADC_INJ_ConfigQueueContext().
4130 * @note On this STM32 series, setting of this feature is conditioned to
4131 * ADC state:
4132 * ADC must not be disabled. Can be enabled with or without conversion
4133 * on going on either groups regular or injected.
4134 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4135 * @param ADCx ADC instance
4136 * @param SequencerNbRanks This parameter can be one of the following values:
4137 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4138 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4139 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4140 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4141 * @retval None
4142 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4143 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4144 {
4145 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4146 }
4147
4148 /**
4149 * @brief Get ADC group injected sequencer length and scan direction.
4150 * @note This function retrieves:
4151 * - Sequence length: Number of ranks in the scan sequence.
4152 * - Sequence direction: Unless specified in parameters, sequencer
4153 * scan direction is forward (from rank 1 to rank n).
4154 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4155 * ADC conversion on only 1 channel.
4156 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4157 * @param ADCx ADC instance
4158 * @retval Returned value can be one of the following values:
4159 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4160 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4161 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4162 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4163 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)4164 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4165 {
4166 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4167 }
4168
4169 /**
4170 * @brief Set ADC group injected sequencer discontinuous mode:
4171 * sequence subdivided and scan conversions interrupted every selected
4172 * number of ranks.
4173 * @note It is not possible to enable both ADC group injected
4174 * auto-injected mode and sequencer discontinuous mode.
4175 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4176 * @param ADCx ADC instance
4177 * @param SeqDiscont This parameter can be one of the following values:
4178 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4179 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4180 * @retval None
4181 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4182 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4183 {
4184 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4185 }
4186
4187 /**
4188 * @brief Get ADC group injected sequencer discontinuous mode:
4189 * sequence subdivided and scan conversions interrupted every selected
4190 * number of ranks.
4191 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4192 * @param ADCx ADC instance
4193 * @retval Returned value can be one of the following values:
4194 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4195 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4196 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)4197 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4198 {
4199 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4200 }
4201
4202 /**
4203 * @brief Set ADC group injected sequence: channel on the selected
4204 * sequence rank.
4205 * @note Depending on devices and packages, some channels may not be available.
4206 * Refer to device datasheet for channels availability.
4207 * @note On this STM32 series, to measure internal channels (VrefInt,
4208 * TempSensor, ...), measurement paths to internal channels must be
4209 * enabled separately.
4210 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4211 * @note Caution to ADC group injected contexts queue: On this STM32 series,
4212 * using successively several times this function will appear has
4213 * having no effect.
4214 * This is due to ADC group injected contexts queue (this feature
4215 * cannot be disabled on this STM32 series).
4216 * To set several features of ADC group injected, use
4217 * function @ref LL_ADC_INJ_ConfigQueueContext().
4218 * @note On this STM32 series, setting of this feature is conditioned to
4219 * ADC state:
4220 * ADC must not be disabled. Can be enabled with or without conversion
4221 * on going on either groups regular or injected.
4222 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4223 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4224 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4225 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4226 * @param ADCx ADC instance
4227 * @param Rank This parameter can be one of the following values:
4228 * @arg @ref LL_ADC_INJ_RANK_1
4229 * @arg @ref LL_ADC_INJ_RANK_2
4230 * @arg @ref LL_ADC_INJ_RANK_3
4231 * @arg @ref LL_ADC_INJ_RANK_4
4232 * @param Channel This parameter can be one of the following values:
4233 * @arg @ref LL_ADC_CHANNEL_0
4234 * @arg @ref LL_ADC_CHANNEL_1
4235 * @arg @ref LL_ADC_CHANNEL_2
4236 * @arg @ref LL_ADC_CHANNEL_3
4237 * @arg @ref LL_ADC_CHANNEL_4
4238 * @arg @ref LL_ADC_CHANNEL_5
4239 * @arg @ref LL_ADC_CHANNEL_6
4240 * @arg @ref LL_ADC_CHANNEL_7
4241 * @arg @ref LL_ADC_CHANNEL_8
4242 * @arg @ref LL_ADC_CHANNEL_9
4243 * @arg @ref LL_ADC_CHANNEL_10
4244 * @arg @ref LL_ADC_CHANNEL_11
4245 * @arg @ref LL_ADC_CHANNEL_12
4246 * @arg @ref LL_ADC_CHANNEL_13
4247 * @arg @ref LL_ADC_CHANNEL_14
4248 * @arg @ref LL_ADC_CHANNEL_15
4249 * @arg @ref LL_ADC_CHANNEL_16
4250 * @arg @ref LL_ADC_CHANNEL_17
4251 * @arg @ref LL_ADC_CHANNEL_18
4252 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4253 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4254 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4255 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4256 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4257 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4258 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4259 *
4260 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4261 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4262 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4263 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4264 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4265 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4266 * @retval None
4267 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4268 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4269 {
4270 /* Set bits with content of parameter "Channel" with bits position */
4271 /* in register depending on parameter "Rank". */
4272 /* Parameters "Rank" and "Channel" are used with masks because containing */
4273 /* other bits reserved for other purpose. */
4274 MODIFY_REG(ADCx->JSQR,
4275 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4276 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4277 }
4278
4279 /**
4280 * @brief Get ADC group injected sequence: channel on the selected
4281 * sequence rank.
4282 * @note Depending on devices and packages, some channels may not be available.
4283 * Refer to device datasheet for channels availability.
4284 * @note Usage of the returned channel number:
4285 * - To reinject this channel into another function LL_ADC_xxx:
4286 * the returned channel number is only partly formatted on definition
4287 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4288 * with parts of literals LL_ADC_CHANNEL_x or using
4289 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4290 * Then the selected literal LL_ADC_CHANNEL_x can be used
4291 * as parameter for another function.
4292 * - To get the channel number in decimal format:
4293 * process the returned value with the helper macro
4294 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4295 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4296 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4297 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4298 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4299 * @param ADCx ADC instance
4300 * @param Rank This parameter can be one of the following values:
4301 * @arg @ref LL_ADC_INJ_RANK_1
4302 * @arg @ref LL_ADC_INJ_RANK_2
4303 * @arg @ref LL_ADC_INJ_RANK_3
4304 * @arg @ref LL_ADC_INJ_RANK_4
4305 * @retval Returned value can be one of the following values:
4306 * @arg @ref LL_ADC_CHANNEL_0
4307 * @arg @ref LL_ADC_CHANNEL_1
4308 * @arg @ref LL_ADC_CHANNEL_2
4309 * @arg @ref LL_ADC_CHANNEL_3
4310 * @arg @ref LL_ADC_CHANNEL_4
4311 * @arg @ref LL_ADC_CHANNEL_5
4312 * @arg @ref LL_ADC_CHANNEL_6
4313 * @arg @ref LL_ADC_CHANNEL_7
4314 * @arg @ref LL_ADC_CHANNEL_8
4315 * @arg @ref LL_ADC_CHANNEL_9
4316 * @arg @ref LL_ADC_CHANNEL_10
4317 * @arg @ref LL_ADC_CHANNEL_11
4318 * @arg @ref LL_ADC_CHANNEL_12
4319 * @arg @ref LL_ADC_CHANNEL_13
4320 * @arg @ref LL_ADC_CHANNEL_14
4321 * @arg @ref LL_ADC_CHANNEL_15
4322 * @arg @ref LL_ADC_CHANNEL_16
4323 * @arg @ref LL_ADC_CHANNEL_17
4324 * @arg @ref LL_ADC_CHANNEL_18
4325 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4326 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4327 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4328 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4329 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4330 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4331 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4332 *
4333 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4334 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4335 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4336 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4337 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4338 * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
4339 * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
4340 * comparison with internal channel parameter to be done
4341 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4342 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4343 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4344 {
4345 return (uint32_t)((READ_BIT(ADCx->JSQR,
4346 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4347 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4348 );
4349 }
4350
4351 /**
4352 * @brief Set ADC group injected conversion trigger:
4353 * independent or from ADC group regular.
4354 * @note This mode can be used to extend number of data registers
4355 * updated after one ADC conversion trigger and with data
4356 * permanently kept (not erased by successive conversions of scan of
4357 * ADC sequencer ranks), up to 5 data registers:
4358 * 1 data register on ADC group regular, 4 data registers
4359 * on ADC group injected.
4360 * @note If ADC group injected injected trigger source is set to an
4361 * external trigger, this feature must be must be set to
4362 * independent trigger.
4363 * ADC group injected automatic trigger is compliant only with
4364 * group injected trigger source set to SW start, without any
4365 * further action on ADC group injected conversion start or stop:
4366 * in this case, ADC group injected is controlled only
4367 * from ADC group regular.
4368 * @note It is not possible to enable both ADC group injected
4369 * auto-injected mode and sequencer discontinuous mode.
4370 * @note On this STM32 series, setting of this feature is conditioned to
4371 * ADC state:
4372 * ADC must be disabled or enabled without conversion on going
4373 * on either groups regular or injected.
4374 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4375 * @param ADCx ADC instance
4376 * @param TrigAuto This parameter can be one of the following values:
4377 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4378 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4379 * @retval None
4380 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4381 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4382 {
4383 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4384 }
4385
4386 /**
4387 * @brief Get ADC group injected conversion trigger:
4388 * independent or from ADC group regular.
4389 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4390 * @param ADCx ADC instance
4391 * @retval Returned value can be one of the following values:
4392 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4393 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4394 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4395 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4396 {
4397 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4398 }
4399
4400 /**
4401 * @brief Set ADC group injected contexts queue mode.
4402 * @note A context is a setting of group injected sequencer:
4403 * - group injected trigger
4404 * - sequencer length
4405 * - sequencer ranks
4406 * If contexts queue is disabled:
4407 * - only 1 sequence can be configured
4408 * and is active perpetually.
4409 * If contexts queue is enabled:
4410 * - up to 2 contexts can be queued
4411 * and are checked in and out as a FIFO stack (first-in, first-out).
4412 * - If a new context is set when queues is full, error is triggered
4413 * by interruption "Injected Queue Overflow".
4414 * - Two behaviors are possible when all contexts have been processed:
4415 * the contexts queue can maintain the last context active perpetually
4416 * or can be empty and injected group triggers are disabled.
4417 * - Triggers can be only external (not internal SW start)
4418 * - Caution: The sequence must be fully configured in one time
4419 * (one write of register JSQR makes a check-in of a new context
4420 * into the queue).
4421 * Therefore functions to set separately injected trigger and
4422 * sequencer channels cannot be used, register JSQR must be set
4423 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4424 * @note This parameter can be modified only when no conversion is on going
4425 * on either groups regular or injected.
4426 * @note A modification of the context mode (bit JQDIS) causes the contexts
4427 * queue to be flushed and the register JSQR is cleared.
4428 * @note On this STM32 series, setting of this feature is conditioned to
4429 * ADC state:
4430 * ADC must be disabled or enabled without conversion on going
4431 * on either groups regular or injected.
4432 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode
4433 * @param ADCx ADC instance
4434 * @param QueueMode This parameter can be one of the following values:
4435 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4436 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4437 * @retval None
4438 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4439 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4440 {
4441 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM, QueueMode);
4442 }
4443
4444 /**
4445 * @brief Get ADC group injected context queue mode.
4446 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode
4447 * @param ADCx ADC instance
4448 * @retval Returned value can be one of the following values:
4449 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4450 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4451 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4452 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4453 {
4454 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM));
4455 }
4456
4457 /**
4458 * @brief Set one context on ADC group injected that will be checked in
4459 * contexts queue.
4460 * @note A context is a setting of group injected sequencer:
4461 * - group injected trigger
4462 * - sequencer length
4463 * - sequencer ranks
4464 * This function is intended to be used when contexts queue is enabled,
4465 * because the sequence must be fully configured in one time
4466 * (functions to set separately injected trigger and sequencer channels
4467 * cannot be used):
4468 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4469 * @note In the contexts queue, only the active context can be read.
4470 * The parameters of this function can be read using functions:
4471 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4472 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4473 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4474 * @note On this STM32 series, to measure internal channels (VrefInt,
4475 * TempSensor, ...), measurement paths to internal channels must be
4476 * enabled separately.
4477 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4478 * @note On this STM32 series, setting of this feature is conditioned to
4479 * ADC state:
4480 * ADC must not be disabled. Can be enabled with or without conversion
4481 * on going on either groups regular or injected.
4482 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4483 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4484 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4485 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4486 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4487 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4488 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4489 * @param ADCx ADC instance
4490 * @param TriggerSource This parameter can be one of the following values:
4491 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4492 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4493 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4494 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
4495 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4496 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
4497 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
4498 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
4499 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
4500 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
4501 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
4502 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
4503 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
4504 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
4505 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
4506 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
4507 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
4508 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
4509 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
4510 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
4511 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
4512 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
4513 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
4514 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
4515 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
4516 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
4517 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
4518 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
4519 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
4520 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
4521 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4522 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
4523 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
4524 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
4525 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
4526 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
4527 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
4528 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
4529 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
4530 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
4531 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
4532 *
4533 * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
4534 * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
4535 * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
4536 * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
4537 * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
4538 * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
4539 * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
4540 * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
4541 * @param ExternalTriggerEdge This parameter can be one of the following values:
4542 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4543 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4544 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4545 *
4546 * Note: This parameter is discarded in case of SW start:
4547 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4548 * @param SequencerNbRanks This parameter can be one of the following values:
4549 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4550 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4551 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4552 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4553 * @param Rank1_Channel This parameter can be one of the following values:
4554 * @arg @ref LL_ADC_CHANNEL_0
4555 * @arg @ref LL_ADC_CHANNEL_1
4556 * @arg @ref LL_ADC_CHANNEL_2
4557 * @arg @ref LL_ADC_CHANNEL_3
4558 * @arg @ref LL_ADC_CHANNEL_4
4559 * @arg @ref LL_ADC_CHANNEL_5
4560 * @arg @ref LL_ADC_CHANNEL_6
4561 * @arg @ref LL_ADC_CHANNEL_7
4562 * @arg @ref LL_ADC_CHANNEL_8
4563 * @arg @ref LL_ADC_CHANNEL_9
4564 * @arg @ref LL_ADC_CHANNEL_10
4565 * @arg @ref LL_ADC_CHANNEL_11
4566 * @arg @ref LL_ADC_CHANNEL_12
4567 * @arg @ref LL_ADC_CHANNEL_13
4568 * @arg @ref LL_ADC_CHANNEL_14
4569 * @arg @ref LL_ADC_CHANNEL_15
4570 * @arg @ref LL_ADC_CHANNEL_16
4571 * @arg @ref LL_ADC_CHANNEL_17
4572 * @arg @ref LL_ADC_CHANNEL_18
4573 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4574 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4575 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4576 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4577 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4578 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4579 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4580 *
4581 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4582 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4583 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4584 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4585 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4586 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4587 * @param Rank2_Channel This parameter can be one of the following values:
4588 * @arg @ref LL_ADC_CHANNEL_0
4589 * @arg @ref LL_ADC_CHANNEL_1
4590 * @arg @ref LL_ADC_CHANNEL_2
4591 * @arg @ref LL_ADC_CHANNEL_3
4592 * @arg @ref LL_ADC_CHANNEL_4
4593 * @arg @ref LL_ADC_CHANNEL_5
4594 * @arg @ref LL_ADC_CHANNEL_6
4595 * @arg @ref LL_ADC_CHANNEL_7
4596 * @arg @ref LL_ADC_CHANNEL_8
4597 * @arg @ref LL_ADC_CHANNEL_9
4598 * @arg @ref LL_ADC_CHANNEL_10
4599 * @arg @ref LL_ADC_CHANNEL_11
4600 * @arg @ref LL_ADC_CHANNEL_12
4601 * @arg @ref LL_ADC_CHANNEL_13
4602 * @arg @ref LL_ADC_CHANNEL_14
4603 * @arg @ref LL_ADC_CHANNEL_15
4604 * @arg @ref LL_ADC_CHANNEL_16
4605 * @arg @ref LL_ADC_CHANNEL_17
4606 * @arg @ref LL_ADC_CHANNEL_18
4607 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4608 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4609 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4610 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4611 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4612 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4613 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4614 *
4615 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4616 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4617 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4618 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4619 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4620 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4621 * @param Rank3_Channel This parameter can be one of the following values:
4622 * @arg @ref LL_ADC_CHANNEL_0
4623 * @arg @ref LL_ADC_CHANNEL_1
4624 * @arg @ref LL_ADC_CHANNEL_2
4625 * @arg @ref LL_ADC_CHANNEL_3
4626 * @arg @ref LL_ADC_CHANNEL_4
4627 * @arg @ref LL_ADC_CHANNEL_5
4628 * @arg @ref LL_ADC_CHANNEL_6
4629 * @arg @ref LL_ADC_CHANNEL_7
4630 * @arg @ref LL_ADC_CHANNEL_8
4631 * @arg @ref LL_ADC_CHANNEL_9
4632 * @arg @ref LL_ADC_CHANNEL_10
4633 * @arg @ref LL_ADC_CHANNEL_11
4634 * @arg @ref LL_ADC_CHANNEL_12
4635 * @arg @ref LL_ADC_CHANNEL_13
4636 * @arg @ref LL_ADC_CHANNEL_14
4637 * @arg @ref LL_ADC_CHANNEL_15
4638 * @arg @ref LL_ADC_CHANNEL_16
4639 * @arg @ref LL_ADC_CHANNEL_17
4640 * @arg @ref LL_ADC_CHANNEL_18
4641 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4642 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4643 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4644 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4645 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4646 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4647 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4648 *
4649 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4650 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4651 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4652 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4653 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4654 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4655 * @param Rank4_Channel This parameter can be one of the following values:
4656 * @arg @ref LL_ADC_CHANNEL_0
4657 * @arg @ref LL_ADC_CHANNEL_1
4658 * @arg @ref LL_ADC_CHANNEL_2
4659 * @arg @ref LL_ADC_CHANNEL_3
4660 * @arg @ref LL_ADC_CHANNEL_4
4661 * @arg @ref LL_ADC_CHANNEL_5
4662 * @arg @ref LL_ADC_CHANNEL_6
4663 * @arg @ref LL_ADC_CHANNEL_7
4664 * @arg @ref LL_ADC_CHANNEL_8
4665 * @arg @ref LL_ADC_CHANNEL_9
4666 * @arg @ref LL_ADC_CHANNEL_10
4667 * @arg @ref LL_ADC_CHANNEL_11
4668 * @arg @ref LL_ADC_CHANNEL_12
4669 * @arg @ref LL_ADC_CHANNEL_13
4670 * @arg @ref LL_ADC_CHANNEL_14
4671 * @arg @ref LL_ADC_CHANNEL_15
4672 * @arg @ref LL_ADC_CHANNEL_16
4673 * @arg @ref LL_ADC_CHANNEL_17
4674 * @arg @ref LL_ADC_CHANNEL_18
4675 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4676 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4677 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4678 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4679 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4680 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4681 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4682 *
4683 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4684 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4685 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4686 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4687 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4688 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4689 * @retval None
4690 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)4691 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4692 uint32_t TriggerSource,
4693 uint32_t ExternalTriggerEdge,
4694 uint32_t SequencerNbRanks,
4695 uint32_t Rank1_Channel,
4696 uint32_t Rank2_Channel,
4697 uint32_t Rank3_Channel,
4698 uint32_t Rank4_Channel)
4699 {
4700 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4701 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4702 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4703 /* because containing other bits reserved for other purpose. */
4704 /* If parameter "TriggerSource" is set to SW start, then parameter */
4705 /* "ExternalTriggerEdge" is discarded. */
4706 MODIFY_REG(ADCx->JSQR ,
4707 ADC_JSQR_JEXTSEL |
4708 ADC_JSQR_JEXTEN |
4709 ADC_JSQR_JSQ4 |
4710 ADC_JSQR_JSQ3 |
4711 ADC_JSQR_JSQ2 |
4712 ADC_JSQR_JSQ1 |
4713 ADC_JSQR_JL ,
4714 TriggerSource |
4715 (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
4716 ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4717 ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4718 ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4719 ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
4720 SequencerNbRanks
4721 );
4722 }
4723
4724 /**
4725 * @}
4726 */
4727
4728 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4729 * @{
4730 */
4731
4732 /**
4733 * @brief Set sampling time of the selected ADC channel
4734 * Unit: ADC clock cycles.
4735 * @note On this device, sampling time is on channel scope: independently
4736 * of channel mapped on ADC group regular or injected.
4737 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4738 * converted:
4739 * sampling time constraints must be respected (sampling time can be
4740 * adjusted in function of ADC clock frequency and sampling time
4741 * setting).
4742 * Refer to device datasheet for timings values (parameters TS_vrefint,
4743 * TS_temp, ...).
4744 * @note Conversion time is the addition of sampling time and processing time.
4745 * On this STM32 series, ADC processing time is:
4746 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4747 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4748 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4749 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4750 * @note In case of ADC conversion of internal channel (VrefInt,
4751 * temperature sensor, ...), a sampling time minimum value
4752 * is required.
4753 * Refer to device datasheet.
4754 * @note On this STM32 series, setting of this feature is conditioned to
4755 * ADC state:
4756 * ADC must be disabled or enabled without conversion on going
4757 * on either groups regular or injected.
4758 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4759 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4760 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4761 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4762 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4763 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4764 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4765 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4766 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4767 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4768 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4769 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4770 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4771 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4772 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4773 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4774 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4775 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4776 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4777 * @param ADCx ADC instance
4778 * @param Channel This parameter can be one of the following values:
4779 * @arg @ref LL_ADC_CHANNEL_0
4780 * @arg @ref LL_ADC_CHANNEL_1
4781 * @arg @ref LL_ADC_CHANNEL_2
4782 * @arg @ref LL_ADC_CHANNEL_3
4783 * @arg @ref LL_ADC_CHANNEL_4
4784 * @arg @ref LL_ADC_CHANNEL_5
4785 * @arg @ref LL_ADC_CHANNEL_6
4786 * @arg @ref LL_ADC_CHANNEL_7
4787 * @arg @ref LL_ADC_CHANNEL_8
4788 * @arg @ref LL_ADC_CHANNEL_9
4789 * @arg @ref LL_ADC_CHANNEL_10
4790 * @arg @ref LL_ADC_CHANNEL_11
4791 * @arg @ref LL_ADC_CHANNEL_12
4792 * @arg @ref LL_ADC_CHANNEL_13
4793 * @arg @ref LL_ADC_CHANNEL_14
4794 * @arg @ref LL_ADC_CHANNEL_15
4795 * @arg @ref LL_ADC_CHANNEL_16
4796 * @arg @ref LL_ADC_CHANNEL_17
4797 * @arg @ref LL_ADC_CHANNEL_18
4798 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4799 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4800 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4801 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4802 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4803 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4804 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4805 *
4806 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4807 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4808 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4809 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4810 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4811 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4812 * @param SamplingTime This parameter can be one of the following values:
4813 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4814 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4815 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
4816 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
4817 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
4818 * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
4819 * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
4820 * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
4821 * @retval None
4822 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4823 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4824 {
4825 /* Set bits with content of parameter "SamplingTime" with bits position */
4826 /* in register and register position depending on parameter "Channel". */
4827 /* Parameter "Channel" is used with masks because containing */
4828 /* other bits reserved for other purpose. */
4829 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
4830
4831 MODIFY_REG(*preg,
4832 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
4833 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
4834 }
4835
4836 /**
4837 * @brief Get sampling time of the selected ADC channel
4838 * Unit: ADC clock cycles.
4839 * @note On this device, sampling time is on channel scope: independently
4840 * of channel mapped on ADC group regular or injected.
4841 * @note Conversion time is the addition of sampling time and processing time.
4842 * On this STM32 series, ADC processing time is:
4843 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4844 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4845 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4846 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4847 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4848 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4849 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4850 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4851 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4852 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4853 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4854 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4855 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4856 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4857 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4858 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4859 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4860 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4861 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4862 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4863 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4864 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4865 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4866 * @param ADCx ADC instance
4867 * @param Channel This parameter can be one of the following values:
4868 * @arg @ref LL_ADC_CHANNEL_0
4869 * @arg @ref LL_ADC_CHANNEL_1
4870 * @arg @ref LL_ADC_CHANNEL_2
4871 * @arg @ref LL_ADC_CHANNEL_3
4872 * @arg @ref LL_ADC_CHANNEL_4
4873 * @arg @ref LL_ADC_CHANNEL_5
4874 * @arg @ref LL_ADC_CHANNEL_6
4875 * @arg @ref LL_ADC_CHANNEL_7
4876 * @arg @ref LL_ADC_CHANNEL_8
4877 * @arg @ref LL_ADC_CHANNEL_9
4878 * @arg @ref LL_ADC_CHANNEL_10
4879 * @arg @ref LL_ADC_CHANNEL_11
4880 * @arg @ref LL_ADC_CHANNEL_12
4881 * @arg @ref LL_ADC_CHANNEL_13
4882 * @arg @ref LL_ADC_CHANNEL_14
4883 * @arg @ref LL_ADC_CHANNEL_15
4884 * @arg @ref LL_ADC_CHANNEL_16
4885 * @arg @ref LL_ADC_CHANNEL_17
4886 * @arg @ref LL_ADC_CHANNEL_18
4887 * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
4888 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4889 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4890 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4891 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4892 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
4893 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
4894 *
4895 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
4896 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
4897 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
4898 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
4899 * (5) On STM32F3, ADC channel available only on all ADC instances, but
4900 * only one ADC instance is allowed to be connected to VrefInt at the same time.
4901 * @retval Returned value can be one of the following values:
4902 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4903 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4904 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
4905 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
4906 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
4907 * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
4908 * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
4909 * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
4910 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)4911 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4912 {
4913 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
4914
4915 return (uint32_t)(READ_BIT(*preg,
4916 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
4917 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
4918 );
4919 }
4920
4921 /**
4922 * @brief Set mode single-ended or differential input of the selected
4923 * ADC channel.
4924 * @note Channel ending is on channel scope: independently of channel mapped
4925 * on ADC group regular or injected.
4926 * In differential mode: Differential measurement is carried out
4927 * between the selected channel 'i' (positive input) and
4928 * channel 'i+1' (negative input). Only channel 'i' has to be
4929 * configured, channel 'i+1' is configured automatically.
4930 * @note Refer to Reference Manual to ensure the selected channel is
4931 * available in differential mode.
4932 * For example, internal channels (VrefInt, TempSensor, ...) are
4933 * not available in differential mode.
4934 * @note When configuring a channel 'i' in differential mode,
4935 * the channel 'i+1' is not usable separately.
4936 * @note On STM32F3, channels 16, 17, 18 of ADC1,
4937 * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
4938 * are internally fixed to single-ended inputs configuration.
4939 * @note For ADC channels configured in differential mode, both inputs
4940 * should be biased at (Vref+)/2 +/-200mV.
4941 * (Vref+ is the analog voltage reference)
4942 * @note On this STM32 series, setting of this feature is conditioned to
4943 * ADC state:
4944 * ADC must be ADC disabled.
4945 * @note One or several values can be selected.
4946 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4947 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
4948 * @param ADCx ADC instance
4949 * @param Channel This parameter can be one of the following values:
4950 * @arg @ref LL_ADC_CHANNEL_1
4951 * @arg @ref LL_ADC_CHANNEL_2
4952 * @arg @ref LL_ADC_CHANNEL_3
4953 * @arg @ref LL_ADC_CHANNEL_4
4954 * @arg @ref LL_ADC_CHANNEL_5
4955 * @arg @ref LL_ADC_CHANNEL_6
4956 * @arg @ref LL_ADC_CHANNEL_7
4957 * @arg @ref LL_ADC_CHANNEL_8
4958 * @arg @ref LL_ADC_CHANNEL_9
4959 * @arg @ref LL_ADC_CHANNEL_10
4960 * @arg @ref LL_ADC_CHANNEL_11
4961 * @arg @ref LL_ADC_CHANNEL_12
4962 * @arg @ref LL_ADC_CHANNEL_13
4963 * @arg @ref LL_ADC_CHANNEL_14
4964 * @arg @ref LL_ADC_CHANNEL_15
4965 * @arg @ref LL_ADC_CHANNEL_16 (1)
4966 *
4967 * (1) On STM32F3, parameter available only on ADC instance: ADC1.
4968 * @param SingleDiff This parameter can be a combination of the following values:
4969 * @arg @ref LL_ADC_SINGLE_ENDED
4970 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4971 * @retval None
4972 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)4973 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4974 {
4975 /* Bits of channels in single or differential mode are set only for */
4976 /* differential mode (for single mode, mask of bits allowed to be set is */
4977 /* shifted out of range of bits of channels in single or differential mode. */
4978 MODIFY_REG(ADCx->DIFSEL,
4979 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4980 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4981 }
4982
4983 /**
4984 * @brief Get mode single-ended or differential input of the selected
4985 * ADC channel.
4986 * @note When configuring a channel 'i' in differential mode,
4987 * the channel 'i+1' is not usable separately.
4988 * Therefore, to ensure a channel is configured in single-ended mode,
4989 * the configuration of channel itself and the channel 'i-1' must be
4990 * read back (to ensure that the selected channel channel has not been
4991 * configured in differential mode by the previous channel).
4992 * @note Refer to Reference Manual to ensure the selected channel is
4993 * available in differential mode.
4994 * For example, internal channels (VrefInt, TempSensor, ...) are
4995 * not available in differential mode.
4996 * @note When configuring a channel 'i' in differential mode,
4997 * the channel 'i+1' is not usable separately.
4998 * @note On STM32F3, channels 16, 17, 18 of ADC1,
4999 * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
5000 * are internally fixed to single-ended inputs configuration.
5001 * @note One or several values can be selected. In this case, the value
5002 * returned is null if all channels are in single ended-mode.
5003 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5004 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
5005 * @param ADCx ADC instance
5006 * @param Channel This parameter can be a combination of the following values:
5007 * @arg @ref LL_ADC_CHANNEL_0
5008 * @arg @ref LL_ADC_CHANNEL_1
5009 * @arg @ref LL_ADC_CHANNEL_2
5010 * @arg @ref LL_ADC_CHANNEL_3
5011 * @arg @ref LL_ADC_CHANNEL_4
5012 * @arg @ref LL_ADC_CHANNEL_5
5013 * @arg @ref LL_ADC_CHANNEL_6
5014 * @arg @ref LL_ADC_CHANNEL_7
5015 * @arg @ref LL_ADC_CHANNEL_8
5016 * @arg @ref LL_ADC_CHANNEL_9
5017 * @arg @ref LL_ADC_CHANNEL_10
5018 * @arg @ref LL_ADC_CHANNEL_11
5019 * @arg @ref LL_ADC_CHANNEL_12
5020 * @arg @ref LL_ADC_CHANNEL_13
5021 * @arg @ref LL_ADC_CHANNEL_14
5022 * @arg @ref LL_ADC_CHANNEL_15
5023 * @arg @ref LL_ADC_CHANNEL_16 (1)
5024 *
5025 * (1) On STM32F3, parameter available only on ADC instance: ADC1.
5026 * @retval 0: channel in single-ended mode, else: channel in differential mode
5027 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)5028 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5029 {
5030 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5031 }
5032
5033 /**
5034 * @}
5035 */
5036
5037 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5038 * @{
5039 */
5040
5041 /**
5042 * @brief Set ADC analog watchdog monitored channels:
5043 * a single channel, multiple channels or all channels,
5044 * on ADC groups regular and-or injected.
5045 * @note Once monitored channels are selected, analog watchdog
5046 * is enabled.
5047 * @note In case of need to define a single channel to monitor
5048 * with analog watchdog from sequencer channel definition,
5049 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5050 * @note On this STM32 series, there are 2 kinds of analog watchdog
5051 * instance:
5052 * - AWD standard (instance AWD1):
5053 * - channels monitored: can monitor 1 channel or all channels.
5054 * - groups monitored: ADC groups regular and-or injected.
5055 * - resolution: resolution is not limited (corresponds to
5056 * ADC resolution configured).
5057 * - AWD flexible (instances AWD2, AWD3):
5058 * - channels monitored: flexible on channels monitored, selection is
5059 * channel wise, from from 1 to all channels.
5060 * Specificity of this analog watchdog: Multiple channels can
5061 * be selected. For example:
5062 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5063 * - groups monitored: not selection possible (monitoring on both
5064 * groups regular and injected).
5065 * Channels selected are monitored on groups regular and injected:
5066 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5067 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5068 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5069 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5070 * the 2 LSB are ignored.
5071 * @note On this STM32 series, setting of this feature is conditioned to
5072 * ADC state:
5073 * ADC must be disabled or enabled without conversion on going
5074 * on either groups regular or injected.
5075 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5076 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5077 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5078 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5079 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5080 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5081 * @param ADCx ADC instance
5082 * @param AWDy This parameter can be one of the following values:
5083 * @arg @ref LL_ADC_AWD1
5084 * @arg @ref LL_ADC_AWD2
5085 * @arg @ref LL_ADC_AWD3
5086 * @param AWDChannelGroup This parameter can be one of the following values:
5087 * @arg @ref LL_ADC_AWD_DISABLE
5088 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5089 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5090 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5091 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5092 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5093 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5094 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5095 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5096 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5097 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5098 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5099 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5100 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5101 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5102 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5103 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5104 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5105 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5106 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5107 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5108 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5109 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5110 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5111 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5112 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5113 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5114 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5115 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5116 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5117 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5118 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5119 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5120 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5121 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5122 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5123 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5124 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5125 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5126 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5127 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5128 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5129 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5130 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5131 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5132 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5133 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5134 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5135 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5136 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5137 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5138 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5139 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5140 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5141 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5142 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5143 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5144 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5145 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5146 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5147 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5148 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
5149 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
5150 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
5151 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5152 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5153 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5154 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5155 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5156 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5157 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
5158 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
5159 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
5160 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
5161 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
5162 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
5163 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
5164 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
5165 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
5166 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
5167 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
5168 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
5169 *
5170 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
5171 * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
5172 * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
5173 * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
5174 * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
5175 * (5) On STM32F3, ADC channel available only on all ADC instances, but
5176 * only one ADC instance is allowed to be connected to VrefInt at the same time.
5177 * @retval None
5178 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5179 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5180 {
5181 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5182 /* in register and register position depending on parameter "AWDy". */
5183 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5184 /* containing other bits reserved for other purpose. */
5185 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
5186 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5187
5188 MODIFY_REG(*preg,
5189 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5190 AWDChannelGroup & AWDy);
5191 }
5192
5193 /**
5194 * @brief Get ADC analog watchdog monitored channel.
5195 * @note Usage of the returned channel number:
5196 * - To reinject this channel into another function LL_ADC_xxx:
5197 * the returned channel number is only partly formatted on definition
5198 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5199 * with parts of literals LL_ADC_CHANNEL_x or using
5200 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5201 * Then the selected literal LL_ADC_CHANNEL_x can be used
5202 * as parameter for another function.
5203 * - To get the channel number in decimal format:
5204 * process the returned value with the helper macro
5205 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5206 * Applicable only when the analog watchdog is set to monitor
5207 * one channel.
5208 * @note On this STM32 series, there are 2 kinds of analog watchdog
5209 * instance:
5210 * - AWD standard (instance AWD1):
5211 * - channels monitored: can monitor 1 channel or all channels.
5212 * - groups monitored: ADC groups regular and-or injected.
5213 * - resolution: resolution is not limited (corresponds to
5214 * ADC resolution configured).
5215 * - AWD flexible (instances AWD2, AWD3):
5216 * - channels monitored: flexible on channels monitored, selection is
5217 * channel wise, from from 1 to all channels.
5218 * Specificity of this analog watchdog: Multiple channels can
5219 * be selected. For example:
5220 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5221 * - groups monitored: not selection possible (monitoring on both
5222 * groups regular and injected).
5223 * Channels selected are monitored on groups regular and injected:
5224 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5225 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5226 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5227 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5228 * the 2 LSB are ignored.
5229 * @note On this STM32 series, setting of this feature is conditioned to
5230 * ADC state:
5231 * ADC must be disabled or enabled without conversion on going
5232 * on either groups regular or injected.
5233 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5234 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5235 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5236 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5237 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5238 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5239 * @param ADCx ADC instance
5240 * @param AWDy This parameter can be one of the following values:
5241 * @arg @ref LL_ADC_AWD1
5242 * @arg @ref LL_ADC_AWD2 (1)
5243 * @arg @ref LL_ADC_AWD3 (1)
5244 *
5245 * (1) On this AWD number, monitored channel can be retrieved
5246 * if only 1 channel is programmed (or none or all channels).
5247 * This function cannot retrieve monitored channel if
5248 * multiple channels are programmed simultaneously
5249 * by bitfield.
5250 * @retval Returned value can be one of the following values:
5251 * @arg @ref LL_ADC_AWD_DISABLE
5252 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5253 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5254 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5255 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5256 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5257 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5258 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5259 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5260 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5261 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5262 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5263 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5264 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5265 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5266 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5267 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5268 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5269 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5270 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5271 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5272 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5273 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5274 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5275 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5276 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5277 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5278 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5279 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5280 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5281 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5282 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5283 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5284 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5285 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5286 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5287 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5288 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5289 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5290 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5291 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5292 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5293 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5294 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5295 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5296 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5297 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5298 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5299 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5300 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5301 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5302 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5303 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5304 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5305 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5306 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5307 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5308 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5309 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5310 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5311 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5312 *
5313 * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.
5314 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)5315 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5316 {
5317 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
5318 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5319
5320 /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
5321 /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
5322 uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
5323
5324 /* Set variable of AWD1 monitored channel according to AWD1 features */
5325 /* and ADC channel definition: */
5326 /* - channel ID with number */
5327 /* - channel ID with bitfield */
5328 /* - AWD1 single or all channels */
5329 /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
5330 /* AWD2 or AWD3 selected). */
5331 uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
5332
5333 uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
5334 | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
5335 | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
5336 )
5337 * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
5338 );
5339
5340 /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */
5341 /* features and ADC channel definition: */
5342 /* - channel ID with number */
5343 /* - channel ID with bitfield */
5344 /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */
5345 /* shift AWD1 equivalent single-all channels out of register) */
5346 /* - AWD2-3 enable or disable */
5347 /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */
5348 /* channel can be read back if only 1 channel monitoring */
5349 /* is activated, therefore the channel monitoring value channel "3" */
5350 /* is not not supported by this function, there is no risk of */
5351 /* conflict. */
5352 uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
5353
5354 uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
5355 | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5356 | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
5357 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
5358 ) >> AWD23Enabled
5359 ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
5360
5361 return (AWD1ChannelGroup | AWD23ChannelGroup);
5362 }
5363
5364 /**
5365 * @brief Set ADC analog watchdog thresholds value of both thresholds
5366 * high and low.
5367 * @note If value of only one threshold high or low must be set,
5368 * use function @ref LL_ADC_SetAnalogWDThresholds().
5369 * @note In case of ADC resolution different of 12 bits,
5370 * analog watchdog thresholds data require a specific shift.
5371 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5372 * @note On this STM32 series, there are 2 kinds of analog watchdog
5373 * instance:
5374 * - AWD standard (instance AWD1):
5375 * - channels monitored: can monitor 1 channel or all channels.
5376 * - groups monitored: ADC groups regular and-or injected.
5377 * - resolution: resolution is not limited (corresponds to
5378 * ADC resolution configured).
5379 * - AWD flexible (instances AWD2, AWD3):
5380 * - channels monitored: flexible on channels monitored, selection is
5381 * channel wise, from from 1 to all channels.
5382 * Specificity of this analog watchdog: Multiple channels can
5383 * be selected. For example:
5384 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5385 * - groups monitored: not selection possible (monitoring on both
5386 * groups regular and injected).
5387 * Channels selected are monitored on groups regular and injected:
5388 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5389 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5390 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5391 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5392 * the 2 LSB are ignored.
5393 * @note On this STM32 series, setting of this feature is conditioned to
5394 * ADC state:
5395 * ADC must be disabled or enabled without conversion on going
5396 * on either groups regular or injected.
5397 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5398 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5399 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5400 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5401 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5402 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5403 * @param ADCx ADC instance
5404 * @param AWDy This parameter can be one of the following values:
5405 * @arg @ref LL_ADC_AWD1
5406 * @arg @ref LL_ADC_AWD2
5407 * @arg @ref LL_ADC_AWD3
5408 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5409 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5410 * @retval None
5411 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5412 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
5413 {
5414 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5415 /* position in register and register position depending on parameter */
5416 /* "AWDy". */
5417 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5418 /* containing other bits reserved for other purpose. */
5419 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5420
5421 MODIFY_REG(*preg,
5422 ADC_TR1_HT1 | ADC_TR1_LT1,
5423 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5424 }
5425
5426 /**
5427 * @brief Set ADC analog watchdog threshold value of threshold
5428 * high or low.
5429 * @note If values of both thresholds high or low must be set,
5430 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5431 * @note In case of ADC resolution different of 12 bits,
5432 * analog watchdog thresholds data require a specific shift.
5433 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5434 * @note On this STM32 series, there are 2 kinds of analog watchdog
5435 * instance:
5436 * - AWD standard (instance AWD1):
5437 * - channels monitored: can monitor 1 channel or all channels.
5438 * - groups monitored: ADC groups regular and-or injected.
5439 * - resolution: resolution is not limited (corresponds to
5440 * ADC resolution configured).
5441 * - AWD flexible (instances AWD2, AWD3):
5442 * - channels monitored: flexible on channels monitored, selection is
5443 * channel wise, from from 1 to all channels.
5444 * Specificity of this analog watchdog: Multiple channels can
5445 * be selected. For example:
5446 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5447 * - groups monitored: not selection possible (monitoring on both
5448 * groups regular and injected).
5449 * Channels selected are monitored on groups regular and injected:
5450 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5451 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5452 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5453 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5454 * the 2 LSB are ignored.
5455 * @note On this STM32 series, setting of this feature is conditioned to
5456 * ADC state:
5457 * ADC must be disabled or enabled without conversion on going
5458 * on either groups regular or injected.
5459 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5460 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5461 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5462 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5463 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5464 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5465 * @param ADCx ADC instance
5466 * @param AWDy This parameter can be one of the following values:
5467 * @arg @ref LL_ADC_AWD1
5468 * @arg @ref LL_ADC_AWD2
5469 * @arg @ref LL_ADC_AWD3
5470 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5471 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5472 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5473 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5474 * @retval None
5475 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5476 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
5477 {
5478 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5479 /* position in register and register position depending on parameters */
5480 /* "AWDThresholdsHighLow" and "AWDy". */
5481 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5482 /* containing other bits reserved for other purpose. */
5483 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5484
5485 MODIFY_REG(*preg,
5486 AWDThresholdsHighLow,
5487 AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
5488 }
5489
5490 /**
5491 * @brief Get ADC analog watchdog threshold value of threshold high,
5492 * threshold low or raw data with ADC thresholds high and low
5493 * concatenated.
5494 * @note If raw data with ADC thresholds high and low is retrieved,
5495 * the data of each threshold high or low can be isolated
5496 * using helper macro:
5497 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5498 * @note In case of ADC resolution different of 12 bits,
5499 * analog watchdog thresholds data require a specific shift.
5500 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5501 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5502 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5503 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5504 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5505 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5506 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5507 * @param ADCx ADC instance
5508 * @param AWDy This parameter can be one of the following values:
5509 * @arg @ref LL_ADC_AWD1
5510 * @arg @ref LL_ADC_AWD2
5511 * @arg @ref LL_ADC_AWD3
5512 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5513 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5514 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5515 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5516 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5517 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5518 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5519 {
5520 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
5521
5522 return (uint32_t)(READ_BIT(*preg,
5523 (AWDThresholdsHighLow | ADC_TR1_LT1))
5524 >> POSITION_VAL(AWDThresholdsHighLow)
5525 );
5526 }
5527
5528 /**
5529 * @}
5530 */
5531
5532 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5533 * @{
5534 */
5535
5536 #if defined(ADC_MULTIMODE_SUPPORT)
5537 /**
5538 * @brief Set ADC multimode configuration to operate in independent mode
5539 * or multimode (for devices with several ADC instances).
5540 * @note If multimode configuration: the selected ADC instance is
5541 * either master or slave depending on hardware.
5542 * Refer to reference manual.
5543 * @note On this STM32 series, setting of this feature is conditioned to
5544 * ADC state:
5545 * All ADC instances of the ADC common group must be disabled.
5546 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5547 * ADC instance or by using helper macro
5548 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5549 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5550 * @param ADCxy_COMMON ADC common instance
5551 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5552 * @param Multimode This parameter can be one of the following values:
5553 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5554 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5555 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5556 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5557 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5558 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5559 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5560 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5561 * @retval None
5562 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5563 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5564 {
5565 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5566 }
5567
5568 /**
5569 * @brief Get ADC multimode configuration to operate in independent mode
5570 * or multimode (for devices with several ADC instances).
5571 * @note If multimode configuration: the selected ADC instance is
5572 * either master or slave depending on hardware.
5573 * Refer to reference manual.
5574 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5575 * @param ADCxy_COMMON ADC common instance
5576 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5577 * @retval Returned value can be one of the following values:
5578 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5579 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5580 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5581 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5582 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5583 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5584 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5585 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5586 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)5587 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5588 {
5589 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5590 }
5591
5592 /**
5593 * @brief Set ADC multimode conversion data transfer: no transfer
5594 * or transfer by DMA.
5595 * @note If ADC multimode transfer by DMA is not selected:
5596 * each ADC uses its own DMA channel, with its individual
5597 * DMA transfer settings.
5598 * If ADC multimode transfer by DMA is selected:
5599 * One DMA channel is used for both ADC (DMA of ADC master)
5600 * Specifies the DMA requests mode:
5601 * - Limited mode (One shot mode): DMA transfer requests are stopped
5602 * when number of DMA data transfers (number of
5603 * ADC conversions) is reached.
5604 * This ADC mode is intended to be used with DMA mode non-circular.
5605 * - Unlimited mode: DMA transfer requests are unlimited,
5606 * whatever number of DMA data transfers (number of
5607 * ADC conversions).
5608 * This ADC mode is intended to be used with DMA mode circular.
5609 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5610 * mode non-circular:
5611 * when DMA transfers size will be reached, DMA will stop transfers of
5612 * ADC conversions data ADC will raise an overrun error
5613 * (overrun flag and interruption if enabled).
5614 * @note How to retrieve multimode conversion data:
5615 * Whatever multimode transfer by DMA setting: using function
5616 * @ref LL_ADC_REG_ReadMultiConversionData32().
5617 * If ADC multimode transfer by DMA is selected: conversion data
5618 * is a raw data with ADC master and slave concatenated.
5619 * A macro is available to get the conversion data of
5620 * ADC master or ADC slave: see helper macro
5621 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5622 * @note On this STM32 series, setting of this feature is conditioned to
5623 * ADC state:
5624 * All ADC instances of the ADC common group must be disabled
5625 * or enabled without conversion on going on group regular.
5626 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
5627 * CCR DMACFG LL_ADC_SetMultiDMATransfer
5628 * @param ADCxy_COMMON ADC common instance
5629 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5630 * @param MultiDMATransfer This parameter can be one of the following values:
5631 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5632 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5633 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5634 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5635 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5636 * @retval None
5637 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)5638 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5639 {
5640 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
5641 }
5642
5643 /**
5644 * @brief Get ADC multimode conversion data transfer: no transfer
5645 * or transfer by DMA.
5646 * @note If ADC multimode transfer by DMA is not selected:
5647 * each ADC uses its own DMA channel, with its individual
5648 * DMA transfer settings.
5649 * If ADC multimode transfer by DMA is selected:
5650 * One DMA channel is used for both ADC (DMA of ADC master)
5651 * Specifies the DMA requests mode:
5652 * - Limited mode (One shot mode): DMA transfer requests are stopped
5653 * when number of DMA data transfers (number of
5654 * ADC conversions) is reached.
5655 * This ADC mode is intended to be used with DMA mode non-circular.
5656 * - Unlimited mode: DMA transfer requests are unlimited,
5657 * whatever number of DMA data transfers (number of
5658 * ADC conversions).
5659 * This ADC mode is intended to be used with DMA mode circular.
5660 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5661 * mode non-circular:
5662 * when DMA transfers size will be reached, DMA will stop transfers of
5663 * ADC conversions data ADC will raise an overrun error
5664 * (overrun flag and interruption if enabled).
5665 * @note How to retrieve multimode conversion data:
5666 * Whatever multimode transfer by DMA setting: using function
5667 * @ref LL_ADC_REG_ReadMultiConversionData32().
5668 * If ADC multimode transfer by DMA is selected: conversion data
5669 * is a raw data with ADC master and slave concatenated.
5670 * A macro is available to get the conversion data of
5671 * ADC master or ADC slave: see helper macro
5672 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5673 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
5674 * CCR DMACFG LL_ADC_GetMultiDMATransfer
5675 * @param ADCxy_COMMON ADC common instance
5676 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5677 * @retval Returned value can be one of the following values:
5678 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5679 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5680 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5681 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5682 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5683 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)5684 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5685 {
5686 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
5687 }
5688
5689 /**
5690 * @brief Set ADC multimode delay between 2 sampling phases.
5691 * @note The sampling delay range depends on ADC resolution:
5692 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5693 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5694 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5695 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5696 * @note On this STM32 series, setting of this feature is conditioned to
5697 * ADC state:
5698 * All ADC instances of the ADC common group must be disabled.
5699 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5700 * ADC instance or by using helper macro helper macro
5701 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5702 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5703 * @param ADCxy_COMMON ADC common instance
5704 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5705 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5706 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5707 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5708 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5709 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5710 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5711 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5712 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5718 *
5719 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5720 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5721 * (3) Parameter available only if ADC resolution is 12 bits.
5722 * @retval None
5723 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)5724 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5725 {
5726 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5727 }
5728
5729 /**
5730 * @brief Get ADC multimode delay between 2 sampling phases.
5731 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5732 * @param ADCxy_COMMON ADC common instance
5733 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5734 * @retval Returned value can be one of the following values:
5735 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5736 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5737 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5738 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5739 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5740 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5741 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5747 *
5748 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5749 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5750 * (3) Parameter available only if ADC resolution is 12 bits.
5751 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)5752 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5753 {
5754 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5755 }
5756 #endif /* ADC_MULTIMODE_SUPPORT */
5757
5758 /**
5759 * @}
5760 */
5761 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5762 * @{
5763 */
5764
5765 /**
5766 * @brief Enable ADC instance internal voltage regulator.
5767 * @note On this STM32 series, after ADC internal voltage regulator enable,
5768 * a delay for ADC internal voltage regulator stabilization
5769 * is required before performing a ADC calibration or ADC enable.
5770 * Refer to device datasheet, parameter tADCVREG_STUP.
5771 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5772 * @note On this STM32 series, setting of this feature is conditioned to
5773 * ADC state:
5774 * ADC must be ADC disabled.
5775 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5776 * @param ADCx ADC instance
5777 * @retval None
5778 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)5779 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5780 {
5781 /* 1. Set the intermediate state before moving the ADC voltage regulator */
5782 /* to state enable. */
5783 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
5784 /* 2. Set the final state of ADC voltage regulator enable */
5785 /* (ADVREGEN bits set to 0x01). */
5786 /* Note: Write register with some additional bits forced to state reset */
5787 /* instead of modifying only the selected bit for this function, */
5788 /* to not interfere with bits with HW property "rs". */
5789 MODIFY_REG(ADCx->CR,
5790 ADC_CR_BITS_PROPERTY_RS,
5791 ADC_CR_ADVREGEN_0);
5792 }
5793
5794 /**
5795 * @brief Disable ADC internal voltage regulator.
5796 * @note On this STM32 series, setting of this feature is conditioned to
5797 * ADC state:
5798 * ADC must be ADC disabled.
5799 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5800 * @param ADCx ADC instance
5801 * @retval None
5802 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)5803 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5804 {
5805 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5806 }
5807
5808 /**
5809 * @brief Get the selected ADC instance internal voltage regulator state.
5810 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5811 * @param ADCx ADC instance
5812 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5813 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)5814 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5815 {
5816 return (READ_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)) == (ADC_CR_ADVREGEN_0));
5817 }
5818
5819 /**
5820 * @brief Enable the selected ADC instance.
5821 * @note On this STM32 series, after ADC enable, a delay for
5822 * ADC internal analog stabilization is required before performing a
5823 * ADC conversion start.
5824 * Refer to device datasheet, parameter tSTAB.
5825 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5826 * is enabled and when conversion clock is active.
5827 * (not only core clock: this ADC has a dual clock domain)
5828 * @note On this STM32 series, setting of this feature is conditioned to
5829 * ADC state:
5830 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
5831 * @rmtoll CR ADEN LL_ADC_Enable
5832 * @param ADCx ADC instance
5833 * @retval None
5834 */
LL_ADC_Enable(ADC_TypeDef * ADCx)5835 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
5836 {
5837 /* Note: Write register with some additional bits forced to state reset */
5838 /* instead of modifying only the selected bit for this function, */
5839 /* to not interfere with bits with HW property "rs". */
5840 MODIFY_REG(ADCx->CR,
5841 ADC_CR_BITS_PROPERTY_RS,
5842 ADC_CR_ADEN);
5843 }
5844
5845 /**
5846 * @brief Disable the selected ADC instance.
5847 * @note On this STM32 series, setting of this feature is conditioned to
5848 * ADC state:
5849 * ADC must be not disabled. Must be enabled without conversion on going
5850 * on either groups regular or injected.
5851 * @rmtoll CR ADDIS LL_ADC_Disable
5852 * @param ADCx ADC instance
5853 * @retval None
5854 */
LL_ADC_Disable(ADC_TypeDef * ADCx)5855 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
5856 {
5857 /* Note: Write register with some additional bits forced to state reset */
5858 /* instead of modifying only the selected bit for this function, */
5859 /* to not interfere with bits with HW property "rs". */
5860 MODIFY_REG(ADCx->CR,
5861 ADC_CR_BITS_PROPERTY_RS,
5862 ADC_CR_ADDIS);
5863 }
5864
5865 /**
5866 * @brief Get the selected ADC instance enable state.
5867 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5868 * is enabled and when conversion clock is active.
5869 * (not only core clock: this ADC has a dual clock domain)
5870 * @rmtoll CR ADEN LL_ADC_IsEnabled
5871 * @param ADCx ADC instance
5872 * @retval 0: ADC is disabled, 1: ADC is enabled.
5873 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)5874 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
5875 {
5876 return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
5877 }
5878
5879 /**
5880 * @brief Get the selected ADC instance disable state.
5881 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
5882 * @param ADCx ADC instance
5883 * @retval 0: no ADC disable command on going.
5884 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)5885 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
5886 {
5887 return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
5888 }
5889
5890 /**
5891 * @brief Start ADC calibration in the mode single-ended
5892 * or differential (for devices with differential mode available).
5893 * @note On this STM32 series, a minimum number of ADC clock cycles
5894 * are required between ADC end of calibration and ADC enable.
5895 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
5896 * @note For devices with differential mode available:
5897 * Calibration of offset is specific to each of
5898 * single-ended and differential modes
5899 * (calibration run must be performed for each of these
5900 * differential modes, if used afterwards and if the application
5901 * requires their calibration).
5902 * @note On this STM32 series, setting of this feature is conditioned to
5903 * ADC state:
5904 * ADC must be ADC disabled.
5905 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
5906 * CR ADCALDIF LL_ADC_StartCalibration
5907 * @param ADCx ADC instance
5908 * @param SingleDiff This parameter can be one of the following values:
5909 * @arg @ref LL_ADC_SINGLE_ENDED
5910 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5911 * @retval None
5912 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)5913 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
5914 {
5915 /* Note: Write register with some additional bits forced to state reset */
5916 /* instead of modifying only the selected bit for this function, */
5917 /* to not interfere with bits with HW property "rs". */
5918 MODIFY_REG(ADCx->CR,
5919 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
5920 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
5921 }
5922
5923 /**
5924 * @brief Get ADC calibration state.
5925 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
5926 * @param ADCx ADC instance
5927 * @retval 0: calibration complete, 1: calibration in progress.
5928 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)5929 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
5930 {
5931 return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
5932 }
5933
5934 /**
5935 * @}
5936 */
5937
5938 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
5939 * @{
5940 */
5941
5942 /**
5943 * @brief Start ADC group regular conversion.
5944 * @note On this STM32 series, this function is relevant for both
5945 * internal trigger (SW start) and external trigger:
5946 * - If ADC trigger has been set to software start, ADC conversion
5947 * starts immediately.
5948 * - If ADC trigger has been set to external trigger, ADC conversion
5949 * will start at next trigger event (on the selected trigger edge)
5950 * following the ADC start conversion command.
5951 * @note On this STM32 series, setting of this feature is conditioned to
5952 * ADC state:
5953 * ADC must be enabled without conversion on going on group regular,
5954 * without conversion stop command on going on group regular,
5955 * without ADC disable command on going.
5956 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
5957 * @param ADCx ADC instance
5958 * @retval None
5959 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)5960 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
5961 {
5962 /* Note: Write register with some additional bits forced to state reset */
5963 /* instead of modifying only the selected bit for this function, */
5964 /* to not interfere with bits with HW property "rs". */
5965 MODIFY_REG(ADCx->CR,
5966 ADC_CR_BITS_PROPERTY_RS,
5967 ADC_CR_ADSTART);
5968 }
5969
5970 /**
5971 * @brief Stop ADC group regular conversion.
5972 * @note On this STM32 series, setting of this feature is conditioned to
5973 * ADC state:
5974 * ADC must be enabled with conversion on going on group regular,
5975 * without ADC disable command on going.
5976 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
5977 * @param ADCx ADC instance
5978 * @retval None
5979 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)5980 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
5981 {
5982 /* Note: Write register with some additional bits forced to state reset */
5983 /* instead of modifying only the selected bit for this function, */
5984 /* to not interfere with bits with HW property "rs". */
5985 MODIFY_REG(ADCx->CR,
5986 ADC_CR_BITS_PROPERTY_RS,
5987 ADC_CR_ADSTP);
5988 }
5989
5990 /**
5991 * @brief Get ADC group regular conversion state.
5992 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
5993 * @param ADCx ADC instance
5994 * @retval 0: no conversion is on going on ADC group regular.
5995 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)5996 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
5997 {
5998 return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
5999 }
6000
6001 /**
6002 * @brief Get ADC group regular command of conversion stop state
6003 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6004 * @param ADCx ADC instance
6005 * @retval 0: no command of conversion stop is on going on ADC group regular.
6006 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)6007 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6008 {
6009 return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
6010 }
6011
6012 /**
6013 * @brief Get ADC group regular conversion data, range fit for
6014 * all ADC configurations: all ADC resolutions and
6015 * all oversampling increased data width (for devices
6016 * with feature oversampling).
6017 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6018 * @param ADCx ADC instance
6019 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6020 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)6021 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6022 {
6023 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6024 }
6025
6026 /**
6027 * @brief Get ADC group regular conversion data, range fit for
6028 * ADC resolution 12 bits.
6029 * @note For devices with feature oversampling: Oversampling
6030 * can increase data width, function for extended range
6031 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6032 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6033 * @param ADCx ADC instance
6034 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6035 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)6036 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6037 {
6038 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6039 }
6040
6041 /**
6042 * @brief Get ADC group regular conversion data, range fit for
6043 * ADC resolution 10 bits.
6044 * @note For devices with feature oversampling: Oversampling
6045 * can increase data width, function for extended range
6046 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6047 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6048 * @param ADCx ADC instance
6049 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6050 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)6051 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6052 {
6053 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6054 }
6055
6056 /**
6057 * @brief Get ADC group regular conversion data, range fit for
6058 * ADC resolution 8 bits.
6059 * @note For devices with feature oversampling: Oversampling
6060 * can increase data width, function for extended range
6061 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6062 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6063 * @param ADCx ADC instance
6064 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6065 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)6066 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6067 {
6068 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6069 }
6070
6071 /**
6072 * @brief Get ADC group regular conversion data, range fit for
6073 * ADC resolution 6 bits.
6074 * @note For devices with feature oversampling: Oversampling
6075 * can increase data width, function for extended range
6076 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6077 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6078 * @param ADCx ADC instance
6079 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6080 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)6081 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6082 {
6083 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6084 }
6085
6086 #if defined(ADC_MULTIMODE_SUPPORT)
6087 /**
6088 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6089 * or raw data with ADC master and slave concatenated.
6090 * @note If raw data with ADC master and slave concatenated is retrieved,
6091 * a macro is available to get the conversion data of
6092 * ADC master or ADC slave: see helper macro
6093 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6094 * (however this macro is mainly intended for multimode
6095 * transfer by DMA, because this function can do the same
6096 * by getting multimode conversion data of ADC master or ADC slave
6097 * separately).
6098 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6099 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6100 * @param ADCxy_COMMON ADC common instance
6101 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6102 * @param ConversionData This parameter can be one of the following values:
6103 * @arg @ref LL_ADC_MULTI_MASTER
6104 * @arg @ref LL_ADC_MULTI_SLAVE
6105 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6106 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6107 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6108 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6109 {
6110 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6111 ConversionData)
6112 >> POSITION_VAL(ConversionData)
6113 );
6114 }
6115 #endif /* ADC_MULTIMODE_SUPPORT */
6116
6117 /**
6118 * @}
6119 */
6120
6121 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6122 * @{
6123 */
6124
6125 /**
6126 * @brief Start ADC group injected conversion.
6127 * @note On this STM32 series, this function is relevant for both
6128 * internal trigger (SW start) and external trigger:
6129 * - If ADC trigger has been set to software start, ADC conversion
6130 * starts immediately.
6131 * - If ADC trigger has been set to external trigger, ADC conversion
6132 * will start at next trigger event (on the selected trigger edge)
6133 * following the ADC start conversion command.
6134 * @note On this STM32 series, setting of this feature is conditioned to
6135 * ADC state:
6136 * ADC must be enabled without conversion on going on group injected,
6137 * without conversion stop command on going on group injected,
6138 * without ADC disable command on going.
6139 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6140 * @param ADCx ADC instance
6141 * @retval None
6142 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6143 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6144 {
6145 /* Note: Write register with some additional bits forced to state reset */
6146 /* instead of modifying only the selected bit for this function, */
6147 /* to not interfere with bits with HW property "rs". */
6148 MODIFY_REG(ADCx->CR,
6149 ADC_CR_BITS_PROPERTY_RS,
6150 ADC_CR_JADSTART);
6151 }
6152
6153 /**
6154 * @brief Stop ADC group injected conversion.
6155 * @note On this STM32 series, setting of this feature is conditioned to
6156 * ADC state:
6157 * ADC must be enabled with conversion on going on group injected,
6158 * without ADC disable command on going.
6159 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6160 * @param ADCx ADC instance
6161 * @retval None
6162 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6163 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6164 {
6165 /* Note: Write register with some additional bits forced to state reset */
6166 /* instead of modifying only the selected bit for this function, */
6167 /* to not interfere with bits with HW property "rs". */
6168 MODIFY_REG(ADCx->CR,
6169 ADC_CR_BITS_PROPERTY_RS,
6170 ADC_CR_JADSTP);
6171 }
6172
6173 /**
6174 * @brief Get ADC group injected conversion state.
6175 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6176 * @param ADCx ADC instance
6177 * @retval 0: no conversion is on going on ADC group injected.
6178 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)6179 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6180 {
6181 return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
6182 }
6183
6184 /**
6185 * @brief Get ADC group injected command of conversion stop state
6186 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6187 * @param ADCx ADC instance
6188 * @retval 0: no command of conversion stop is on going on ADC group injected.
6189 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)6190 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6191 {
6192 return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
6193 }
6194
6195 /**
6196 * @brief Get ADC group regular conversion data, range fit for
6197 * all ADC configurations: all ADC resolutions and
6198 * all oversampling increased data width (for devices
6199 * with feature oversampling).
6200 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6201 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6202 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6203 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6204 * @param ADCx ADC instance
6205 * @param Rank This parameter can be one of the following values:
6206 * @arg @ref LL_ADC_INJ_RANK_1
6207 * @arg @ref LL_ADC_INJ_RANK_2
6208 * @arg @ref LL_ADC_INJ_RANK_3
6209 * @arg @ref LL_ADC_INJ_RANK_4
6210 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6211 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)6212 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6213 {
6214 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6215
6216 return (uint32_t)(READ_BIT(*preg,
6217 ADC_JDR1_JDATA)
6218 );
6219 }
6220
6221 /**
6222 * @brief Get ADC group injected conversion data, range fit for
6223 * ADC resolution 12 bits.
6224 * @note For devices with feature oversampling: Oversampling
6225 * can increase data width, function for extended range
6226 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6227 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6228 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6229 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6230 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6231 * @param ADCx ADC instance
6232 * @param Rank This parameter can be one of the following values:
6233 * @arg @ref LL_ADC_INJ_RANK_1
6234 * @arg @ref LL_ADC_INJ_RANK_2
6235 * @arg @ref LL_ADC_INJ_RANK_3
6236 * @arg @ref LL_ADC_INJ_RANK_4
6237 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6238 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)6239 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6240 {
6241 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6242
6243 return (uint16_t)(READ_BIT(*preg,
6244 ADC_JDR1_JDATA)
6245 );
6246 }
6247
6248 /**
6249 * @brief Get ADC group injected conversion data, range fit for
6250 * ADC resolution 10 bits.
6251 * @note For devices with feature oversampling: Oversampling
6252 * can increase data width, function for extended range
6253 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6254 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6255 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6256 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6257 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6258 * @param ADCx ADC instance
6259 * @param Rank This parameter can be one of the following values:
6260 * @arg @ref LL_ADC_INJ_RANK_1
6261 * @arg @ref LL_ADC_INJ_RANK_2
6262 * @arg @ref LL_ADC_INJ_RANK_3
6263 * @arg @ref LL_ADC_INJ_RANK_4
6264 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6265 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)6266 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6267 {
6268 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6269
6270 return (uint16_t)(READ_BIT(*preg,
6271 ADC_JDR1_JDATA)
6272 );
6273 }
6274
6275 /**
6276 * @brief Get ADC group injected conversion data, range fit for
6277 * ADC resolution 8 bits.
6278 * @note For devices with feature oversampling: Oversampling
6279 * can increase data width, function for extended range
6280 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6281 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6282 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6283 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6284 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6285 * @param ADCx ADC instance
6286 * @param Rank This parameter can be one of the following values:
6287 * @arg @ref LL_ADC_INJ_RANK_1
6288 * @arg @ref LL_ADC_INJ_RANK_2
6289 * @arg @ref LL_ADC_INJ_RANK_3
6290 * @arg @ref LL_ADC_INJ_RANK_4
6291 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6292 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)6293 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6294 {
6295 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6296
6297 return (uint8_t)(READ_BIT(*preg,
6298 ADC_JDR1_JDATA)
6299 );
6300 }
6301
6302 /**
6303 * @brief Get ADC group injected conversion data, range fit for
6304 * ADC resolution 6 bits.
6305 * @note For devices with feature oversampling: Oversampling
6306 * can increase data width, function for extended range
6307 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6308 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6309 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6310 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6311 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6312 * @param ADCx ADC instance
6313 * @param Rank This parameter can be one of the following values:
6314 * @arg @ref LL_ADC_INJ_RANK_1
6315 * @arg @ref LL_ADC_INJ_RANK_2
6316 * @arg @ref LL_ADC_INJ_RANK_3
6317 * @arg @ref LL_ADC_INJ_RANK_4
6318 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6319 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)6320 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
6321 {
6322 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
6323
6324 return (uint8_t)(READ_BIT(*preg,
6325 ADC_JDR1_JDATA)
6326 );
6327 }
6328
6329 /**
6330 * @}
6331 */
6332
6333 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6334 * @{
6335 */
6336
6337 /**
6338 * @brief Get flag ADC ready.
6339 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6340 * is enabled and when conversion clock is active.
6341 * (not only core clock: this ADC has a dual clock domain)
6342 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6343 * @param ADCx ADC instance
6344 * @retval State of bit (1 or 0).
6345 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)6346 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6347 {
6348 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
6349 }
6350
6351 /**
6352 * @brief Get flag ADC group regular end of unitary conversion.
6353 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6354 * @param ADCx ADC instance
6355 * @retval State of bit (1 or 0).
6356 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)6357 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6358 {
6359 return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
6360 }
6361
6362 /**
6363 * @brief Get flag ADC group regular end of sequence conversions.
6364 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6365 * @param ADCx ADC instance
6366 * @retval State of bit (1 or 0).
6367 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)6368 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6369 {
6370 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
6371 }
6372
6373 /**
6374 * @brief Get flag ADC group regular overrun.
6375 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6376 * @param ADCx ADC instance
6377 * @retval State of bit (1 or 0).
6378 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)6379 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6380 {
6381 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
6382 }
6383
6384 /**
6385 * @brief Get flag ADC group regular end of sampling phase.
6386 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6387 * @param ADCx ADC instance
6388 * @retval State of bit (1 or 0).
6389 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)6390 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6391 {
6392 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
6393 }
6394
6395 /**
6396 * @brief Get flag ADC group injected end of unitary conversion.
6397 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6398 * @param ADCx ADC instance
6399 * @retval State of bit (1 or 0).
6400 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)6401 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6402 {
6403 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
6404 }
6405
6406 /**
6407 * @brief Get flag ADC group injected end of sequence conversions.
6408 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6409 * @param ADCx ADC instance
6410 * @retval State of bit (1 or 0).
6411 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)6412 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6413 {
6414 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
6415 }
6416
6417 /**
6418 * @brief Get flag ADC group injected contexts queue overflow.
6419 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6420 * @param ADCx ADC instance
6421 * @retval State of bit (1 or 0).
6422 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)6423 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6424 {
6425 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
6426 }
6427
6428 /**
6429 * @brief Get flag ADC analog watchdog 1 flag
6430 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6431 * @param ADCx ADC instance
6432 * @retval State of bit (1 or 0).
6433 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)6434 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6435 {
6436 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
6437 }
6438
6439 /**
6440 * @brief Get flag ADC analog watchdog 2.
6441 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6442 * @param ADCx ADC instance
6443 * @retval State of bit (1 or 0).
6444 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)6445 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6446 {
6447 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
6448 }
6449
6450 /**
6451 * @brief Get flag ADC analog watchdog 3.
6452 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6453 * @param ADCx ADC instance
6454 * @retval State of bit (1 or 0).
6455 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)6456 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6457 {
6458 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
6459 }
6460
6461 /**
6462 * @brief Clear flag ADC ready.
6463 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6464 * is enabled and when conversion clock is active.
6465 * (not only core clock: this ADC has a dual clock domain)
6466 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6467 * @param ADCx ADC instance
6468 * @retval None
6469 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6470 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6471 {
6472 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6473 }
6474
6475 /**
6476 * @brief Clear flag ADC group regular end of unitary conversion.
6477 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6478 * @param ADCx ADC instance
6479 * @retval None
6480 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6481 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6482 {
6483 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6484 }
6485
6486 /**
6487 * @brief Clear flag ADC group regular end of sequence conversions.
6488 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6489 * @param ADCx ADC instance
6490 * @retval None
6491 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6492 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6493 {
6494 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6495 }
6496
6497 /**
6498 * @brief Clear flag ADC group regular overrun.
6499 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6500 * @param ADCx ADC instance
6501 * @retval None
6502 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6503 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6504 {
6505 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6506 }
6507
6508 /**
6509 * @brief Clear flag ADC group regular end of sampling phase.
6510 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6511 * @param ADCx ADC instance
6512 * @retval None
6513 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6514 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6515 {
6516 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6517 }
6518
6519 /**
6520 * @brief Clear flag ADC group injected end of unitary conversion.
6521 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6522 * @param ADCx ADC instance
6523 * @retval None
6524 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6525 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6526 {
6527 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6528 }
6529
6530 /**
6531 * @brief Clear flag ADC group injected end of sequence conversions.
6532 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6533 * @param ADCx ADC instance
6534 * @retval None
6535 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6536 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6537 {
6538 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6539 }
6540
6541 /**
6542 * @brief Clear flag ADC group injected contexts queue overflow.
6543 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6544 * @param ADCx ADC instance
6545 * @retval None
6546 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)6547 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6548 {
6549 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6550 }
6551
6552 /**
6553 * @brief Clear flag ADC analog watchdog 1.
6554 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6555 * @param ADCx ADC instance
6556 * @retval None
6557 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6558 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6559 {
6560 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6561 }
6562
6563 /**
6564 * @brief Clear flag ADC analog watchdog 2.
6565 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6566 * @param ADCx ADC instance
6567 * @retval None
6568 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6569 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6570 {
6571 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6572 }
6573
6574 /**
6575 * @brief Clear flag ADC analog watchdog 3.
6576 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6577 * @param ADCx ADC instance
6578 * @retval None
6579 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6580 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6581 {
6582 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6583 }
6584
6585 #if defined(ADC_MULTIMODE_SUPPORT)
6586 /**
6587 * @brief Get flag multimode ADC ready of the ADC master.
6588 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6589 * @param ADCxy_COMMON ADC common instance
6590 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6591 * @retval State of bit (1 or 0).
6592 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6593 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6594 {
6595 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
6596 }
6597
6598 /**
6599 * @brief Get flag multimode ADC ready of the ADC slave.
6600 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6601 * @param ADCxy_COMMON ADC common instance
6602 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6603 * @retval State of bit (1 or 0).
6604 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6605 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6606 {
6607 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
6608 }
6609
6610 /**
6611 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6612 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6613 * @param ADCxy_COMMON ADC common instance
6614 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6615 * @retval State of bit (1 or 0).
6616 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6617 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6618 {
6619 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
6620 }
6621
6622 /**
6623 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6624 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6625 * @param ADCxy_COMMON ADC common instance
6626 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6627 * @retval State of bit (1 or 0).
6628 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6629 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6630 {
6631 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
6632 }
6633
6634 /**
6635 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6636 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6637 * @param ADCxy_COMMON ADC common instance
6638 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6639 * @retval State of bit (1 or 0).
6640 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6641 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6642 {
6643 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
6644 }
6645
6646 /**
6647 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6648 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6649 * @param ADCxy_COMMON ADC common instance
6650 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6651 * @retval State of bit (1 or 0).
6652 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6653 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6654 {
6655 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
6656 }
6657
6658 /**
6659 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6660 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6661 * @param ADCxy_COMMON ADC common instance
6662 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6663 * @retval State of bit (1 or 0).
6664 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6665 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6666 {
6667 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
6668 }
6669
6670 /**
6671 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6672 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6673 * @param ADCxy_COMMON ADC common instance
6674 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6675 * @retval State of bit (1 or 0).
6676 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6677 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6678 {
6679 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
6680 }
6681
6682 /**
6683 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6684 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6685 * @param ADCxy_COMMON ADC common instance
6686 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6687 * @retval State of bit (1 or 0).
6688 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6689 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6690 {
6691 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
6692 }
6693
6694 /**
6695 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6696 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6697 * @param ADCxy_COMMON ADC common instance
6698 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6699 * @retval State of bit (1 or 0).
6700 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6701 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6702 {
6703 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
6704 }
6705
6706 /**
6707 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6708 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6709 * @param ADCxy_COMMON ADC common instance
6710 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6711 * @retval State of bit (1 or 0).
6712 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6713 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6714 {
6715 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
6716 }
6717
6718 /**
6719 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6720 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6721 * @param ADCxy_COMMON ADC common instance
6722 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6723 * @retval State of bit (1 or 0).
6724 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6725 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6726 {
6727 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
6728 }
6729
6730 /**
6731 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6732 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6733 * @param ADCxy_COMMON ADC common instance
6734 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6735 * @retval State of bit (1 or 0).
6736 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6737 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6738 {
6739 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
6740 }
6741
6742 /**
6743 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6744 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6745 * @param ADCxy_COMMON ADC common instance
6746 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6747 * @retval State of bit (1 or 0).
6748 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6749 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6750 {
6751 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
6752 }
6753
6754 /**
6755 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6756 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6757 * @param ADCxy_COMMON ADC common instance
6758 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6759 * @retval State of bit (1 or 0).
6760 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6761 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6762 {
6763 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
6764 }
6765
6766 /**
6767 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6768 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6769 * @param ADCxy_COMMON ADC common instance
6770 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6771 * @retval State of bit (1 or 0).
6772 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6773 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6774 {
6775 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
6776 }
6777
6778 /**
6779 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6780 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6781 * @param ADCxy_COMMON ADC common instance
6782 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6783 * @retval State of bit (1 or 0).
6784 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6785 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6786 {
6787 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
6788 }
6789
6790 /**
6791 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6792 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6793 * @param ADCxy_COMMON ADC common instance
6794 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6795 * @retval State of bit (1 or 0).
6796 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6797 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6798 {
6799 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
6800 }
6801
6802 /**
6803 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6804 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6805 * @param ADCxy_COMMON ADC common instance
6806 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6807 * @retval State of bit (1 or 0).
6808 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6809 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6810 {
6811 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
6812 }
6813
6814 /**
6815 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6816 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6817 * @param ADCxy_COMMON ADC common instance
6818 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6819 * @retval State of bit (1 or 0).
6820 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6821 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6822 {
6823 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
6824 }
6825
6826 /**
6827 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
6828 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
6829 * @param ADCxy_COMMON ADC common instance
6830 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6831 * @retval State of bit (1 or 0).
6832 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6833 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6834 {
6835 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
6836 }
6837
6838 /**
6839 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
6840 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
6841 * @param ADCxy_COMMON ADC common instance
6842 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6843 * @retval State of bit (1 or 0).
6844 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6845 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6846 {
6847 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
6848 }
6849 #endif /* ADC_MULTIMODE_SUPPORT */
6850
6851 /**
6852 * @}
6853 */
6854
6855 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
6856 * @{
6857 */
6858
6859 /**
6860 * @brief Enable ADC ready.
6861 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
6862 * @param ADCx ADC instance
6863 * @retval None
6864 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)6865 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
6866 {
6867 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6868 }
6869
6870 /**
6871 * @brief Enable interruption ADC group regular end of unitary conversion.
6872 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
6873 * @param ADCx ADC instance
6874 * @retval None
6875 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)6876 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
6877 {
6878 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
6879 }
6880
6881 /**
6882 * @brief Enable interruption ADC group regular end of sequence conversions.
6883 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
6884 * @param ADCx ADC instance
6885 * @retval None
6886 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)6887 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
6888 {
6889 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
6890 }
6891
6892 /**
6893 * @brief Enable ADC group regular interruption overrun.
6894 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
6895 * @param ADCx ADC instance
6896 * @retval None
6897 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)6898 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
6899 {
6900 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
6901 }
6902
6903 /**
6904 * @brief Enable interruption ADC group regular end of sampling.
6905 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
6906 * @param ADCx ADC instance
6907 * @retval None
6908 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)6909 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
6910 {
6911 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
6912 }
6913
6914 /**
6915 * @brief Enable interruption ADC group injected end of unitary conversion.
6916 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
6917 * @param ADCx ADC instance
6918 * @retval None
6919 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)6920 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
6921 {
6922 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
6923 }
6924
6925 /**
6926 * @brief Enable interruption ADC group injected end of sequence conversions.
6927 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
6928 * @param ADCx ADC instance
6929 * @retval None
6930 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)6931 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
6932 {
6933 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
6934 }
6935
6936 /**
6937 * @brief Enable interruption ADC group injected context queue overflow.
6938 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
6939 * @param ADCx ADC instance
6940 * @retval None
6941 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)6942 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
6943 {
6944 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
6945 }
6946
6947 /**
6948 * @brief Enable interruption ADC analog watchdog 1.
6949 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
6950 * @param ADCx ADC instance
6951 * @retval None
6952 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)6953 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
6954 {
6955 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
6956 }
6957
6958 /**
6959 * @brief Enable interruption ADC analog watchdog 2.
6960 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
6961 * @param ADCx ADC instance
6962 * @retval None
6963 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)6964 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
6965 {
6966 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
6967 }
6968
6969 /**
6970 * @brief Enable interruption ADC analog watchdog 3.
6971 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
6972 * @param ADCx ADC instance
6973 * @retval None
6974 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)6975 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
6976 {
6977 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
6978 }
6979
6980 /**
6981 * @brief Disable interruption ADC ready.
6982 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
6983 * @param ADCx ADC instance
6984 * @retval None
6985 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)6986 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
6987 {
6988 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6989 }
6990
6991 /**
6992 * @brief Disable interruption ADC group regular end of unitary conversion.
6993 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
6994 * @param ADCx ADC instance
6995 * @retval None
6996 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)6997 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
6998 {
6999 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7000 }
7001
7002 /**
7003 * @brief Disable interruption ADC group regular end of sequence conversions.
7004 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7005 * @param ADCx ADC instance
7006 * @retval None
7007 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7008 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7009 {
7010 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7011 }
7012
7013 /**
7014 * @brief Disable interruption ADC group regular overrun.
7015 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7016 * @param ADCx ADC instance
7017 * @retval None
7018 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7019 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7020 {
7021 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7022 }
7023
7024 /**
7025 * @brief Disable interruption ADC group regular end of sampling.
7026 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7027 * @param ADCx ADC instance
7028 * @retval None
7029 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7030 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7031 {
7032 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7033 }
7034
7035 /**
7036 * @brief Disable interruption ADC group regular end of unitary conversion.
7037 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7038 * @param ADCx ADC instance
7039 * @retval None
7040 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7041 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7042 {
7043 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7044 }
7045
7046 /**
7047 * @brief Disable interruption ADC group injected end of sequence conversions.
7048 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7049 * @param ADCx ADC instance
7050 * @retval None
7051 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7052 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7053 {
7054 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7055 }
7056
7057 /**
7058 * @brief Disable interruption ADC group injected context queue overflow.
7059 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7060 * @param ADCx ADC instance
7061 * @retval None
7062 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7063 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7064 {
7065 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7066 }
7067
7068 /**
7069 * @brief Disable interruption ADC analog watchdog 1.
7070 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7071 * @param ADCx ADC instance
7072 * @retval None
7073 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7074 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7075 {
7076 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7077 }
7078
7079 /**
7080 * @brief Disable interruption ADC analog watchdog 2.
7081 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7082 * @param ADCx ADC instance
7083 * @retval None
7084 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7085 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7086 {
7087 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7088 }
7089
7090 /**
7091 * @brief Disable interruption ADC analog watchdog 3.
7092 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7093 * @param ADCx ADC instance
7094 * @retval None
7095 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7096 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7097 {
7098 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7099 }
7100
7101 /**
7102 * @brief Get state of interruption ADC ready
7103 * (0: interrupt disabled, 1: interrupt enabled).
7104 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7105 * @param ADCx ADC instance
7106 * @retval State of bit (1 or 0).
7107 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)7108 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7109 {
7110 return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
7111 }
7112
7113 /**
7114 * @brief Get state of interruption ADC group regular end of unitary conversion
7115 * (0: interrupt disabled, 1: interrupt enabled).
7116 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7117 * @param ADCx ADC instance
7118 * @retval State of bit (1 or 0).
7119 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)7120 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7121 {
7122 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
7123 }
7124
7125 /**
7126 * @brief Get state of interruption ADC group regular end of sequence conversions
7127 * (0: interrupt disabled, 1: interrupt enabled).
7128 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7129 * @param ADCx ADC instance
7130 * @retval State of bit (1 or 0).
7131 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)7132 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7133 {
7134 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
7135 }
7136
7137 /**
7138 * @brief Get state of interruption ADC group regular overrun
7139 * (0: interrupt disabled, 1: interrupt enabled).
7140 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7141 * @param ADCx ADC instance
7142 * @retval State of bit (1 or 0).
7143 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)7144 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7145 {
7146 return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
7147 }
7148
7149 /**
7150 * @brief Get state of interruption ADC group regular end of sampling
7151 * (0: interrupt disabled, 1: interrupt enabled).
7152 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7153 * @param ADCx ADC instance
7154 * @retval State of bit (1 or 0).
7155 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)7156 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7157 {
7158 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
7159 }
7160
7161 /**
7162 * @brief Get state of interruption ADC group injected end of unitary conversion
7163 * (0: interrupt disabled, 1: interrupt enabled).
7164 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7165 * @param ADCx ADC instance
7166 * @retval State of bit (1 or 0).
7167 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)7168 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7169 {
7170 return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
7171 }
7172
7173 /**
7174 * @brief Get state of interruption ADC group injected end of sequence conversions
7175 * (0: interrupt disabled, 1: interrupt enabled).
7176 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7177 * @param ADCx ADC instance
7178 * @retval State of bit (1 or 0).
7179 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)7180 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7181 {
7182 return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
7183 }
7184
7185 /**
7186 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7187 * (0: interrupt disabled, 1: interrupt enabled).
7188 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7189 * @param ADCx ADC instance
7190 * @retval State of bit (1 or 0).
7191 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)7192 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7193 {
7194 return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
7195 }
7196
7197 /**
7198 * @brief Get state of interruption ADC analog watchdog 1
7199 * (0: interrupt disabled, 1: interrupt enabled).
7200 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7201 * @param ADCx ADC instance
7202 * @retval State of bit (1 or 0).
7203 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)7204 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7205 {
7206 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
7207 }
7208
7209 /**
7210 * @brief Get state of interruption Get ADC analog watchdog 2
7211 * (0: interrupt disabled, 1: interrupt enabled).
7212 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7213 * @param ADCx ADC instance
7214 * @retval State of bit (1 or 0).
7215 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)7216 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7217 {
7218 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
7219 }
7220
7221 /**
7222 * @brief Get state of interruption Get ADC analog watchdog 3
7223 * (0: interrupt disabled, 1: interrupt enabled).
7224 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7225 * @param ADCx ADC instance
7226 * @retval State of bit (1 or 0).
7227 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)7228 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7229 {
7230 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
7231 }
7232
7233 /**
7234 * @}
7235 */
7236
7237 #if defined(USE_FULL_LL_DRIVER)
7238 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7239 * @{
7240 */
7241
7242 /* Initialization of some features of ADC common parameters and multimode */
7243 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7244 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7245 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7246
7247 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7248 /* (availability of ADC group injected depends on STM32 families) */
7249 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7250
7251 /* Initialization of some features of ADC instance */
7252 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7253 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7254
7255 /* Initialization of some features of ADC instance and ADC group regular */
7256 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7257 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7258
7259 /* Initialization of some features of ADC instance and ADC group injected */
7260 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7261 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7262
7263 /**
7264 * @}
7265 */
7266 #endif /* USE_FULL_LL_DRIVER */
7267
7268 /**
7269 * @}
7270 */
7271
7272 /**
7273 * @}
7274 */
7275
7276 #endif /* ADC1 || ADC2 || ADC3 || ADC4 */
7277
7278
7279 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
7280
7281 #if defined (ADC1_V2_5)
7282
7283 #if defined (ADC1)
7284
7285 /** @defgroup ADC_LL ADC
7286 * @{
7287 */
7288
7289 /* Private types -------------------------------------------------------------*/
7290 /* Private variables ---------------------------------------------------------*/
7291
7292 /* Private constants ---------------------------------------------------------*/
7293 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
7294 * @{
7295 */
7296
7297 /* Internal mask for ADC group regular sequencer: */
7298 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
7299 /* - sequencer register offset */
7300 /* - sequencer rank bits position into the selected register */
7301
7302 /* Internal register offset for ADC group regular sequencer configuration */
7303 /* (offset placed into a spare area of literal definition) */
7304 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
7305 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
7306 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
7307 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
7308
7309 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
7310 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
7311
7312 /* Definition of ADC group regular sequencer bits information to be inserted */
7313 /* into ADC group regular sequencer ranks literals definition. */
7314 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
7315 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
7316 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
7317 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
7318 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
7319 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
7320 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
7321 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
7322 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
7323 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
7324 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
7325 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
7326 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
7327 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
7328 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
7329 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
7330
7331
7332
7333 /* Internal mask for ADC group injected sequencer: */
7334 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
7335 /* - data register offset */
7336 /* - offset register offset */
7337 /* - sequencer rank bits position into the selected register */
7338
7339 /* Internal register offset for ADC group injected data register */
7340 /* (offset placed into a spare area of literal definition) */
7341 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
7342 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
7343 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
7344 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
7345
7346 /* Internal register offset for ADC group injected offset configuration */
7347 /* (offset placed into a spare area of literal definition) */
7348 #define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
7349 #define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
7350 #define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
7351 #define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
7352
7353 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
7354 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
7355 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
7356
7357 /* Definition of ADC group injected sequencer bits information to be inserted */
7358 /* into ADC group injected sequencer ranks literals definition. */
7359 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
7360 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
7361 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
7362 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
7363
7364
7365
7366 /* Internal mask for ADC channel: */
7367 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
7368 /* - channel identifier defined by number */
7369 /* - channel differentiation between external channels (connected to */
7370 /* GPIO pins) and internal channels (connected to internal paths) */
7371 /* - channel sampling time defined by SMPRx register offset */
7372 /* and SMPx bits positions into SMPRx register */
7373 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
7374 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
7375 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
7376 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
7377 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
7378
7379 /* Channel differentiation between external and internal channels */
7380 #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
7381 #define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
7382 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
7383
7384 /* Internal register offset for ADC channel sampling time configuration */
7385 /* (offset placed into a spare area of literal definition) */
7386 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
7387 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
7388 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
7389
7390 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
7391 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
7392
7393 /* Definition of channels ID number information to be inserted into */
7394 /* channels literals definition. */
7395 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
7396 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
7397 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
7398 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7399 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
7400 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
7401 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
7402 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7403 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
7404 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
7405 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
7406 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7407 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
7408 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
7409 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
7410 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
7411 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
7412 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
7413
7414 /* Definition of channels sampling time information to be inserted into */
7415 /* channels literals definition. */
7416 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
7417 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
7418 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
7419 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
7420 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
7421 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
7422 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
7423 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
7424 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
7425 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
7426 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
7427 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
7428 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
7429 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
7430 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
7431 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
7432 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
7433 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
7434
7435
7436 /* Internal mask for ADC analog watchdog: */
7437 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
7438 /* (concatenation of multiple bits used in different analog watchdogs, */
7439 /* (feature of several watchdogs not available on all STM32 families)). */
7440 /* - analog watchdog 1: monitored channel defined by number, */
7441 /* selection of ADC group (ADC groups regular and-or injected). */
7442
7443 /* Internal register offset for ADC analog watchdog channel configuration */
7444 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
7445
7446 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
7447
7448 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
7449 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
7450
7451 /* Internal register offset for ADC analog watchdog threshold configuration */
7452 #define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
7453 #define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
7454 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
7455
7456
7457 /* ADC registers bits positions */
7458 #define ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
7459
7460
7461 /* ADC internal channels related definitions */
7462 /* Internal voltage reference VrefInt */
7463 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7464 #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
7465 /* Temperature sensor */
7466 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7467 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
7468 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
7469 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
7470 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
7471
7472
7473 /**
7474 * @}
7475 */
7476
7477
7478 /* Private macros ------------------------------------------------------------*/
7479 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
7480 * @{
7481 */
7482
7483 /**
7484 * @brief Driver macro reserved for internal use: isolate bits with the
7485 * selected mask and shift them to the register LSB
7486 * (shift mask on register position bit 0).
7487 * @param __BITS__ Bits in register 32 bits
7488 * @param __MASK__ Mask in register 32 bits
7489 * @retval Bits in register 32 bits
7490 */
7491 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
7492 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
7493
7494 /**
7495 * @brief Driver macro reserved for internal use: set a pointer to
7496 * a register from a register basis from which an offset
7497 * is applied.
7498 * @param __REG__ Register basis from which the offset is applied.
7499 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
7500 * @retval Pointer to register address
7501 */
7502 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
7503 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
7504
7505 /**
7506 * @}
7507 */
7508
7509
7510 /* Exported types ------------------------------------------------------------*/
7511 #if defined(USE_FULL_LL_DRIVER)
7512 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
7513 * @{
7514 */
7515
7516 /**
7517 * @brief Structure definition of some features of ADC instance.
7518 * @note These parameters have an impact on ADC scope: ADC instance.
7519 * Affects both group regular and group injected (availability
7520 * of ADC group injected depends on STM32 families).
7521 * Refer to corresponding unitary functions into
7522 * @ref ADC_LL_EF_Configuration_ADC_Instance .
7523 * @note The setting of these parameters by function @ref LL_ADC_Init()
7524 * is conditioned to ADC state:
7525 * ADC instance must be disabled.
7526 * This condition is applied to all ADC features, for efficiency
7527 * and compatibility over all STM32 families. However, the different
7528 * features can be set under different ADC state conditions
7529 * (setting possible with ADC enabled without conversion on going,
7530 * ADC enabled with conversion on going, ...)
7531 * Each feature can be updated afterwards with a unitary function
7532 * and potentially with ADC in a different state than disabled,
7533 * refer to description of each function for setting
7534 * conditioned to ADC state.
7535 */
7536 typedef struct
7537 {
7538 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
7539 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
7540
7541 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
7542
7543 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
7544 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
7545
7546 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
7547
7548 } LL_ADC_InitTypeDef;
7549
7550 /**
7551 * @brief Structure definition of some features of ADC group regular.
7552 * @note These parameters have an impact on ADC scope: ADC group regular.
7553 * Refer to corresponding unitary functions into
7554 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
7555 * (functions with prefix "REG").
7556 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
7557 * is conditioned to ADC state:
7558 * ADC instance must be disabled.
7559 * This condition is applied to all ADC features, for efficiency
7560 * and compatibility over all STM32 families. However, the different
7561 * features can be set under different ADC state conditions
7562 * (setting possible with ADC enabled without conversion on going,
7563 * ADC enabled with conversion on going, ...)
7564 * Each feature can be updated afterwards with a unitary function
7565 * and potentially with ADC in a different state than disabled,
7566 * refer to description of each function for setting
7567 * conditioned to ADC state.
7568 */
7569 typedef struct
7570 {
7571 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
7572 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
7573 @note On this STM32 series, external trigger is set with trigger polarity: rising edge
7574 (only trigger polarity available on this STM32 series).
7575
7576 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
7577
7578 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
7579 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
7580 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
7581
7582 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
7583
7584 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
7585 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
7586 @note This parameter has an effect only if group regular sequencer is enabled
7587 (scan length of 2 ranks or more).
7588
7589 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
7590
7591 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
7592 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
7593 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
7594
7595 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
7596
7597 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
7598 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
7599
7600 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
7601
7602 } LL_ADC_REG_InitTypeDef;
7603
7604 /**
7605 * @brief Structure definition of some features of ADC group injected.
7606 * @note These parameters have an impact on ADC scope: ADC group injected.
7607 * Refer to corresponding unitary functions into
7608 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
7609 * (functions with prefix "INJ").
7610 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
7611 * is conditioned to ADC state:
7612 * ADC instance must be disabled.
7613 * This condition is applied to all ADC features, for efficiency
7614 * and compatibility over all STM32 families. However, the different
7615 * features can be set under different ADC state conditions
7616 * (setting possible with ADC enabled without conversion on going,
7617 * ADC enabled with conversion on going, ...)
7618 * Each feature can be updated afterwards with a unitary function
7619 * and potentially with ADC in a different state than disabled,
7620 * refer to description of each function for setting
7621 * conditioned to ADC state.
7622 */
7623 typedef struct
7624 {
7625 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
7626 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
7627 @note On this STM32 series, external trigger is set with trigger polarity: rising edge
7628 (only trigger polarity available on this STM32 series).
7629
7630 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
7631
7632 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
7633 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
7634 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
7635
7636 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
7637
7638 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
7639 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
7640 @note This parameter has an effect only if group injected sequencer is enabled
7641 (scan length of 2 ranks or more).
7642
7643 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
7644
7645 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
7646 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
7647 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
7648
7649 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
7650
7651 } LL_ADC_INJ_InitTypeDef;
7652
7653 /**
7654 * @}
7655 */
7656 #endif /* USE_FULL_LL_DRIVER */
7657
7658 /* Exported constants --------------------------------------------------------*/
7659 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
7660 * @{
7661 */
7662
7663 /** @defgroup ADC_LL_EC_FLAG ADC flags
7664 * @brief Flags defines which can be used with LL_ADC_ReadReg function
7665 * @{
7666 */
7667 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
7668 #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
7669 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
7670 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
7671 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
7672 /**
7673 * @}
7674 */
7675
7676 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
7677 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
7678 * @{
7679 */
7680 #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
7681 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
7682 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
7683 /**
7684 * @}
7685 */
7686
7687 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
7688 * @{
7689 */
7690 /* List of ADC registers intended to be used (most commonly) with */
7691 /* DMA transfer. */
7692 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
7693 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
7694 /**
7695 * @}
7696 */
7697
7698 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
7699 * @{
7700 */
7701 /* Note: Other measurement paths to internal channels may be available */
7702 /* (connections to other peripherals). */
7703 /* If they are not listed below, they do not require any specific */
7704 /* path enable. In this case, Access to measurement path is done */
7705 /* only by selecting the corresponding ADC internal channel. */
7706 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement paths all disabled */
7707 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
7708 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
7709 /**
7710 * @}
7711 */
7712
7713 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
7714 * @{
7715 */
7716 #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
7717 /**
7718 * @}
7719 */
7720
7721 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
7722 * @{
7723 */
7724 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
7725 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
7726 /**
7727 * @}
7728 */
7729
7730 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
7731 * @{
7732 */
7733 #define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
7734 #define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
7735 /**
7736 * @}
7737 */
7738
7739 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
7740 * @{
7741 */
7742 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
7743 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
7744 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
7745 /**
7746 * @}
7747 */
7748
7749 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
7750 * @{
7751 */
7752 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
7753 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
7754 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
7755 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
7756 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
7757 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
7758 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
7759 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
7760 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
7761 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
7762 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
7763 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
7764 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
7765 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
7766 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
7767 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
7768 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
7769 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
7770 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1. */
7771 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
7772 /**
7773 * @}
7774 */
7775
7776 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
7777 * @{
7778 */
7779 #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal (SW start) */
7780 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
7781 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
7782 #define LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
7783 #define LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting). */
7784 #define LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting). */
7785 #define LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting). */
7786 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
7787 /**
7788 * @}
7789 */
7790
7791 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
7792 * @{
7793 */
7794 #define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger polarity set to rising edge */
7795 /**
7796 * @}
7797 */
7798
7799 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
7800 * @{
7801 */
7802 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)/*!< ADC conversions are performed in single mode: one conversion per trigger */
7803 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
7804 /**
7805 * @}
7806 */
7807
7808 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer
7809 * @{
7810 */
7811 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
7812 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
7813 /**
7814 * @}
7815 */
7816
7817 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
7818 * @{
7819 */
7820 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
7821 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
7822 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
7823 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
7824 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
7825 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
7826 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
7827 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
7828 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
7829 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
7830 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
7831 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
7832 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
7833 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
7834 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
7835 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
7836 /**
7837 * @}
7838 */
7839
7840 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
7841 * @{
7842 */
7843 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
7844 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
7845 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
7846 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
7847 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
7848 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
7849 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
7850 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
7851 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
7852 /**
7853 * @}
7854 */
7855
7856 /** @defgroup ADC_LL_EC_REG_RANKS ADC group regular - Sequencer ranks
7857 * @{
7858 */
7859 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
7860 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
7861 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
7862 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
7863 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
7864 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
7865 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
7866 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
7867 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
7868 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
7869 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
7870 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
7871 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
7872 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
7873 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
7874 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
7875 /**
7876 * @}
7877 */
7878
7879 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
7880 * @{
7881 */
7882 #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal (SW start) */
7883 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
7884 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
7885 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
7886 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
7887 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting). */
7888 #define LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting). */
7889 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
7890 /**
7891 * @}
7892 */
7893
7894 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
7895 * @{
7896 */
7897 #define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger polarity set to rising edge */
7898 /**
7899 * @}
7900 */
7901
7902 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
7903 * @{
7904 */
7905 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
7906 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
7907 /**
7908 * @}
7909 */
7910
7911
7912 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
7913 * @{
7914 */
7915 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
7916 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
7917 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
7918 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
7919 /**
7920 * @}
7921 */
7922
7923 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
7924 * @{
7925 */
7926 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
7927 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
7928 /**
7929 * @}
7930 */
7931
7932 /** @defgroup ADC_LL_EC_INJ_RANKS ADC group injected - Sequencer ranks
7933 * @{
7934 */
7935 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
7936 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
7937 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
7938 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
7939 /**
7940 * @}
7941 */
7942
7943 /** @defgroup ADC_LL_EC_SAMPLINGTIME Channel - Sampling time
7944 * @{
7945 */
7946 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
7947 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
7948 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
7949 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
7950 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
7951 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
7952 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
7953 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
7954 /**
7955 * @}
7956 */
7957
7958 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
7959 * @{
7960 */
7961 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
7962 /**
7963 * @}
7964 */
7965
7966 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
7967 * @{
7968 */
7969 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
7970 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
7971 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
7972 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
7973 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
7974 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
7975 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
7976 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
7977 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
7978 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
7979 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
7980 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
7981 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
7982 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
7983 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
7984 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
7985 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
7986 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
7987 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
7988 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
7989 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
7990 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
7991 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
7992 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
7993 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
7994 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
7995 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
7996 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
7997 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
7998 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
7999 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
8000 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
8001 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
8002 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
8003 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
8004 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
8005 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
8006 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
8007 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
8008 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
8009 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
8010 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
8011 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
8012 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
8013 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
8014 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
8015 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
8016 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
8017 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
8018 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
8019 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
8020 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
8021 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
8022 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
8023 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
8024 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
8025 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
8026 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
8027 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
8028 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
8029 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
8030 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
8031 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
8032 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
8033 /**
8034 * @}
8035 */
8036
8037 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
8038 * @{
8039 */
8040 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
8041 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
8042 /**
8043 * @}
8044 */
8045
8046
8047 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
8048 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
8049 * not timeout values.
8050 * For details on delays values, refer to descriptions in source code
8051 * above each literal definition.
8052 * @{
8053 */
8054
8055 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
8056 /* not timeout values. */
8057 /* Timeout values for ADC operations are dependent to device clock */
8058 /* configuration (system clock versus ADC clock), */
8059 /* and therefore must be defined in user application. */
8060 /* Indications for estimation of ADC timeout delays, for this */
8061 /* STM32 series: */
8062 /* - ADC enable time: maximum delay is 1us */
8063 /* (refer to device datasheet, parameter "tSTAB") */
8064 /* - ADC conversion time: duration depending on ADC clock and ADC */
8065 /* configuration. */
8066 /* (refer to device reference manual, section "Timing") */
8067
8068 /* Delay for temperature sensor stabilization time. */
8069 /* Literal set to maximum value (refer to device datasheet, */
8070 /* parameter "tSTART"). */
8071 /* Unit: us */
8072 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
8073
8074 /* Delay required between ADC disable and ADC calibration start. */
8075 /* Note: On this STM32 series, before starting a calibration, */
8076 /* ADC must be disabled. */
8077 /* A minimum number of ADC clock cycles are required */
8078 /* between ADC disable state and calibration start. */
8079 /* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */
8080 /* Wait time can be computed in user application by waiting for the */
8081 /* equivalent number of CPU cycles, by taking into account */
8082 /* ratio of CPU clock versus ADC clock prescalers. */
8083 /* Unit: ADC clock cycles. */
8084 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC disable and ADC calibration start */
8085
8086 /**
8087 * @}
8088 */
8089
8090 /**
8091 * @}
8092 */
8093
8094
8095 /* Exported macro ------------------------------------------------------------*/
8096 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
8097 * @{
8098 */
8099
8100 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
8101 * @{
8102 */
8103
8104 /**
8105 * @brief Write a value in ADC register
8106 * @param __INSTANCE__ ADC Instance
8107 * @param __REG__ Register to be written
8108 * @param __VALUE__ Value to be written in the register
8109 * @retval None
8110 */
8111 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
8112
8113 /**
8114 * @brief Read a value in ADC register
8115 * @param __INSTANCE__ ADC Instance
8116 * @param __REG__ Register to be read
8117 * @retval Register value
8118 */
8119 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
8120 /**
8121 * @}
8122 */
8123
8124 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
8125 * @{
8126 */
8127
8128 /**
8129 * @brief Helper macro to get ADC channel number in decimal format
8130 * from literals LL_ADC_CHANNEL_x.
8131 * @note Example:
8132 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
8133 * will return decimal number "4".
8134 * @note The input can be a value from functions where a channel
8135 * number is returned, either defined with number
8136 * or with bitfield (only one bit must be set).
8137 * @param __CHANNEL__ This parameter can be one of the following values:
8138 * @arg @ref LL_ADC_CHANNEL_0
8139 * @arg @ref LL_ADC_CHANNEL_1
8140 * @arg @ref LL_ADC_CHANNEL_2
8141 * @arg @ref LL_ADC_CHANNEL_3
8142 * @arg @ref LL_ADC_CHANNEL_4
8143 * @arg @ref LL_ADC_CHANNEL_5
8144 * @arg @ref LL_ADC_CHANNEL_6
8145 * @arg @ref LL_ADC_CHANNEL_7
8146 * @arg @ref LL_ADC_CHANNEL_8
8147 * @arg @ref LL_ADC_CHANNEL_9
8148 * @arg @ref LL_ADC_CHANNEL_10
8149 * @arg @ref LL_ADC_CHANNEL_11
8150 * @arg @ref LL_ADC_CHANNEL_12
8151 * @arg @ref LL_ADC_CHANNEL_13
8152 * @arg @ref LL_ADC_CHANNEL_14
8153 * @arg @ref LL_ADC_CHANNEL_15
8154 * @arg @ref LL_ADC_CHANNEL_16
8155 * @arg @ref LL_ADC_CHANNEL_17
8156 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8157 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8158 *
8159 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8160 * @retval Value between Min_Data=0 and Max_Data=18
8161 */
8162 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
8163 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
8164
8165 /**
8166 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
8167 * from number in decimal format.
8168 * @note Example:
8169 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
8170 * will return a data equivalent to "LL_ADC_CHANNEL_4".
8171 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
8172 * @retval Returned value can be one of the following values:
8173 * @arg @ref LL_ADC_CHANNEL_0
8174 * @arg @ref LL_ADC_CHANNEL_1
8175 * @arg @ref LL_ADC_CHANNEL_2
8176 * @arg @ref LL_ADC_CHANNEL_3
8177 * @arg @ref LL_ADC_CHANNEL_4
8178 * @arg @ref LL_ADC_CHANNEL_5
8179 * @arg @ref LL_ADC_CHANNEL_6
8180 * @arg @ref LL_ADC_CHANNEL_7
8181 * @arg @ref LL_ADC_CHANNEL_8
8182 * @arg @ref LL_ADC_CHANNEL_9
8183 * @arg @ref LL_ADC_CHANNEL_10
8184 * @arg @ref LL_ADC_CHANNEL_11
8185 * @arg @ref LL_ADC_CHANNEL_12
8186 * @arg @ref LL_ADC_CHANNEL_13
8187 * @arg @ref LL_ADC_CHANNEL_14
8188 * @arg @ref LL_ADC_CHANNEL_15
8189 * @arg @ref LL_ADC_CHANNEL_16
8190 * @arg @ref LL_ADC_CHANNEL_17
8191 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8192 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8193 *
8194 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
8195 * (1) For ADC channel read back from ADC register,
8196 * comparison with internal channel parameter to be done
8197 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
8198 */
8199 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
8200 (((__DECIMAL_NB__) <= 9U) \
8201 ? ( \
8202 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
8203 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
8204 ) \
8205 : \
8206 ( \
8207 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
8208 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
8209 ) \
8210 )
8211
8212 /**
8213 * @brief Helper macro to determine whether the selected channel
8214 * corresponds to literal definitions of driver.
8215 * @note The different literal definitions of ADC channels are:
8216 * - ADC internal channel:
8217 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
8218 * - ADC external channel (channel connected to a GPIO pin):
8219 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
8220 * @note The channel parameter must be a value defined from literal
8221 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8222 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8223 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
8224 * must not be a value from functions where a channel number is
8225 * returned from ADC registers,
8226 * because internal and external channels share the same channel
8227 * number in ADC registers. The differentiation is made only with
8228 * parameters definitions of driver.
8229 * @param __CHANNEL__ This parameter can be one of the following values:
8230 * @arg @ref LL_ADC_CHANNEL_0
8231 * @arg @ref LL_ADC_CHANNEL_1
8232 * @arg @ref LL_ADC_CHANNEL_2
8233 * @arg @ref LL_ADC_CHANNEL_3
8234 * @arg @ref LL_ADC_CHANNEL_4
8235 * @arg @ref LL_ADC_CHANNEL_5
8236 * @arg @ref LL_ADC_CHANNEL_6
8237 * @arg @ref LL_ADC_CHANNEL_7
8238 * @arg @ref LL_ADC_CHANNEL_8
8239 * @arg @ref LL_ADC_CHANNEL_9
8240 * @arg @ref LL_ADC_CHANNEL_10
8241 * @arg @ref LL_ADC_CHANNEL_11
8242 * @arg @ref LL_ADC_CHANNEL_12
8243 * @arg @ref LL_ADC_CHANNEL_13
8244 * @arg @ref LL_ADC_CHANNEL_14
8245 * @arg @ref LL_ADC_CHANNEL_15
8246 * @arg @ref LL_ADC_CHANNEL_16
8247 * @arg @ref LL_ADC_CHANNEL_17
8248 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8249 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8250 *
8251 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8252 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
8253 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel
8254 */
8255 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
8256 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
8257
8258 /**
8259 * @brief Helper macro to convert a channel defined from parameter
8260 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8261 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8262 * to its equivalent parameter definition of a ADC external channel
8263 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
8264 * @note The channel parameter can be, additionally to a value
8265 * defined from parameter definition of a ADC internal channel
8266 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
8267 * a value defined from parameter definition of
8268 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
8269 * or a value from functions where a channel number is returned
8270 * from ADC registers.
8271 * @param __CHANNEL__ This parameter can be one of the following values:
8272 * @arg @ref LL_ADC_CHANNEL_0
8273 * @arg @ref LL_ADC_CHANNEL_1
8274 * @arg @ref LL_ADC_CHANNEL_2
8275 * @arg @ref LL_ADC_CHANNEL_3
8276 * @arg @ref LL_ADC_CHANNEL_4
8277 * @arg @ref LL_ADC_CHANNEL_5
8278 * @arg @ref LL_ADC_CHANNEL_6
8279 * @arg @ref LL_ADC_CHANNEL_7
8280 * @arg @ref LL_ADC_CHANNEL_8
8281 * @arg @ref LL_ADC_CHANNEL_9
8282 * @arg @ref LL_ADC_CHANNEL_10
8283 * @arg @ref LL_ADC_CHANNEL_11
8284 * @arg @ref LL_ADC_CHANNEL_12
8285 * @arg @ref LL_ADC_CHANNEL_13
8286 * @arg @ref LL_ADC_CHANNEL_14
8287 * @arg @ref LL_ADC_CHANNEL_15
8288 * @arg @ref LL_ADC_CHANNEL_16
8289 * @arg @ref LL_ADC_CHANNEL_17
8290 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8291 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8292 *
8293 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8294 * @retval Returned value can be one of the following values:
8295 * @arg @ref LL_ADC_CHANNEL_0
8296 * @arg @ref LL_ADC_CHANNEL_1
8297 * @arg @ref LL_ADC_CHANNEL_2
8298 * @arg @ref LL_ADC_CHANNEL_3
8299 * @arg @ref LL_ADC_CHANNEL_4
8300 * @arg @ref LL_ADC_CHANNEL_5
8301 * @arg @ref LL_ADC_CHANNEL_6
8302 * @arg @ref LL_ADC_CHANNEL_7
8303 * @arg @ref LL_ADC_CHANNEL_8
8304 * @arg @ref LL_ADC_CHANNEL_9
8305 * @arg @ref LL_ADC_CHANNEL_10
8306 * @arg @ref LL_ADC_CHANNEL_11
8307 * @arg @ref LL_ADC_CHANNEL_12
8308 * @arg @ref LL_ADC_CHANNEL_13
8309 * @arg @ref LL_ADC_CHANNEL_14
8310 * @arg @ref LL_ADC_CHANNEL_15
8311 * @arg @ref LL_ADC_CHANNEL_16
8312 * @arg @ref LL_ADC_CHANNEL_17
8313 */
8314 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
8315 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
8316
8317 /**
8318 * @brief Helper macro to determine whether the internal channel
8319 * selected is available on the ADC instance selected.
8320 * @note The channel parameter must be a value defined from parameter
8321 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
8322 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
8323 * must not be a value defined from parameter definition of
8324 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
8325 * or a value from functions where a channel number is
8326 * returned from ADC registers,
8327 * because internal and external channels share the same channel
8328 * number in ADC registers. The differentiation is made only with
8329 * parameters definitions of driver.
8330 * @param __ADC_INSTANCE__ ADC instance
8331 * @param __CHANNEL__ This parameter can be one of the following values:
8332 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8333 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8334 *
8335 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8336 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
8337 * Value "1" if the internal channel selected is available on the ADC instance selected.
8338 */
8339 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
8340 (((__ADC_INSTANCE__) == ADC1) \
8341 ? ( \
8342 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
8343 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
8344 ) \
8345 : \
8346 (0U) \
8347 )
8348
8349 /**
8350 * @brief Helper macro to define ADC analog watchdog parameter:
8351 * define a single channel to monitor with analog watchdog
8352 * from sequencer channel and groups definition.
8353 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
8354 * Example:
8355 * LL_ADC_SetAnalogWDMonitChannels(
8356 * ADC1, LL_ADC_AWD1,
8357 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
8358 * @param __CHANNEL__ This parameter can be one of the following values:
8359 * @arg @ref LL_ADC_CHANNEL_0
8360 * @arg @ref LL_ADC_CHANNEL_1
8361 * @arg @ref LL_ADC_CHANNEL_2
8362 * @arg @ref LL_ADC_CHANNEL_3
8363 * @arg @ref LL_ADC_CHANNEL_4
8364 * @arg @ref LL_ADC_CHANNEL_5
8365 * @arg @ref LL_ADC_CHANNEL_6
8366 * @arg @ref LL_ADC_CHANNEL_7
8367 * @arg @ref LL_ADC_CHANNEL_8
8368 * @arg @ref LL_ADC_CHANNEL_9
8369 * @arg @ref LL_ADC_CHANNEL_10
8370 * @arg @ref LL_ADC_CHANNEL_11
8371 * @arg @ref LL_ADC_CHANNEL_12
8372 * @arg @ref LL_ADC_CHANNEL_13
8373 * @arg @ref LL_ADC_CHANNEL_14
8374 * @arg @ref LL_ADC_CHANNEL_15
8375 * @arg @ref LL_ADC_CHANNEL_16
8376 * @arg @ref LL_ADC_CHANNEL_17
8377 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
8378 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
8379 *
8380 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
8381 * (1) For ADC channel read back from ADC register,
8382 * comparison with internal channel parameter to be done
8383 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
8384 * @param __GROUP__ This parameter can be one of the following values:
8385 * @arg @ref LL_ADC_GROUP_REGULAR
8386 * @arg @ref LL_ADC_GROUP_INJECTED
8387 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
8388 * @retval Returned value can be one of the following values:
8389 * @arg @ref LL_ADC_AWD_DISABLE
8390 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
8391 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
8392 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
8393 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
8394 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
8395 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
8396 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
8397 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
8398 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
8399 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
8400 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
8401 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
8402 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
8403 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
8404 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
8405 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
8406 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
8407 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
8408 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
8409 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
8410 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
8411 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
8412 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
8413 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
8414 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
8415 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
8416 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
8417 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
8418 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
8419 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
8420 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
8421 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
8422 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
8423 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
8424 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
8425 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
8426 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
8427 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
8428 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
8429 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
8430 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
8431 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
8432 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
8433 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
8434 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
8435 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
8436 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
8437 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
8438 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
8439 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
8440 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
8441 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
8442 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
8443 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
8444 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
8445 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
8446 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
8447 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
8448 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
8449 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
8450 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
8451 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
8452 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
8453 *
8454 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
8455 */
8456 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
8457 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
8458 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
8459 : \
8460 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
8461 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
8462 : \
8463 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
8464 )
8465
8466 /**
8467 * @brief Helper macro to set the value of ADC analog watchdog threshold high
8468 * or low in function of ADC resolution, when ADC resolution is
8469 * different of 12 bits.
8470 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
8471 * Example, with a ADC resolution of 8 bits, to set the value of
8472 * analog watchdog threshold high (on 8 bits):
8473 * LL_ADC_SetAnalogWDThresholds
8474 * (< ADCx param >,
8475 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
8476 * );
8477 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8478 * @arg @ref LL_ADC_RESOLUTION_12B
8479 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
8480 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8481 */
8482 /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
8483 /* This macro has been kept anyway for compatibility with other */
8484 /* STM32 families featuring different ADC resolutions. */
8485 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
8486 ((__AWD_THRESHOLD__) << (0U))
8487
8488 /**
8489 * @brief Helper macro to get the value of ADC analog watchdog threshold high
8490 * or low in function of ADC resolution, when ADC resolution is
8491 * different of 12 bits.
8492 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
8493 * Example, with a ADC resolution of 8 bits, to get the value of
8494 * analog watchdog threshold high (on 8 bits):
8495 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
8496 * (LL_ADC_RESOLUTION_8B,
8497 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
8498 * );
8499 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8500 * @arg @ref LL_ADC_RESOLUTION_12B
8501 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
8502 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
8503 */
8504 /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
8505 /* This macro has been kept anyway for compatibility with other */
8506 /* STM32 families featuring different ADC resolutions. */
8507 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
8508 (__AWD_THRESHOLD_12_BITS__)
8509
8510 /**
8511 * @brief Helper macro to select the ADC common instance
8512 * to which is belonging the selected ADC instance.
8513 * @note ADC common register instance can be used for:
8514 * - Set parameters common to several ADC instances
8515 * - Multimode (for devices with several ADC instances)
8516 * Refer to functions having argument "ADCxy_COMMON" as parameter.
8517 * @note On STM32F37x, there is no common ADC instance.
8518 * However, ADC instance ADC1 has a role of common ADC instance
8519 * (equivalence with other STM32 families featuring several
8520 * ADC instances).
8521 * @param __ADCx__ ADC instance
8522 * @retval ADC common register instance
8523 */
8524 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
8525 (ADC1_COMMON)
8526
8527 /**
8528 * @brief Helper macro to check if all ADC instances sharing the same
8529 * ADC common instance are disabled.
8530 * @note This check is required by functions with setting conditioned to
8531 * ADC state:
8532 * All ADC instances of the ADC common group must be disabled.
8533 * Refer to functions having argument "ADCxy_COMMON" as parameter.
8534 * @note On devices with only 1 ADC common instance, parameter of this macro
8535 * is useless and can be ignored (parameter kept for compatibility
8536 * with devices featuring several ADC common instances).
8537 * @note On STM32F37x, there is no common ADC instance.
8538 * However, ADC instance ADC1 has a role of common ADC instance
8539 * (equivalence with other STM32 families featuring several
8540 * ADC instances).
8541 * @param __ADCXY_COMMON__ ADC common instance
8542 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8543 * @retval Value "0" All ADC instances sharing the same ADC common instance
8544 * are disabled.
8545 * Value "1" At least one ADC instance sharing the same ADC common instance
8546 * is enabled
8547 */
8548 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
8549 LL_ADC_IsEnabled(ADC1)
8550
8551 /**
8552 * @brief Helper macro to define the ADC conversion data full-scale digital
8553 * value corresponding to the selected ADC resolution.
8554 * @note ADC conversion data full-scale corresponds to voltage range
8555 * determined by analog voltage references Vref+ and Vref-
8556 * (refer to reference manual).
8557 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8558 * @arg @ref LL_ADC_RESOLUTION_12B
8559 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
8560 */
8561 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
8562 ((uint32_t)0xFFFU)
8563
8564 /**
8565 * @brief Helper macro to convert the ADC conversion data from
8566 * a resolution to another resolution.
8567 * @note On STM32F37x, the only ADC resolution available is 12 bits.
8568 * This macro has been kept for compatibility purpose over other
8569 * STM32 families.
8570 * @param __DATA__ ADC conversion data to be converted
8571 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
8572 * This parameter can be one of the following values:
8573 * @arg @ref LL_ADC_RESOLUTION_12B
8574 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
8575 * This parameter can be one of the following values:
8576 * @arg @ref LL_ADC_RESOLUTION_12B
8577 * @retval ADC conversion data to the requested resolution
8578 */
8579 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
8580 __ADC_RESOLUTION_CURRENT__,\
8581 __ADC_RESOLUTION_TARGET__) \
8582 (((__DATA__) \
8583 << ((__ADC_RESOLUTION_CURRENT__) >> (0U))) \
8584 >> ((__ADC_RESOLUTION_TARGET__) >> (0U)) \
8585 )
8586
8587 /**
8588 * @brief Helper macro to calculate the voltage (unit: mVolt)
8589 * corresponding to a ADC conversion data (unit: digital value).
8590 * @note Analog reference voltage (Vref+) must be either known from
8591 * user board environment or can be calculated using ADC measurement
8592 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8593 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
8594 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
8595 * (unit: digital value).
8596 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8597 * @arg @ref LL_ADC_RESOLUTION_12B
8598 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
8599 */
8600 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
8601 __ADC_DATA__,\
8602 __ADC_RESOLUTION__) \
8603 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
8604 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
8605 )
8606
8607
8608 /**
8609 * @brief Helper macro to calculate analog reference voltage (Vref+)
8610 * (unit: mVolt) from ADC conversion data of internal voltage
8611 * reference VrefInt.
8612 * @note Computation is using VrefInt calibration value
8613 * stored in system memory for each device during production.
8614 * @note This voltage depends on user board environment: voltage level
8615 * connected to pin Vref+.
8616 * On devices with small package, the pin Vref+ is not present
8617 * and internally bonded to pin Vdda.
8618 * @note On this STM32 series, calibration data of internal voltage reference
8619 * VrefInt corresponds to a resolution of 12 bits,
8620 * this is the recommended ADC resolution to convert voltage of
8621 * internal voltage reference VrefInt.
8622 * On STM32F37x, the only ADC resolution available is 12 bits.
8623 * The parameter of ADC resolution is kept for compatibility purpose
8624 * over other STM32 families.
8625 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
8626 * of internal voltage reference VrefInt (unit: digital value).
8627 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
8628 * @arg @ref LL_ADC_RESOLUTION_12B
8629 * @retval Analog reference voltage (unit: mV)
8630 */
8631 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
8632 __ADC_RESOLUTION__) \
8633 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
8634 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
8635 (__ADC_RESOLUTION__), \
8636 LL_ADC_RESOLUTION_12B) \
8637 )
8638
8639 /**
8640 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
8641 * from ADC conversion data of internal temperature sensor.
8642 * @note Computation is using temperature sensor calibration values
8643 * stored in system memory for each device during production.
8644 * @note Calculation formula:
8645 * Temperature = ((TS_ADC_DATA - TS_CAL1)
8646 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
8647 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
8648 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8649 * Avg_Slope = (TS_CAL2 - TS_CAL1)
8650 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
8651 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
8652 * TEMP_DEGC_CAL1 (calibrated in factory)
8653 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
8654 * TEMP_DEGC_CAL2 (calibrated in factory)
8655 * Caution: Calculation relevancy under reserve that calibration
8656 * parameters are correct (address and data).
8657 * To calculate temperature using temperature sensor
8658 * datasheet typical values (generic values less, therefore
8659 * less accurate than calibrated values),
8660 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
8661 * @note As calculation input, the analog reference voltage (Vref+) must be
8662 * defined as it impacts the ADC LSB equivalent voltage.
8663 * @note Analog reference voltage (Vref+) must be either known from
8664 * user board environment or can be calculated using ADC measurement
8665 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8666 * @note On this STM32 series, calibration data of temperature sensor
8667 * corresponds to a resolution of 12 bits,
8668 * this is the recommended ADC resolution to convert voltage of
8669 * temperature sensor.
8670 * On STM32F37x, the only ADC resolution available is 12 bits.
8671 * The parameter of ADC resolution is kept for compatibility purpose
8672 * over other STM32 families.
8673 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
8674 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
8675 * temperature sensor (unit: digital value).
8676 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
8677 * sensor voltage has been measured.
8678 * This parameter can be one of the following values:
8679 * @arg @ref LL_ADC_RESOLUTION_12B
8680 * @retval Temperature (unit: degree Celsius)
8681 */
8682 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
8683 __TEMPSENSOR_ADC_DATA__,\
8684 __ADC_RESOLUTION__) \
8685 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
8686 (__ADC_RESOLUTION__), \
8687 LL_ADC_RESOLUTION_12B) \
8688 * (__VREFANALOG_VOLTAGE__)) \
8689 / TEMPSENSOR_CAL_VREFANALOG) \
8690 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
8691 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
8692 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
8693 ) + TEMPSENSOR_CAL1_TEMP \
8694 )
8695
8696 /**
8697 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
8698 * from ADC conversion data of internal temperature sensor.
8699 * @note Computation is using temperature sensor typical values
8700 * (refer to device datasheet).
8701 * @note Calculation formula:
8702 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
8703 * / Avg_Slope + CALx_TEMP
8704 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8705 * (unit: digital value)
8706 * Avg_Slope = temperature sensor slope
8707 * (unit: uV/Degree Celsius)
8708 * TS_TYP_CALx_VOLT = temperature sensor digital value at
8709 * temperature CALx_TEMP (unit: mV)
8710 * Caution: Calculation relevancy under reserve the temperature sensor
8711 * of the current device has characteristics in line with
8712 * datasheet typical values.
8713 * If temperature sensor calibration values are available on
8714 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
8715 * temperature calculation will be more accurate using
8716 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
8717 * @note As calculation input, the analog reference voltage (Vref+) must be
8718 * defined as it impacts the ADC LSB equivalent voltage.
8719 * @note Analog reference voltage (Vref+) must be either known from
8720 * user board environment or can be calculated using ADC measurement
8721 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
8722 * @note ADC measurement data must correspond to a resolution of 12bits
8723 * (full scale digital value 4095). If not the case, the data must be
8724 * preliminarily rescaled to an equivalent resolution of 12 bits.
8725 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
8726 * On STM32F37x, refer to device datasheet parameter "Avg_Slope".
8727 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
8728 * On STM32F37x, refer to device datasheet parameter "V25".
8729 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: degC)
8730 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
8731 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
8732 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
8733 * This parameter can be one of the following values:
8734 * @arg @ref LL_ADC_RESOLUTION_12B
8735 * @retval Temperature (unit: degree Celsius)
8736 */
8737 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
8738 __TEMPSENSOR_TYP_CALX_V__,\
8739 __TEMPSENSOR_CALX_TEMP__,\
8740 __VREFANALOG_VOLTAGE__,\
8741 __TEMPSENSOR_ADC_DATA__,\
8742 __ADC_RESOLUTION__) \
8743 ((( ( \
8744 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
8745 * 1000) \
8746 - \
8747 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
8748 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
8749 * 1000) \
8750 ) \
8751 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
8752 ) + (__TEMPSENSOR_CALX_TEMP__) \
8753 )
8754
8755 /**
8756 * @}
8757 */
8758
8759 /**
8760 * @}
8761 */
8762
8763
8764 /* Exported functions --------------------------------------------------------*/
8765 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
8766 * @{
8767 */
8768
8769 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
8770 * @{
8771 */
8772 /* Note: LL ADC functions to set DMA transfer are located into sections of */
8773 /* configuration of ADC instance, groups and multimode (if available): */
8774 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
8775
8776 /**
8777 * @brief Function to help to configure DMA transfer from ADC: retrieve the
8778 * ADC register address from ADC instance and a list of ADC registers
8779 * intended to be used (most commonly) with DMA transfer.
8780 * @note These ADC registers are data registers:
8781 * when ADC conversion data is available in ADC data registers,
8782 * ADC generates a DMA transfer request.
8783 * @note This macro is intended to be used with LL DMA driver, refer to
8784 * function "LL_DMA_ConfigAddresses()".
8785 * Example:
8786 * LL_DMA_ConfigAddresses(DMA1,
8787 * LL_DMA_CHANNEL_1,
8788 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
8789 * (uint32_t)&< array or variable >,
8790 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
8791 * @note For devices with several ADC: in multimode, some devices
8792 * use a different data register outside of ADC instance scope
8793 * (common data register). This macro manages this register difference,
8794 * only ADC instance has to be set as parameter.
8795 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
8796 * @param ADCx ADC instance
8797 * @param Register This parameter can be one of the following values:
8798 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
8799 * @retval ADC register address
8800 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)8801 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
8802 {
8803 /* Prevent unused argument compilation warning */
8804 (void)Register;
8805
8806 /* Retrieve address of register DR */
8807 return (uint32_t)&(ADCx->DR);
8808 }
8809
8810 /**
8811 * @}
8812 */
8813
8814 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
8815 * @{
8816 */
8817
8818 /**
8819 * @brief Set parameter common to several ADC: measurement path to internal
8820 * channels (VrefInt, temperature sensor, ...).
8821 * @note One or several values can be selected.
8822 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
8823 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
8824 * @note Stabilization time of measurement path to internal channel:
8825 * After enabling internal paths, before starting ADC conversion,
8826 * a delay is required for internal voltage reference and
8827 * temperature sensor stabilization time.
8828 * Refer to device datasheet.
8829 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
8830 * @note ADC internal channel sampling time constraint:
8831 * For ADC conversion of internal channels,
8832 * a sampling time minimum value is required.
8833 * Refer to device datasheet.
8834 * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
8835 * @param ADCxy_COMMON ADC common instance
8836 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8837 * @param PathInternal This parameter can be a combination of the following values:
8838 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
8839 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
8840 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
8841 * @retval None
8842 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)8843 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
8844 {
8845 MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
8846 }
8847
8848 /**
8849 * @brief Get parameter common to several ADC: measurement path to internal
8850 * channels (VrefInt, temperature sensor, ...).
8851 * @note One or several values can be selected.
8852 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
8853 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
8854 * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
8855 * @param ADCxy_COMMON ADC common instance
8856 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
8857 * @retval Returned value can be a combination of the following values:
8858 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
8859 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
8860 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
8861 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)8862 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
8863 {
8864 return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
8865 }
8866
8867 /**
8868 * @}
8869 */
8870
8871 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
8872 * @{
8873 */
8874
8875 /**
8876 * @brief Set ADC conversion data alignment.
8877 * @note Refer to reference manual for alignments formats
8878 * dependencies to ADC resolutions.
8879 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
8880 * @param ADCx ADC instance
8881 * @param DataAlignment This parameter can be one of the following values:
8882 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
8883 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
8884 * @retval None
8885 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)8886 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
8887 {
8888 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
8889 }
8890
8891 /**
8892 * @brief Get ADC conversion data alignment.
8893 * @note Refer to reference manual for alignments formats
8894 * dependencies to ADC resolutions.
8895 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
8896 * @param ADCx ADC instance
8897 * @retval Returned value can be one of the following values:
8898 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
8899 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
8900 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)8901 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
8902 {
8903 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
8904 }
8905
8906 /**
8907 * @brief Set ADC sequencers scan mode, for all ADC groups
8908 * (group regular, group injected).
8909 * @note According to sequencers scan mode :
8910 * - If disabled: ADC conversion is performed in unitary conversion
8911 * mode (one channel converted, that defined in rank 1).
8912 * Configuration of sequencers of all ADC groups
8913 * (sequencer scan length, ...) is discarded: equivalent to
8914 * scan length of 1 rank.
8915 * - If enabled: ADC conversions are performed in sequence conversions
8916 * mode, according to configuration of sequencers of
8917 * each ADC group (sequencer scan length, ...).
8918 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
8919 * and to function @ref LL_ADC_INJ_SetSequencerLength().
8920 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
8921 * @param ADCx ADC instance
8922 * @param ScanMode This parameter can be one of the following values:
8923 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
8924 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
8925 * @retval None
8926 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)8927 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
8928 {
8929 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
8930 }
8931
8932 /**
8933 * @brief Get ADC sequencers scan mode, for all ADC groups
8934 * (group regular, group injected).
8935 * @note According to sequencers scan mode :
8936 * - If disabled: ADC conversion is performed in unitary conversion
8937 * mode (one channel converted, that defined in rank 1).
8938 * Configuration of sequencers of all ADC groups
8939 * (sequencer scan length, ...) is discarded: equivalent to
8940 * scan length of 1 rank.
8941 * - If enabled: ADC conversions are performed in sequence conversions
8942 * mode, according to configuration of sequencers of
8943 * each ADC group (sequencer scan length, ...).
8944 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
8945 * and to function @ref LL_ADC_INJ_SetSequencerLength().
8946 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
8947 * @param ADCx ADC instance
8948 * @retval Returned value can be one of the following values:
8949 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
8950 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
8951 */
LL_ADC_GetSequencersScanMode(ADC_TypeDef * ADCx)8952 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
8953 {
8954 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
8955 }
8956
8957 /**
8958 * @}
8959 */
8960
8961 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
8962 * @{
8963 */
8964
8965 /**
8966 * @brief Set ADC group regular conversion trigger source:
8967 * internal (SW start) or external from timer or external interrupt.
8968 * @note On this STM32 series, external trigger is set with trigger polarity:
8969 * rising edge (only trigger polarity available on this STM32 series).
8970 * @note Availability of parameters of trigger sources from timer
8971 * depends on timers availability on the selected device.
8972 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
8973 * @param ADCx ADC instance
8974 * @param TriggerSource This parameter can be one of the following values:
8975 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
8976 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
8977 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
8978 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
8979 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
8980 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
8981 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
8982 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
8983 * @retval None
8984 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)8985 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
8986 {
8987 /* Note: On this STM32 series, ADC group regular external trigger edge */
8988 /* is used to perform a ADC conversion start. */
8989 /* This function does not set external trigger edge. */
8990 /* This feature is set using function */
8991 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
8992 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
8993 }
8994
8995 /**
8996 * @brief Get ADC group regular conversion trigger source:
8997 * internal (SW start) or external from timer or external interrupt.
8998 * @note To determine whether group regular trigger source is
8999 * internal (SW start) or external, without detail
9000 * of which peripheral is selected as external trigger,
9001 * (equivalent to
9002 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
9003 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
9004 * @note Availability of parameters of trigger sources from timer
9005 * depends on timers availability on the selected device.
9006 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
9007 * @param ADCx ADC instance
9008 * @retval Returned value can be one of the following values:
9009 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
9010 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
9011 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
9012 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
9013 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
9014 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
9015 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
9016 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
9017 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)9018 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
9019 {
9020 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
9021 }
9022
9023 /**
9024 * @brief Get ADC group regular conversion trigger source internal (SW start)
9025 or external.
9026 * @note In case of group regular trigger source set to external trigger,
9027 * to determine which peripheral is selected as external trigger,
9028 * use function @ref LL_ADC_REG_GetTriggerSource().
9029 * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
9030 * @param ADCx ADC instance
9031 * @retval Value "0" trigger source external trigger
9032 * Value "1" trigger source SW start.
9033 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)9034 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
9035 {
9036 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
9037 }
9038
9039
9040 /**
9041 * @brief Set ADC group regular sequencer length and scan direction.
9042 * @note Description of ADC group regular sequencer features:
9043 * - For devices with sequencer fully configurable
9044 * (function "LL_ADC_REG_SetSequencerRanks()" available):
9045 * sequencer length and each rank affectation to a channel
9046 * are configurable.
9047 * This function performs configuration of:
9048 * - Sequence length: Number of ranks in the scan sequence.
9049 * - Sequence direction: Unless specified in parameters, sequencer
9050 * scan direction is forward (from rank 1 to rank n).
9051 * Sequencer ranks are selected using
9052 * function "LL_ADC_REG_SetSequencerRanks()".
9053 * - For devices with sequencer not fully configurable
9054 * (function "LL_ADC_REG_SetSequencerChannels()" available):
9055 * sequencer length and each rank affectation to a channel
9056 * are defined by channel number.
9057 * This function performs configuration of:
9058 * - Sequence length: Number of ranks in the scan sequence is
9059 * defined by number of channels set in the sequence,
9060 * rank of each channel is fixed by channel HW number.
9061 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
9062 * - Sequence direction: Unless specified in parameters, sequencer
9063 * scan direction is forward (from lowest channel number to
9064 * highest channel number).
9065 * Sequencer ranks are selected using
9066 * function "LL_ADC_REG_SetSequencerChannels()".
9067 * @note On this STM32 series, group regular sequencer configuration
9068 * is conditioned to ADC instance sequencer mode.
9069 * If ADC instance sequencer mode is disabled, sequencers of
9070 * all groups (group regular, group injected) can be configured
9071 * but their execution is disabled (limited to rank 1).
9072 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9073 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9074 * ADC conversion on only 1 channel.
9075 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
9076 * @param ADCx ADC instance
9077 * @param SequencerNbRanks This parameter can be one of the following values:
9078 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
9079 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
9080 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
9081 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
9082 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
9083 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
9084 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
9085 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
9086 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
9087 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
9088 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
9089 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
9090 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
9091 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
9092 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
9093 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
9094 * @retval None
9095 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)9096 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
9097 {
9098 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
9099 }
9100
9101 /**
9102 * @brief Get ADC group regular sequencer length and scan direction.
9103 * @note Description of ADC group regular sequencer features:
9104 * - For devices with sequencer fully configurable
9105 * (function "LL_ADC_REG_SetSequencerRanks()" available):
9106 * sequencer length and each rank affectation to a channel
9107 * are configurable.
9108 * This function retrieves:
9109 * - Sequence length: Number of ranks in the scan sequence.
9110 * - Sequence direction: Unless specified in parameters, sequencer
9111 * scan direction is forward (from rank 1 to rank n).
9112 * Sequencer ranks are selected using
9113 * function "LL_ADC_REG_SetSequencerRanks()".
9114 * - For devices with sequencer not fully configurable
9115 * (function "LL_ADC_REG_SetSequencerChannels()" available):
9116 * sequencer length and each rank affectation to a channel
9117 * are defined by channel number.
9118 * This function retrieves:
9119 * - Sequence length: Number of ranks in the scan sequence is
9120 * defined by number of channels set in the sequence,
9121 * rank of each channel is fixed by channel HW number.
9122 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
9123 * - Sequence direction: Unless specified in parameters, sequencer
9124 * scan direction is forward (from lowest channel number to
9125 * highest channel number).
9126 * Sequencer ranks are selected using
9127 * function "LL_ADC_REG_SetSequencerChannels()".
9128 * @note On this STM32 series, group regular sequencer configuration
9129 * is conditioned to ADC instance sequencer mode.
9130 * If ADC instance sequencer mode is disabled, sequencers of
9131 * all groups (group regular, group injected) can be configured
9132 * but their execution is disabled (limited to rank 1).
9133 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9134 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9135 * ADC conversion on only 1 channel.
9136 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
9137 * @param ADCx ADC instance
9138 * @retval Returned value can be one of the following values:
9139 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
9140 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
9141 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
9142 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
9143 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
9144 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
9145 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
9146 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
9147 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
9148 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
9149 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
9150 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
9151 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
9152 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
9153 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
9154 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
9155 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)9156 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
9157 {
9158 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
9159 }
9160
9161 /**
9162 * @brief Set ADC group regular sequencer discontinuous mode:
9163 * sequence subdivided and scan conversions interrupted every selected
9164 * number of ranks.
9165 * @note It is not possible to enable both ADC group regular
9166 * continuous mode and sequencer discontinuous mode.
9167 * @note It is not possible to enable both ADC auto-injected mode
9168 * and ADC group regular sequencer discontinuous mode.
9169 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
9170 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
9171 * @param ADCx ADC instance
9172 * @param SeqDiscont This parameter can be one of the following values:
9173 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
9174 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
9175 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
9176 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
9177 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
9178 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
9179 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
9180 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
9181 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
9182 * @retval None
9183 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)9184 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
9185 {
9186 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
9187 }
9188
9189 /**
9190 * @brief Get ADC group regular sequencer discontinuous mode:
9191 * sequence subdivided and scan conversions interrupted every selected
9192 * number of ranks.
9193 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
9194 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
9195 * @param ADCx ADC instance
9196 * @retval Returned value can be one of the following values:
9197 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
9198 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
9199 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
9200 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
9201 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
9202 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
9203 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
9204 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
9205 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
9206 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)9207 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
9208 {
9209 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
9210 }
9211
9212 /**
9213 * @brief Set ADC group regular sequence: channel on the selected
9214 * scan sequence rank.
9215 * @note This function performs configuration of:
9216 * - Channels ordering into each rank of scan sequence:
9217 * whatever channel can be placed into whatever rank.
9218 * @note On this STM32 series, ADC group regular sequencer is
9219 * fully configurable: sequencer length and each rank
9220 * affectation to a channel are configurable.
9221 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
9222 * @note Depending on devices and packages, some channels may not be available.
9223 * Refer to device datasheet for channels availability.
9224 * @note On this STM32 series, to measure internal channels (VrefInt,
9225 * TempSensor, ...), measurement paths to internal channels must be
9226 * enabled separately.
9227 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
9228 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
9229 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
9230 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
9231 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
9232 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
9233 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
9234 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
9235 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
9236 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
9237 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
9238 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
9239 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
9240 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
9241 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
9242 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
9243 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
9244 * @param ADCx ADC instance
9245 * @param Rank This parameter can be one of the following values:
9246 * @arg @ref LL_ADC_REG_RANK_1
9247 * @arg @ref LL_ADC_REG_RANK_2
9248 * @arg @ref LL_ADC_REG_RANK_3
9249 * @arg @ref LL_ADC_REG_RANK_4
9250 * @arg @ref LL_ADC_REG_RANK_5
9251 * @arg @ref LL_ADC_REG_RANK_6
9252 * @arg @ref LL_ADC_REG_RANK_7
9253 * @arg @ref LL_ADC_REG_RANK_8
9254 * @arg @ref LL_ADC_REG_RANK_9
9255 * @arg @ref LL_ADC_REG_RANK_10
9256 * @arg @ref LL_ADC_REG_RANK_11
9257 * @arg @ref LL_ADC_REG_RANK_12
9258 * @arg @ref LL_ADC_REG_RANK_13
9259 * @arg @ref LL_ADC_REG_RANK_14
9260 * @arg @ref LL_ADC_REG_RANK_15
9261 * @arg @ref LL_ADC_REG_RANK_16
9262 * @param Channel This parameter can be one of the following values:
9263 * @arg @ref LL_ADC_CHANNEL_0
9264 * @arg @ref LL_ADC_CHANNEL_1
9265 * @arg @ref LL_ADC_CHANNEL_2
9266 * @arg @ref LL_ADC_CHANNEL_3
9267 * @arg @ref LL_ADC_CHANNEL_4
9268 * @arg @ref LL_ADC_CHANNEL_5
9269 * @arg @ref LL_ADC_CHANNEL_6
9270 * @arg @ref LL_ADC_CHANNEL_7
9271 * @arg @ref LL_ADC_CHANNEL_8
9272 * @arg @ref LL_ADC_CHANNEL_9
9273 * @arg @ref LL_ADC_CHANNEL_10
9274 * @arg @ref LL_ADC_CHANNEL_11
9275 * @arg @ref LL_ADC_CHANNEL_12
9276 * @arg @ref LL_ADC_CHANNEL_13
9277 * @arg @ref LL_ADC_CHANNEL_14
9278 * @arg @ref LL_ADC_CHANNEL_15
9279 * @arg @ref LL_ADC_CHANNEL_16
9280 * @arg @ref LL_ADC_CHANNEL_17
9281 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9282 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9283 *
9284 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9285 * @retval None
9286 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)9287 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
9288 {
9289 /* Set bits with content of parameter "Channel" with bits position */
9290 /* in register and register position depending on parameter "Rank". */
9291 /* Parameters "Rank" and "Channel" are used with masks because containing */
9292 /* other bits reserved for other purpose. */
9293 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
9294
9295 MODIFY_REG(*preg,
9296 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
9297 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
9298 }
9299
9300 /**
9301 * @brief Get ADC group regular sequence: channel on the selected
9302 * scan sequence rank.
9303 * @note On this STM32 series, ADC group regular sequencer is
9304 * fully configurable: sequencer length and each rank
9305 * affectation to a channel are configurable.
9306 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
9307 * @note Depending on devices and packages, some channels may not be available.
9308 * Refer to device datasheet for channels availability.
9309 * @note Usage of the returned channel number:
9310 * - To reinject this channel into another function LL_ADC_xxx:
9311 * the returned channel number is only partly formatted on definition
9312 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
9313 * with parts of literals LL_ADC_CHANNEL_x or using
9314 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9315 * Then the selected literal LL_ADC_CHANNEL_x can be used
9316 * as parameter for another function.
9317 * - To get the channel number in decimal format:
9318 * process the returned value with the helper macro
9319 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9320 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
9321 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
9322 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
9323 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
9324 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
9325 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
9326 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
9327 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
9328 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
9329 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
9330 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
9331 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
9332 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
9333 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
9334 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
9335 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
9336 * @param ADCx ADC instance
9337 * @param Rank This parameter can be one of the following values:
9338 * @arg @ref LL_ADC_REG_RANK_1
9339 * @arg @ref LL_ADC_REG_RANK_2
9340 * @arg @ref LL_ADC_REG_RANK_3
9341 * @arg @ref LL_ADC_REG_RANK_4
9342 * @arg @ref LL_ADC_REG_RANK_5
9343 * @arg @ref LL_ADC_REG_RANK_6
9344 * @arg @ref LL_ADC_REG_RANK_7
9345 * @arg @ref LL_ADC_REG_RANK_8
9346 * @arg @ref LL_ADC_REG_RANK_9
9347 * @arg @ref LL_ADC_REG_RANK_10
9348 * @arg @ref LL_ADC_REG_RANK_11
9349 * @arg @ref LL_ADC_REG_RANK_12
9350 * @arg @ref LL_ADC_REG_RANK_13
9351 * @arg @ref LL_ADC_REG_RANK_14
9352 * @arg @ref LL_ADC_REG_RANK_15
9353 * @arg @ref LL_ADC_REG_RANK_16
9354 * @retval Returned value can be one of the following values:
9355 * @arg @ref LL_ADC_CHANNEL_0
9356 * @arg @ref LL_ADC_CHANNEL_1
9357 * @arg @ref LL_ADC_CHANNEL_2
9358 * @arg @ref LL_ADC_CHANNEL_3
9359 * @arg @ref LL_ADC_CHANNEL_4
9360 * @arg @ref LL_ADC_CHANNEL_5
9361 * @arg @ref LL_ADC_CHANNEL_6
9362 * @arg @ref LL_ADC_CHANNEL_7
9363 * @arg @ref LL_ADC_CHANNEL_8
9364 * @arg @ref LL_ADC_CHANNEL_9
9365 * @arg @ref LL_ADC_CHANNEL_10
9366 * @arg @ref LL_ADC_CHANNEL_11
9367 * @arg @ref LL_ADC_CHANNEL_12
9368 * @arg @ref LL_ADC_CHANNEL_13
9369 * @arg @ref LL_ADC_CHANNEL_14
9370 * @arg @ref LL_ADC_CHANNEL_15
9371 * @arg @ref LL_ADC_CHANNEL_16
9372 * @arg @ref LL_ADC_CHANNEL_17
9373 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9374 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9375 *
9376 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
9377 * (1) For ADC channel read back from ADC register,
9378 * comparison with internal channel parameter to be done
9379 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
9380 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)9381 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
9382 {
9383 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
9384
9385 return (uint32_t) (READ_BIT(*preg,
9386 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
9387 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
9388 );
9389 }
9390
9391 /**
9392 * @brief Set ADC continuous conversion mode on ADC group regular.
9393 * @note Description of ADC continuous conversion mode:
9394 * - single mode: one conversion per trigger
9395 * - continuous mode: after the first trigger, following
9396 * conversions launched successively automatically.
9397 * @note It is not possible to enable both ADC group regular
9398 * continuous mode and sequencer discontinuous mode.
9399 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
9400 * @param ADCx ADC instance
9401 * @param Continuous This parameter can be one of the following values:
9402 * @arg @ref LL_ADC_REG_CONV_SINGLE
9403 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
9404 * @retval None
9405 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)9406 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
9407 {
9408 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
9409 }
9410
9411 /**
9412 * @brief Get ADC continuous conversion mode on ADC group regular.
9413 * @note Description of ADC continuous conversion mode:
9414 * - single mode: one conversion per trigger
9415 * - continuous mode: after the first trigger, following
9416 * conversions launched successively automatically.
9417 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
9418 * @param ADCx ADC instance
9419 * @retval Returned value can be one of the following values:
9420 * @arg @ref LL_ADC_REG_CONV_SINGLE
9421 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
9422 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)9423 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
9424 {
9425 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
9426 }
9427
9428 /**
9429 * @brief Set ADC group regular conversion data transfer: no transfer or
9430 * transfer by DMA, and DMA requests mode.
9431 * @note If transfer by DMA selected, specifies the DMA requests
9432 * mode:
9433 * - Limited mode (One shot mode): DMA transfer requests are stopped
9434 * when number of DMA data transfers (number of
9435 * ADC conversions) is reached.
9436 * This ADC mode is intended to be used with DMA mode non-circular.
9437 * - Unlimited mode: DMA transfer requests are unlimited,
9438 * whatever number of DMA data transfers (number of
9439 * ADC conversions).
9440 * This ADC mode is intended to be used with DMA mode circular.
9441 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
9442 * mode non-circular:
9443 * when DMA transfers size will be reached, DMA will stop transfers of
9444 * ADC conversions data ADC will raise an overrun error
9445 * (overrun flag and interruption if enabled).
9446 * @note To configure DMA source address (peripheral address),
9447 * use function @ref LL_ADC_DMA_GetRegAddr().
9448 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
9449 * @param ADCx ADC instance
9450 * @param DMATransfer This parameter can be one of the following values:
9451 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
9452 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
9453 * @retval None
9454 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)9455 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
9456 {
9457 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
9458 }
9459
9460 /**
9461 * @brief Get ADC group regular conversion data transfer: no transfer or
9462 * transfer by DMA, and DMA requests mode.
9463 * @note If transfer by DMA selected, specifies the DMA requests
9464 * mode:
9465 * - Limited mode (One shot mode): DMA transfer requests are stopped
9466 * when number of DMA data transfers (number of
9467 * ADC conversions) is reached.
9468 * This ADC mode is intended to be used with DMA mode non-circular.
9469 * - Unlimited mode: DMA transfer requests are unlimited,
9470 * whatever number of DMA data transfers (number of
9471 * ADC conversions).
9472 * This ADC mode is intended to be used with DMA mode circular.
9473 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
9474 * mode non-circular:
9475 * when DMA transfers size will be reached, DMA will stop transfers of
9476 * ADC conversions data ADC will raise an overrun error
9477 * (overrun flag and interruption if enabled).
9478 * @note To configure DMA source address (peripheral address),
9479 * use function @ref LL_ADC_DMA_GetRegAddr().
9480 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
9481 * @param ADCx ADC instance
9482 * @retval Returned value can be one of the following values:
9483 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
9484 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
9485 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)9486 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
9487 {
9488 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
9489 }
9490
9491 /**
9492 * @}
9493 */
9494
9495 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
9496 * @{
9497 */
9498
9499 /**
9500 * @brief Set ADC group injected conversion trigger source:
9501 * internal (SW start) or external from timer or external interrupt.
9502 * @note On this STM32 series, external trigger is set with trigger polarity:
9503 * rising edge (only trigger polarity available on this STM32 series).
9504 * @note Availability of parameters of trigger sources from timer
9505 * depends on timers availability on the selected device.
9506 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
9507 * @param ADCx ADC instance
9508 * @param TriggerSource This parameter can be one of the following values:
9509 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
9510 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
9511 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
9512 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
9513 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
9514 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
9515 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
9516 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
9517 * @retval None
9518 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)9519 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
9520 {
9521 /* Note: On this STM32 series, ADC group injected external trigger edge */
9522 /* is used to perform a ADC conversion start. */
9523 /* This function does not set external trigger edge. */
9524 /* This feature is set using function */
9525 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
9526 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
9527 }
9528
9529 /**
9530 * @brief Get ADC group injected conversion trigger source:
9531 * internal (SW start) or external from timer or external interrupt.
9532 * @note To determine whether group injected trigger source is
9533 * internal (SW start) or external, without detail
9534 * of which peripheral is selected as external trigger,
9535 * (equivalent to
9536 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
9537 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
9538 * @note Availability of parameters of trigger sources from timer
9539 * depends on timers availability on the selected device.
9540 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
9541 * @param ADCx ADC instance
9542 * @retval Returned value can be one of the following values:
9543 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
9544 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
9545 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
9546 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
9547 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
9548 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
9549 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
9550 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
9551 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)9552 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
9553 {
9554 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
9555 }
9556
9557 /**
9558 * @brief Get ADC group injected conversion trigger source internal (SW start)
9559 or external
9560 * @note In case of group injected trigger source set to external trigger,
9561 * to determine which peripheral is selected as external trigger,
9562 * use function @ref LL_ADC_INJ_GetTriggerSource.
9563 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
9564 * @param ADCx ADC instance
9565 * @retval Value "0" trigger source external trigger
9566 * Value "1" trigger source SW start.
9567 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)9568 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
9569 {
9570 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
9571 }
9572
9573 /**
9574 * @brief Set ADC group injected sequencer length and scan direction.
9575 * @note This function performs configuration of:
9576 * - Sequence length: Number of ranks in the scan sequence.
9577 * - Sequence direction: Unless specified in parameters, sequencer
9578 * scan direction is forward (from rank 1 to rank n).
9579 * @note On this STM32 series, group injected sequencer configuration
9580 * is conditioned to ADC instance sequencer mode.
9581 * If ADC instance sequencer mode is disabled, sequencers of
9582 * all groups (group regular, group injected) can be configured
9583 * but their execution is disabled (limited to rank 1).
9584 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9585 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9586 * ADC conversion on only 1 channel.
9587 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
9588 * @param ADCx ADC instance
9589 * @param SequencerNbRanks This parameter can be one of the following values:
9590 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
9591 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
9592 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
9593 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
9594 * @retval None
9595 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)9596 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
9597 {
9598 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
9599 }
9600
9601 /**
9602 * @brief Get ADC group injected sequencer length and scan direction.
9603 * @note This function retrieves:
9604 * - Sequence length: Number of ranks in the scan sequence.
9605 * - Sequence direction: Unless specified in parameters, sequencer
9606 * scan direction is forward (from rank 1 to rank n).
9607 * @note On this STM32 series, group injected sequencer configuration
9608 * is conditioned to ADC instance sequencer mode.
9609 * If ADC instance sequencer mode is disabled, sequencers of
9610 * all groups (group regular, group injected) can be configured
9611 * but their execution is disabled (limited to rank 1).
9612 * Refer to function @ref LL_ADC_SetSequencersScanMode().
9613 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
9614 * ADC conversion on only 1 channel.
9615 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
9616 * @param ADCx ADC instance
9617 * @retval Returned value can be one of the following values:
9618 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
9619 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
9620 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
9621 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
9622 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)9623 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
9624 {
9625 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
9626 }
9627
9628 /**
9629 * @brief Set ADC group injected sequencer discontinuous mode:
9630 * sequence subdivided and scan conversions interrupted every selected
9631 * number of ranks.
9632 * @note It is not possible to enable both ADC group injected
9633 * auto-injected mode and sequencer discontinuous mode.
9634 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
9635 * @param ADCx ADC instance
9636 * @param SeqDiscont This parameter can be one of the following values:
9637 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
9638 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
9639 * @retval None
9640 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)9641 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
9642 {
9643 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
9644 }
9645
9646 /**
9647 * @brief Get ADC group injected sequencer discontinuous mode:
9648 * sequence subdivided and scan conversions interrupted every selected
9649 * number of ranks.
9650 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
9651 * @param ADCx ADC instance
9652 * @retval Returned value can be one of the following values:
9653 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
9654 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
9655 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)9656 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
9657 {
9658 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
9659 }
9660
9661 /**
9662 * @brief Set ADC group injected sequence: channel on the selected
9663 * sequence rank.
9664 * @note Depending on devices and packages, some channels may not be available.
9665 * Refer to device datasheet for channels availability.
9666 * @note On this STM32 series, to measure internal channels (VrefInt,
9667 * TempSensor, ...), measurement paths to internal channels must be
9668 * enabled separately.
9669 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
9670 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
9671 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
9672 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
9673 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
9674 * @param ADCx ADC instance
9675 * @param Rank This parameter can be one of the following values:
9676 * @arg @ref LL_ADC_INJ_RANK_1
9677 * @arg @ref LL_ADC_INJ_RANK_2
9678 * @arg @ref LL_ADC_INJ_RANK_3
9679 * @arg @ref LL_ADC_INJ_RANK_4
9680 * @param Channel This parameter can be one of the following values:
9681 * @arg @ref LL_ADC_CHANNEL_0
9682 * @arg @ref LL_ADC_CHANNEL_1
9683 * @arg @ref LL_ADC_CHANNEL_2
9684 * @arg @ref LL_ADC_CHANNEL_3
9685 * @arg @ref LL_ADC_CHANNEL_4
9686 * @arg @ref LL_ADC_CHANNEL_5
9687 * @arg @ref LL_ADC_CHANNEL_6
9688 * @arg @ref LL_ADC_CHANNEL_7
9689 * @arg @ref LL_ADC_CHANNEL_8
9690 * @arg @ref LL_ADC_CHANNEL_9
9691 * @arg @ref LL_ADC_CHANNEL_10
9692 * @arg @ref LL_ADC_CHANNEL_11
9693 * @arg @ref LL_ADC_CHANNEL_12
9694 * @arg @ref LL_ADC_CHANNEL_13
9695 * @arg @ref LL_ADC_CHANNEL_14
9696 * @arg @ref LL_ADC_CHANNEL_15
9697 * @arg @ref LL_ADC_CHANNEL_16
9698 * @arg @ref LL_ADC_CHANNEL_17
9699 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9700 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9701 *
9702 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9703 * @retval None
9704 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)9705 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
9706 {
9707 /* Set bits with content of parameter "Channel" with bits position */
9708 /* in register depending on parameter "Rank". */
9709 /* Parameters "Rank" and "Channel" are used with masks because containing */
9710 /* other bits reserved for other purpose. */
9711 MODIFY_REG(ADCx->JSQR,
9712 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
9713 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
9714 }
9715
9716 /**
9717 * @brief Get ADC group injected sequence: channel on the selected
9718 * sequence rank.
9719 * @note Depending on devices and packages, some channels may not be available.
9720 * Refer to device datasheet for channels availability.
9721 * @note Usage of the returned channel number:
9722 * - To reinject this channel into another function LL_ADC_xxx:
9723 * the returned channel number is only partly formatted on definition
9724 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
9725 * with parts of literals LL_ADC_CHANNEL_x or using
9726 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9727 * Then the selected literal LL_ADC_CHANNEL_x can be used
9728 * as parameter for another function.
9729 * - To get the channel number in decimal format:
9730 * process the returned value with the helper macro
9731 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
9732 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
9733 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
9734 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
9735 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
9736 * @param ADCx ADC instance
9737 * @param Rank This parameter can be one of the following values:
9738 * @arg @ref LL_ADC_INJ_RANK_1
9739 * @arg @ref LL_ADC_INJ_RANK_2
9740 * @arg @ref LL_ADC_INJ_RANK_3
9741 * @arg @ref LL_ADC_INJ_RANK_4
9742 * @retval Returned value can be one of the following values:
9743 * @arg @ref LL_ADC_CHANNEL_0
9744 * @arg @ref LL_ADC_CHANNEL_1
9745 * @arg @ref LL_ADC_CHANNEL_2
9746 * @arg @ref LL_ADC_CHANNEL_3
9747 * @arg @ref LL_ADC_CHANNEL_4
9748 * @arg @ref LL_ADC_CHANNEL_5
9749 * @arg @ref LL_ADC_CHANNEL_6
9750 * @arg @ref LL_ADC_CHANNEL_7
9751 * @arg @ref LL_ADC_CHANNEL_8
9752 * @arg @ref LL_ADC_CHANNEL_9
9753 * @arg @ref LL_ADC_CHANNEL_10
9754 * @arg @ref LL_ADC_CHANNEL_11
9755 * @arg @ref LL_ADC_CHANNEL_12
9756 * @arg @ref LL_ADC_CHANNEL_13
9757 * @arg @ref LL_ADC_CHANNEL_14
9758 * @arg @ref LL_ADC_CHANNEL_15
9759 * @arg @ref LL_ADC_CHANNEL_16
9760 * @arg @ref LL_ADC_CHANNEL_17
9761 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9762 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9763 *
9764 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
9765 * (1) For ADC channel read back from ADC register,
9766 * comparison with internal channel parameter to be done
9767 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
9768 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)9769 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
9770 {
9771 return (uint32_t)(READ_BIT(ADCx->JSQR,
9772 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
9773 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
9774 );
9775 }
9776
9777 /**
9778 * @brief Set ADC group injected conversion trigger:
9779 * independent or from ADC group regular.
9780 * @note This mode can be used to extend number of data registers
9781 * updated after one ADC conversion trigger and with data
9782 * permanently kept (not erased by successive conversions of scan of
9783 * ADC sequencer ranks), up to 5 data registers:
9784 * 1 data register on ADC group regular, 4 data registers
9785 * on ADC group injected.
9786 * @note If ADC group injected injected trigger source is set to an
9787 * external trigger, this feature must be must be set to
9788 * independent trigger.
9789 * ADC group injected automatic trigger is compliant only with
9790 * group injected trigger source set to SW start, without any
9791 * further action on ADC group injected conversion start or stop:
9792 * in this case, ADC group injected is controlled only
9793 * from ADC group regular.
9794 * @note It is not possible to enable both ADC group injected
9795 * auto-injected mode and sequencer discontinuous mode.
9796 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
9797 * @param ADCx ADC instance
9798 * @param TrigAuto This parameter can be one of the following values:
9799 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
9800 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
9801 * @retval None
9802 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)9803 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
9804 {
9805 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
9806 }
9807
9808 /**
9809 * @brief Get ADC group injected conversion trigger:
9810 * independent or from ADC group regular.
9811 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
9812 * @param ADCx ADC instance
9813 * @retval Returned value can be one of the following values:
9814 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
9815 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
9816 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)9817 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
9818 {
9819 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
9820 }
9821
9822 /**
9823 * @brief Set ADC group injected offset.
9824 * @note It sets:
9825 * - ADC group injected rank to which the offset programmed
9826 * will be applied
9827 * - Offset level (offset to be subtracted from the raw
9828 * converted data).
9829 * Caution: Offset format is dependent to ADC resolution:
9830 * offset has to be left-aligned on bit 11, the LSB (right bits)
9831 * are set to 0.
9832 * @note Offset cannot be enabled or disabled.
9833 * To emulate offset disabled, set an offset value equal to 0.
9834 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
9835 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
9836 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
9837 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
9838 * @param ADCx ADC instance
9839 * @param Rank This parameter can be one of the following values:
9840 * @arg @ref LL_ADC_INJ_RANK_1
9841 * @arg @ref LL_ADC_INJ_RANK_2
9842 * @arg @ref LL_ADC_INJ_RANK_3
9843 * @arg @ref LL_ADC_INJ_RANK_4
9844 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
9845 * @retval None
9846 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)9847 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
9848 {
9849 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
9850
9851 MODIFY_REG(*preg,
9852 ADC_JOFR1_JOFFSET1,
9853 OffsetLevel);
9854 }
9855
9856 /**
9857 * @brief Get ADC group injected offset.
9858 * @note It gives offset level (offset to be subtracted from the raw converted data).
9859 * Caution: Offset format is dependent to ADC resolution:
9860 * offset has to be left-aligned on bit 11, the LSB (right bits)
9861 * are set to 0.
9862 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
9863 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
9864 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
9865 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
9866 * @param ADCx ADC instance
9867 * @param Rank This parameter can be one of the following values:
9868 * @arg @ref LL_ADC_INJ_RANK_1
9869 * @arg @ref LL_ADC_INJ_RANK_2
9870 * @arg @ref LL_ADC_INJ_RANK_3
9871 * @arg @ref LL_ADC_INJ_RANK_4
9872 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
9873 */
LL_ADC_INJ_GetOffset(ADC_TypeDef * ADCx,uint32_t Rank)9874 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
9875 {
9876 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
9877
9878 return (uint32_t)(READ_BIT(*preg,
9879 ADC_JOFR1_JOFFSET1)
9880 );
9881 }
9882
9883 /**
9884 * @}
9885 */
9886
9887 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
9888 * @{
9889 */
9890
9891 /**
9892 * @brief Set sampling time of the selected ADC channel
9893 * Unit: ADC clock cycles.
9894 * @note On this device, sampling time is on channel scope: independently
9895 * of channel mapped on ADC group regular or injected.
9896 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
9897 * converted:
9898 * sampling time constraints must be respected (sampling time can be
9899 * adjusted in function of ADC clock frequency and sampling time
9900 * setting).
9901 * Refer to device datasheet for timings values (parameters TS_vrefint,
9902 * TS_temp, ...).
9903 * @note Conversion time is the addition of sampling time and processing time.
9904 * Refer to reference manual for ADC processing time of
9905 * this STM32 series.
9906 * @note In case of ADC conversion of internal channel (VrefInt,
9907 * temperature sensor, ...), a sampling time minimum value
9908 * is required.
9909 * Refer to device datasheet.
9910 * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
9911 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
9912 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
9913 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
9914 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
9915 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
9916 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
9917 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
9918 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
9919 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
9920 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
9921 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
9922 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
9923 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
9924 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
9925 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
9926 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
9927 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
9928 * @param ADCx ADC instance
9929 * @param Channel This parameter can be one of the following values:
9930 * @arg @ref LL_ADC_CHANNEL_0
9931 * @arg @ref LL_ADC_CHANNEL_1
9932 * @arg @ref LL_ADC_CHANNEL_2
9933 * @arg @ref LL_ADC_CHANNEL_3
9934 * @arg @ref LL_ADC_CHANNEL_4
9935 * @arg @ref LL_ADC_CHANNEL_5
9936 * @arg @ref LL_ADC_CHANNEL_6
9937 * @arg @ref LL_ADC_CHANNEL_7
9938 * @arg @ref LL_ADC_CHANNEL_8
9939 * @arg @ref LL_ADC_CHANNEL_9
9940 * @arg @ref LL_ADC_CHANNEL_10
9941 * @arg @ref LL_ADC_CHANNEL_11
9942 * @arg @ref LL_ADC_CHANNEL_12
9943 * @arg @ref LL_ADC_CHANNEL_13
9944 * @arg @ref LL_ADC_CHANNEL_14
9945 * @arg @ref LL_ADC_CHANNEL_15
9946 * @arg @ref LL_ADC_CHANNEL_16
9947 * @arg @ref LL_ADC_CHANNEL_17
9948 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
9949 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
9950 *
9951 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
9952 * @param SamplingTime This parameter can be one of the following values:
9953 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
9954 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
9955 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
9956 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
9957 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
9958 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
9959 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
9960 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
9961 * @retval None
9962 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)9963 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
9964 {
9965 /* Set bits with content of parameter "SamplingTime" with bits position */
9966 /* in register and register position depending on parameter "Channel". */
9967 /* Parameter "Channel" is used with masks because containing */
9968 /* other bits reserved for other purpose. */
9969 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
9970
9971 MODIFY_REG(*preg,
9972 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
9973 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
9974 }
9975
9976 /**
9977 * @brief Get sampling time of the selected ADC channel
9978 * Unit: ADC clock cycles.
9979 * @note On this device, sampling time is on channel scope: independently
9980 * of channel mapped on ADC group regular or injected.
9981 * @note Conversion time is the addition of sampling time and processing time.
9982 * Refer to reference manual for ADC processing time of
9983 * this STM32 series.
9984 * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
9985 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
9986 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
9987 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
9988 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
9989 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
9990 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
9991 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
9992 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
9993 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
9994 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
9995 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
9996 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
9997 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
9998 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
9999 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
10000 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
10001 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
10002 * @param ADCx ADC instance
10003 * @param Channel This parameter can be one of the following values:
10004 * @arg @ref LL_ADC_CHANNEL_0
10005 * @arg @ref LL_ADC_CHANNEL_1
10006 * @arg @ref LL_ADC_CHANNEL_2
10007 * @arg @ref LL_ADC_CHANNEL_3
10008 * @arg @ref LL_ADC_CHANNEL_4
10009 * @arg @ref LL_ADC_CHANNEL_5
10010 * @arg @ref LL_ADC_CHANNEL_6
10011 * @arg @ref LL_ADC_CHANNEL_7
10012 * @arg @ref LL_ADC_CHANNEL_8
10013 * @arg @ref LL_ADC_CHANNEL_9
10014 * @arg @ref LL_ADC_CHANNEL_10
10015 * @arg @ref LL_ADC_CHANNEL_11
10016 * @arg @ref LL_ADC_CHANNEL_12
10017 * @arg @ref LL_ADC_CHANNEL_13
10018 * @arg @ref LL_ADC_CHANNEL_14
10019 * @arg @ref LL_ADC_CHANNEL_15
10020 * @arg @ref LL_ADC_CHANNEL_16
10021 * @arg @ref LL_ADC_CHANNEL_17
10022 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
10023 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
10024 *
10025 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10026 * @retval Returned value can be one of the following values:
10027 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
10028 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
10029 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
10030 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
10031 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
10032 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
10033 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
10034 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
10035 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)10036 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
10037 {
10038 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
10039
10040 return (uint32_t)(READ_BIT(*preg,
10041 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
10042 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
10043 );
10044 }
10045
10046 /**
10047 * @}
10048 */
10049
10050 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
10051 * @{
10052 */
10053
10054 /**
10055 * @brief Set ADC analog watchdog monitored channels:
10056 * a single channel or all channels,
10057 * on ADC groups regular and-or injected.
10058 * @note Once monitored channels are selected, analog watchdog
10059 * is enabled.
10060 * @note In case of need to define a single channel to monitor
10061 * with analog watchdog from sequencer channel definition,
10062 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
10063 * @note On this STM32 series, there is only 1 kind of analog watchdog
10064 * instance:
10065 * - AWD standard (instance AWD1):
10066 * - channels monitored: can monitor 1 channel or all channels.
10067 * - groups monitored: ADC groups regular and-or injected.
10068 * - resolution: resolution is not limited (corresponds to
10069 * ADC resolution configured).
10070 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
10071 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
10072 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
10073 * @param ADCx ADC instance
10074 * @param AWDChannelGroup This parameter can be one of the following values:
10075 * @arg @ref LL_ADC_AWD_DISABLE
10076 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10077 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10078 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10079 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10080 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10081 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10082 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10083 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10084 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10085 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10086 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10087 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10088 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10089 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10090 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10091 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10092 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10093 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10094 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10095 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10096 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10097 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10098 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10099 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10100 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10101 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10102 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10103 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10104 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10105 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10106 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10107 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10108 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10109 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10110 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10111 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10112 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10113 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10114 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10115 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10116 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10117 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10118 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10119 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10120 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10121 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10122 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10123 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10124 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10125 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10126 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10127 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10128 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10129 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10130 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10131 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10132 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10133 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
10134 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
10135 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
10136 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
10137 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
10138 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
10139 *
10140 * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
10141 * @retval None
10142 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)10143 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
10144 {
10145 MODIFY_REG(ADCx->CR1,
10146 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
10147 AWDChannelGroup);
10148 }
10149
10150 /**
10151 * @brief Get ADC analog watchdog monitored channel.
10152 * @note Usage of the returned channel number:
10153 * - To reinject this channel into another function LL_ADC_xxx:
10154 * the returned channel number is only partly formatted on definition
10155 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
10156 * with parts of literals LL_ADC_CHANNEL_x or using
10157 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10158 * Then the selected literal LL_ADC_CHANNEL_x can be used
10159 * as parameter for another function.
10160 * - To get the channel number in decimal format:
10161 * process the returned value with the helper macro
10162 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
10163 * Applicable only when the analog watchdog is set to monitor
10164 * one channel.
10165 * @note On this STM32 series, there is only 1 kind of analog watchdog
10166 * instance:
10167 * - AWD standard (instance AWD1):
10168 * - channels monitored: can monitor 1 channel or all channels.
10169 * - groups monitored: ADC groups regular and-or injected.
10170 * - resolution: resolution is not limited (corresponds to
10171 * ADC resolution configured).
10172 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
10173 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
10174 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
10175 * @param ADCx ADC instance
10176 * @retval Returned value can be one of the following values:
10177 * @arg @ref LL_ADC_AWD_DISABLE
10178 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
10179 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
10180 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
10181 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
10182 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
10183 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
10184 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
10185 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
10186 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
10187 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
10188 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
10189 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
10190 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
10191 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
10192 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
10193 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
10194 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
10195 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
10196 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
10197 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
10198 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
10199 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
10200 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
10201 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
10202 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
10203 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
10204 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
10205 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
10206 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
10207 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
10208 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
10209 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
10210 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
10211 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
10212 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
10213 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
10214 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
10215 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
10216 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
10217 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
10218 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
10219 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
10220 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
10221 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
10222 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
10223 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
10224 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
10225 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
10226 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
10227 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
10228 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
10229 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
10230 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
10231 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
10232 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
10233 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
10234 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
10235 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx)10236 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
10237 {
10238 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
10239 }
10240
10241 /**
10242 * @brief Set ADC analog watchdog threshold value of threshold
10243 * high or low.
10244 * @note On this STM32 series, there is only 1 kind of analog watchdog
10245 * instance:
10246 * - AWD standard (instance AWD1):
10247 * - channels monitored: can monitor 1 channel or all channels.
10248 * - groups monitored: ADC groups regular and-or injected.
10249 * - resolution: resolution is not limited (corresponds to
10250 * ADC resolution configured).
10251 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
10252 * LTR LT LL_ADC_SetAnalogWDThresholds
10253 * @param ADCx ADC instance
10254 * @param AWDThresholdsHighLow This parameter can be one of the following values:
10255 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10256 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10257 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
10258 * @retval None
10259 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)10260 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
10261 {
10262 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
10263
10264 MODIFY_REG(*preg,
10265 ADC_HTR_HT,
10266 AWDThresholdValue);
10267 }
10268
10269 /**
10270 * @brief Get ADC analog watchdog threshold value of threshold high or
10271 * threshold low.
10272 * @note In case of ADC resolution different of 12 bits,
10273 * analog watchdog thresholds data require a specific shift.
10274 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
10275 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
10276 * LTR LT LL_ADC_GetAnalogWDThresholds
10277 * @param ADCx ADC instance
10278 * @param AWDThresholdsHighLow This parameter can be one of the following values:
10279 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
10280 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
10281 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10282 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)10283 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
10284 {
10285 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
10286
10287 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
10288 }
10289
10290 /**
10291 * @}
10292 */
10293
10294 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
10295 * @{
10296 */
10297
10298 /**
10299 * @brief Enable the selected ADC instance.
10300 * @note On this STM32 series, after ADC enable, a delay for
10301 * ADC internal analog stabilization is required before performing a
10302 * ADC conversion start.
10303 * Refer to device datasheet, parameter tSTAB.
10304 * @rmtoll CR2 ADON LL_ADC_Enable
10305 * @param ADCx ADC instance
10306 * @retval None
10307 */
LL_ADC_Enable(ADC_TypeDef * ADCx)10308 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
10309 {
10310 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
10311 }
10312
10313 /**
10314 * @brief Disable the selected ADC instance.
10315 * @rmtoll CR2 ADON LL_ADC_Disable
10316 * @param ADCx ADC instance
10317 * @retval None
10318 */
LL_ADC_Disable(ADC_TypeDef * ADCx)10319 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
10320 {
10321 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
10322 }
10323
10324 /**
10325 * @brief Get the selected ADC instance enable state.
10326 * @rmtoll CR2 ADON LL_ADC_IsEnabled
10327 * @param ADCx ADC instance
10328 * @retval 0: ADC is disabled, 1: ADC is enabled.
10329 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)10330 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
10331 {
10332 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
10333 }
10334
10335 /**
10336 * @brief Start ADC calibration in the mode single-ended
10337 * or differential (for devices with differential mode available).
10338 * @note On this STM32 series, before starting a calibration,
10339 * ADC must be disabled.
10340 * A minimum number of ADC clock cycles are required
10341 * between ADC disable state and calibration start.
10342 * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
10343 * @note On this STM32 series, hardware prerequisite before starting a calibration:
10344 the ADC must have been in power-on state for at least
10345 two ADC clock cycles.
10346 * @rmtoll CR2 CAL LL_ADC_StartCalibration
10347 * @param ADCx ADC instance
10348 * @retval None
10349 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)10350 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
10351 {
10352 SET_BIT(ADCx->CR2, ADC_CR2_CAL);
10353 }
10354
10355 /**
10356 * @brief Get ADC calibration state.
10357 * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
10358 * @param ADCx ADC instance
10359 * @retval 0: calibration complete, 1: calibration in progress.
10360 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)10361 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
10362 {
10363 return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
10364 }
10365
10366 /**
10367 * @}
10368 */
10369
10370 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
10371 * @{
10372 */
10373
10374 /**
10375 * @brief Start ADC group regular conversion.
10376 * @note On this STM32 series, this function is relevant for both
10377 * internal trigger (SW start) and external trigger:
10378 * - If ADC trigger has been set to software start, ADC conversion
10379 * starts immediately.
10380 * - If ADC trigger has been set to external trigger, ADC conversion
10381 * will start at next trigger event (on the selected trigger edge)
10382 * following the ADC start conversion command.
10383 * @rmtoll CR2 EXTTRIG LL_ADC_REG_StartConversion
10384 * @param ADCx ADC instance
10385 * @retval None
10386 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)10387 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
10388 {
10389 /* Note: Set bit ADC_CR2_SWSTART for case of trigger source set to */
10390 /* SW start. In case of external trigger selected, this bit */
10391 /* has no effect. */
10392 SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
10393 }
10394
10395 /**
10396 * @brief Stop ADC group regular conversion from external trigger.
10397 * @note No more ADC conversion will start at next trigger event
10398 * following the ADC stop conversion command.
10399 * If a conversion is on-going, it will be completed.
10400 * @note On this STM32 series, there is no specific command
10401 * to stop a conversion on-going or to stop ADC converting
10402 * in continuous mode. These actions can be performed
10403 * using function @ref LL_ADC_Disable().
10404 * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
10405 * @param ADCx ADC instance
10406 * @retval None
10407 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)10408 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
10409 {
10410 SET_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
10411 }
10412
10413 /**
10414 * @brief Get ADC group regular conversion data, range fit for
10415 * all ADC configurations: all ADC resolutions and
10416 * all oversampling increased data width (for devices
10417 * with feature oversampling).
10418 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
10419 * @param ADCx ADC instance
10420 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10421 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)10422 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
10423 {
10424 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
10425 }
10426
10427 /**
10428 * @brief Get ADC group regular conversion data, range fit for
10429 * ADC resolution 12 bits.
10430 * @note For devices with feature oversampling: Oversampling
10431 * can increase data width, function for extended range
10432 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
10433 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
10434 * @param ADCx ADC instance
10435 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10436 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)10437 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
10438 {
10439 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
10440 }
10441
10442 /**
10443 * @}
10444 */
10445
10446 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
10447 * @{
10448 */
10449
10450 /**
10451 * @brief Start ADC group injected conversion.
10452 * @note On this STM32 series, this function is relevant for both
10453 * internal trigger (SW start) and external trigger:
10454 * - If ADC trigger has been set to software start, ADC conversion
10455 * starts immediately.
10456 * - If ADC trigger has been set to external trigger, ADC conversion
10457 * will start at next trigger event (on the selected trigger edge)
10458 * following the ADC start conversion command.
10459 * @rmtoll CR2 JEXTTRIG LL_ADC_REG_StartConversion
10460 * @param ADCx ADC instance
10461 * @retval None
10462 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)10463 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
10464 {
10465 /* Note: Set bit ADC_CR2_JSWSTART for case of trigger source set to */
10466 /* SW start. In case of external trigger selected, this bit */
10467 /* has no effect. */
10468 SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
10469 }
10470
10471 /**
10472 * @brief Stop ADC group injected conversion from external trigger.
10473 * @note No more ADC conversion will start at next trigger event
10474 * following the ADC stop conversion command.
10475 * If a conversion is on-going, it will be completed.
10476 * @note On this STM32 series, there is no specific command
10477 * to stop a conversion on-going or to stop ADC converting
10478 * in continuous mode. These actions can be performed
10479 * using function @ref LL_ADC_Disable().
10480 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
10481 * @param ADCx ADC instance
10482 * @retval None
10483 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)10484 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
10485 {
10486 SET_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
10487 }
10488
10489 /**
10490 * @brief Get ADC group regular conversion data, range fit for
10491 * all ADC configurations: all ADC resolutions and
10492 * all oversampling increased data width (for devices
10493 * with feature oversampling).
10494 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
10495 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
10496 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
10497 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
10498 * @param ADCx ADC instance
10499 * @param Rank This parameter can be one of the following values:
10500 * @arg @ref LL_ADC_INJ_RANK_1
10501 * @arg @ref LL_ADC_INJ_RANK_2
10502 * @arg @ref LL_ADC_INJ_RANK_3
10503 * @arg @ref LL_ADC_INJ_RANK_4
10504 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
10505 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)10506 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
10507 {
10508 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10509
10510 return (uint32_t)(READ_BIT(*preg,
10511 ADC_JDR1_JDATA)
10512 );
10513 }
10514
10515 /**
10516 * @brief Get ADC group injected conversion data, range fit for
10517 * ADC resolution 12 bits.
10518 * @note For devices with feature oversampling: Oversampling
10519 * can increase data width, function for extended range
10520 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
10521 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
10522 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
10523 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
10524 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
10525 * @param ADCx ADC instance
10526 * @param Rank This parameter can be one of the following values:
10527 * @arg @ref LL_ADC_INJ_RANK_1
10528 * @arg @ref LL_ADC_INJ_RANK_2
10529 * @arg @ref LL_ADC_INJ_RANK_3
10530 * @arg @ref LL_ADC_INJ_RANK_4
10531 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
10532 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)10533 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
10534 {
10535 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
10536
10537 return (uint16_t)(READ_BIT(*preg,
10538 ADC_JDR1_JDATA)
10539 );
10540 }
10541
10542 /**
10543 * @}
10544 */
10545
10546 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
10547 * @{
10548 */
10549
10550 /**
10551 * @brief Get flag ADC group regular end of sequence conversions.
10552 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
10553 * @param ADCx ADC instance
10554 * @retval State of bit (1 or 0).
10555 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)10556 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
10557 {
10558 /* Note: on this STM32 series, there is no flag ADC group regular */
10559 /* end of unitary conversion. */
10560 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10561 /* in other STM32 families). */
10562 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
10563 }
10564
10565
10566 /**
10567 * @brief Get flag ADC group injected end of sequence conversions.
10568 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
10569 * @param ADCx ADC instance
10570 * @retval State of bit (1 or 0).
10571 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)10572 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
10573 {
10574 /* Note: on this STM32 series, there is no flag ADC group injected */
10575 /* end of unitary conversion. */
10576 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10577 /* in other STM32 families). */
10578 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
10579 }
10580
10581 /**
10582 * @brief Get flag ADC analog watchdog 1 flag
10583 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
10584 * @param ADCx ADC instance
10585 * @retval State of bit (1 or 0).
10586 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)10587 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
10588 {
10589 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
10590 }
10591
10592 /**
10593 * @brief Clear flag ADC group regular end of sequence conversions.
10594 * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
10595 * @param ADCx ADC instance
10596 * @retval None
10597 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)10598 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
10599 {
10600 /* Note: on this STM32 series, there is no flag ADC group regular */
10601 /* end of unitary conversion. */
10602 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10603 /* in other STM32 families). */
10604 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
10605 }
10606
10607
10608 /**
10609 * @brief Clear flag ADC group injected end of sequence conversions.
10610 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
10611 * @param ADCx ADC instance
10612 * @retval None
10613 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)10614 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
10615 {
10616 /* Note: on this STM32 series, there is no flag ADC group injected */
10617 /* end of unitary conversion. */
10618 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10619 /* in other STM32 families). */
10620 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
10621 }
10622
10623 /**
10624 * @brief Clear flag ADC analog watchdog 1.
10625 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
10626 * @param ADCx ADC instance
10627 * @retval None
10628 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)10629 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
10630 {
10631 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
10632 }
10633
10634 /**
10635 * @}
10636 */
10637
10638 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
10639 * @{
10640 */
10641
10642 /**
10643 * @brief Enable interruption ADC group regular end of sequence conversions.
10644 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
10645 * @param ADCx ADC instance
10646 * @retval None
10647 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)10648 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
10649 {
10650 /* Note: on this STM32 series, there is no flag ADC group regular */
10651 /* end of unitary conversion. */
10652 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10653 /* in other STM32 families). */
10654 SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
10655 }
10656
10657
10658 /**
10659 * @brief Enable interruption ADC group injected end of sequence conversions.
10660 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10661 * @param ADCx ADC instance
10662 * @retval None
10663 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)10664 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
10665 {
10666 /* Note: on this STM32 series, there is no flag ADC group injected */
10667 /* end of unitary conversion. */
10668 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10669 /* in other STM32 families). */
10670 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
10671 }
10672
10673 /**
10674 * @brief Enable interruption ADC analog watchdog 1.
10675 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10676 * @param ADCx ADC instance
10677 * @retval None
10678 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)10679 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
10680 {
10681 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
10682 }
10683
10684 /**
10685 * @brief Disable interruption ADC group regular end of sequence conversions.
10686 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
10687 * @param ADCx ADC instance
10688 * @retval None
10689 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)10690 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
10691 {
10692 /* Note: on this STM32 series, there is no flag ADC group regular */
10693 /* end of unitary conversion. */
10694 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10695 /* in other STM32 families). */
10696 CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
10697 }
10698
10699
10700 /**
10701 * @brief Disable interruption ADC group injected end of sequence conversions.
10702 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10703 * @param ADCx ADC instance
10704 * @retval None
10705 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)10706 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
10707 {
10708 /* Note: on this STM32 series, there is no flag ADC group injected */
10709 /* end of unitary conversion. */
10710 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10711 /* in other STM32 families). */
10712 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
10713 }
10714
10715 /**
10716 * @brief Disable interruption ADC analog watchdog 1.
10717 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10718 * @param ADCx ADC instance
10719 * @retval None
10720 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)10721 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
10722 {
10723 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
10724 }
10725
10726 /**
10727 * @brief Get state of interruption ADC group regular end of sequence conversions
10728 * (0: interrupt disabled, 1: interrupt enabled).
10729 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
10730 * @param ADCx ADC instance
10731 * @retval State of bit (1 or 0).
10732 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)10733 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
10734 {
10735 /* Note: on this STM32 series, there is no flag ADC group regular */
10736 /* end of unitary conversion. */
10737 /* Flag noted as "EOC" is corresponding to flag "EOS" */
10738 /* in other STM32 families). */
10739 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
10740 }
10741
10742
10743 /**
10744 * @brief Get state of interruption ADC group injected end of sequence conversions
10745 * (0: interrupt disabled, 1: interrupt enabled).
10746 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
10747 * @param ADCx ADC instance
10748 * @retval State of bit (1 or 0).
10749 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)10750 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
10751 {
10752 /* Note: on this STM32 series, there is no flag ADC group injected */
10753 /* end of unitary conversion. */
10754 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
10755 /* in other STM32 families). */
10756 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
10757 }
10758
10759 /**
10760 * @brief Get state of interruption ADC analog watchdog 1
10761 * (0: interrupt disabled, 1: interrupt enabled).
10762 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
10763 * @param ADCx ADC instance
10764 * @retval State of bit (1 or 0).
10765 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)10766 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
10767 {
10768 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
10769 }
10770
10771 /**
10772 * @}
10773 */
10774
10775 #if defined(USE_FULL_LL_DRIVER)
10776 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
10777 * @{
10778 */
10779
10780 /* Initialization of some features of ADC common parameters and multimode */
10781 /* Note: On STM32F37x ADC, there is no ADC common initialization */
10782 /* function. */
10783 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
10784
10785 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
10786 /* (availability of ADC group injected depends on STM32 families) */
10787 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
10788
10789 /* Initialization of some features of ADC instance */
10790 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
10791 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
10792
10793 /* Initialization of some features of ADC instance and ADC group regular */
10794 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
10795 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
10796
10797 /* Initialization of some features of ADC instance and ADC group injected */
10798 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
10799 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
10800
10801 /**
10802 * @}
10803 */
10804 #endif /* USE_FULL_LL_DRIVER */
10805
10806 /**
10807 * @}
10808 */
10809
10810 /**
10811 * @}
10812 */
10813
10814 #endif /* ADC1 */
10815
10816
10817 #endif /* STM32F373xC || STM32F378xx */
10818
10819 /**
10820 * @}
10821 */
10822
10823 #ifdef __cplusplus
10824 }
10825 #endif
10826
10827 #endif /* __STM32F3xx_LL_ADC_H */
10828
10829
