1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F3xx_HAL_TIM_H 21 #define STM32F3xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f3xx_hal_def.h" 29 30 /** @addtogroup STM32F3xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 62 reaches zero, an update event is generated and counting restarts 63 from the RCR value (N). 64 This means in PWM mode that (N+1) corresponds to: 65 - the number of PWM periods in edge-aligned mode 66 - the number of half PWM period in center-aligned mode 67 GP timers: this parameter must be a number between Min_Data = 0x00 and 68 Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 70 Max_Data = 0xFFFF. */ 71 72 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 73 This parameter can be a value of @ref TIM_AutoReloadPreload */ 74 } TIM_Base_InitTypeDef; 75 76 /** 77 * @brief TIM Output Compare Configuration Structure definition 78 */ 79 typedef struct 80 { 81 uint32_t OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 85 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 86 87 uint32_t OCPolarity; /*!< Specifies the output polarity. 88 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 89 90 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 91 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 92 @note This parameter is valid only for timer instances supporting break feature. */ 93 94 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 95 This parameter can be a value of @ref TIM_Output_Fast_State 96 @note This parameter is valid only in PWM1 and PWM2 mode. */ 97 98 99 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 100 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 101 @note This parameter is valid only for timer instances supporting break feature. */ 102 103 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 } TIM_OC_InitTypeDef; 107 108 /** 109 * @brief TIM One Pulse Mode Configuration Structure definition 110 */ 111 typedef struct 112 { 113 uint32_t OCMode; /*!< Specifies the TIM mode. 114 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 115 116 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 117 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 118 119 uint32_t OCPolarity; /*!< Specifies the output polarity. 120 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 121 122 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 123 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 124 @note This parameter is valid only for timer instances supporting break feature. */ 125 126 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 127 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 128 @note This parameter is valid only for timer instances supporting break feature. */ 129 130 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 131 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 132 @note This parameter is valid only for timer instances supporting break feature. */ 133 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 136 137 uint32_t ICSelection; /*!< Specifies the input. 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 139 140 uint32_t ICFilter; /*!< Specifies the input capture filter. 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 142 } TIM_OnePulse_InitTypeDef; 143 144 /** 145 * @brief TIM Input Capture Configuration Structure definition 146 */ 147 typedef struct 148 { 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 151 152 uint32_t ICSelection; /*!< Specifies the input. 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 154 155 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 156 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 157 158 uint32_t ICFilter; /*!< Specifies the input capture filter. 159 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 160 } TIM_IC_InitTypeDef; 161 162 /** 163 * @brief TIM Encoder Configuration Structure definition 164 */ 165 typedef struct 166 { 167 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 168 This parameter can be a value of @ref TIM_Encoder_Mode */ 169 170 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 171 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 172 173 uint32_t IC1Selection; /*!< Specifies the input. 174 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 175 176 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 178 179 uint32_t IC1Filter; /*!< Specifies the input capture filter. 180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 181 182 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 183 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 184 185 uint32_t IC2Selection; /*!< Specifies the input. 186 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 187 188 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 189 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 190 191 uint32_t IC2Filter; /*!< Specifies the input capture filter. 192 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 193 } TIM_Encoder_InitTypeDef; 194 195 /** 196 * @brief Clock Configuration Handle Structure definition 197 */ 198 typedef struct 199 { 200 uint32_t ClockSource; /*!< TIM clock sources 201 This parameter can be a value of @ref TIM_Clock_Source */ 202 uint32_t ClockPolarity; /*!< TIM clock polarity 203 This parameter can be a value of @ref TIM_Clock_Polarity */ 204 uint32_t ClockPrescaler; /*!< TIM clock prescaler 205 This parameter can be a value of @ref TIM_Clock_Prescaler */ 206 uint32_t ClockFilter; /*!< TIM clock filter 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 208 } TIM_ClockConfigTypeDef; 209 210 /** 211 * @brief TIM Clear Input Configuration Handle Structure definition 212 */ 213 typedef struct 214 { 215 uint32_t ClearInputState; /*!< TIM clear Input state 216 This parameter can be ENABLE or DISABLE */ 217 uint32_t ClearInputSource; /*!< TIM clear Input sources 218 This parameter can be a value of @ref TIM_ClearInput_Source */ 219 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 220 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 221 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 222 This parameter must be 0: When OCRef clear feature is used with ETR source, 223 ETR prescaler must be off */ 224 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 226 } TIM_ClearInputConfigTypeDef; 227 228 /** 229 * @brief TIM Master configuration Structure definition 230 * @note Advanced timers provide TRGO2 internal line which is redirected 231 * to the ADC 232 */ 233 typedef struct 234 { 235 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 236 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 237 #if defined(TIM_CR2_MMS2) 238 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 239 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 240 #endif /* TIM_CR2_MMS2 */ 241 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 242 This parameter can be a value of @ref TIM_Master_Slave_Mode 243 @note When the Master/slave mode is enabled, the effect of 244 an event on the trigger input (TRGI) is delayed to allow a 245 perfect synchronization between the current timer and its 246 slaves (through TRGO). It is not mandatory in case of timer 247 synchronization mode. */ 248 } TIM_MasterConfigTypeDef; 249 250 /** 251 * @brief TIM Slave configuration Structure definition 252 */ 253 typedef struct 254 { 255 uint32_t SlaveMode; /*!< Slave mode selection 256 This parameter can be a value of @ref TIM_Slave_Mode */ 257 uint32_t InputTrigger; /*!< Input Trigger source 258 This parameter can be a value of @ref TIM_Trigger_Selection */ 259 uint32_t TriggerPolarity; /*!< Input Trigger polarity 260 This parameter can be a value of @ref TIM_Trigger_Polarity */ 261 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 262 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 263 uint32_t TriggerFilter; /*!< Input trigger filter 264 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 265 266 } TIM_SlaveConfigTypeDef; 267 268 /** 269 * @brief TIM Break input(s) and Dead time configuration Structure definition 270 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 271 * filter and polarity. 272 */ 273 typedef struct 274 { 275 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 276 277 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 278 279 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 280 281 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 282 283 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 284 285 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 286 287 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 288 289 #if defined(TIM_BDTR_BK2E) 290 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 291 292 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 293 294 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 295 296 #endif /*TIM_BDTR_BK2E */ 297 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 298 299 } TIM_BreakDeadTimeConfigTypeDef; 300 301 /** 302 * @brief HAL State structures definition 303 */ 304 typedef enum 305 { 306 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 307 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 308 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 309 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 310 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 311 } HAL_TIM_StateTypeDef; 312 313 /** 314 * @brief TIM Channel States definition 315 */ 316 typedef enum 317 { 318 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 319 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 320 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 321 } HAL_TIM_ChannelStateTypeDef; 322 323 /** 324 * @brief DMA Burst States definition 325 */ 326 typedef enum 327 { 328 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 329 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 330 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 331 } HAL_TIM_DMABurstStateTypeDef; 332 333 /** 334 * @brief HAL Active channel structures definition 335 */ 336 typedef enum 337 { 338 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 339 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 340 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 341 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 342 #if defined(TIM_CCER_CC5E) 343 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 344 #endif /* TIM_CCER_CC5E */ 345 #if defined(TIM_CCER_CC6E) 346 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 347 #endif /* TIM_CCER_CC6E */ 348 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 349 } HAL_TIM_ActiveChannel; 350 351 /** 352 * @brief TIM Time Base Handle Structure definition 353 */ 354 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 355 typedef struct __TIM_HandleTypeDef 356 #else 357 typedef struct 358 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 359 { 360 TIM_TypeDef *Instance; /*!< Register base address */ 361 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 362 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 363 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 364 This array is accessed by a @ref DMA_Handle_index */ 365 HAL_LockTypeDef Lock; /*!< Locking object */ 366 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 367 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 368 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 369 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 370 371 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 372 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 373 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 374 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 375 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 376 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 377 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 378 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 379 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 380 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 381 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 382 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 383 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 384 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 385 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 386 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 387 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 388 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 389 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 390 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 391 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 392 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 393 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 394 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 395 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 396 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 397 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 398 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 399 #if defined(TIM_BDTR_BK2E) 400 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 401 #endif /* */ 402 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 403 } TIM_HandleTypeDef; 404 405 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 406 /** 407 * @brief HAL TIM Callback ID enumeration definition 408 */ 409 typedef enum 410 { 411 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 412 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 413 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 414 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 415 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 416 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 417 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 418 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 419 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 420 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 421 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 422 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 423 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 424 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 425 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 426 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 427 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 428 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 429 430 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 431 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 432 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 433 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 434 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 435 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 436 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 437 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 438 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 439 #if defined(TIM_BDTR_BK2E) 440 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 441 #endif /* TIM_BDTR_BK2E */ 442 } HAL_TIM_CallbackIDTypeDef; 443 444 /** 445 * @brief HAL TIM Callback pointer definition 446 */ 447 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 448 449 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 450 451 /** 452 * @} 453 */ 454 /* End of exported types -----------------------------------------------------*/ 455 456 /* Exported constants --------------------------------------------------------*/ 457 /** @defgroup TIM_Exported_Constants TIM Exported Constants 458 * @{ 459 */ 460 461 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 462 * @{ 463 */ 464 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 465 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 466 #if defined(TIM_SMCR_OCCS) 467 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 468 #endif /* TIM_SMCR_OCCS */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 474 * @{ 475 */ 476 #define TIM_DMABASE_CR1 0x00000000U 477 #define TIM_DMABASE_CR2 0x00000001U 478 #define TIM_DMABASE_SMCR 0x00000002U 479 #define TIM_DMABASE_DIER 0x00000003U 480 #define TIM_DMABASE_SR 0x00000004U 481 #define TIM_DMABASE_EGR 0x00000005U 482 #define TIM_DMABASE_CCMR1 0x00000006U 483 #define TIM_DMABASE_CCMR2 0x00000007U 484 #define TIM_DMABASE_CCER 0x00000008U 485 #define TIM_DMABASE_CNT 0x00000009U 486 #define TIM_DMABASE_PSC 0x0000000AU 487 #define TIM_DMABASE_ARR 0x0000000BU 488 #define TIM_DMABASE_RCR 0x0000000CU 489 #define TIM_DMABASE_CCR1 0x0000000DU 490 #define TIM_DMABASE_CCR2 0x0000000EU 491 #define TIM_DMABASE_CCR3 0x0000000FU 492 #define TIM_DMABASE_CCR4 0x00000010U 493 #define TIM_DMABASE_BDTR 0x00000011U 494 #define TIM_DMABASE_DCR 0x00000012U 495 #define TIM_DMABASE_DMAR 0x00000013U 496 #define TIM_DMABASE_OR 0x00000014U 497 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 498 #define TIM_DMABASE_CCMR3 0x00000015U 499 #define TIM_DMABASE_CCR5 0x00000016U 500 #define TIM_DMABASE_CCR6 0x00000017U 501 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup TIM_Event_Source TIM Event Source 507 * @{ 508 */ 509 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 510 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 511 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 512 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 513 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 514 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 515 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 516 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 517 #if defined(TIM_EGR_B2G) 518 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 519 #endif /* TIM_EGR_B2G */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 525 * @{ 526 */ 527 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 528 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 529 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 530 /** 531 * @} 532 */ 533 534 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 535 * @{ 536 */ 537 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 538 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 539 /** 540 * @} 541 */ 542 543 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 544 * @{ 545 */ 546 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 547 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 548 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 549 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup TIM_Counter_Mode TIM Counter Mode 555 * @{ 556 */ 557 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 558 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 559 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 560 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 561 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 562 /** 563 * @} 564 */ 565 566 #if defined(TIM_CR1_UIFREMAP) 567 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 568 * @{ 569 */ 570 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 571 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 572 /** 573 * @} 574 */ 575 576 #endif /* TIM_CR1_UIFREMAP */ 577 /** @defgroup TIM_ClockDivision TIM Clock Division 578 * @{ 579 */ 580 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 581 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 582 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 583 /** 584 * @} 585 */ 586 587 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 588 * @{ 589 */ 590 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 591 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 597 * @{ 598 */ 599 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 600 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 601 602 /** 603 * @} 604 */ 605 606 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 607 * @{ 608 */ 609 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 610 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 616 * @{ 617 */ 618 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 619 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 625 * @{ 626 */ 627 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 628 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 634 * @{ 635 */ 636 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 637 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 643 * @{ 644 */ 645 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 646 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 652 * @{ 653 */ 654 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 655 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 661 * @{ 662 */ 663 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 664 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 665 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 666 /** 667 * @} 668 */ 669 670 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 671 * @{ 672 */ 673 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 674 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 675 /** 676 * @} 677 */ 678 679 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 680 * @{ 681 */ 682 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 683 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 684 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 685 /** 686 * @} 687 */ 688 689 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 690 * @{ 691 */ 692 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 693 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 694 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 695 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 701 * @{ 702 */ 703 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 704 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 710 * @{ 711 */ 712 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 713 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 714 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 715 /** 716 * @} 717 */ 718 719 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 720 * @{ 721 */ 722 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 723 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 724 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 725 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 726 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 727 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 728 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 729 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 730 /** 731 * @} 732 */ 733 734 /** @defgroup TIM_Commutation_Source TIM Commutation Source 735 * @{ 736 */ 737 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 738 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 739 /** 740 * @} 741 */ 742 743 /** @defgroup TIM_DMA_sources TIM DMA Sources 744 * @{ 745 */ 746 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 747 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 748 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 749 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 750 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 751 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 752 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 753 /** 754 * @} 755 */ 756 757 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 758 * @{ 759 */ 760 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 761 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 762 /** 763 * @} 764 */ 765 766 /** @defgroup TIM_Flag_definition TIM Flag Definition 767 * @{ 768 */ 769 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 770 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 771 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 772 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 773 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 774 #if defined(TIM_SR_CC5IF) 775 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 776 #endif /* TIM_SR_CC5IF */ 777 #if defined(TIM_SR_CC6IF) 778 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 779 #endif /* TIM_SR_CC6IF */ 780 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 781 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 782 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 783 #if defined(TIM_SR_B2IF) 784 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 785 #endif /* TIM_SR_B2IF */ 786 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 787 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 788 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 789 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 790 /** 791 * @} 792 */ 793 794 /** @defgroup TIM_Channel TIM Channel 795 * @{ 796 */ 797 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 798 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 799 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 800 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 801 #if defined(TIM_CCER_CC5E) 802 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 803 #endif /* TIM_CCER_CC5E */ 804 #if defined(TIM_CCER_CC6E) 805 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 806 #endif /* TIM_CCER_CC6E */ 807 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 808 /** 809 * @} 810 */ 811 812 /** @defgroup TIM_Clock_Source TIM Clock Source 813 * @{ 814 */ 815 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 816 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 817 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 818 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 819 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 820 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 821 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 822 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 823 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 824 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 830 * @{ 831 */ 832 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 833 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 834 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 835 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 836 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 837 /** 838 * @} 839 */ 840 841 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 842 * @{ 843 */ 844 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 845 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 846 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 847 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 853 * @{ 854 */ 855 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 856 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 857 /** 858 * @} 859 */ 860 861 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 862 * @{ 863 */ 864 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 865 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 866 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 867 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 868 /** 869 * @} 870 */ 871 872 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 873 * @{ 874 */ 875 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 876 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 877 /** 878 * @} 879 */ 880 881 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 882 * @{ 883 */ 884 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 885 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 886 /** 887 * @} 888 */ 889 /** @defgroup TIM_Lock_level TIM Lock level 890 * @{ 891 */ 892 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 893 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 894 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 895 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 896 /** 897 * @} 898 */ 899 900 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 901 * @{ 902 */ 903 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 904 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 905 /** 906 * @} 907 */ 908 909 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 910 * @{ 911 */ 912 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 913 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 914 /** 915 * @} 916 */ 917 918 #if defined(TIM_BDTR_BK2E) 919 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 920 * @{ 921 */ 922 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 923 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 924 /** 925 * @} 926 */ 927 928 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 929 * @{ 930 */ 931 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 932 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 933 /** 934 * @} 935 */ 936 #endif /* TIM_BDTR_BK2E */ 937 938 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 939 * @{ 940 */ 941 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 942 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 943 /** 944 * @} 945 */ 946 947 #if defined(TIM_CCR5_CCR5) 948 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 949 * @{ 950 */ 951 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 952 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 953 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 954 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 955 /** 956 * @} 957 */ 958 #endif /* TIM_CCR5_CCR5 */ 959 960 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 961 * @{ 962 */ 963 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 964 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 965 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 966 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 967 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 968 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 969 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 970 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 971 /** 972 * @} 973 */ 974 975 #if defined(TIM_CR2_MMS2) 976 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 977 * @{ 978 */ 979 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 980 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 981 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 982 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 983 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 984 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 985 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 986 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 987 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 988 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 989 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 990 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 991 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 992 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 993 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 994 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 995 /** 996 * @} 997 */ 998 #endif /* TIM_CR2_MMS2 */ 999 1000 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 1001 * @{ 1002 */ 1003 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 1004 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 1005 /** 1006 * @} 1007 */ 1008 1009 /** @defgroup TIM_Slave_Mode TIM Slave mode 1010 * @{ 1011 */ 1012 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 1013 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 1014 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 1015 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 1016 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 1017 #if defined (TIM_SMCR_SMS_3) 1018 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 1019 #endif /* TIM_SMCR_SMS_3 */ 1020 /** 1021 * @} 1022 */ 1023 1024 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 1025 * @{ 1026 */ 1027 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 1028 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 1029 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 1030 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 1031 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 1032 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 1033 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1034 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1035 #if defined(TIM_CCMR1_OC1M_3) 1036 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1037 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1038 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1039 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1040 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1041 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1042 #endif /* TIM_CCMR1_OC1M_3 */ 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1048 * @{ 1049 */ 1050 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1051 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1052 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1053 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1054 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1055 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1056 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1057 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1058 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1059 /** 1060 * @} 1061 */ 1062 1063 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1064 * @{ 1065 */ 1066 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1067 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1068 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1069 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1070 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1071 /** 1072 * @} 1073 */ 1074 1075 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1076 * @{ 1077 */ 1078 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1079 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1080 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1081 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1082 /** 1083 * @} 1084 */ 1085 1086 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1087 * @{ 1088 */ 1089 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1090 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1096 * @{ 1097 */ 1098 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1099 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1100 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1101 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1102 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1103 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1104 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1105 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1106 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1107 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1108 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1109 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1110 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1111 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1112 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1113 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1114 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1115 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1116 /** 1117 * @} 1118 */ 1119 1120 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1121 * @{ 1122 */ 1123 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1124 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1125 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1126 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1127 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1128 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1129 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1135 * @{ 1136 */ 1137 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1138 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1139 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1140 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1141 /** 1142 * @} 1143 */ 1144 1145 /** 1146 * @} 1147 */ 1148 /* End of exported constants -------------------------------------------------*/ 1149 1150 /* Exported macros -----------------------------------------------------------*/ 1151 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1152 * @{ 1153 */ 1154 1155 /** @brief Reset TIM handle state. 1156 * @param __HANDLE__ TIM handle. 1157 * @retval None 1158 */ 1159 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1160 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1161 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1162 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1163 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1164 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1165 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1166 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1167 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1168 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1169 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1170 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1171 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1172 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1173 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1174 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1175 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1176 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1177 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1178 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1179 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1180 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1181 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1182 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1183 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1184 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1185 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1186 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1187 } while(0) 1188 #else 1189 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1190 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1191 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1192 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1193 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1194 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1195 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1196 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1197 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1198 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1199 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1200 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1201 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1202 } while(0) 1203 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1204 1205 /** 1206 * @brief Enable the TIM peripheral. 1207 * @param __HANDLE__ TIM handle 1208 * @retval None 1209 */ 1210 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1211 1212 /** 1213 * @brief Enable the TIM main Output. 1214 * @param __HANDLE__ TIM handle 1215 * @retval None 1216 */ 1217 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1218 1219 /** 1220 * @brief Disable the TIM peripheral. 1221 * @param __HANDLE__ TIM handle 1222 * @retval None 1223 */ 1224 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1225 do { \ 1226 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1227 { \ 1228 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1229 { \ 1230 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1231 } \ 1232 } \ 1233 } while(0) 1234 1235 /** 1236 * @brief Disable the TIM main Output. 1237 * @param __HANDLE__ TIM handle 1238 * @retval None 1239 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1240 * disabled 1241 */ 1242 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1243 do { \ 1244 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1245 { \ 1246 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1247 { \ 1248 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1249 } \ 1250 } \ 1251 } while(0) 1252 1253 /** 1254 * @brief Disable the TIM main Output. 1255 * @param __HANDLE__ TIM handle 1256 * @retval None 1257 * @note The Main Output Enable of a timer instance is disabled unconditionally 1258 */ 1259 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1260 1261 /** @brief Enable the specified TIM interrupt. 1262 * @param __HANDLE__ specifies the TIM Handle. 1263 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1264 * This parameter can be one of the following values: 1265 * @arg TIM_IT_UPDATE: Update interrupt 1266 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1267 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1268 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1269 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1270 * @arg TIM_IT_COM: Commutation interrupt 1271 * @arg TIM_IT_TRIGGER: Trigger interrupt 1272 * @arg TIM_IT_BREAK: Break interrupt 1273 * @retval None 1274 */ 1275 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1276 1277 /** @brief Disable the specified TIM interrupt. 1278 * @param __HANDLE__ specifies the TIM Handle. 1279 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1280 * This parameter can be one of the following values: 1281 * @arg TIM_IT_UPDATE: Update interrupt 1282 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1283 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1284 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1285 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1286 * @arg TIM_IT_COM: Commutation interrupt 1287 * @arg TIM_IT_TRIGGER: Trigger interrupt 1288 * @arg TIM_IT_BREAK: Break interrupt 1289 * @retval None 1290 */ 1291 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1292 1293 /** @brief Enable the specified DMA request. 1294 * @param __HANDLE__ specifies the TIM Handle. 1295 * @param __DMA__ specifies the TIM DMA request to enable. 1296 * This parameter can be one of the following values: 1297 * @arg TIM_DMA_UPDATE: Update DMA request 1298 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1299 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1300 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1301 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1302 * @arg TIM_DMA_COM: Commutation DMA request 1303 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1304 * @retval None 1305 */ 1306 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1307 1308 /** @brief Disable the specified DMA request. 1309 * @param __HANDLE__ specifies the TIM Handle. 1310 * @param __DMA__ specifies the TIM DMA request to disable. 1311 * This parameter can be one of the following values: 1312 * @arg TIM_DMA_UPDATE: Update DMA request 1313 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1314 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1315 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1316 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1317 * @arg TIM_DMA_COM: Commutation DMA request 1318 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1319 * @retval None 1320 */ 1321 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1322 1323 /** @brief Check whether the specified TIM interrupt flag is set or not. 1324 * @param __HANDLE__ specifies the TIM Handle. 1325 * @param __FLAG__ specifies the TIM interrupt flag to check. 1326 * This parameter can be one of the following values: 1327 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1328 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1329 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1330 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1331 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1332 * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) 1333 * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) 1334 * @arg TIM_FLAG_COM: Commutation interrupt flag 1335 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1336 * @arg TIM_FLAG_BREAK: Break interrupt flag 1337 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) 1338 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1339 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1340 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1341 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1342 * (*) Value not defined for all devices 1343 * @retval The new state of __FLAG__ (TRUE or FALSE). 1344 */ 1345 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1346 1347 /** @brief Clear the specified TIM interrupt flag. 1348 * @param __HANDLE__ specifies the TIM Handle. 1349 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1350 * This parameter can be one of the following values: 1351 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1352 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1353 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1354 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1355 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1356 * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) 1357 * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) 1358 * @arg TIM_FLAG_COM: Commutation interrupt flag 1359 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1360 * @arg TIM_FLAG_BREAK: Break interrupt flag 1361 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) 1362 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1363 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1364 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1365 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1366 * (*) Value not defined for all devices 1367 * @retval The new state of __FLAG__ (TRUE or FALSE). 1368 */ 1369 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1370 1371 /** 1372 * @brief Check whether the specified TIM interrupt source is enabled or not. 1373 * @param __HANDLE__ TIM handle 1374 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1375 * This parameter can be one of the following values: 1376 * @arg TIM_IT_UPDATE: Update interrupt 1377 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1378 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1379 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1380 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1381 * @arg TIM_IT_COM: Commutation interrupt 1382 * @arg TIM_IT_TRIGGER: Trigger interrupt 1383 * @arg TIM_IT_BREAK: Break interrupt 1384 * @retval The state of TIM_IT (SET or RESET). 1385 */ 1386 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1387 == (__INTERRUPT__)) ? SET : RESET) 1388 1389 /** @brief Clear the TIM interrupt pending bits. 1390 * @param __HANDLE__ TIM handle 1391 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1392 * This parameter can be one of the following values: 1393 * @arg TIM_IT_UPDATE: Update interrupt 1394 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1395 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1396 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1397 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1398 * @arg TIM_IT_COM: Commutation interrupt 1399 * @arg TIM_IT_TRIGGER: Trigger interrupt 1400 * @arg TIM_IT_BREAK: Break interrupt 1401 * @retval None 1402 */ 1403 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1404 #if defined(TIM_CR1_UIFREMAP) 1405 1406 /** 1407 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1408 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1409 * in an atomic way. 1410 * @param __HANDLE__ TIM handle. 1411 * @retval None 1412 mode. 1413 */ 1414 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1415 1416 /** 1417 * @brief Disable update interrupt flag (UIF) remapping. 1418 * @param __HANDLE__ TIM handle. 1419 * @retval None 1420 mode. 1421 */ 1422 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1423 1424 /** 1425 * @brief Get update interrupt flag (UIF) copy status. 1426 * @param __COUNTER__ Counter value. 1427 * @retval The state of UIFCPY (TRUE or FALSE). 1428 mode. 1429 */ 1430 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1431 #endif /* TIM_CR1_UIFREMAP */ 1432 1433 /** 1434 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1435 * @param __HANDLE__ TIM handle. 1436 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1437 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1438 * or Encoder mode. 1439 */ 1440 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1441 1442 /** 1443 * @brief Set the TIM Prescaler on runtime. 1444 * @param __HANDLE__ TIM handle. 1445 * @param __PRESC__ specifies the Prescaler new value. 1446 * @retval None 1447 */ 1448 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1449 1450 /** 1451 * @brief Set the TIM Counter Register value on runtime. 1452 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1453 * case of 32 bits counter TIM instance. 1454 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1455 * @param __HANDLE__ TIM handle. 1456 * @param __COUNTER__ specifies the Counter register new value. 1457 * @retval None 1458 */ 1459 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1460 1461 /** 1462 * @brief Get the TIM Counter Register value on runtime. 1463 * @param __HANDLE__ TIM handle. 1464 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1465 */ 1466 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1467 1468 /** 1469 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1470 * @param __HANDLE__ TIM handle. 1471 * @param __AUTORELOAD__ specifies the Counter register new value. 1472 * @retval None 1473 */ 1474 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1475 do{ \ 1476 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1477 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1478 } while(0) 1479 1480 /** 1481 * @brief Get the TIM Autoreload Register value on runtime. 1482 * @param __HANDLE__ TIM handle. 1483 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1484 */ 1485 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1486 1487 /** 1488 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1489 * @param __HANDLE__ TIM handle. 1490 * @param __CKD__ specifies the clock division value. 1491 * This parameter can be one of the following value: 1492 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1493 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1494 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1495 * @retval None 1496 */ 1497 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1498 do{ \ 1499 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1500 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1501 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1502 } while(0) 1503 1504 /** 1505 * @brief Get the TIM Clock Division value on runtime. 1506 * @param __HANDLE__ TIM handle. 1507 * @retval The clock division can be one of the following values: 1508 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1509 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1510 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1511 */ 1512 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1513 1514 /** 1515 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1516 * function. 1517 * @param __HANDLE__ TIM handle. 1518 * @param __CHANNEL__ TIM Channels to be configured. 1519 * This parameter can be one of the following values: 1520 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1521 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1522 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1523 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1524 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1525 * This parameter can be one of the following values: 1526 * @arg TIM_ICPSC_DIV1: no prescaler 1527 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1528 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1529 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1530 * @retval None 1531 */ 1532 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1533 do{ \ 1534 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1535 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1536 } while(0) 1537 1538 /** 1539 * @brief Get the TIM Input Capture prescaler on runtime. 1540 * @param __HANDLE__ TIM handle. 1541 * @param __CHANNEL__ TIM Channels to be configured. 1542 * This parameter can be one of the following values: 1543 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1544 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1545 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1546 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1547 * @retval The input capture prescaler can be one of the following values: 1548 * @arg TIM_ICPSC_DIV1: no prescaler 1549 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1550 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1551 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1552 */ 1553 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1554 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1555 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1556 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1557 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1558 1559 /** 1560 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1561 * @param __HANDLE__ TIM handle. 1562 * @param __CHANNEL__ TIM Channels to be configured. 1563 * This parameter can be one of the following values: 1564 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1565 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1566 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1567 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1568 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1569 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1570 * (*) Value not defined for all devices 1571 * @param __COMPARE__ specifies the Capture Compare register new value. 1572 * @retval None 1573 */ 1574 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1575 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1576 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1577 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1578 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1579 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1580 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1581 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1582 #else 1583 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1584 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1585 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1586 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1587 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) 1588 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1589 1590 /** 1591 * @brief Get the TIM Capture Compare Register value on runtime. 1592 * @param __HANDLE__ TIM handle. 1593 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1594 * This parameter can be one of the following values: 1595 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1596 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1597 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1598 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1599 * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) 1600 * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) 1601 * (*) Value not defined for all devices 1602 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1603 */ 1604 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1605 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1606 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1607 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1608 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1609 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1610 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1611 ((__HANDLE__)->Instance->CCR6)) 1612 #else 1613 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1614 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1615 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1616 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1617 ((__HANDLE__)->Instance->CCR4)) 1618 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1619 1620 /** 1621 * @brief Set the TIM Output compare preload. 1622 * @param __HANDLE__ TIM handle. 1623 * @param __CHANNEL__ TIM Channels to be configured. 1624 * This parameter can be one of the following values: 1625 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1626 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1627 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1628 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1629 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1630 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1631 * (*) Value not defined for all devices 1632 * @retval None 1633 */ 1634 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1635 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1636 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1637 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1638 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1639 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1640 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1641 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1642 #else 1643 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1644 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1645 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1646 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1647 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) 1648 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1649 1650 /** 1651 * @brief Reset the TIM Output compare preload. 1652 * @param __HANDLE__ TIM handle. 1653 * @param __CHANNEL__ TIM Channels to be configured. 1654 * This parameter can be one of the following values: 1655 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1656 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1657 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1658 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1659 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1660 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1661 * (*) Value not defined for all devices 1662 * @retval None 1663 */ 1664 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1665 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1666 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1667 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1668 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1669 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1670 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1671 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1672 #else 1673 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1674 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1675 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1676 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1677 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) 1678 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1679 1680 /** 1681 * @brief Enable fast mode for a given channel. 1682 * @param __HANDLE__ TIM handle. 1683 * @param __CHANNEL__ TIM Channels to be configured. 1684 * This parameter can be one of the following values: 1685 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1686 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1687 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1688 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1689 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1690 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1691 * (*) Value not defined for all devices 1692 * @note When fast mode is enabled an active edge on the trigger input acts 1693 * like a compare match on CCx output. Delay to sample the trigger 1694 * input and to activate CCx output is reduced to 3 clock cycles. 1695 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1696 * @retval None 1697 */ 1698 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1699 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1700 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1701 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1702 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1703 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1704 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1705 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1706 #else 1707 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1708 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1709 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1710 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1711 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) 1712 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1713 1714 /** 1715 * @brief Disable fast mode for a given channel. 1716 * @param __HANDLE__ TIM handle. 1717 * @param __CHANNEL__ TIM Channels to be configured. 1718 * This parameter can be one of the following values: 1719 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1720 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1721 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1722 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1723 * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) 1724 * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) 1725 * (*) Value not defined for all devices 1726 * @note When fast mode is disabled CCx output behaves normally depending 1727 * on counter and CCRx values even when the trigger is ON. The minimum 1728 * delay to activate CCx output when an active edge occurs on the 1729 * trigger input is 5 clock cycles. 1730 * @retval None 1731 */ 1732 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1733 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1734 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1735 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1736 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1737 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1738 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1739 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1740 #else 1741 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1742 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1743 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1744 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1745 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) 1746 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1747 1748 /** 1749 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1750 * @param __HANDLE__ TIM handle. 1751 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1752 * overflow/underflow generates an update interrupt or DMA request (if 1753 * enabled) 1754 * @retval None 1755 */ 1756 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1757 1758 /** 1759 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1760 * @param __HANDLE__ TIM handle. 1761 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1762 * following events generate an update interrupt or DMA request (if 1763 * enabled): 1764 * _ Counter overflow underflow 1765 * _ Setting the UG bit 1766 * _ Update generation through the slave mode controller 1767 * @retval None 1768 */ 1769 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1770 1771 /** 1772 * @brief Set the TIM Capture x input polarity on runtime. 1773 * @param __HANDLE__ TIM handle. 1774 * @param __CHANNEL__ TIM Channels to be configured. 1775 * This parameter can be one of the following values: 1776 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1777 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1778 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1779 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1780 * @param __POLARITY__ Polarity for TIx source 1781 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1782 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1783 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1784 * @retval None 1785 */ 1786 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1787 do{ \ 1788 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1789 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1790 }while(0) 1791 1792 /** @brief Select the Capture/compare DMA request source. 1793 * @param __HANDLE__ specifies the TIM Handle. 1794 * @param __CCDMA__ specifies Capture/compare DMA request source 1795 * This parameter can be one of the following values: 1796 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1797 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1798 * @retval None 1799 */ 1800 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1801 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1802 1803 /** 1804 * @} 1805 */ 1806 /* End of exported macros ----------------------------------------------------*/ 1807 1808 /* Private constants ---------------------------------------------------------*/ 1809 /** @defgroup TIM_Private_Constants TIM Private Constants 1810 * @{ 1811 */ 1812 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1813 channels have been disabled */ 1814 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1815 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1816 /** 1817 * @} 1818 */ 1819 /* End of private constants --------------------------------------------------*/ 1820 1821 /* Private macros ------------------------------------------------------------*/ 1822 /** @defgroup TIM_Private_Macros TIM Private Macros 1823 * @{ 1824 */ 1825 #if defined(TIM_SMCR_OCCS) 1826 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1827 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1828 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) 1829 #else 1830 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1831 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1832 #endif /* TIM_SMCR_OCCS */ 1833 1834 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1835 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1836 ((__BASE__) == TIM_DMABASE_CR2) || \ 1837 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1838 ((__BASE__) == TIM_DMABASE_DIER) || \ 1839 ((__BASE__) == TIM_DMABASE_SR) || \ 1840 ((__BASE__) == TIM_DMABASE_EGR) || \ 1841 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1842 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1843 ((__BASE__) == TIM_DMABASE_CCER) || \ 1844 ((__BASE__) == TIM_DMABASE_CNT) || \ 1845 ((__BASE__) == TIM_DMABASE_PSC) || \ 1846 ((__BASE__) == TIM_DMABASE_ARR) || \ 1847 ((__BASE__) == TIM_DMABASE_RCR) || \ 1848 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1849 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1850 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1851 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1852 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1853 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1854 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1855 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1856 ((__BASE__) == TIM_DMABASE_OR)) 1857 #else 1858 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1859 ((__BASE__) == TIM_DMABASE_CR2) || \ 1860 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1861 ((__BASE__) == TIM_DMABASE_DIER) || \ 1862 ((__BASE__) == TIM_DMABASE_SR) || \ 1863 ((__BASE__) == TIM_DMABASE_EGR) || \ 1864 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1865 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1866 ((__BASE__) == TIM_DMABASE_CCER) || \ 1867 ((__BASE__) == TIM_DMABASE_CNT) || \ 1868 ((__BASE__) == TIM_DMABASE_PSC) || \ 1869 ((__BASE__) == TIM_DMABASE_ARR) || \ 1870 ((__BASE__) == TIM_DMABASE_RCR) || \ 1871 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1872 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1873 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1874 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1875 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1876 ((__BASE__) == TIM_DMABASE_OR)) 1877 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 1878 1879 #if defined(TIM_EGR_B2G) 1880 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1881 #else 1882 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1883 #endif /* TIM_EGR_B2G */ 1884 1885 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1886 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1887 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1888 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1889 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1890 1891 #if defined(TIM_CR1_UIFREMAP) 1892 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1893 ((__MODE__) == TIM_UIFREMAP_ENABLE)) 1894 1895 #endif /* TIM_CR1_UIFREMAP */ 1896 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1897 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1898 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1899 1900 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1901 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1902 1903 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1904 ((__STATE__) == TIM_OCFAST_ENABLE)) 1905 1906 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1907 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1908 1909 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1910 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1911 1912 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1913 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1914 1915 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1916 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1917 1918 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1919 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1920 1921 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1922 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1923 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1924 1925 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1926 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1927 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1928 1929 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1930 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1931 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1932 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1933 1934 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1935 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1936 1937 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1938 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1939 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1940 1941 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1942 1943 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 1944 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1945 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1946 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1947 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1948 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1949 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1950 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1951 #else 1952 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1953 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1954 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1955 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1956 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1957 #endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ 1958 1959 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1960 ((__CHANNEL__) == TIM_CHANNEL_2)) 1961 1962 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ 1963 ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) 1964 1965 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1966 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1967 ((__CHANNEL__) == TIM_CHANNEL_3)) 1968 1969 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1970 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1971 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1972 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1973 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1974 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1975 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1976 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1977 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1978 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) 1979 1980 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1981 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1982 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1983 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1984 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1985 1986 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1987 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1988 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1989 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1990 1991 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1992 1993 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1994 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1995 1996 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1997 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1998 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1999 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 2000 2001 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2002 2003 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 2004 ((__STATE__) == TIM_OSSR_DISABLE)) 2005 2006 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 2007 ((__STATE__) == TIM_OSSI_DISABLE)) 2008 2009 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 2010 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 2011 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 2012 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 2013 2014 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 2015 2016 2017 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 2018 ((__STATE__) == TIM_BREAK_DISABLE)) 2019 2020 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 2021 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 2022 2023 #if defined(TIM_BDTR_BK2E) 2024 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 2025 ((__STATE__) == TIM_BREAK2_DISABLE)) 2026 2027 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 2028 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 2029 #endif /* TIM_BDTR_BK2E */ 2030 2031 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 2032 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 2033 2034 #if defined(TIM_CCR5_CCR5) 2035 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 2036 #endif /* TIM_CCR5_CCR5 */ 2037 2038 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 2039 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 2040 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 2041 ((__SOURCE__) == TIM_TRGO_OC1) || \ 2042 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 2043 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 2044 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 2045 ((__SOURCE__) == TIM_TRGO_OC4REF)) 2046 2047 #if defined(TIM_CR2_MMS2) 2048 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 2049 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 2050 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 2051 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 2052 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 2053 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 2054 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2055 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2056 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 2057 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 2058 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 2059 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 2060 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 2061 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 2062 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 2063 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 2064 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 2065 #endif /* TIM_CR2_MMS2 */ 2066 2067 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 2068 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 2069 2070 #if defined (TIM_SMCR_SMS_3) 2071 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2072 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2073 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2074 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2075 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2076 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2077 #else 2078 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2079 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2080 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2081 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2082 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) 2083 #endif /* TIM_SMCR_SMS_3 */ 2084 2085 #if defined(TIM_CCMR1_OC1M_3) 2086 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2087 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2088 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2089 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2090 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 2091 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 2092 #else 2093 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2094 ((__MODE__) == TIM_OCMODE_PWM2)) 2095 #endif /* TIM_CCMR1_OC1M_3 */ 2096 2097 #if defined(TIM_CCMR1_OC1M_3) 2098 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2099 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2100 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2101 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2102 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2103 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2104 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2105 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 2106 #else 2107 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2108 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2109 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2110 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2111 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2112 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) 2113 #endif /* TIM_CCMR1_OC1M_3 */ 2114 2115 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2116 ((__SELECTION__) == TIM_TS_ITR1) || \ 2117 ((__SELECTION__) == TIM_TS_ITR2) || \ 2118 ((__SELECTION__) == TIM_TS_ITR3) || \ 2119 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 2120 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 2121 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 2122 ((__SELECTION__) == TIM_TS_ETRF)) 2123 2124 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2125 ((__SELECTION__) == TIM_TS_ITR1) || \ 2126 ((__SELECTION__) == TIM_TS_ITR2) || \ 2127 ((__SELECTION__) == TIM_TS_ITR3) || \ 2128 ((__SELECTION__) == TIM_TS_NONE)) 2129 2130 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2131 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2132 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2133 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2134 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2135 2136 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2137 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2138 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2139 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2140 2141 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2142 2143 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2144 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2145 2146 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2147 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2148 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2149 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2150 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2151 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2152 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2153 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2154 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2155 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2156 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2157 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2158 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2159 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2160 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2161 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2162 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2163 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 2164 2165 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2166 2167 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2168 2169 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2170 2171 #if defined (TIM_SMCR_SMS_3) 2172 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2173 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2174 #else 2175 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) 2176 #endif /* TIM_SMCR_SMS_3 */ 2177 2178 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2179 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2180 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2181 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2182 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2183 2184 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2185 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2186 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2187 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2188 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2189 2190 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2191 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2192 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2193 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2194 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2195 2196 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2197 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2198 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2199 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2200 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2201 2202 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) 2203 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2204 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2205 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2206 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2207 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2208 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2209 (__HANDLE__)->ChannelState[5]) 2210 2211 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2212 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2213 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2214 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2215 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2216 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2217 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2218 2219 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2220 (__HANDLE__)->ChannelState[0] = \ 2221 (__CHANNEL_STATE__); \ 2222 (__HANDLE__)->ChannelState[1] = \ 2223 (__CHANNEL_STATE__); \ 2224 (__HANDLE__)->ChannelState[2] = \ 2225 (__CHANNEL_STATE__); \ 2226 (__HANDLE__)->ChannelState[3] = \ 2227 (__CHANNEL_STATE__); \ 2228 (__HANDLE__)->ChannelState[4] = \ 2229 (__CHANNEL_STATE__); \ 2230 (__HANDLE__)->ChannelState[5] = \ 2231 (__CHANNEL_STATE__); \ 2232 } while(0) 2233 #else 2234 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2235 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2236 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2237 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2238 (__HANDLE__)->ChannelState[3]) 2239 2240 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2241 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2242 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2243 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2244 ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) 2245 2246 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2247 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 2248 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 2249 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 2250 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 2251 } while(0) 2252 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ 2253 2254 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2255 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2256 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2257 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2258 (__HANDLE__)->ChannelNState[3]) 2259 2260 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2261 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2262 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2263 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2264 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2265 2266 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2267 (__HANDLE__)->ChannelNState[0] = \ 2268 (__CHANNEL_STATE__); \ 2269 (__HANDLE__)->ChannelNState[1] = \ 2270 (__CHANNEL_STATE__); \ 2271 (__HANDLE__)->ChannelNState[2] = \ 2272 (__CHANNEL_STATE__); \ 2273 (__HANDLE__)->ChannelNState[3] = \ 2274 (__CHANNEL_STATE__); \ 2275 } while(0) 2276 2277 /** 2278 * @} 2279 */ 2280 /* End of private macros -----------------------------------------------------*/ 2281 2282 /* Include TIM HAL Extended module */ 2283 #include "stm32f3xx_hal_tim_ex.h" 2284 2285 /* Exported functions --------------------------------------------------------*/ 2286 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2287 * @{ 2288 */ 2289 2290 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2291 * @brief Time Base functions 2292 * @{ 2293 */ 2294 /* Time Base functions ********************************************************/ 2295 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2296 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2297 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2298 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2299 /* Blocking mode: Polling */ 2300 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2301 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2302 /* Non-Blocking mode: Interrupt */ 2303 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2304 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2305 /* Non-Blocking mode: DMA */ 2306 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 2307 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2308 /** 2309 * @} 2310 */ 2311 2312 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2313 * @brief TIM Output Compare functions 2314 * @{ 2315 */ 2316 /* Timer Output Compare functions *********************************************/ 2317 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2318 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2319 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2320 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2321 /* Blocking mode: Polling */ 2322 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2323 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2324 /* Non-Blocking mode: Interrupt */ 2325 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2326 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2327 /* Non-Blocking mode: DMA */ 2328 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2329 uint16_t Length); 2330 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2331 /** 2332 * @} 2333 */ 2334 2335 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2336 * @brief TIM PWM functions 2337 * @{ 2338 */ 2339 /* Timer PWM functions ********************************************************/ 2340 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2341 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2342 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2343 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2344 /* Blocking mode: Polling */ 2345 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2346 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2347 /* Non-Blocking mode: Interrupt */ 2348 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2349 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2350 /* Non-Blocking mode: DMA */ 2351 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2352 uint16_t Length); 2353 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2354 /** 2355 * @} 2356 */ 2357 2358 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2359 * @brief TIM Input Capture functions 2360 * @{ 2361 */ 2362 /* Timer Input Capture functions **********************************************/ 2363 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2364 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2365 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2366 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2367 /* Blocking mode: Polling */ 2368 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2369 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2370 /* Non-Blocking mode: Interrupt */ 2371 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2372 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2373 /* Non-Blocking mode: DMA */ 2374 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2375 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2376 /** 2377 * @} 2378 */ 2379 2380 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2381 * @brief TIM One Pulse functions 2382 * @{ 2383 */ 2384 /* Timer One Pulse functions **************************************************/ 2385 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2386 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2387 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2388 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2389 /* Blocking mode: Polling */ 2390 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2391 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2392 /* Non-Blocking mode: Interrupt */ 2393 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2394 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2395 /** 2396 * @} 2397 */ 2398 2399 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2400 * @brief TIM Encoder functions 2401 * @{ 2402 */ 2403 /* Timer Encoder functions ****************************************************/ 2404 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); 2405 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2406 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2407 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2408 /* Blocking mode: Polling */ 2409 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2410 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2411 /* Non-Blocking mode: Interrupt */ 2412 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2413 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2414 /* Non-Blocking mode: DMA */ 2415 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2416 uint32_t *pData2, uint16_t Length); 2417 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2418 /** 2419 * @} 2420 */ 2421 2422 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2423 * @brief IRQ handler management 2424 * @{ 2425 */ 2426 /* Interrupt Handler functions ***********************************************/ 2427 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2428 /** 2429 * @} 2430 */ 2431 2432 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2433 * @brief Peripheral Control functions 2434 * @{ 2435 */ 2436 /* Control functions *********************************************************/ 2437 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2438 uint32_t Channel); 2439 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2440 uint32_t Channel); 2441 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 2442 uint32_t Channel); 2443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2444 uint32_t OutputChannel, uint32_t InputChannel); 2445 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 2446 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 2447 uint32_t Channel); 2448 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 2449 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2450 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2451 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2452 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2453 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); 2454 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2455 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2456 uint32_t BurstLength, uint32_t DataLength); 2457 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2458 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2459 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2460 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2461 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2462 uint32_t BurstLength, uint32_t DataLength); 2463 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2464 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2465 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 2466 /** 2467 * @} 2468 */ 2469 2470 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2471 * @brief TIM Callbacks functions 2472 * @{ 2473 */ 2474 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2475 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2476 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2477 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2478 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2479 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2480 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2481 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2482 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2483 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2484 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2485 2486 /* Callbacks Register/UnRegister functions ***********************************/ 2487 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2488 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2489 pTIM_CallbackTypeDef pCallback); 2490 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2491 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2492 2493 /** 2494 * @} 2495 */ 2496 2497 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2498 * @brief Peripheral State functions 2499 * @{ 2500 */ 2501 /* Peripheral State functions ************************************************/ 2502 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 2503 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 2504 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 2505 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 2506 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 2507 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 2508 2509 /* Peripheral Channel state functions ************************************************/ 2510 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 2511 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 2512 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 2513 /** 2514 * @} 2515 */ 2516 2517 /** 2518 * @} 2519 */ 2520 /* End of exported functions -------------------------------------------------*/ 2521 2522 /* Private functions----------------------------------------------------------*/ 2523 /** @defgroup TIM_Private_Functions TIM Private Functions 2524 * @{ 2525 */ 2526 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); 2527 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2528 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); 2529 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2530 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2531 2532 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2533 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2534 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2535 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2536 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2537 2538 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2539 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2540 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2541 2542 /** 2543 * @} 2544 */ 2545 /* End of private functions --------------------------------------------------*/ 2546 2547 /** 2548 * @} 2549 */ 2550 2551 /** 2552 * @} 2553 */ 2554 2555 #ifdef __cplusplus 2556 } 2557 #endif 2558 2559 #endif /* STM32F3xx_HAL_TIM_H */ 2560
