1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F3xx_HAL_DMA_H 21 #define __STM32F3xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f3xx_hal_def.h" 29 30 /** @addtogroup STM32F3xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 50 from memory to memory or from peripheral to memory. 51 This parameter can be a value of @ref DMA_Data_transfer_direction */ 52 53 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 54 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 55 56 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 58 59 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 60 This parameter can be a value of @ref DMA_Peripheral_data_size */ 61 62 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 63 This parameter can be a value of @ref DMA_Memory_data_size */ 64 65 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 66 This parameter can be a value of @ref DMA_mode 67 @note The circular buffer mode cannot be used if the memory-to-memory 68 data transfer is configured on the selected Channel */ 69 70 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 71 This parameter can be a value of @ref DMA_Priority_level */ 72 } DMA_InitTypeDef; 73 74 /** 75 * @brief HAL DMA State structures definition 76 */ 77 typedef enum 78 { 79 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 80 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 81 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 82 HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */ 83 }HAL_DMA_StateTypeDef; 84 85 /** 86 * @brief HAL DMA Error Code structure definition 87 */ 88 typedef enum 89 { 90 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 91 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ 92 }HAL_DMA_LevelCompleteTypeDef; 93 94 /** 95 * @brief HAL DMA Callback ID structure definition 96 */ 97 typedef enum 98 { 99 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 100 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 101 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 102 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 103 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ 104 }HAL_DMA_CallbackIDTypeDef; 105 106 /** 107 * @brief DMA handle Structure definition 108 */ 109 typedef struct __DMA_HandleTypeDef 110 { 111 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 112 113 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 114 115 HAL_LockTypeDef Lock; /*!< DMA locking object */ 116 117 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 118 119 void *Parent; /*!< Parent object state */ 120 121 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 122 123 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 124 125 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 126 127 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 128 129 __IO uint32_t ErrorCode; /*!< DMA Error code */ 130 131 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 132 133 uint32_t ChannelIndex; /*!< DMA Channel Index */ 134 } DMA_HandleTypeDef; 135 /** 136 * @} 137 */ 138 139 /* Exported constants --------------------------------------------------------*/ 140 141 /** @defgroup DMA_Exported_Constants DMA Exported Constants 142 * @{ 143 */ 144 145 /** @defgroup DMA_Error_Code DMA Error Code 146 * @{ 147 */ 148 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 149 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 150 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ 151 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 152 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 153 /** 154 * @} 155 */ 156 157 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 158 * @{ 159 */ 160 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ 161 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 162 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ 163 164 /** 165 * @} 166 */ 167 168 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 169 * @{ 170 */ 171 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 172 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ 173 /** 174 * @} 175 */ 176 177 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 178 * @{ 179 */ 180 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 181 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ 182 /** 183 * @} 184 */ 185 186 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 187 * @{ 188 */ 189 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ 190 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ 191 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup DMA_Memory_data_size DMA Memory data size 197 * @{ 198 */ 199 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ 200 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ 201 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ 202 /** 203 * @} 204 */ 205 206 /** @defgroup DMA_mode DMA mode 207 * @{ 208 */ 209 #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ 210 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup DMA_Priority_level DMA Priority level 216 * @{ 217 */ 218 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ 219 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 220 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 221 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 222 /** 223 * @} 224 */ 225 226 227 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 228 * @{ 229 */ 230 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 231 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 232 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 233 /** 234 * @} 235 */ 236 237 /** @defgroup DMA_flag_definitions DMA flag definitions 238 * @{ 239 */ 240 #define DMA_FLAG_GL1 (0x00000001U) 241 #define DMA_FLAG_TC1 (0x00000002U) 242 #define DMA_FLAG_HT1 (0x00000004U) 243 #define DMA_FLAG_TE1 (0x00000008U) 244 #define DMA_FLAG_GL2 (0x00000010U) 245 #define DMA_FLAG_TC2 (0x00000020U) 246 #define DMA_FLAG_HT2 (0x00000040U) 247 #define DMA_FLAG_TE2 (0x00000080U) 248 #define DMA_FLAG_GL3 (0x00000100U) 249 #define DMA_FLAG_TC3 (0x00000200U) 250 #define DMA_FLAG_HT3 (0x00000400U) 251 #define DMA_FLAG_TE3 (0x00000800U) 252 #define DMA_FLAG_GL4 (0x00001000U) 253 #define DMA_FLAG_TC4 (0x00002000U) 254 #define DMA_FLAG_HT4 (0x00004000U) 255 #define DMA_FLAG_TE4 (0x00008000U) 256 #define DMA_FLAG_GL5 (0x00010000U) 257 #define DMA_FLAG_TC5 (0x00020000U) 258 #define DMA_FLAG_HT5 (0x00040000U) 259 #define DMA_FLAG_TE5 (0x00080000U) 260 #define DMA_FLAG_GL6 (0x00100000U) 261 #define DMA_FLAG_TC6 (0x00200000U) 262 #define DMA_FLAG_HT6 (0x00400000U) 263 #define DMA_FLAG_TE6 (0x00800000U) 264 #define DMA_FLAG_GL7 (0x01000000U) 265 #define DMA_FLAG_TC7 (0x02000000U) 266 #define DMA_FLAG_HT7 (0x04000000U) 267 #define DMA_FLAG_TE7 (0x08000000U) 268 /** 269 * @} 270 */ 271 272 /** 273 * @} 274 */ 275 276 277 /* Exported macro ------------------------------------------------------------*/ 278 /** @defgroup DMA_Exported_Macros DMA Exported Macros 279 * @{ 280 */ 281 282 /** @brief Reset DMA handle state 283 * @param __HANDLE__ DMA handle. 284 * @retval None 285 */ 286 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 287 288 /** 289 * @brief Enable the specified DMA Channel. 290 * @param __HANDLE__ DMA handle 291 * @retval None 292 */ 293 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 294 295 /** 296 * @brief Disable the specified DMA Channel. 297 * @param __HANDLE__ DMA handle 298 * @retval None 299 */ 300 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 301 302 303 /* Interrupt & Flag management */ 304 305 /** 306 * @brief Enables the specified DMA Channel interrupts. 307 * @param __HANDLE__ DMA handle 308 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 309 * This parameter can be any combination of the following values: 310 * @arg DMA_IT_TC: Transfer complete interrupt mask 311 * @arg DMA_IT_HT: Half transfer complete interrupt mask 312 * @arg DMA_IT_TE: Transfer error interrupt mask 313 * @retval None 314 */ 315 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 316 317 /** 318 * @brief Disables the specified DMA Channel interrupts. 319 * @param __HANDLE__ DMA handle 320 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 321 * This parameter can be any combination of the following values: 322 * @arg DMA_IT_TC: Transfer complete interrupt mask 323 * @arg DMA_IT_HT: Half transfer complete interrupt mask 324 * @arg DMA_IT_TE: Transfer error interrupt mask 325 * @retval None 326 */ 327 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 328 329 /** 330 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. 331 * @param __HANDLE__ DMA handle 332 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 333 * This parameter can be one of the following values: 334 * @arg DMA_IT_TC: Transfer complete interrupt mask 335 * @arg DMA_IT_HT: Half transfer complete interrupt mask 336 * @arg DMA_IT_TE: Transfer error interrupt mask 337 * @retval The state of DMA_IT (SET or RESET). 338 */ 339 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 340 341 /** 342 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. 343 * @param __HANDLE__ DMA handle 344 * 345 * @retval The number of remaining data units in the current DMA Channel transfer. 346 */ 347 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 348 349 /** 350 * @} 351 */ 352 353 /* Include DMA HAL Extended module */ 354 #include "stm32f3xx_hal_dma_ex.h" 355 356 /* Exported functions --------------------------------------------------------*/ 357 /** @addtogroup DMA_Exported_Functions 358 * @{ 359 */ 360 361 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 362 * @{ 363 */ 364 /* Initialization and de-initialization functions *****************************/ 365 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 366 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 367 /** 368 * @} 369 */ 370 371 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions 372 * @{ 373 */ 374 /* Input and Output operation functions *****************************************************/ 375 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 376 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 377 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 378 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 379 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 380 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 381 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 382 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 383 /** 384 * @} 385 */ 386 387 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions 388 * @{ 389 */ 390 /* Peripheral State and Error functions ***************************************/ 391 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 392 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 /* Private macros ------------------------------------------------------------*/ 401 /** @defgroup DMA_Private_Macros DMA Private Macros 402 * @brief DMA private macros 403 * @{ 404 */ 405 406 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 407 408 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 409 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 410 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 411 412 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 413 ((STATE) == DMA_PINC_DISABLE)) 414 415 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 416 ((STATE) == DMA_MINC_DISABLE)) 417 418 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 419 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 420 ((SIZE) == DMA_PDATAALIGN_WORD)) 421 422 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 423 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 424 ((SIZE) == DMA_MDATAALIGN_WORD )) 425 426 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 427 ((MODE) == DMA_CIRCULAR)) 428 429 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 430 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 431 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 432 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 433 434 /** 435 * @} 436 */ 437 438 439 /** 440 * @} 441 */ 442 443 /** 444 * @} 445 */ 446 447 #ifdef __cplusplus 448 } 449 #endif 450 451 #endif /* __STM32F3xx_HAL_DMA_H */ 452 453
