1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f2xx_ll_utils.h"
21 #include "stm32f2xx_ll_rcc.h"
22 #include "stm32f2xx_ll_system.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32F2xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #define UTILS_MAX_FREQUENCY 120000000U /*!< Maximum frequency for system clock, in Hz */
44
45 /* Defines used for PLL range */
46 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
47 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
48 #define UTILS_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
49 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
50
51 /* Defines used for HSE range */
52 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
53 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
54
55 /* Defines used for FLASH latency according to HCLK Frequency */
56 #define UTILS_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
57 #define UTILS_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
58 #define UTILS_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
59 /**
60 * @}
61 */
62
63 /* Private macros ------------------------------------------------------------*/
64 /** @addtogroup UTILS_LL_Private_Macros
65 * @{
66 */
67 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
68 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
69 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
70 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
71 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
72 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
73 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
74 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
75 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
76
77 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
78 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
79 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
80 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
81 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
82
83 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
84 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
85 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
86 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
87 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
88
89 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
90 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
91 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
92 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
93 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
94 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
95 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
96 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
97 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
98 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
99 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
100 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
101 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
102 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
103 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
104 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
105 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
106 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
107 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
108 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
109 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
110 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
111 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
112 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
113 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
114 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
115 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
116 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
117 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
118 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
119 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
120 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
121 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
122 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
123 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
124 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
125 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
126 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
127 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
128 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
129 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
130 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
131 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
132 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
133 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
134 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
151
152 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((192 <= (__VALUE__)) && ((__VALUE__) <= 432))
153
154 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
155 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
156 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
157 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
158
159 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
160
161 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
162
163 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
164
165 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
166 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
167
168 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
169 /**
170 * @}
171 */
172 /* Private function prototypes -----------------------------------------------*/
173 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
174 * @{
175 */
176 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
177 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
178 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
179 static ErrorStatus UTILS_PLL_IsBusy(void);
180 /**
181 * @}
182 */
183
184 /* Exported functions --------------------------------------------------------*/
185 /** @addtogroup UTILS_LL_Exported_Functions
186 * @{
187 */
188
189 /** @addtogroup UTILS_LL_EF_DELAY
190 * @{
191 */
192
193 /**
194 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
195 * @note When a RTOS is used, it is recommended to avoid changing the Systick
196 * configuration by calling this function, for a delay use rather osDelay RTOS service.
197 * @param HCLKFrequency HCLK frequency in Hz
198 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
199 * @retval None
200 */
LL_Init1msTick(uint32_t HCLKFrequency)201 void LL_Init1msTick(uint32_t HCLKFrequency)
202 {
203 /* Use frequency provided in argument */
204 LL_InitTick(HCLKFrequency, 1000U);
205 }
206
207 /**
208 * @brief This function provides accurate delay (in milliseconds) based
209 * on SysTick counter flag
210 * @note When a RTOS is used, it is recommended to avoid using blocking delay
211 * and use rather osDelay service.
212 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
213 * will configure Systick to 1ms
214 * @param Delay specifies the delay time length, in milliseconds.
215 * @retval None
216 */
LL_mDelay(uint32_t Delay)217 void LL_mDelay(uint32_t Delay)
218 {
219 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
220 /* Add this code to indicate that local variable is not used */
221 ((void)tmp);
222
223 /* Add a period to guaranty minimum wait */
224 if(Delay < LL_MAX_DELAY)
225 {
226 Delay++;
227 }
228
229 while (Delay)
230 {
231 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
232 {
233 Delay--;
234 }
235 }
236 }
237
238 /**
239 * @}
240 */
241
242 /** @addtogroup UTILS_EF_SYSTEM
243 * @brief System Configuration functions
244 *
245 @verbatim
246 ===============================================================================
247 ##### System Configuration functions #####
248 ===============================================================================
249 [..]
250 System, AHB and APB buses clocks configuration
251
252 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 120000000 Hz.
253 @endverbatim
254 @internal
255 Depending on the device voltage range, the maximum frequency should be
256 adapted accordingly:
257
258 (++) Table 1. HCLK clock frequency.
259 (++) +------------------------------------------------------------------------------------------------+
260 (++) | Wait states | HCLK clock frequency (MHz) |
261 (++) | |-------------------------------------------------------------------------------|
262 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
263 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V |
264 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
265 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 18 | 0 < HCLK <= 16 |
266 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
267 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 18 < HCLK <= 36 | 16 < HCLK <= 32 |
268 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
269 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 36 < HCLK <= 54 | 32 < HCLK <= 48 |
270 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
271 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 54 < HCLK <= 72 | 48 < HCLK <= 64 |
272 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
273 (++) |4WS(5CPU cycle) | | 96 < HCLK <= 120 | 72 < HCLK <= 90 | 64 < HCLK <= 80 |
274 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
275 (++) |5WS(6CPU cycle) | | | 90 < HCLK <= 108 | 80 < HCLK <= 96 |
276 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
277 (++) |6WS(7CPU cycle) | | | 108 < HCLK <= 120 | 96 < HCLK <= 112 |
278 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
279 (++) |7WS(8CPU cycle) | | | | 112 < HCLK <= 120 |
280 (++) +------------------------------------------------------------------------------------------------+
281 @endinternal
282 * @{
283 */
284
285 /**
286 * @brief This function sets directly SystemCoreClock CMSIS variable.
287 * @note Variable can be calculated also through SystemCoreClockUpdate function.
288 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
289 * @retval None
290 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)291 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
292 {
293 /* HCLK clock frequency */
294 SystemCoreClock = HCLKFrequency;
295 }
296
297 /**
298 * @brief Update number of Flash wait states in line with new frequency and current
299 voltage range.
300 * @param HCLK_Frequency HCLK frequency
301 * @retval An ErrorStatus enumeration value:
302 * - SUCCESS: Latency has been modified
303 * - ERROR: Latency cannot be modified
304 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)305 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
306 {
307 uint32_t timeout;
308 uint32_t getlatency;
309 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
310 ErrorStatus status = SUCCESS;
311
312 /* Frequency cannot be equal to 0 */
313 if(HCLK_Frequency == 0U)
314 {
315 status = ERROR;
316 }
317 else
318 {
319 if(HCLK_Frequency > UTILS_LATENCY3_FREQ)
320 {
321 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
322 latency = LL_FLASH_LATENCY_3;
323 }
324 else if(HCLK_Frequency > UTILS_LATENCY2_FREQ)
325 {
326 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
327 latency = LL_FLASH_LATENCY_2;
328 }
329 else
330 {
331 if(HCLK_Frequency > UTILS_LATENCY1_FREQ)
332 {
333 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
334 latency = LL_FLASH_LATENCY_1;
335 }
336 else
337 {
338 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
339 latency = LL_FLASH_LATENCY_0;
340 }
341 }
342 if (status != ERROR)
343 {
344 LL_FLASH_SetLatency(latency);
345
346 /* Check that the new number of wait states is taken into account to access the Flash
347 memory by reading the FLASH_ACR register */
348 timeout = 2;
349 do
350 {
351 /* Wait for Flash latency to be updated */
352 getlatency = LL_FLASH_GetLatency();
353 timeout--;
354 } while ((getlatency != latency) && (timeout > 0));
355
356 if(getlatency != latency)
357 {
358 status = ERROR;
359 }
360 else
361 {
362 status = SUCCESS;
363 }
364 }
365 }
366 return status;
367 }
368
369 /**
370 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
371 * @note The application need to ensure that PLL is disabled.
372 * @note Function is based on the following formula:
373 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
374 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSI frequency / PLLM)
375 * - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
376 * - PLLP: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLP)
377 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
378 * the configuration information for the PLL.
379 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
380 * the configuration information for the BUS prescalers.
381 * @retval An ErrorStatus enumeration value:
382 * - SUCCESS: Max frequency configuration done
383 * - ERROR: Max frequency configuration not done
384 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)385 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
386 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
387 {
388 ErrorStatus status = SUCCESS;
389 uint32_t pllfreq = 0U;
390
391 /* Check if one of the PLL is enabled */
392 if(UTILS_PLL_IsBusy() == SUCCESS)
393 {
394 /* Calculate the new PLL output frequency */
395 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
396
397 /* Enable HSI if not enabled */
398 if(LL_RCC_HSI_IsReady() != 1U)
399 {
400 LL_RCC_HSI_Enable();
401 while (LL_RCC_HSI_IsReady() != 1U)
402 {
403 /* Wait for HSI ready */
404 }
405 }
406
407 /* Configure PLL */
408 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
409 UTILS_PLLInitStruct->PLLP);
410
411 /* Enable PLL and switch system clock to PLL */
412 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
413 }
414 else
415 {
416 /* Current PLL configuration cannot be modified */
417 status = ERROR;
418 }
419
420 return status;
421 }
422
423 /**
424 * @brief This function configures system clock with HSE as clock source of the PLL
425 * @note The application need to ensure that PLL is disabled.
426 * @note Function is based on the following formula:
427 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
428 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
429 * - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
430 * - PLLP: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLP)
431 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
432 * @param HSEBypass This parameter can be one of the following values:
433 * @arg @ref LL_UTILS_HSEBYPASS_ON
434 * @arg @ref LL_UTILS_HSEBYPASS_OFF
435 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
436 * the configuration information for the PLL.
437 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
438 * the configuration information for the BUS prescalers.
439 * @retval An ErrorStatus enumeration value:
440 * - SUCCESS: Max frequency configuration done
441 * - ERROR: Max frequency configuration not done
442 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)443 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
444 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
445 {
446 ErrorStatus status = SUCCESS;
447 uint32_t pllfreq = 0U;
448
449 /* Check the parameters */
450 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
451 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
452
453 /* Check if one of the PLL is enabled */
454 if(UTILS_PLL_IsBusy() == SUCCESS)
455 {
456 /* Calculate the new PLL output frequency */
457 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
458
459 /* Enable HSE if not enabled */
460 if(LL_RCC_HSE_IsReady() != 1U)
461 {
462 /* Check if need to enable HSE bypass feature or not */
463 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
464 {
465 LL_RCC_HSE_EnableBypass();
466 }
467 else
468 {
469 LL_RCC_HSE_DisableBypass();
470 }
471
472 /* Enable HSE */
473 LL_RCC_HSE_Enable();
474 while (LL_RCC_HSE_IsReady() != 1U)
475 {
476 /* Wait for HSE ready */
477 }
478 }
479
480 /* Configure PLL */
481 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
482 UTILS_PLLInitStruct->PLLP);
483
484 /* Enable PLL and switch system clock to PLL */
485 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
486 }
487 else
488 {
489 /* Current PLL configuration cannot be modified */
490 status = ERROR;
491 }
492
493 return status;
494 }
495
496 /**
497 * @}
498 */
499
500 /**
501 * @}
502 */
503
504 /** @addtogroup UTILS_LL_Private_Functions
505 * @{
506 */
507 /**
508 * @brief Function to check that PLL can be modified
509 * @param PLL_InputFrequency PLL input frequency (in Hz)
510 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
511 * the configuration information for the PLL.
512 * @retval PLL output frequency (in Hz)
513 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)514 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
515 {
516 uint32_t pllfreq = 0U;
517
518 /* Check the parameters */
519 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
520 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
521 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
522
523 /* Check different PLL parameters according to RM */
524 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
525 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
526 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
527
528 /* - PLLN: ensure that the VCO output frequency is between 192 and 432 MHz.*/
529 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
530 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
531
532 /* - PLLP: ensure that max frequency at 120000000 Hz is reached */
533 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
534 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
535
536 return pllfreq;
537 }
538
539 /**
540 * @brief Function to check that PLL can be modified
541 * @retval An ErrorStatus enumeration value:
542 * - SUCCESS: PLL modification can be done
543 * - ERROR: PLL is busy
544 */
UTILS_PLL_IsBusy(void)545 static ErrorStatus UTILS_PLL_IsBusy(void)
546 {
547 ErrorStatus status = SUCCESS;
548
549 /* Check if PLL is busy*/
550 if(LL_RCC_PLL_IsReady() != 0U)
551 {
552 /* PLL configuration cannot be modified */
553 status = ERROR;
554 }
555
556 /* Check if PLLI2S is busy*/
557 if(LL_RCC_PLLI2S_IsReady() != 0U)
558 {
559 /* PLLI2S configuration cannot be modified */
560 status = ERROR;
561 }
562 return status;
563 }
564
565 /**
566 * @brief Function to enable PLL and switch system clock to PLL
567 * @param SYSCLK_Frequency SYSCLK frequency
568 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
569 * the configuration information for the BUS prescalers.
570 * @retval An ErrorStatus enumeration value:
571 * - SUCCESS: No problem to switch system to PLL
572 * - ERROR: Problem to switch system to PLL
573 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)574 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
575 {
576 ErrorStatus status = SUCCESS;
577 uint32_t hclk_frequency = 0U;
578
579 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
580 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
581 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
582
583 /* Calculate HCLK frequency */
584 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
585
586 /* Increasing the number of wait states because of higher CPU frequency */
587 if(SystemCoreClock < hclk_frequency)
588 {
589 /* Set FLASH latency to highest latency */
590 status = LL_SetFlashLatency(hclk_frequency);
591 }
592
593 /* Update system clock configuration */
594 if(status == SUCCESS)
595 {
596 /* Enable PLL */
597 LL_RCC_PLL_Enable();
598 while (LL_RCC_PLL_IsReady() != 1U)
599 {
600 /* Wait for PLL ready */
601 }
602
603 /* Sysclk activation on the main PLL */
604 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
605 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
606 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
607 {
608 /* Wait for system clock switch to PLL */
609 }
610
611 /* Set APB1 & APB2 prescaler*/
612 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
613 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
614 }
615
616 /* Decreasing the number of wait states because of lower CPU frequency */
617 if(SystemCoreClock > hclk_frequency)
618 {
619 /* Set FLASH latency to lowest latency */
620 status = LL_SetFlashLatency(hclk_frequency);
621 }
622
623 /* Update SystemCoreClock variable */
624 if(status == SUCCESS)
625 {
626 LL_SetSystemCoreClock(hclk_frequency);
627 }
628
629 return status;
630 }
631
632 /**
633 * @}
634 */
635
636 /**
637 * @}
638 */
639
640 /**
641 * @}
642 */
643
