1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_usart.c
4 * @author MCD Application Team
5 * @brief USART LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f2xx_ll_usart.h"
23 #include "stm32f2xx_ll_rcc.h"
24 #include "stm32f2xx_ll_bus.h"
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F2xx_LL_Driver
32 * @{
33 */
34
35 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5)
36
37 /** @addtogroup USART_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup USART_LL_Private_Constants
45 * @{
46 */
47
48 /**
49 * @}
50 */
51
52
53 /* Private macros ------------------------------------------------------------*/
54 /** @addtogroup USART_LL_Private_Macros
55 * @{
56 */
57
58 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
59 * divided by the smallest oversampling used on the USART (i.e. 8) */
60 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 7500000U)
61
62 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
63 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
64
65 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
66 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
67 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
68 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
69
70 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
71 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
72 || ((__VALUE__) == LL_USART_PARITY_ODD))
73
74 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
75 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
76
77 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
78 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
79
80 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
81 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
82
83 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
84 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
85
86 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
87 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
88
89 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
90 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
91
92 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
93 || ((__VALUE__) == LL_USART_STOPBITS_1) \
94 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
95 || ((__VALUE__) == LL_USART_STOPBITS_2))
96
97 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
98 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
99 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
100 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
101
102 /**
103 * @}
104 */
105
106 /* Private function prototypes -----------------------------------------------*/
107
108 /* Exported functions --------------------------------------------------------*/
109 /** @addtogroup USART_LL_Exported_Functions
110 * @{
111 */
112
113 /** @addtogroup USART_LL_EF_Init
114 * @{
115 */
116
117 /**
118 * @brief De-initialize USART registers (Registers restored to their default values).
119 * @param USARTx USART Instance
120 * @retval An ErrorStatus enumeration value:
121 * - SUCCESS: USART registers are de-initialized
122 * - ERROR: USART registers are not de-initialized
123 */
LL_USART_DeInit(const USART_TypeDef * USARTx)124 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
125 {
126 ErrorStatus status = SUCCESS;
127
128 /* Check the parameters */
129 assert_param(IS_UART_INSTANCE(USARTx));
130
131 if (USARTx == USART1)
132 {
133 /* Force reset of USART clock */
134 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
135
136 /* Release reset of USART clock */
137 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
138 }
139 else if (USARTx == USART2)
140 {
141 /* Force reset of USART clock */
142 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
143
144 /* Release reset of USART clock */
145 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
146 }
147 else if (USARTx == USART3)
148 {
149 /* Force reset of USART clock */
150 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
151
152 /* Release reset of USART clock */
153 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
154 }
155 else if (USARTx == USART6)
156 {
157 /* Force reset of USART clock */
158 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
159
160 /* Release reset of USART clock */
161 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
162 }
163 else if (USARTx == UART4)
164 {
165 /* Force reset of UART clock */
166 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
167
168 /* Release reset of UART clock */
169 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
170 }
171 else if (USARTx == UART5)
172 {
173 /* Force reset of UART clock */
174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
175
176 /* Release reset of UART clock */
177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
178 }
179 else
180 {
181 status = ERROR;
182 }
183
184 return (status);
185 }
186
187 /**
188 * @brief Initialize USART registers according to the specified
189 * parameters in USART_InitStruct.
190 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
191 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
192 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
193 * @param USARTx USART Instance
194 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
195 * that contains the configuration information for the specified USART peripheral.
196 * @retval An ErrorStatus enumeration value:
197 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
198 * - ERROR: Problem occurred during USART Registers initialization
199 */
LL_USART_Init(USART_TypeDef * USARTx,const LL_USART_InitTypeDef * USART_InitStruct)200 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
201 {
202 ErrorStatus status = ERROR;
203 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
204 LL_RCC_ClocksTypeDef rcc_clocks;
205
206 /* Check the parameters */
207 assert_param(IS_UART_INSTANCE(USARTx));
208 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
209 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
210 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
211 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
212 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
213 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
214 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
215
216 /* USART needs to be in disabled state, in order to be able to configure some bits in
217 CRx registers */
218 if (LL_USART_IsEnabled(USARTx) == 0U)
219 {
220 /*---------------------------- USART CR1 Configuration -----------------------
221 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
222 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
223 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
224 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
225 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
226 */
227 MODIFY_REG(USARTx->CR1,
228 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
229 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
230 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
231 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
232
233 /*---------------------------- USART CR2 Configuration -----------------------
234 * Configure USARTx CR2 (Stop bits) with parameters:
235 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
236 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
237 */
238 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
239
240 /*---------------------------- USART CR3 Configuration -----------------------
241 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
242 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
243 */
244 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
245
246 /*---------------------------- USART BRR Configuration -----------------------
247 * Retrieve Clock frequency used for USART Peripheral
248 */
249 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
250 if (USARTx == USART1)
251 {
252 periphclk = rcc_clocks.PCLK2_Frequency;
253 }
254 else if (USARTx == USART2)
255 {
256 periphclk = rcc_clocks.PCLK1_Frequency;
257 }
258 else if (USARTx == USART3)
259 {
260 periphclk = rcc_clocks.PCLK1_Frequency;
261 }
262 else if (USARTx == USART6)
263 {
264 periphclk = rcc_clocks.PCLK2_Frequency;
265 }
266 else if (USARTx == UART4)
267 {
268 periphclk = rcc_clocks.PCLK1_Frequency;
269 }
270 else if (USARTx == UART5)
271 {
272 periphclk = rcc_clocks.PCLK1_Frequency;
273 }
274 else
275 {
276 /* Nothing to do, as error code is already assigned to ERROR value */
277 }
278
279 /* Configure the USART Baud Rate :
280 - valid baud rate value (different from 0) is required
281 - Peripheral clock as returned by RCC service, should be valid (different from 0).
282 */
283 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
284 && (USART_InitStruct->BaudRate != 0U))
285 {
286 status = SUCCESS;
287 LL_USART_SetBaudRate(USARTx,
288 periphclk,
289 USART_InitStruct->OverSampling,
290 USART_InitStruct->BaudRate);
291
292 /* Check BRR is greater than or equal to 16d */
293 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
294 }
295 }
296 /* Endif (=> USART not in Disabled state => return ERROR) */
297
298 return (status);
299 }
300
301 /**
302 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
303 * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
304 * whose fields will be set to default values.
305 * @retval None
306 */
307
LL_USART_StructInit(LL_USART_InitTypeDef * USART_InitStruct)308 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
309 {
310 /* Set USART_InitStruct fields to default values */
311 USART_InitStruct->BaudRate = 9600U;
312 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
313 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
314 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
315 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
316 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
317 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
318 }
319
320 /**
321 * @brief Initialize USART Clock related settings according to the
322 * specified parameters in the USART_ClockInitStruct.
323 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
324 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
325 * @param USARTx USART Instance
326 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
327 * that contains the Clock configuration information for the specified USART peripheral.
328 * @retval An ErrorStatus enumeration value:
329 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
330 * - ERROR: Problem occurred during USART Registers initialization
331 */
LL_USART_ClockInit(USART_TypeDef * USARTx,const LL_USART_ClockInitTypeDef * USART_ClockInitStruct)332 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
333 {
334 ErrorStatus status = SUCCESS;
335
336 /* Check USART Instance and Clock signal output parameters */
337 assert_param(IS_UART_INSTANCE(USARTx));
338 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
339
340 /* USART needs to be in disabled state, in order to be able to configure some bits in
341 CRx registers */
342 if (LL_USART_IsEnabled(USARTx) == 0U)
343 {
344 /*---------------------------- USART CR2 Configuration -----------------------*/
345 /* If Clock signal has to be output */
346 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
347 {
348 /* Deactivate Clock signal delivery :
349 * - Disable Clock Output: USART_CR2_CLKEN cleared
350 */
351 LL_USART_DisableSCLKOutput(USARTx);
352 }
353 else
354 {
355 /* Ensure USART instance is USART capable */
356 assert_param(IS_USART_INSTANCE(USARTx));
357
358 /* Check clock related parameters */
359 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
360 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
361 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
362
363 /*---------------------------- USART CR2 Configuration -----------------------
364 * Configure USARTx CR2 (Clock signal related bits) with parameters:
365 * - Enable Clock Output: USART_CR2_CLKEN set
366 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
367 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
368 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
369 */
370 MODIFY_REG(USARTx->CR2,
371 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
372 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
373 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
374 }
375 }
376 /* Else (USART not in Disabled state => return ERROR */
377 else
378 {
379 status = ERROR;
380 }
381
382 return (status);
383 }
384
385 /**
386 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
387 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
388 * whose fields will be set to default values.
389 * @retval None
390 */
LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef * USART_ClockInitStruct)391 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
392 {
393 /* Set LL_USART_ClockInitStruct fields with default values */
394 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
395 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
396 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
397 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
398 }
399
400 /**
401 * @}
402 */
403
404 /**
405 * @}
406 */
407
408 /**
409 * @}
410 */
411
412 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 */
413
414 /**
415 * @}
416 */
417
418 #endif /* USE_FULL_LL_DRIVER */
419
420
421
