1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f2xx_ll_spi.h"
22 #include "stm32f2xx_ll_bus.h"
23 #include "stm32f2xx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32F2xx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
72
73 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
74 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
75
76 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
77 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
78
79 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
80 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
81 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
82
83 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
84 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
85 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
86 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
87 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
88 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
89 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
90 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
91
92 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
93 || ((__VALUE__) == LL_SPI_MSB_FIRST))
94
95 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
96 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
97
98 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
99
100 /**
101 * @}
102 */
103
104 /* Private function prototypes -----------------------------------------------*/
105
106 /* Exported functions --------------------------------------------------------*/
107 /** @addtogroup SPI_LL_Exported_Functions
108 * @{
109 */
110
111 /** @addtogroup SPI_LL_EF_Init
112 * @{
113 */
114
115 /**
116 * @brief De-initialize the SPI registers to their default reset values.
117 * @param SPIx SPI Instance
118 * @retval An ErrorStatus enumeration value:
119 * - SUCCESS: SPI registers are de-initialized
120 * - ERROR: SPI registers are not de-initialized
121 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)122 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
123 {
124 ErrorStatus status = ERROR;
125
126 /* Check the parameters */
127 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
128
129 #if defined(SPI1)
130 if (SPIx == SPI1)
131 {
132 /* Force reset of SPI clock */
133 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
134
135 /* Release reset of SPI clock */
136 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
137
138 status = SUCCESS;
139 }
140 #endif /* SPI1 */
141 #if defined(SPI2)
142 if (SPIx == SPI2)
143 {
144 /* Force reset of SPI clock */
145 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
146
147 /* Release reset of SPI clock */
148 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
149
150 status = SUCCESS;
151 }
152 #endif /* SPI2 */
153 #if defined(SPI3)
154 if (SPIx == SPI3)
155 {
156 /* Force reset of SPI clock */
157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
158
159 /* Release reset of SPI clock */
160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
161
162 status = SUCCESS;
163 }
164 #endif /* SPI3 */
165
166 return status;
167 }
168
169 /**
170 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
171 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
172 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
173 * @param SPIx SPI Instance
174 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
175 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
176 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)177 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
178 {
179 ErrorStatus status = ERROR;
180
181 /* Check the SPI Instance SPIx*/
182 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
183
184 /* Check the SPI parameters from SPI_InitStruct*/
185 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
186 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
187 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
188 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
189 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
190 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
191 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
192 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
193 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
194
195 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
196 {
197 /*---------------------------- SPIx CR1 Configuration ------------------------
198 * Configure SPIx CR1 with parameters:
199 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
200 * - Master/Slave Mode: SPI_CR1_MSTR bit
201 * - DataWidth: SPI_CR1_DFF bit
202 * - ClockPolarity: SPI_CR1_CPOL bit
203 * - ClockPhase: SPI_CR1_CPHA bit
204 * - NSS management: SPI_CR1_SSM bit
205 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
206 * - BitOrder: SPI_CR1_LSBFIRST bit
207 * - CRCCalculation: SPI_CR1_CRCEN bit
208 */
209 MODIFY_REG(SPIx->CR1,
210 SPI_CR1_CLEAR_MASK,
211 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
212 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
213 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
214 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
215
216 /*---------------------------- SPIx CR2 Configuration ------------------------
217 * Configure SPIx CR2 with parameters:
218 * - NSS management: SSOE bit
219 */
220 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
221
222 /*---------------------------- SPIx CRCPR Configuration ----------------------
223 * Configure SPIx CRCPR with parameters:
224 * - CRCPoly: CRCPOLY[15:0] bits
225 */
226 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
227 {
228 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
229 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
230 }
231 status = SUCCESS;
232 }
233
234 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
235 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
236 return status;
237 }
238
239 /**
240 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
241 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
242 * whose fields will be set to default values.
243 * @retval None
244 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)245 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
246 {
247 /* Set SPI_InitStruct fields to default values */
248 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
249 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
250 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
251 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
252 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
253 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
254 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
255 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
256 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
257 SPI_InitStruct->CRCPoly = 7U;
258 }
259
260 /**
261 * @}
262 */
263
264 /**
265 * @}
266 */
267
268 /**
269 * @}
270 */
271
272 /** @addtogroup I2S_LL
273 * @{
274 */
275
276 /* Private types -------------------------------------------------------------*/
277 /* Private variables ---------------------------------------------------------*/
278 /* Private constants ---------------------------------------------------------*/
279 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
280 * @{
281 */
282 /* I2S registers Masks */
283 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
284 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
285 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
286
287 #define I2S_I2SPR_CLEAR_MASK 0x0002U
288 /**
289 * @}
290 */
291 /* Private macros ------------------------------------------------------------*/
292 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
293 * @{
294 */
295
296 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
297 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
298 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
299 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
300
301 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
302 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
303
304 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
305 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
306 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
307 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
308 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
309
310 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
311 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
312 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
313 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
314
315 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
316 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
317
318 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
319 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
320 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
321
322 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
323
324 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
325 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
326 /**
327 * @}
328 */
329
330 /* Private function prototypes -----------------------------------------------*/
331
332 /* Exported functions --------------------------------------------------------*/
333 /** @addtogroup I2S_LL_Exported_Functions
334 * @{
335 */
336
337 /** @addtogroup I2S_LL_EF_Init
338 * @{
339 */
340
341 /**
342 * @brief De-initialize the SPI/I2S registers to their default reset values.
343 * @param SPIx SPI Instance
344 * @retval An ErrorStatus enumeration value:
345 * - SUCCESS: SPI registers are de-initialized
346 * - ERROR: SPI registers are not de-initialized
347 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)348 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
349 {
350 return LL_SPI_DeInit(SPIx);
351 }
352
353 /**
354 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
355 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
356 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
357 * @param SPIx SPI Instance
358 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
359 * @retval An ErrorStatus enumeration value:
360 * - SUCCESS: SPI registers are Initialized
361 * - ERROR: SPI registers are not Initialized
362 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)363 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
364 {
365 uint32_t i2sdiv = 2U;
366 uint32_t i2sodd = 0U;
367 uint32_t packetlength = 1U;
368 uint32_t tmp;
369 uint32_t sourceclock;
370 ErrorStatus status = ERROR;
371
372 /* Check the I2S parameters */
373 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
374 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
375 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
376 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
377 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
378 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
379 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
380
381 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
382 {
383 /*---------------------------- SPIx I2SCFGR Configuration --------------------
384 * Configure SPIx I2SCFGR with parameters:
385 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
386 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
387 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
388 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
389 */
390
391 /* Write to SPIx I2SCFGR */
392 MODIFY_REG(SPIx->I2SCFGR,
393 I2S_I2SCFGR_CLEAR_MASK,
394 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
395 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
396 SPI_I2SCFGR_I2SMOD);
397
398 /*---------------------------- SPIx I2SPR Configuration ----------------------
399 * Configure SPIx I2SPR with parameters:
400 * - MCLKOutput: SPI_I2SPR_MCKOE bit
401 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
402 */
403
404 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
405 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
406 */
407 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
408 {
409 /* Check the frame length (For the Prescaler computing)
410 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
411 */
412 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
413 {
414 /* Packet length is 32 bits */
415 packetlength = 2U;
416 }
417
418 /* If an external I2S clock has to be used, the specific define should be set
419 in the project configuration or in the stm32f2xx_ll_rcc.h file */
420 /* Get the I2S source clock value */
421 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
422
423 /* Compute the Real divider depending on the MCLK output state with a floating point */
424 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
425 {
426 /* MCLK output is enabled */
427 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
428 }
429 else
430 {
431 /* MCLK output is disabled */
432 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
433 }
434
435 /* Remove the floating point */
436 tmp = tmp / 10U;
437
438 /* Check the parity of the divider */
439 i2sodd = (tmp & (uint16_t)0x0001U);
440
441 /* Compute the i2sdiv prescaler */
442 i2sdiv = ((tmp - i2sodd) / 2U);
443
444 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
445 i2sodd = (i2sodd << 8U);
446 }
447
448 /* Test if the divider is 1 or 0 or greater than 0xFF */
449 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
450 {
451 /* Set the default values */
452 i2sdiv = 2U;
453 i2sodd = 0U;
454 }
455
456 /* Write to SPIx I2SPR register the computed value */
457 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
458
459 status = SUCCESS;
460 }
461 return status;
462 }
463
464 /**
465 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
466 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
467 * whose fields will be set to default values.
468 * @retval None
469 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)470 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
471 {
472 /*--------------- Reset I2S init structure parameters values -----------------*/
473 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
474 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
475 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
476 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
477 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
478 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
479 }
480
481 /**
482 * @brief Set linear and parity prescaler.
483 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
484 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
485 * @param SPIx SPI Instance
486 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
487 * @param PrescalerParity This parameter can be one of the following values:
488 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
489 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
490 * @retval None
491 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)492 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
493 {
494 /* Check the I2S parameters */
495 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
496 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
497 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
498
499 /* Write to SPIx I2SPR */
500 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
501 }
502
503 /**
504 * @}
505 */
506
507 /**
508 * @}
509 */
510
511 /**
512 * @}
513 */
514
515 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
516
517 /**
518 * @}
519 */
520
521 #endif /* USE_FULL_LL_DRIVER */
522
523
