1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f2xx_ll_dma.h"
23 #include "stm32f2xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup DMA_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
49 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
50
51 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
52 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
53 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
54
55 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
56 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
57
58 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
59 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
60
61 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
62 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
63 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
64
65 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
66 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
67 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
68
69 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
70
71 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
72 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
73 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
74 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
75 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
76 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
77 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
78 ((__VALUE__) == LL_DMA_CHANNEL_7))
79
80 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
81 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
82 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
83 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
84
85
86 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
87 (((STREAM) == LL_DMA_STREAM_0) || \
88 ((STREAM) == LL_DMA_STREAM_1) || \
89 ((STREAM) == LL_DMA_STREAM_2) || \
90 ((STREAM) == LL_DMA_STREAM_3) || \
91 ((STREAM) == LL_DMA_STREAM_4) || \
92 ((STREAM) == LL_DMA_STREAM_5) || \
93 ((STREAM) == LL_DMA_STREAM_6) || \
94 ((STREAM) == LL_DMA_STREAM_7) || \
95 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
96 (((INSTANCE) == DMA2) && \
97 (((STREAM) == LL_DMA_STREAM_0) || \
98 ((STREAM) == LL_DMA_STREAM_1) || \
99 ((STREAM) == LL_DMA_STREAM_2) || \
100 ((STREAM) == LL_DMA_STREAM_3) || \
101 ((STREAM) == LL_DMA_STREAM_4) || \
102 ((STREAM) == LL_DMA_STREAM_5) || \
103 ((STREAM) == LL_DMA_STREAM_6) || \
104 ((STREAM) == LL_DMA_STREAM_7) || \
105 ((STREAM) == LL_DMA_STREAM_ALL))))
106
107 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
108 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
109
110 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
111 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
112 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
113 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
114
115 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
116 ((BURST) == LL_DMA_MBURST_INC4) || \
117 ((BURST) == LL_DMA_MBURST_INC8) || \
118 ((BURST) == LL_DMA_MBURST_INC16))
119
120 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
121 ((BURST) == LL_DMA_PBURST_INC4) || \
122 ((BURST) == LL_DMA_PBURST_INC8) || \
123 ((BURST) == LL_DMA_PBURST_INC16))
124
125 /**
126 * @}
127 */
128
129 /* Private function prototypes -----------------------------------------------*/
130
131 /* Exported functions --------------------------------------------------------*/
132 /** @addtogroup DMA_LL_Exported_Functions
133 * @{
134 */
135
136 /** @addtogroup DMA_LL_EF_Init
137 * @{
138 */
139
140 /**
141 * @brief De-initialize the DMA registers to their default reset values.
142 * @param DMAx DMAx Instance
143 * @param Stream This parameter can be one of the following values:
144 * @arg @ref LL_DMA_STREAM_0
145 * @arg @ref LL_DMA_STREAM_1
146 * @arg @ref LL_DMA_STREAM_2
147 * @arg @ref LL_DMA_STREAM_3
148 * @arg @ref LL_DMA_STREAM_4
149 * @arg @ref LL_DMA_STREAM_5
150 * @arg @ref LL_DMA_STREAM_6
151 * @arg @ref LL_DMA_STREAM_7
152 * @arg @ref LL_DMA_STREAM_ALL
153 * @retval An ErrorStatus enumeration value:
154 * - SUCCESS: DMA registers are de-initialized
155 * - ERROR: DMA registers are not de-initialized
156 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Stream)157 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
158 {
159 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
160 ErrorStatus status = SUCCESS;
161
162 /* Check the DMA Instance DMAx and Stream parameters*/
163 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
164
165 if (Stream == LL_DMA_STREAM_ALL)
166 {
167 if (DMAx == DMA1)
168 {
169 /* Force reset of DMA clock */
170 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
171
172 /* Release reset of DMA clock */
173 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
174 }
175 else if (DMAx == DMA2)
176 {
177 /* Force reset of DMA clock */
178 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
179
180 /* Release reset of DMA clock */
181 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
182 }
183 else
184 {
185 status = ERROR;
186 }
187 }
188 else
189 {
190 /* Disable the selected Stream */
191 LL_DMA_DisableStream(DMAx,Stream);
192
193 /* Get the DMA Stream Instance */
194 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
195
196 /* Reset DMAx_Streamy configuration register */
197 LL_DMA_WriteReg(tmp, CR, 0U);
198
199 /* Reset DMAx_Streamy remaining bytes register */
200 LL_DMA_WriteReg(tmp, NDTR, 0U);
201
202 /* Reset DMAx_Streamy peripheral address register */
203 LL_DMA_WriteReg(tmp, PAR, 0U);
204
205 /* Reset DMAx_Streamy memory address register */
206 LL_DMA_WriteReg(tmp, M0AR, 0U);
207
208 /* Reset DMAx_Streamy memory address register */
209 LL_DMA_WriteReg(tmp, M1AR, 0U);
210
211 /* Reset DMAx_Streamy FIFO control register */
212 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
213
214 /* Reset Channel register field for DMAx Stream*/
215 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
216
217 if(Stream == LL_DMA_STREAM_0)
218 {
219 /* Reset the Stream0 pending flags */
220 DMAx->LIFCR = 0x0000003F ;
221 }
222 else if(Stream == LL_DMA_STREAM_1)
223 {
224 /* Reset the Stream1 pending flags */
225 DMAx->LIFCR = 0x00000F40 ;
226 }
227 else if(Stream == LL_DMA_STREAM_2)
228 {
229 /* Reset the Stream2 pending flags */
230 DMAx->LIFCR = 0x003F0000 ;
231 }
232 else if(Stream == LL_DMA_STREAM_3)
233 {
234 /* Reset the Stream3 pending flags */
235 DMAx->LIFCR = 0x0F400000 ;
236 }
237 else if(Stream == LL_DMA_STREAM_4)
238 {
239 /* Reset the Stream4 pending flags */
240 DMAx->HIFCR = 0x0000003F ;
241 }
242 else if(Stream == LL_DMA_STREAM_5)
243 {
244 /* Reset the Stream5 pending flags */
245 DMAx->HIFCR = 0x00000F40 ;
246 }
247 else if(Stream == LL_DMA_STREAM_6)
248 {
249 /* Reset the Stream6 pending flags */
250 DMAx->HIFCR = 0x003F0000 ;
251 }
252 else if(Stream == LL_DMA_STREAM_7)
253 {
254 /* Reset the Stream7 pending flags */
255 DMAx->HIFCR = 0x0F400000 ;
256 }
257 else
258 {
259 status = ERROR;
260 }
261 }
262
263 return status;
264 }
265
266 /**
267 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
268 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
269 * @arg @ref __LL_DMA_GET_INSTANCE
270 * @arg @ref __LL_DMA_GET_STREAM
271 * @param DMAx DMAx Instance
272 * @param Stream This parameter can be one of the following values:
273 * @arg @ref LL_DMA_STREAM_0
274 * @arg @ref LL_DMA_STREAM_1
275 * @arg @ref LL_DMA_STREAM_2
276 * @arg @ref LL_DMA_STREAM_3
277 * @arg @ref LL_DMA_STREAM_4
278 * @arg @ref LL_DMA_STREAM_5
279 * @arg @ref LL_DMA_STREAM_6
280 * @arg @ref LL_DMA_STREAM_7
281 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
282 * @retval An ErrorStatus enumeration value:
283 * - SUCCESS: DMA registers are initialized
284 * - ERROR: Not applicable
285 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Stream,LL_DMA_InitTypeDef * DMA_InitStruct)286 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
287 {
288 /* Check the DMA Instance DMAx and Stream parameters*/
289 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
290
291 /* Check the DMA parameters from DMA_InitStruct */
292 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
293 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
294 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
295 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
296 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
297 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
298 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
299 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
300 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
301 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
302 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
303 when FIFO mode is enabled */
304 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
305 {
306 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
307 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
308 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
309 }
310
311 /*---------------------------- DMAx SxCR Configuration ------------------------
312 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
313 * peripheral and memory increment mode,
314 * data size alignment and priority level with parameters :
315 * - Direction: DMA_SxCR_DIR[1:0] bits
316 * - Mode: DMA_SxCR_CIRC bit
317 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
318 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
319 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
320 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
321 * - Priority: DMA_SxCR_PL[1:0] bits
322 */
323 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
324 DMA_InitStruct->Mode | \
325 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
326 DMA_InitStruct->MemoryOrM2MDstIncMode | \
327 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
328 DMA_InitStruct->MemoryOrM2MDstDataSize | \
329 DMA_InitStruct->Priority
330 );
331
332 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
333 {
334 /*---------------------------- DMAx SxFCR Configuration ------------------------
335 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
336 * - FIFOMode: DMA_SxFCR_DMDIS bit
337 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
338 */
339 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
340
341 /*---------------------------- DMAx SxCR Configuration --------------------------
342 * Configure DMAx_Streamy: memory burst transfer with parameters :
343 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
344 */
345 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
346
347 /*---------------------------- DMAx SxCR Configuration --------------------------
348 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
349 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
350 */
351 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
352 }
353
354 /*-------------------------- DMAx SxM0AR Configuration --------------------------
355 * Configure the memory or destination base address with parameter :
356 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
357 */
358 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
359
360 /*-------------------------- DMAx SxPAR Configuration ---------------------------
361 * Configure the peripheral or source base address with parameter :
362 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
363 */
364 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
365
366 /*--------------------------- DMAx SxNDTR Configuration -------------------------
367 * Configure the peripheral base address with parameter :
368 * - NbData: DMA_SxNDT[15:0] bits
369 */
370 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
371
372 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
373 * Configure the peripheral base address with parameter :
374 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
375 */
376 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
377
378 return SUCCESS;
379 }
380
381 /**
382 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
383 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
384 * @retval None
385 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)386 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
387 {
388 /* Set DMA_InitStruct fields to default values */
389 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
390 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
391 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
392 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
393 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
394 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
395 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
396 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
397 DMA_InitStruct->NbData = 0x00000000U;
398 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
399 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
400 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
401 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
402 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
403 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
404 }
405
406 /**
407 * @}
408 */
409
410 /**
411 * @}
412 */
413
414 /**
415 * @}
416 */
417
418 #endif /* DMA1 || DMA2 */
419
420 /**
421 * @}
422 */
423
424 #endif /* USE_FULL_LL_DRIVER */
425
426
