1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f2xx_ll_adc.h"
23 #include "stm32f2xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F2xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /** @addtogroup ADC_LL_Private_Macros
47 * @{
48 */
49
50 /* Check of parameters for configuration of ADC hierarchical scope: */
51 /* common to several ADC instances. */
52 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
53 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
54 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
55 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
56 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
57 )
58
59 /* Check of parameters for configuration of ADC hierarchical scope: */
60 /* ADC instance. */
61 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
62 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
63 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
64 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
65 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
66 )
67
68 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
69 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
70 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
71 )
72
73 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
74 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
75 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
76 )
77
78 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
79 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
80 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
81 )
82
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* ADC group regular */
85 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
86 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
87 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
88 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
89 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
90 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
91 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
92 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
101 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
102 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
103 )
104 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
105 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
106 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
107 )
108
109 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
110 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
111 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
112 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
113 )
114
115 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
116 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
117 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
118 )
119
120 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
121 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
135 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
136 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
137 )
138
139 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
140 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
147 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
148 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
149 )
150
151 /* Check of parameters for configuration of ADC hierarchical scope: */
152 /* ADC group injected */
153 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
154 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
167 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
168 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
169 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
170 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
171 )
172
173 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
174 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
175 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
176 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
177 )
178
179 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
180 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
181 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
182 )
183
184 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
185 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
186 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
187 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
188 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
189 )
190
191 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
192 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
193 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
194 )
195
196 #if defined(ADC_MULTIMODE_SUPPORT)
197 /* Check of parameters for configuration of ADC hierarchical scope: */
198 /* multimode. */
199 #if defined(ADC3)
200 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
201 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
203 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
204 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
205 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
206 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
207 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
208 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
209 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
210 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
211 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
212 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
213 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
214 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
215 )
216 #else
217 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
218 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
226 )
227 #endif
228
229 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
230 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
231 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
232 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
233 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
234 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
235 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
236 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
237 )
238
239 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
240 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
250 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
251 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
252 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
253 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
254 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
255 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
256 )
257
258 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
259 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
260 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
261 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
262 )
263
264 #endif /* ADC_MULTIMODE_SUPPORT */
265
266 #ifndef UNUSED
267 #define UNUSED(x) ((void)(x))
268 #endif
269
270 /**
271 * @}
272 */
273
274
275 /* Private function prototypes -----------------------------------------------*/
276
277 /* Exported functions --------------------------------------------------------*/
278 /** @addtogroup ADC_LL_Exported_Functions
279 * @{
280 */
281
282 /** @addtogroup ADC_LL_EF_Init
283 * @{
284 */
285
286 /**
287 * @brief De-initialize registers of all ADC instances belonging to
288 * the same ADC common instance to their default reset values.
289 * @param ADCxy_COMMON ADC common instance
290 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
291 * @retval An ErrorStatus enumeration value:
292 * - SUCCESS: ADC common registers are de-initialized
293 * - ERROR: not applicable
294 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)295 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
296 {
297 /* Prevent unused argument(s) compilation warning */
298 UNUSED(ADCxy_COMMON);
299
300 /* Check the parameters */
301 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
302
303 /* Force reset of ADC clock (core clock) */
304 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
305
306 /* Release reset of ADC clock (core clock) */
307 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
308
309 return SUCCESS;
310 }
311
312 /**
313 * @brief Initialize some features of ADC common parameters
314 * (all ADC instances belonging to the same ADC common instance)
315 * and multimode (for devices with several ADC instances available).
316 * @note The setting of ADC common parameters is conditioned to
317 * ADC instances state:
318 * All ADC instances belonging to the same ADC common instance
319 * must be disabled.
320 * @param ADCxy_COMMON ADC common instance
321 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
322 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
323 * @retval An ErrorStatus enumeration value:
324 * - SUCCESS: ADC common registers are initialized
325 * - ERROR: ADC common registers are not initialized
326 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)327 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
328 {
329 ErrorStatus status = SUCCESS;
330
331 /* Check the parameters */
332 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
333 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
334
335 #if defined(ADC_MULTIMODE_SUPPORT)
336 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
337 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
338 {
339 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
340 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
341 }
342 #endif /* ADC_MULTIMODE_SUPPORT */
343
344 /* Note: Hardware constraint (refer to description of functions */
345 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
346 /* On this STM32 series, setting of these features is conditioned to */
347 /* ADC state: */
348 /* All ADC instances of the ADC common group must be disabled. */
349 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
350 {
351 /* Configuration of ADC hierarchical scope: */
352 /* - common to several ADC */
353 /* (all ADC instances belonging to the same ADC common instance) */
354 /* - Set ADC clock (conversion clock) */
355 /* - multimode (if several ADC instances available on the */
356 /* selected device) */
357 /* - Set ADC multimode configuration */
358 /* - Set ADC multimode DMA transfer */
359 /* - Set ADC multimode: delay between 2 sampling phases */
360 #if defined(ADC_MULTIMODE_SUPPORT)
361 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
362 {
363 MODIFY_REG(ADCxy_COMMON->CCR,
364 ADC_CCR_ADCPRE
365 | ADC_CCR_MULTI
366 | ADC_CCR_DMA
367 | ADC_CCR_DDS
368 | ADC_CCR_DELAY
369 ,
370 ADC_CommonInitStruct->CommonClock
371 | ADC_CommonInitStruct->Multimode
372 | ADC_CommonInitStruct->MultiDMATransfer
373 | ADC_CommonInitStruct->MultiTwoSamplingDelay
374 );
375 }
376 else
377 {
378 MODIFY_REG(ADCxy_COMMON->CCR,
379 ADC_CCR_ADCPRE
380 | ADC_CCR_MULTI
381 | ADC_CCR_DMA
382 | ADC_CCR_DDS
383 | ADC_CCR_DELAY
384 ,
385 ADC_CommonInitStruct->CommonClock
386 | LL_ADC_MULTI_INDEPENDENT
387 );
388 }
389 #else
390 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
391 #endif
392 }
393 else
394 {
395 /* Initialization error: One or several ADC instances belonging to */
396 /* the same ADC common instance are not disabled. */
397 status = ERROR;
398 }
399
400 return status;
401 }
402
403 /**
404 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
405 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
406 * whose fields will be set to default values.
407 * @retval None
408 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)409 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
410 {
411 /* Set ADC_CommonInitStruct fields to default values */
412 /* Set fields of ADC common */
413 /* (all ADC instances belonging to the same ADC common instance) */
414 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
415
416 #if defined(ADC_MULTIMODE_SUPPORT)
417 /* Set fields of ADC multimode */
418 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
419 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
420 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
421 #endif /* ADC_MULTIMODE_SUPPORT */
422 }
423
424 /**
425 * @brief De-initialize registers of the selected ADC instance
426 * to their default reset values.
427 * @note To reset all ADC instances quickly (perform a hard reset),
428 * use function @ref LL_ADC_CommonDeInit().
429 * @param ADCx ADC instance
430 * @retval An ErrorStatus enumeration value:
431 * - SUCCESS: ADC registers are de-initialized
432 * - ERROR: ADC registers are not de-initialized
433 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)434 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
435 {
436 ErrorStatus status = SUCCESS;
437
438 /* Check the parameters */
439 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
440
441 /* Disable ADC instance if not already disabled. */
442 if(LL_ADC_IsEnabled(ADCx) == 1U)
443 {
444 /* Set ADC group regular trigger source to SW start to ensure to not */
445 /* have an external trigger event occurring during the conversion stop */
446 /* ADC disable process. */
447 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
448
449 /* Set ADC group injected trigger source to SW start to ensure to not */
450 /* have an external trigger event occurring during the conversion stop */
451 /* ADC disable process. */
452 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
453
454 /* Disable the ADC instance */
455 LL_ADC_Disable(ADCx);
456 }
457
458 /* Check whether ADC state is compliant with expected state */
459 /* (hardware requirements of bits state to reset registers below) */
460 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
461 {
462 /* ========== Reset ADC registers ========== */
463 /* Reset register SR */
464 CLEAR_BIT(ADCx->SR,
465 ( LL_ADC_FLAG_STRT
466 | LL_ADC_FLAG_JSTRT
467 | LL_ADC_FLAG_EOCS
468 | LL_ADC_FLAG_OVR
469 | LL_ADC_FLAG_JEOS
470 | LL_ADC_FLAG_AWD1 )
471 );
472
473 /* Reset register CR1 */
474 CLEAR_BIT(ADCx->CR1,
475 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
476 | ADC_CR1_JAWDEN
477 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
478 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
479 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
480 | ADC_CR1_AWDCH )
481 );
482
483 /* Reset register CR2 */
484 CLEAR_BIT(ADCx->CR2,
485 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
486 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
487 | ADC_CR2_ALIGN | ADC_CR2_EOCS
488 | ADC_CR2_DDS | ADC_CR2_DMA
489 | ADC_CR2_CONT | ADC_CR2_ADON )
490 );
491
492 /* Reset register SMPR1 */
493 CLEAR_BIT(ADCx->SMPR1,
494 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
495 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
496 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
497 );
498
499 /* Reset register SMPR2 */
500 CLEAR_BIT(ADCx->SMPR2,
501 ( ADC_SMPR2_SMP9
502 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
503 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
504 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
505 );
506
507 /* Reset register JOFR1 */
508 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
509 /* Reset register JOFR2 */
510 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
511 /* Reset register JOFR3 */
512 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
513 /* Reset register JOFR4 */
514 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
515
516 /* Reset register HTR */
517 SET_BIT(ADCx->HTR, ADC_HTR_HT);
518 /* Reset register LTR */
519 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
520
521 /* Reset register SQR1 */
522 CLEAR_BIT(ADCx->SQR1,
523 ( ADC_SQR1_L
524 | ADC_SQR1_SQ16
525 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
526 );
527
528 /* Reset register SQR2 */
529 CLEAR_BIT(ADCx->SQR2,
530 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
531 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
532 );
533
534 /* Reset register SQR3 */
535 CLEAR_BIT(ADCx->SQR3,
536 ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4
537 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1)
538 );
539
540 /* Reset register JSQR */
541 CLEAR_BIT(ADCx->JSQR,
542 ( ADC_JSQR_JL
543 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
544 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
545 );
546
547 /* Reset register DR */
548 /* bits in access mode read only, no direct reset applicable */
549
550 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
551 /* bits in access mode read only, no direct reset applicable */
552
553 /* Reset register CCR */
554 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
555 }
556
557 return status;
558 }
559
560 /**
561 * @brief Initialize some features of ADC instance.
562 * @note These parameters have an impact on ADC scope: ADC instance.
563 * Affects both group regular and group injected (availability
564 * of ADC group injected depends on STM32 families).
565 * Refer to corresponding unitary functions into
566 * @ref ADC_LL_EF_Configuration_ADC_Instance .
567 * @note The setting of these parameters by function @ref LL_ADC_Init()
568 * is conditioned to ADC state:
569 * ADC instance must be disabled.
570 * This condition is applied to all ADC features, for efficiency
571 * and compatibility over all STM32 families. However, the different
572 * features can be set under different ADC state conditions
573 * (setting possible with ADC enabled without conversion on going,
574 * ADC enabled with conversion on going, ...)
575 * Each feature can be updated afterwards with a unitary function
576 * and potentially with ADC in a different state than disabled,
577 * refer to description of each function for setting
578 * conditioned to ADC state.
579 * @note After using this function, some other features must be configured
580 * using LL unitary functions.
581 * The minimum configuration remaining to be done is:
582 * - Set ADC group regular or group injected sequencer:
583 * map channel on the selected sequencer rank.
584 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
585 * - Set ADC channel sampling time
586 * Refer to function LL_ADC_SetChannelSamplingTime();
587 * @param ADCx ADC instance
588 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
589 * @retval An ErrorStatus enumeration value:
590 * - SUCCESS: ADC registers are initialized
591 * - ERROR: ADC registers are not initialized
592 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)593 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
594 {
595 ErrorStatus status = SUCCESS;
596
597 /* Check the parameters */
598 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
599
600 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
601 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
602 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
603
604 /* Note: Hardware constraint (refer to description of this function): */
605 /* ADC instance must be disabled. */
606 if(LL_ADC_IsEnabled(ADCx) == 0U)
607 {
608 /* Configuration of ADC hierarchical scope: */
609 /* - ADC instance */
610 /* - Set ADC data resolution */
611 /* - Set ADC conversion data alignment */
612 MODIFY_REG(ADCx->CR1,
613 ADC_CR1_RES
614 | ADC_CR1_SCAN
615 ,
616 ADC_InitStruct->Resolution
617 | ADC_InitStruct->SequencersScanMode
618 );
619
620 MODIFY_REG(ADCx->CR2,
621 ADC_CR2_ALIGN
622 ,
623 ADC_InitStruct->DataAlignment
624 );
625
626 }
627 else
628 {
629 /* Initialization error: ADC instance is not disabled. */
630 status = ERROR;
631 }
632 return status;
633 }
634
635 /**
636 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
637 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
638 * whose fields will be set to default values.
639 * @retval None
640 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)641 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
642 {
643 /* Set ADC_InitStruct fields to default values */
644 /* Set fields of ADC instance */
645 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
646 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
647
648 /* Enable scan mode to have a generic behavior with ADC of other */
649 /* STM32 families, without this setting available: */
650 /* ADC group regular sequencer and ADC group injected sequencer depend */
651 /* only of their own configuration. */
652 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
653
654 }
655
656 /**
657 * @brief Initialize some features of ADC group regular.
658 * @note These parameters have an impact on ADC scope: ADC group regular.
659 * Refer to corresponding unitary functions into
660 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
661 * (functions with prefix "REG").
662 * @note The setting of these parameters by function @ref LL_ADC_Init()
663 * is conditioned to ADC state:
664 * ADC instance must be disabled.
665 * This condition is applied to all ADC features, for efficiency
666 * and compatibility over all STM32 families. However, the different
667 * features can be set under different ADC state conditions
668 * (setting possible with ADC enabled without conversion on going,
669 * ADC enabled with conversion on going, ...)
670 * Each feature can be updated afterwards with a unitary function
671 * and potentially with ADC in a different state than disabled,
672 * refer to description of each function for setting
673 * conditioned to ADC state.
674 * @note After using this function, other features must be configured
675 * using LL unitary functions.
676 * The minimum configuration remaining to be done is:
677 * - Set ADC group regular or group injected sequencer:
678 * map channel on the selected sequencer rank.
679 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
680 * - Set ADC channel sampling time
681 * Refer to function LL_ADC_SetChannelSamplingTime();
682 * @param ADCx ADC instance
683 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
684 * @retval An ErrorStatus enumeration value:
685 * - SUCCESS: ADC registers are initialized
686 * - ERROR: ADC registers are not initialized
687 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)688 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
689 {
690 ErrorStatus status = SUCCESS;
691
692 /* Check the parameters */
693 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
694 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
695 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
696 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
697 {
698 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
699 }
700 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
701 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
702
703 /* ADC group regular continuous mode and discontinuous mode */
704 /* can not be enabled simultenaeously */
705 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
706 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
707
708 /* Note: Hardware constraint (refer to description of this function): */
709 /* ADC instance must be disabled. */
710 if(LL_ADC_IsEnabled(ADCx) == 0U)
711 {
712 /* Configuration of ADC hierarchical scope: */
713 /* - ADC group regular */
714 /* - Set ADC group regular trigger source */
715 /* - Set ADC group regular sequencer length */
716 /* - Set ADC group regular sequencer discontinuous mode */
717 /* - Set ADC group regular continuous mode */
718 /* - Set ADC group regular conversion data transfer: no transfer or */
719 /* transfer by DMA, and DMA requests mode */
720 /* Note: On this STM32 series, ADC trigger edge is set when starting */
721 /* ADC conversion. */
722 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
723 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
724 {
725 MODIFY_REG(ADCx->CR1,
726 ADC_CR1_DISCEN
727 | ADC_CR1_DISCNUM
728 ,
729 ADC_REG_InitStruct->SequencerLength
730 | ADC_REG_InitStruct->SequencerDiscont
731 );
732 }
733 else
734 {
735 MODIFY_REG(ADCx->CR1,
736 ADC_CR1_DISCEN
737 | ADC_CR1_DISCNUM
738 ,
739 ADC_REG_InitStruct->SequencerLength
740 | LL_ADC_REG_SEQ_DISCONT_DISABLE
741 );
742 }
743
744 MODIFY_REG(ADCx->CR2,
745 ADC_CR2_EXTSEL
746 | ADC_CR2_EXTEN
747 | ADC_CR2_CONT
748 | ADC_CR2_DMA
749 | ADC_CR2_DDS
750 ,
751 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
752 | ADC_REG_InitStruct->ContinuousMode
753 | ADC_REG_InitStruct->DMATransfer
754 );
755
756 /* Set ADC group regular sequencer length and scan direction */
757 /* Note: Hardware constraint (refer to description of this function): */
758 /* Note: If ADC instance feature scan mode is disabled */
759 /* (refer to ADC instance initialization structure */
760 /* parameter @ref SequencersScanMode */
761 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
762 /* this parameter is discarded. */
763 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
764 }
765 else
766 {
767 /* Initialization error: ADC instance is not disabled. */
768 status = ERROR;
769 }
770 return status;
771 }
772
773 /**
774 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
775 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
776 * whose fields will be set to default values.
777 * @retval None
778 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)779 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
780 {
781 /* Set ADC_REG_InitStruct fields to default values */
782 /* Set fields of ADC group regular */
783 /* Note: On this STM32 series, ADC trigger edge is set when starting */
784 /* ADC conversion. */
785 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
786 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
787 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
788 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
789 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
790 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
791 }
792
793 /**
794 * @brief Initialize some features of ADC group injected.
795 * @note These parameters have an impact on ADC scope: ADC group injected.
796 * Refer to corresponding unitary functions into
797 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
798 * (functions with prefix "INJ").
799 * @note The setting of these parameters by function @ref LL_ADC_Init()
800 * is conditioned to ADC state:
801 * ADC instance must be disabled.
802 * This condition is applied to all ADC features, for efficiency
803 * and compatibility over all STM32 families. However, the different
804 * features can be set under different ADC state conditions
805 * (setting possible with ADC enabled without conversion on going,
806 * ADC enabled with conversion on going, ...)
807 * Each feature can be updated afterwards with a unitary function
808 * and potentially with ADC in a different state than disabled,
809 * refer to description of each function for setting
810 * conditioned to ADC state.
811 * @note After using this function, other features must be configured
812 * using LL unitary functions.
813 * The minimum configuration remaining to be done is:
814 * - Set ADC group injected sequencer:
815 * map channel on the selected sequencer rank.
816 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
817 * - Set ADC channel sampling time
818 * Refer to function LL_ADC_SetChannelSamplingTime();
819 * @param ADCx ADC instance
820 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
821 * @retval An ErrorStatus enumeration value:
822 * - SUCCESS: ADC registers are initialized
823 * - ERROR: ADC registers are not initialized
824 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)825 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
826 {
827 ErrorStatus status = SUCCESS;
828
829 /* Check the parameters */
830 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
831 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
832 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
833 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
834 {
835 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
836 }
837 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
838
839 /* Note: Hardware constraint (refer to description of this function): */
840 /* ADC instance must be disabled. */
841 if(LL_ADC_IsEnabled(ADCx) == 0U)
842 {
843 /* Configuration of ADC hierarchical scope: */
844 /* - ADC group injected */
845 /* - Set ADC group injected trigger source */
846 /* - Set ADC group injected sequencer length */
847 /* - Set ADC group injected sequencer discontinuous mode */
848 /* - Set ADC group injected conversion trigger: independent or */
849 /* from ADC group regular */
850 /* Note: On this STM32 series, ADC trigger edge is set when starting */
851 /* ADC conversion. */
852 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
853 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
854 {
855 MODIFY_REG(ADCx->CR1,
856 ADC_CR1_JDISCEN
857 | ADC_CR1_JAUTO
858 ,
859 ADC_INJ_InitStruct->SequencerDiscont
860 | ADC_INJ_InitStruct->TrigAuto
861 );
862 }
863 else
864 {
865 MODIFY_REG(ADCx->CR1,
866 ADC_CR1_JDISCEN
867 | ADC_CR1_JAUTO
868 ,
869 LL_ADC_REG_SEQ_DISCONT_DISABLE
870 | ADC_INJ_InitStruct->TrigAuto
871 );
872 }
873
874 MODIFY_REG(ADCx->CR2,
875 ADC_CR2_JEXTSEL
876 | ADC_CR2_JEXTEN
877 ,
878 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
879 );
880
881 /* Note: Hardware constraint (refer to description of this function): */
882 /* Note: If ADC instance feature scan mode is disabled */
883 /* (refer to ADC instance initialization structure */
884 /* parameter @ref SequencersScanMode */
885 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
886 /* this parameter is discarded. */
887 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
888 }
889 else
890 {
891 /* Initialization error: ADC instance is not disabled. */
892 status = ERROR;
893 }
894 return status;
895 }
896
897 /**
898 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
899 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
900 * whose fields will be set to default values.
901 * @retval None
902 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)903 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
904 {
905 /* Set ADC_INJ_InitStruct fields to default values */
906 /* Set fields of ADC group injected */
907 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
908 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
909 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
910 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
911 }
912
913 /**
914 * @}
915 */
916
917 /**
918 * @}
919 */
920
921 /**
922 * @}
923 */
924
925 #endif /* ADC1 || ADC2 || ADC3 */
926
927 /**
928 * @}
929 */
930
931 #endif /* USE_FULL_LL_DRIVER */
932
933
