1 /**
2 ******************************************************************************
3 * @file stm32f2xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156
157 [..]
158 By default, after the Init and when the state is HAL_TIM_STATE_RESET
159 all interrupt callbacks are set to the corresponding weak functions:
160 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
161
162 [..]
163 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
164 functionalities in the Init / DeInit only when these callbacks are null
165 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
166 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
167
168 [..]
169 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
170 Exception done MspInit / MspDeInit that can be registered / unregistered
171 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
172 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
173 In that case first register the MspInit/MspDeInit user callbacks
174 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
175
176 [..]
177 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
178 not defined, the callback registration feature is not available and all callbacks
179 are set to the corresponding weak functions.
180
181 @endverbatim
182 ******************************************************************************
183 */
184
185 /* Includes ------------------------------------------------------------------*/
186 #include "stm32f2xx_hal.h"
187
188 /** @addtogroup STM32F2xx_HAL_Driver
189 * @{
190 */
191
192 /** @defgroup TIM TIM
193 * @brief TIM HAL module driver
194 * @{
195 */
196
197 #ifdef HAL_TIM_MODULE_ENABLED
198
199 /* Private typedef -----------------------------------------------------------*/
200 /* Private define ------------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
202 /* Private variables ---------------------------------------------------------*/
203 /* Private function prototypes -----------------------------------------------*/
204 /** @addtogroup TIM_Private_Functions
205 * @{
206 */
207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
211 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
212 uint32_t TIM_ICFilter);
213 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
219 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
220 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
221 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
224 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
225 const TIM_SlaveConfigTypeDef *sSlaveConfig);
226 /**
227 * @}
228 */
229 /* Exported functions --------------------------------------------------------*/
230
231 /** @defgroup TIM_Exported_Functions TIM Exported Functions
232 * @{
233 */
234
235 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
236 * @brief Time Base functions
237 *
238 @verbatim
239 ==============================================================================
240 ##### Time Base functions #####
241 ==============================================================================
242 [..]
243 This section provides functions allowing to:
244 (+) Initialize and configure the TIM base.
245 (+) De-initialize the TIM base.
246 (+) Start the Time Base.
247 (+) Stop the Time Base.
248 (+) Start the Time Base and enable interrupt.
249 (+) Stop the Time Base and disable interrupt.
250 (+) Start the Time Base and enable DMA transfer.
251 (+) Stop the Time Base and disable DMA transfer.
252
253 @endverbatim
254 * @{
255 */
256 /**
257 * @brief Initializes the TIM Time base Unit according to the specified
258 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
259 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
260 * requires a timer reset to avoid unexpected direction
261 * due to DIR bit readonly in center aligned mode.
262 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
263 * @param htim TIM Base handle
264 * @retval HAL status
265 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)266 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
267 {
268 /* Check the TIM handle allocation */
269 if (htim == NULL)
270 {
271 return HAL_ERROR;
272 }
273
274 /* Check the parameters */
275 assert_param(IS_TIM_INSTANCE(htim->Instance));
276 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
277 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
278 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
279 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
280
281 if (htim->State == HAL_TIM_STATE_RESET)
282 {
283 /* Allocate lock resource and initialize it */
284 htim->Lock = HAL_UNLOCKED;
285
286 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
287 /* Reset interrupt callbacks to legacy weak callbacks */
288 TIM_ResetCallback(htim);
289
290 if (htim->Base_MspInitCallback == NULL)
291 {
292 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
293 }
294 /* Init the low level hardware : GPIO, CLOCK, NVIC */
295 htim->Base_MspInitCallback(htim);
296 #else
297 /* Init the low level hardware : GPIO, CLOCK, NVIC */
298 HAL_TIM_Base_MspInit(htim);
299 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
300 }
301
302 /* Set the TIM state */
303 htim->State = HAL_TIM_STATE_BUSY;
304
305 /* Set the Time Base configuration */
306 TIM_Base_SetConfig(htim->Instance, &htim->Init);
307
308 /* Initialize the DMA burst operation state */
309 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
310
311 /* Initialize the TIM channels state */
312 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
313 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
314
315 /* Initialize the TIM state*/
316 htim->State = HAL_TIM_STATE_READY;
317
318 return HAL_OK;
319 }
320
321 /**
322 * @brief DeInitializes the TIM Base peripheral
323 * @param htim TIM Base handle
324 * @retval HAL status
325 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)326 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
327 {
328 /* Check the parameters */
329 assert_param(IS_TIM_INSTANCE(htim->Instance));
330
331 htim->State = HAL_TIM_STATE_BUSY;
332
333 /* Disable the TIM Peripheral Clock */
334 __HAL_TIM_DISABLE(htim);
335
336 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
337 if (htim->Base_MspDeInitCallback == NULL)
338 {
339 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
340 }
341 /* DeInit the low level hardware */
342 htim->Base_MspDeInitCallback(htim);
343 #else
344 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
345 HAL_TIM_Base_MspDeInit(htim);
346 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
347
348 /* Change the DMA burst operation state */
349 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
350
351 /* Change the TIM channels state */
352 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
353 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
354
355 /* Change TIM state */
356 htim->State = HAL_TIM_STATE_RESET;
357
358 /* Release Lock */
359 __HAL_UNLOCK(htim);
360
361 return HAL_OK;
362 }
363
364 /**
365 * @brief Initializes the TIM Base MSP.
366 * @param htim TIM Base handle
367 * @retval None
368 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)369 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
370 {
371 /* Prevent unused argument(s) compilation warning */
372 UNUSED(htim);
373
374 /* NOTE : This function should not be modified, when the callback is needed,
375 the HAL_TIM_Base_MspInit could be implemented in the user file
376 */
377 }
378
379 /**
380 * @brief DeInitializes TIM Base MSP.
381 * @param htim TIM Base handle
382 * @retval None
383 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
385 {
386 /* Prevent unused argument(s) compilation warning */
387 UNUSED(htim);
388
389 /* NOTE : This function should not be modified, when the callback is needed,
390 the HAL_TIM_Base_MspDeInit could be implemented in the user file
391 */
392 }
393
394
395 /**
396 * @brief Starts the TIM Base generation.
397 * @param htim TIM Base handle
398 * @retval HAL status
399 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)400 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
401 {
402 uint32_t tmpsmcr;
403
404 /* Check the parameters */
405 assert_param(IS_TIM_INSTANCE(htim->Instance));
406
407 /* Check the TIM state */
408 if (htim->State != HAL_TIM_STATE_READY)
409 {
410 return HAL_ERROR;
411 }
412
413 /* Set the TIM state */
414 htim->State = HAL_TIM_STATE_BUSY;
415
416 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
417 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
418 {
419 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
420 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
421 {
422 __HAL_TIM_ENABLE(htim);
423 }
424 }
425 else
426 {
427 __HAL_TIM_ENABLE(htim);
428 }
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Stops the TIM Base generation.
436 * @param htim TIM Base handle
437 * @retval HAL status
438 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)439 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
440 {
441 /* Check the parameters */
442 assert_param(IS_TIM_INSTANCE(htim->Instance));
443
444 /* Disable the Peripheral */
445 __HAL_TIM_DISABLE(htim);
446
447 /* Set the TIM state */
448 htim->State = HAL_TIM_STATE_READY;
449
450 /* Return function status */
451 return HAL_OK;
452 }
453
454 /**
455 * @brief Starts the TIM Base generation in interrupt mode.
456 * @param htim TIM Base handle
457 * @retval HAL status
458 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)459 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
460 {
461 uint32_t tmpsmcr;
462
463 /* Check the parameters */
464 assert_param(IS_TIM_INSTANCE(htim->Instance));
465
466 /* Check the TIM state */
467 if (htim->State != HAL_TIM_STATE_READY)
468 {
469 return HAL_ERROR;
470 }
471
472 /* Set the TIM state */
473 htim->State = HAL_TIM_STATE_BUSY;
474
475 /* Enable the TIM Update interrupt */
476 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
477
478 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
479 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
480 {
481 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
482 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
483 {
484 __HAL_TIM_ENABLE(htim);
485 }
486 }
487 else
488 {
489 __HAL_TIM_ENABLE(htim);
490 }
491
492 /* Return function status */
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Stops the TIM Base generation in interrupt mode.
498 * @param htim TIM Base handle
499 * @retval HAL status
500 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)501 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
502 {
503 /* Check the parameters */
504 assert_param(IS_TIM_INSTANCE(htim->Instance));
505
506 /* Disable the TIM Update interrupt */
507 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
508
509 /* Disable the Peripheral */
510 __HAL_TIM_DISABLE(htim);
511
512 /* Set the TIM state */
513 htim->State = HAL_TIM_STATE_READY;
514
515 /* Return function status */
516 return HAL_OK;
517 }
518
519 /**
520 * @brief Starts the TIM Base generation in DMA mode.
521 * @param htim TIM Base handle
522 * @param pData The source Buffer address.
523 * @param Length The length of data to be transferred from memory to peripheral.
524 * @retval HAL status
525 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)526 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
527 {
528 uint32_t tmpsmcr;
529
530 /* Check the parameters */
531 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
532
533 /* Set the TIM state */
534 if (htim->State == HAL_TIM_STATE_BUSY)
535 {
536 return HAL_BUSY;
537 }
538 else if (htim->State == HAL_TIM_STATE_READY)
539 {
540 if ((pData == NULL) || (Length == 0U))
541 {
542 return HAL_ERROR;
543 }
544 else
545 {
546 htim->State = HAL_TIM_STATE_BUSY;
547 }
548 }
549 else
550 {
551 return HAL_ERROR;
552 }
553
554 /* Set the DMA Period elapsed callbacks */
555 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
556 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
557
558 /* Set the DMA error callback */
559 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
560
561 /* Enable the DMA stream */
562 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
563 Length) != HAL_OK)
564 {
565 /* Return error status */
566 return HAL_ERROR;
567 }
568
569 /* Enable the TIM Update DMA request */
570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
571
572 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
573 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
574 {
575 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
576 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
577 {
578 __HAL_TIM_ENABLE(htim);
579 }
580 }
581 else
582 {
583 __HAL_TIM_ENABLE(htim);
584 }
585
586 /* Return function status */
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Stops the TIM Base generation in DMA mode.
592 * @param htim TIM Base handle
593 * @retval HAL status
594 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)595 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
596 {
597 /* Check the parameters */
598 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
599
600 /* Disable the TIM Update DMA request */
601 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
602
603 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
604
605 /* Disable the Peripheral */
606 __HAL_TIM_DISABLE(htim);
607
608 /* Set the TIM state */
609 htim->State = HAL_TIM_STATE_READY;
610
611 /* Return function status */
612 return HAL_OK;
613 }
614
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
620 * @brief TIM Output Compare functions
621 *
622 @verbatim
623 ==============================================================================
624 ##### TIM Output Compare functions #####
625 ==============================================================================
626 [..]
627 This section provides functions allowing to:
628 (+) Initialize and configure the TIM Output Compare.
629 (+) De-initialize the TIM Output Compare.
630 (+) Start the TIM Output Compare.
631 (+) Stop the TIM Output Compare.
632 (+) Start the TIM Output Compare and enable interrupt.
633 (+) Stop the TIM Output Compare and disable interrupt.
634 (+) Start the TIM Output Compare and enable DMA transfer.
635 (+) Stop the TIM Output Compare and disable DMA transfer.
636
637 @endverbatim
638 * @{
639 */
640 /**
641 * @brief Initializes the TIM Output Compare according to the specified
642 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
643 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
644 * requires a timer reset to avoid unexpected direction
645 * due to DIR bit readonly in center aligned mode.
646 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
647 * @param htim TIM Output Compare handle
648 * @retval HAL status
649 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)650 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
651 {
652 /* Check the TIM handle allocation */
653 if (htim == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_TIM_INSTANCE(htim->Instance));
660 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
661 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
662 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
663 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
664
665 if (htim->State == HAL_TIM_STATE_RESET)
666 {
667 /* Allocate lock resource and initialize it */
668 htim->Lock = HAL_UNLOCKED;
669
670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
671 /* Reset interrupt callbacks to legacy weak callbacks */
672 TIM_ResetCallback(htim);
673
674 if (htim->OC_MspInitCallback == NULL)
675 {
676 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
677 }
678 /* Init the low level hardware : GPIO, CLOCK, NVIC */
679 htim->OC_MspInitCallback(htim);
680 #else
681 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
682 HAL_TIM_OC_MspInit(htim);
683 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
684 }
685
686 /* Set the TIM state */
687 htim->State = HAL_TIM_STATE_BUSY;
688
689 /* Init the base time for the Output Compare */
690 TIM_Base_SetConfig(htim->Instance, &htim->Init);
691
692 /* Initialize the DMA burst operation state */
693 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
694
695 /* Initialize the TIM channels state */
696 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
697 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
698
699 /* Initialize the TIM state*/
700 htim->State = HAL_TIM_STATE_READY;
701
702 return HAL_OK;
703 }
704
705 /**
706 * @brief DeInitializes the TIM peripheral
707 * @param htim TIM Output Compare handle
708 * @retval HAL status
709 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)710 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
711 {
712 /* Check the parameters */
713 assert_param(IS_TIM_INSTANCE(htim->Instance));
714
715 htim->State = HAL_TIM_STATE_BUSY;
716
717 /* Disable the TIM Peripheral Clock */
718 __HAL_TIM_DISABLE(htim);
719
720 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
721 if (htim->OC_MspDeInitCallback == NULL)
722 {
723 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
724 }
725 /* DeInit the low level hardware */
726 htim->OC_MspDeInitCallback(htim);
727 #else
728 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
729 HAL_TIM_OC_MspDeInit(htim);
730 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
731
732 /* Change the DMA burst operation state */
733 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
734
735 /* Change the TIM channels state */
736 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
737 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
738
739 /* Change TIM state */
740 htim->State = HAL_TIM_STATE_RESET;
741
742 /* Release Lock */
743 __HAL_UNLOCK(htim);
744
745 return HAL_OK;
746 }
747
748 /**
749 * @brief Initializes the TIM Output Compare MSP.
750 * @param htim TIM Output Compare handle
751 * @retval None
752 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)753 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
754 {
755 /* Prevent unused argument(s) compilation warning */
756 UNUSED(htim);
757
758 /* NOTE : This function should not be modified, when the callback is needed,
759 the HAL_TIM_OC_MspInit could be implemented in the user file
760 */
761 }
762
763 /**
764 * @brief DeInitializes TIM Output Compare MSP.
765 * @param htim TIM Output Compare handle
766 * @retval None
767 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
769 {
770 /* Prevent unused argument(s) compilation warning */
771 UNUSED(htim);
772
773 /* NOTE : This function should not be modified, when the callback is needed,
774 the HAL_TIM_OC_MspDeInit could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief Starts the TIM Output Compare signal generation.
780 * @param htim TIM Output Compare handle
781 * @param Channel TIM Channel to be enabled
782 * This parameter can be one of the following values:
783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
787 * @retval HAL status
788 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)789 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
790 {
791 uint32_t tmpsmcr;
792
793 /* Check the parameters */
794 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
795
796 /* Check the TIM channel state */
797 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
798 {
799 return HAL_ERROR;
800 }
801
802 /* Set the TIM channel state */
803 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
804
805 /* Enable the Output compare channel */
806 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
807
808 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
809 {
810 /* Enable the main output */
811 __HAL_TIM_MOE_ENABLE(htim);
812 }
813
814 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
815 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
816 {
817 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
818 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
819 {
820 __HAL_TIM_ENABLE(htim);
821 }
822 }
823 else
824 {
825 __HAL_TIM_ENABLE(htim);
826 }
827
828 /* Return function status */
829 return HAL_OK;
830 }
831
832 /**
833 * @brief Stops the TIM Output Compare signal generation.
834 * @param htim TIM Output Compare handle
835 * @param Channel TIM Channel to be disabled
836 * This parameter can be one of the following values:
837 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
838 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
839 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
840 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
841 * @retval HAL status
842 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)843 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
844 {
845 /* Check the parameters */
846 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
847
848 /* Disable the Output compare channel */
849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
850
851 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
852 {
853 /* Disable the Main Output */
854 __HAL_TIM_MOE_DISABLE(htim);
855 }
856
857 /* Disable the Peripheral */
858 __HAL_TIM_DISABLE(htim);
859
860 /* Set the TIM channel state */
861 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
869 * @param htim TIM Output Compare handle
870 * @param Channel TIM Channel to be enabled
871 * This parameter can be one of the following values:
872 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
873 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
874 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
875 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
876 * @retval HAL status
877 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)878 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881 uint32_t tmpsmcr;
882
883 /* Check the parameters */
884 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
885
886 /* Check the TIM channel state */
887 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
888 {
889 return HAL_ERROR;
890 }
891
892 /* Set the TIM channel state */
893 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
894
895 switch (Channel)
896 {
897 case TIM_CHANNEL_1:
898 {
899 /* Enable the TIM Capture/Compare 1 interrupt */
900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
901 break;
902 }
903
904 case TIM_CHANNEL_2:
905 {
906 /* Enable the TIM Capture/Compare 2 interrupt */
907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
908 break;
909 }
910
911 case TIM_CHANNEL_3:
912 {
913 /* Enable the TIM Capture/Compare 3 interrupt */
914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
915 break;
916 }
917
918 case TIM_CHANNEL_4:
919 {
920 /* Enable the TIM Capture/Compare 4 interrupt */
921 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
922 break;
923 }
924
925 default:
926 status = HAL_ERROR;
927 break;
928 }
929
930 if (status == HAL_OK)
931 {
932 /* Enable the Output compare channel */
933 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
934
935 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
936 {
937 /* Enable the main output */
938 __HAL_TIM_MOE_ENABLE(htim);
939 }
940
941 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
942 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
943 {
944 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
945 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
946 {
947 __HAL_TIM_ENABLE(htim);
948 }
949 }
950 else
951 {
952 __HAL_TIM_ENABLE(htim);
953 }
954 }
955
956 /* Return function status */
957 return status;
958 }
959
960 /**
961 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
962 * @param htim TIM Output Compare handle
963 * @param Channel TIM Channel to be disabled
964 * This parameter can be one of the following values:
965 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
966 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
967 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
968 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
969 * @retval HAL status
970 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)971 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
972 {
973 HAL_StatusTypeDef status = HAL_OK;
974
975 /* Check the parameters */
976 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
977
978 switch (Channel)
979 {
980 case TIM_CHANNEL_1:
981 {
982 /* Disable the TIM Capture/Compare 1 interrupt */
983 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
984 break;
985 }
986
987 case TIM_CHANNEL_2:
988 {
989 /* Disable the TIM Capture/Compare 2 interrupt */
990 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
991 break;
992 }
993
994 case TIM_CHANNEL_3:
995 {
996 /* Disable the TIM Capture/Compare 3 interrupt */
997 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
998 break;
999 }
1000
1001 case TIM_CHANNEL_4:
1002 {
1003 /* Disable the TIM Capture/Compare 4 interrupt */
1004 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1005 break;
1006 }
1007
1008 default:
1009 status = HAL_ERROR;
1010 break;
1011 }
1012
1013 if (status == HAL_OK)
1014 {
1015 /* Disable the Output compare channel */
1016 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1017
1018 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1019 {
1020 /* Disable the Main Output */
1021 __HAL_TIM_MOE_DISABLE(htim);
1022 }
1023
1024 /* Disable the Peripheral */
1025 __HAL_TIM_DISABLE(htim);
1026
1027 /* Set the TIM channel state */
1028 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1029 }
1030
1031 /* Return function status */
1032 return status;
1033 }
1034
1035 /**
1036 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1037 * @param htim TIM Output Compare handle
1038 * @param Channel TIM Channel to be enabled
1039 * This parameter can be one of the following values:
1040 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1041 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1042 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1043 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1044 * @param pData The source Buffer address.
1045 * @param Length The length of data to be transferred from memory to TIM peripheral
1046 * @retval HAL status
1047 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1048 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1049 uint16_t Length)
1050 {
1051 HAL_StatusTypeDef status = HAL_OK;
1052 uint32_t tmpsmcr;
1053
1054 /* Check the parameters */
1055 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1056
1057 /* Set the TIM channel state */
1058 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1059 {
1060 return HAL_BUSY;
1061 }
1062 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1063 {
1064 if ((pData == NULL) || (Length == 0U))
1065 {
1066 return HAL_ERROR;
1067 }
1068 else
1069 {
1070 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1071 }
1072 }
1073 else
1074 {
1075 return HAL_ERROR;
1076 }
1077
1078 switch (Channel)
1079 {
1080 case TIM_CHANNEL_1:
1081 {
1082 /* Set the DMA compare callbacks */
1083 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1084 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1085
1086 /* Set the DMA error callback */
1087 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1088
1089 /* Enable the DMA stream */
1090 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1091 Length) != HAL_OK)
1092 {
1093 /* Return error status */
1094 return HAL_ERROR;
1095 }
1096
1097 /* Enable the TIM Capture/Compare 1 DMA request */
1098 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1099 break;
1100 }
1101
1102 case TIM_CHANNEL_2:
1103 {
1104 /* Set the DMA compare callbacks */
1105 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1106 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1107
1108 /* Set the DMA error callback */
1109 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1110
1111 /* Enable the DMA stream */
1112 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1113 Length) != HAL_OK)
1114 {
1115 /* Return error status */
1116 return HAL_ERROR;
1117 }
1118
1119 /* Enable the TIM Capture/Compare 2 DMA request */
1120 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1121 break;
1122 }
1123
1124 case TIM_CHANNEL_3:
1125 {
1126 /* Set the DMA compare callbacks */
1127 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1128 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1129
1130 /* Set the DMA error callback */
1131 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1132
1133 /* Enable the DMA stream */
1134 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1135 Length) != HAL_OK)
1136 {
1137 /* Return error status */
1138 return HAL_ERROR;
1139 }
1140 /* Enable the TIM Capture/Compare 3 DMA request */
1141 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1142 break;
1143 }
1144
1145 case TIM_CHANNEL_4:
1146 {
1147 /* Set the DMA compare callbacks */
1148 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1149 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1150
1151 /* Set the DMA error callback */
1152 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1153
1154 /* Enable the DMA stream */
1155 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1156 Length) != HAL_OK)
1157 {
1158 /* Return error status */
1159 return HAL_ERROR;
1160 }
1161 /* Enable the TIM Capture/Compare 4 DMA request */
1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1163 break;
1164 }
1165
1166 default:
1167 status = HAL_ERROR;
1168 break;
1169 }
1170
1171 if (status == HAL_OK)
1172 {
1173 /* Enable the Output compare channel */
1174 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1175
1176 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1177 {
1178 /* Enable the main output */
1179 __HAL_TIM_MOE_ENABLE(htim);
1180 }
1181
1182 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1183 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1184 {
1185 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1186 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1187 {
1188 __HAL_TIM_ENABLE(htim);
1189 }
1190 }
1191 else
1192 {
1193 __HAL_TIM_ENABLE(htim);
1194 }
1195 }
1196
1197 /* Return function status */
1198 return status;
1199 }
1200
1201 /**
1202 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1203 * @param htim TIM Output Compare handle
1204 * @param Channel TIM Channel to be disabled
1205 * This parameter can be one of the following values:
1206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1210 * @retval HAL status
1211 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1212 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1213 {
1214 HAL_StatusTypeDef status = HAL_OK;
1215
1216 /* Check the parameters */
1217 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1218
1219 switch (Channel)
1220 {
1221 case TIM_CHANNEL_1:
1222 {
1223 /* Disable the TIM Capture/Compare 1 DMA request */
1224 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1225 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1226 break;
1227 }
1228
1229 case TIM_CHANNEL_2:
1230 {
1231 /* Disable the TIM Capture/Compare 2 DMA request */
1232 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1233 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1234 break;
1235 }
1236
1237 case TIM_CHANNEL_3:
1238 {
1239 /* Disable the TIM Capture/Compare 3 DMA request */
1240 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1241 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1242 break;
1243 }
1244
1245 case TIM_CHANNEL_4:
1246 {
1247 /* Disable the TIM Capture/Compare 4 interrupt */
1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1249 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1250 break;
1251 }
1252
1253 default:
1254 status = HAL_ERROR;
1255 break;
1256 }
1257
1258 if (status == HAL_OK)
1259 {
1260 /* Disable the Output compare channel */
1261 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1262
1263 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1264 {
1265 /* Disable the Main Output */
1266 __HAL_TIM_MOE_DISABLE(htim);
1267 }
1268
1269 /* Disable the Peripheral */
1270 __HAL_TIM_DISABLE(htim);
1271
1272 /* Set the TIM channel state */
1273 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1274 }
1275
1276 /* Return function status */
1277 return status;
1278 }
1279
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1285 * @brief TIM PWM functions
1286 *
1287 @verbatim
1288 ==============================================================================
1289 ##### TIM PWM functions #####
1290 ==============================================================================
1291 [..]
1292 This section provides functions allowing to:
1293 (+) Initialize and configure the TIM PWM.
1294 (+) De-initialize the TIM PWM.
1295 (+) Start the TIM PWM.
1296 (+) Stop the TIM PWM.
1297 (+) Start the TIM PWM and enable interrupt.
1298 (+) Stop the TIM PWM and disable interrupt.
1299 (+) Start the TIM PWM and enable DMA transfer.
1300 (+) Stop the TIM PWM and disable DMA transfer.
1301
1302 @endverbatim
1303 * @{
1304 */
1305 /**
1306 * @brief Initializes the TIM PWM Time Base according to the specified
1307 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1308 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1309 * requires a timer reset to avoid unexpected direction
1310 * due to DIR bit readonly in center aligned mode.
1311 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1312 * @param htim TIM PWM handle
1313 * @retval HAL status
1314 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1315 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1316 {
1317 /* Check the TIM handle allocation */
1318 if (htim == NULL)
1319 {
1320 return HAL_ERROR;
1321 }
1322
1323 /* Check the parameters */
1324 assert_param(IS_TIM_INSTANCE(htim->Instance));
1325 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1326 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1327 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1328 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1329
1330 if (htim->State == HAL_TIM_STATE_RESET)
1331 {
1332 /* Allocate lock resource and initialize it */
1333 htim->Lock = HAL_UNLOCKED;
1334
1335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1336 /* Reset interrupt callbacks to legacy weak callbacks */
1337 TIM_ResetCallback(htim);
1338
1339 if (htim->PWM_MspInitCallback == NULL)
1340 {
1341 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1342 }
1343 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1344 htim->PWM_MspInitCallback(htim);
1345 #else
1346 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1347 HAL_TIM_PWM_MspInit(htim);
1348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1349 }
1350
1351 /* Set the TIM state */
1352 htim->State = HAL_TIM_STATE_BUSY;
1353
1354 /* Init the base time for the PWM */
1355 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1356
1357 /* Initialize the DMA burst operation state */
1358 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1359
1360 /* Initialize the TIM channels state */
1361 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1362 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1363
1364 /* Initialize the TIM state*/
1365 htim->State = HAL_TIM_STATE_READY;
1366
1367 return HAL_OK;
1368 }
1369
1370 /**
1371 * @brief DeInitializes the TIM peripheral
1372 * @param htim TIM PWM handle
1373 * @retval HAL status
1374 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1375 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1376 {
1377 /* Check the parameters */
1378 assert_param(IS_TIM_INSTANCE(htim->Instance));
1379
1380 htim->State = HAL_TIM_STATE_BUSY;
1381
1382 /* Disable the TIM Peripheral Clock */
1383 __HAL_TIM_DISABLE(htim);
1384
1385 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1386 if (htim->PWM_MspDeInitCallback == NULL)
1387 {
1388 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1389 }
1390 /* DeInit the low level hardware */
1391 htim->PWM_MspDeInitCallback(htim);
1392 #else
1393 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1394 HAL_TIM_PWM_MspDeInit(htim);
1395 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1396
1397 /* Change the DMA burst operation state */
1398 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1399
1400 /* Change the TIM channels state */
1401 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1402 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1403
1404 /* Change TIM state */
1405 htim->State = HAL_TIM_STATE_RESET;
1406
1407 /* Release Lock */
1408 __HAL_UNLOCK(htim);
1409
1410 return HAL_OK;
1411 }
1412
1413 /**
1414 * @brief Initializes the TIM PWM MSP.
1415 * @param htim TIM PWM handle
1416 * @retval None
1417 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1418 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1419 {
1420 /* Prevent unused argument(s) compilation warning */
1421 UNUSED(htim);
1422
1423 /* NOTE : This function should not be modified, when the callback is needed,
1424 the HAL_TIM_PWM_MspInit could be implemented in the user file
1425 */
1426 }
1427
1428 /**
1429 * @brief DeInitializes TIM PWM MSP.
1430 * @param htim TIM PWM handle
1431 * @retval None
1432 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1433 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1434 {
1435 /* Prevent unused argument(s) compilation warning */
1436 UNUSED(htim);
1437
1438 /* NOTE : This function should not be modified, when the callback is needed,
1439 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1440 */
1441 }
1442
1443 /**
1444 * @brief Starts the PWM signal generation.
1445 * @param htim TIM handle
1446 * @param Channel TIM Channels to be enabled
1447 * This parameter can be one of the following values:
1448 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1449 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1450 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1451 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1452 * @retval HAL status
1453 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1454 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1455 {
1456 uint32_t tmpsmcr;
1457
1458 /* Check the parameters */
1459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1460
1461 /* Check the TIM channel state */
1462 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1463 {
1464 return HAL_ERROR;
1465 }
1466
1467 /* Set the TIM channel state */
1468 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1469
1470 /* Enable the Capture compare channel */
1471 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1472
1473 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1474 {
1475 /* Enable the main output */
1476 __HAL_TIM_MOE_ENABLE(htim);
1477 }
1478
1479 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1480 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1481 {
1482 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1483 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1484 {
1485 __HAL_TIM_ENABLE(htim);
1486 }
1487 }
1488 else
1489 {
1490 __HAL_TIM_ENABLE(htim);
1491 }
1492
1493 /* Return function status */
1494 return HAL_OK;
1495 }
1496
1497 /**
1498 * @brief Stops the PWM signal generation.
1499 * @param htim TIM PWM handle
1500 * @param Channel TIM Channels to be disabled
1501 * This parameter can be one of the following values:
1502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1504 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1505 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1506 * @retval HAL status
1507 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1508 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1509 {
1510 /* Check the parameters */
1511 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1512
1513 /* Disable the Capture compare channel */
1514 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1515
1516 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1517 {
1518 /* Disable the Main Output */
1519 __HAL_TIM_MOE_DISABLE(htim);
1520 }
1521
1522 /* Disable the Peripheral */
1523 __HAL_TIM_DISABLE(htim);
1524
1525 /* Set the TIM channel state */
1526 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1527
1528 /* Return function status */
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Starts the PWM signal generation in interrupt mode.
1534 * @param htim TIM PWM handle
1535 * @param Channel TIM Channel to be enabled
1536 * This parameter can be one of the following values:
1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1541 * @retval HAL status
1542 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1543 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1544 {
1545 HAL_StatusTypeDef status = HAL_OK;
1546 uint32_t tmpsmcr;
1547
1548 /* Check the parameters */
1549 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1550
1551 /* Check the TIM channel state */
1552 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1553 {
1554 return HAL_ERROR;
1555 }
1556
1557 /* Set the TIM channel state */
1558 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1559
1560 switch (Channel)
1561 {
1562 case TIM_CHANNEL_1:
1563 {
1564 /* Enable the TIM Capture/Compare 1 interrupt */
1565 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1566 break;
1567 }
1568
1569 case TIM_CHANNEL_2:
1570 {
1571 /* Enable the TIM Capture/Compare 2 interrupt */
1572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1573 break;
1574 }
1575
1576 case TIM_CHANNEL_3:
1577 {
1578 /* Enable the TIM Capture/Compare 3 interrupt */
1579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1580 break;
1581 }
1582
1583 case TIM_CHANNEL_4:
1584 {
1585 /* Enable the TIM Capture/Compare 4 interrupt */
1586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1587 break;
1588 }
1589
1590 default:
1591 status = HAL_ERROR;
1592 break;
1593 }
1594
1595 if (status == HAL_OK)
1596 {
1597 /* Enable the Capture compare channel */
1598 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1599
1600 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1601 {
1602 /* Enable the main output */
1603 __HAL_TIM_MOE_ENABLE(htim);
1604 }
1605
1606 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1607 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1608 {
1609 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1610 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1611 {
1612 __HAL_TIM_ENABLE(htim);
1613 }
1614 }
1615 else
1616 {
1617 __HAL_TIM_ENABLE(htim);
1618 }
1619 }
1620
1621 /* Return function status */
1622 return status;
1623 }
1624
1625 /**
1626 * @brief Stops the PWM signal generation in interrupt mode.
1627 * @param htim TIM PWM handle
1628 * @param Channel TIM Channels to be disabled
1629 * This parameter can be one of the following values:
1630 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1631 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1632 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1633 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1634 * @retval HAL status
1635 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1636 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1637 {
1638 HAL_StatusTypeDef status = HAL_OK;
1639
1640 /* Check the parameters */
1641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1642
1643 switch (Channel)
1644 {
1645 case TIM_CHANNEL_1:
1646 {
1647 /* Disable the TIM Capture/Compare 1 interrupt */
1648 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1649 break;
1650 }
1651
1652 case TIM_CHANNEL_2:
1653 {
1654 /* Disable the TIM Capture/Compare 2 interrupt */
1655 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1656 break;
1657 }
1658
1659 case TIM_CHANNEL_3:
1660 {
1661 /* Disable the TIM Capture/Compare 3 interrupt */
1662 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1663 break;
1664 }
1665
1666 case TIM_CHANNEL_4:
1667 {
1668 /* Disable the TIM Capture/Compare 4 interrupt */
1669 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1670 break;
1671 }
1672
1673 default:
1674 status = HAL_ERROR;
1675 break;
1676 }
1677
1678 if (status == HAL_OK)
1679 {
1680 /* Disable the Capture compare channel */
1681 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1682
1683 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1684 {
1685 /* Disable the Main Output */
1686 __HAL_TIM_MOE_DISABLE(htim);
1687 }
1688
1689 /* Disable the Peripheral */
1690 __HAL_TIM_DISABLE(htim);
1691
1692 /* Set the TIM channel state */
1693 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1694 }
1695
1696 /* Return function status */
1697 return status;
1698 }
1699
1700 /**
1701 * @brief Starts the TIM PWM signal generation in DMA mode.
1702 * @param htim TIM PWM handle
1703 * @param Channel TIM Channels to be enabled
1704 * This parameter can be one of the following values:
1705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1709 * @param pData The source Buffer address.
1710 * @param Length The length of data to be transferred from memory to TIM peripheral
1711 * @retval HAL status
1712 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1713 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1714 uint16_t Length)
1715 {
1716 HAL_StatusTypeDef status = HAL_OK;
1717 uint32_t tmpsmcr;
1718
1719 /* Check the parameters */
1720 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1721
1722 /* Set the TIM channel state */
1723 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1724 {
1725 return HAL_BUSY;
1726 }
1727 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1728 {
1729 if ((pData == NULL) || (Length == 0U))
1730 {
1731 return HAL_ERROR;
1732 }
1733 else
1734 {
1735 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1736 }
1737 }
1738 else
1739 {
1740 return HAL_ERROR;
1741 }
1742
1743 switch (Channel)
1744 {
1745 case TIM_CHANNEL_1:
1746 {
1747 /* Set the DMA compare callbacks */
1748 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1749 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1750
1751 /* Set the DMA error callback */
1752 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1753
1754 /* Enable the DMA stream */
1755 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1756 Length) != HAL_OK)
1757 {
1758 /* Return error status */
1759 return HAL_ERROR;
1760 }
1761
1762 /* Enable the TIM Capture/Compare 1 DMA request */
1763 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1764 break;
1765 }
1766
1767 case TIM_CHANNEL_2:
1768 {
1769 /* Set the DMA compare callbacks */
1770 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1771 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1772
1773 /* Set the DMA error callback */
1774 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1775
1776 /* Enable the DMA stream */
1777 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1778 Length) != HAL_OK)
1779 {
1780 /* Return error status */
1781 return HAL_ERROR;
1782 }
1783 /* Enable the TIM Capture/Compare 2 DMA request */
1784 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1785 break;
1786 }
1787
1788 case TIM_CHANNEL_3:
1789 {
1790 /* Set the DMA compare callbacks */
1791 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1792 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1793
1794 /* Set the DMA error callback */
1795 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1796
1797 /* Enable the DMA stream */
1798 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1799 Length) != HAL_OK)
1800 {
1801 /* Return error status */
1802 return HAL_ERROR;
1803 }
1804 /* Enable the TIM Output Capture/Compare 3 request */
1805 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1806 break;
1807 }
1808
1809 case TIM_CHANNEL_4:
1810 {
1811 /* Set the DMA compare callbacks */
1812 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1813 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1814
1815 /* Set the DMA error callback */
1816 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1817
1818 /* Enable the DMA stream */
1819 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1820 Length) != HAL_OK)
1821 {
1822 /* Return error status */
1823 return HAL_ERROR;
1824 }
1825 /* Enable the TIM Capture/Compare 4 DMA request */
1826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1827 break;
1828 }
1829
1830 default:
1831 status = HAL_ERROR;
1832 break;
1833 }
1834
1835 if (status == HAL_OK)
1836 {
1837 /* Enable the Capture compare channel */
1838 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1839
1840 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1841 {
1842 /* Enable the main output */
1843 __HAL_TIM_MOE_ENABLE(htim);
1844 }
1845
1846 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1847 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1848 {
1849 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1850 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1851 {
1852 __HAL_TIM_ENABLE(htim);
1853 }
1854 }
1855 else
1856 {
1857 __HAL_TIM_ENABLE(htim);
1858 }
1859 }
1860
1861 /* Return function status */
1862 return status;
1863 }
1864
1865 /**
1866 * @brief Stops the TIM PWM signal generation in DMA mode.
1867 * @param htim TIM PWM handle
1868 * @param Channel TIM Channels to be disabled
1869 * This parameter can be one of the following values:
1870 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1871 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1872 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1873 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1874 * @retval HAL status
1875 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1876 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1877 {
1878 HAL_StatusTypeDef status = HAL_OK;
1879
1880 /* Check the parameters */
1881 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1882
1883 switch (Channel)
1884 {
1885 case TIM_CHANNEL_1:
1886 {
1887 /* Disable the TIM Capture/Compare 1 DMA request */
1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1889 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1890 break;
1891 }
1892
1893 case TIM_CHANNEL_2:
1894 {
1895 /* Disable the TIM Capture/Compare 2 DMA request */
1896 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1897 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1898 break;
1899 }
1900
1901 case TIM_CHANNEL_3:
1902 {
1903 /* Disable the TIM Capture/Compare 3 DMA request */
1904 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1905 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1906 break;
1907 }
1908
1909 case TIM_CHANNEL_4:
1910 {
1911 /* Disable the TIM Capture/Compare 4 interrupt */
1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1913 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1914 break;
1915 }
1916
1917 default:
1918 status = HAL_ERROR;
1919 break;
1920 }
1921
1922 if (status == HAL_OK)
1923 {
1924 /* Disable the Capture compare channel */
1925 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1926
1927 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1928 {
1929 /* Disable the Main Output */
1930 __HAL_TIM_MOE_DISABLE(htim);
1931 }
1932
1933 /* Disable the Peripheral */
1934 __HAL_TIM_DISABLE(htim);
1935
1936 /* Set the TIM channel state */
1937 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1938 }
1939
1940 /* Return function status */
1941 return status;
1942 }
1943
1944 /**
1945 * @}
1946 */
1947
1948 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1949 * @brief TIM Input Capture functions
1950 *
1951 @verbatim
1952 ==============================================================================
1953 ##### TIM Input Capture functions #####
1954 ==============================================================================
1955 [..]
1956 This section provides functions allowing to:
1957 (+) Initialize and configure the TIM Input Capture.
1958 (+) De-initialize the TIM Input Capture.
1959 (+) Start the TIM Input Capture.
1960 (+) Stop the TIM Input Capture.
1961 (+) Start the TIM Input Capture and enable interrupt.
1962 (+) Stop the TIM Input Capture and disable interrupt.
1963 (+) Start the TIM Input Capture and enable DMA transfer.
1964 (+) Stop the TIM Input Capture and disable DMA transfer.
1965
1966 @endverbatim
1967 * @{
1968 */
1969 /**
1970 * @brief Initializes the TIM Input Capture Time base according to the specified
1971 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1972 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1973 * requires a timer reset to avoid unexpected direction
1974 * due to DIR bit readonly in center aligned mode.
1975 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1976 * @param htim TIM Input Capture handle
1977 * @retval HAL status
1978 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1979 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1980 {
1981 /* Check the TIM handle allocation */
1982 if (htim == NULL)
1983 {
1984 return HAL_ERROR;
1985 }
1986
1987 /* Check the parameters */
1988 assert_param(IS_TIM_INSTANCE(htim->Instance));
1989 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1990 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1991 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1992 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1993
1994 if (htim->State == HAL_TIM_STATE_RESET)
1995 {
1996 /* Allocate lock resource and initialize it */
1997 htim->Lock = HAL_UNLOCKED;
1998
1999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2000 /* Reset interrupt callbacks to legacy weak callbacks */
2001 TIM_ResetCallback(htim);
2002
2003 if (htim->IC_MspInitCallback == NULL)
2004 {
2005 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2006 }
2007 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2008 htim->IC_MspInitCallback(htim);
2009 #else
2010 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2011 HAL_TIM_IC_MspInit(htim);
2012 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2013 }
2014
2015 /* Set the TIM state */
2016 htim->State = HAL_TIM_STATE_BUSY;
2017
2018 /* Init the base time for the input capture */
2019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2020
2021 /* Initialize the DMA burst operation state */
2022 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2023
2024 /* Initialize the TIM channels state */
2025 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2026 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2027
2028 /* Initialize the TIM state*/
2029 htim->State = HAL_TIM_STATE_READY;
2030
2031 return HAL_OK;
2032 }
2033
2034 /**
2035 * @brief DeInitializes the TIM peripheral
2036 * @param htim TIM Input Capture handle
2037 * @retval HAL status
2038 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2039 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2040 {
2041 /* Check the parameters */
2042 assert_param(IS_TIM_INSTANCE(htim->Instance));
2043
2044 htim->State = HAL_TIM_STATE_BUSY;
2045
2046 /* Disable the TIM Peripheral Clock */
2047 __HAL_TIM_DISABLE(htim);
2048
2049 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2050 if (htim->IC_MspDeInitCallback == NULL)
2051 {
2052 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2053 }
2054 /* DeInit the low level hardware */
2055 htim->IC_MspDeInitCallback(htim);
2056 #else
2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2058 HAL_TIM_IC_MspDeInit(htim);
2059 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2060
2061 /* Change the DMA burst operation state */
2062 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2063
2064 /* Change the TIM channels state */
2065 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2066 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2067
2068 /* Change TIM state */
2069 htim->State = HAL_TIM_STATE_RESET;
2070
2071 /* Release Lock */
2072 __HAL_UNLOCK(htim);
2073
2074 return HAL_OK;
2075 }
2076
2077 /**
2078 * @brief Initializes the TIM Input Capture MSP.
2079 * @param htim TIM Input Capture handle
2080 * @retval None
2081 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2082 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2083 {
2084 /* Prevent unused argument(s) compilation warning */
2085 UNUSED(htim);
2086
2087 /* NOTE : This function should not be modified, when the callback is needed,
2088 the HAL_TIM_IC_MspInit could be implemented in the user file
2089 */
2090 }
2091
2092 /**
2093 * @brief DeInitializes TIM Input Capture MSP.
2094 * @param htim TIM handle
2095 * @retval None
2096 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2097 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2098 {
2099 /* Prevent unused argument(s) compilation warning */
2100 UNUSED(htim);
2101
2102 /* NOTE : This function should not be modified, when the callback is needed,
2103 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2104 */
2105 }
2106
2107 /**
2108 * @brief Starts the TIM Input Capture measurement.
2109 * @param htim TIM Input Capture handle
2110 * @param Channel TIM Channels to be enabled
2111 * This parameter can be one of the following values:
2112 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2113 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2114 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2115 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2116 * @retval HAL status
2117 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2118 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2119 {
2120 uint32_t tmpsmcr;
2121 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2122 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2123
2124 /* Check the parameters */
2125 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2126
2127 /* Check the TIM channel state */
2128 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2129 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2130 {
2131 return HAL_ERROR;
2132 }
2133
2134 /* Set the TIM channel state */
2135 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2136 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2137
2138 /* Enable the Input Capture channel */
2139 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2140
2141 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2142 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2143 {
2144 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2145 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2146 {
2147 __HAL_TIM_ENABLE(htim);
2148 }
2149 }
2150 else
2151 {
2152 __HAL_TIM_ENABLE(htim);
2153 }
2154
2155 /* Return function status */
2156 return HAL_OK;
2157 }
2158
2159 /**
2160 * @brief Stops the TIM Input Capture measurement.
2161 * @param htim TIM Input Capture handle
2162 * @param Channel TIM Channels to be disabled
2163 * This parameter can be one of the following values:
2164 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2165 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2166 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2167 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2168 * @retval HAL status
2169 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2170 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2171 {
2172 /* Check the parameters */
2173 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2174
2175 /* Disable the Input Capture channel */
2176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2177
2178 /* Disable the Peripheral */
2179 __HAL_TIM_DISABLE(htim);
2180
2181 /* Set the TIM channel state */
2182 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2183 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2184
2185 /* Return function status */
2186 return HAL_OK;
2187 }
2188
2189 /**
2190 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2191 * @param htim TIM Input Capture handle
2192 * @param Channel TIM Channels to be enabled
2193 * This parameter can be one of the following values:
2194 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2195 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2196 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2197 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2198 * @retval HAL status
2199 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2200 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2201 {
2202 HAL_StatusTypeDef status = HAL_OK;
2203 uint32_t tmpsmcr;
2204
2205 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2206 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2207
2208 /* Check the parameters */
2209 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2210
2211 /* Check the TIM channel state */
2212 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2213 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2214 {
2215 return HAL_ERROR;
2216 }
2217
2218 /* Set the TIM channel state */
2219 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2220 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2221
2222 switch (Channel)
2223 {
2224 case TIM_CHANNEL_1:
2225 {
2226 /* Enable the TIM Capture/Compare 1 interrupt */
2227 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_2:
2232 {
2233 /* Enable the TIM Capture/Compare 2 interrupt */
2234 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2235 break;
2236 }
2237
2238 case TIM_CHANNEL_3:
2239 {
2240 /* Enable the TIM Capture/Compare 3 interrupt */
2241 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2242 break;
2243 }
2244
2245 case TIM_CHANNEL_4:
2246 {
2247 /* Enable the TIM Capture/Compare 4 interrupt */
2248 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2249 break;
2250 }
2251
2252 default:
2253 status = HAL_ERROR;
2254 break;
2255 }
2256
2257 if (status == HAL_OK)
2258 {
2259 /* Enable the Input Capture channel */
2260 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2261
2262 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2263 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2264 {
2265 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2266 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2267 {
2268 __HAL_TIM_ENABLE(htim);
2269 }
2270 }
2271 else
2272 {
2273 __HAL_TIM_ENABLE(htim);
2274 }
2275 }
2276
2277 /* Return function status */
2278 return status;
2279 }
2280
2281 /**
2282 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2283 * @param htim TIM Input Capture handle
2284 * @param Channel TIM Channels to be disabled
2285 * This parameter can be one of the following values:
2286 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2287 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2288 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2289 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2290 * @retval HAL status
2291 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2292 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2293 {
2294 HAL_StatusTypeDef status = HAL_OK;
2295
2296 /* Check the parameters */
2297 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2298
2299 switch (Channel)
2300 {
2301 case TIM_CHANNEL_1:
2302 {
2303 /* Disable the TIM Capture/Compare 1 interrupt */
2304 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2305 break;
2306 }
2307
2308 case TIM_CHANNEL_2:
2309 {
2310 /* Disable the TIM Capture/Compare 2 interrupt */
2311 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2312 break;
2313 }
2314
2315 case TIM_CHANNEL_3:
2316 {
2317 /* Disable the TIM Capture/Compare 3 interrupt */
2318 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2319 break;
2320 }
2321
2322 case TIM_CHANNEL_4:
2323 {
2324 /* Disable the TIM Capture/Compare 4 interrupt */
2325 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2326 break;
2327 }
2328
2329 default:
2330 status = HAL_ERROR;
2331 break;
2332 }
2333
2334 if (status == HAL_OK)
2335 {
2336 /* Disable the Input Capture channel */
2337 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2338
2339 /* Disable the Peripheral */
2340 __HAL_TIM_DISABLE(htim);
2341
2342 /* Set the TIM channel state */
2343 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2344 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2345 }
2346
2347 /* Return function status */
2348 return status;
2349 }
2350
2351 /**
2352 * @brief Starts the TIM Input Capture measurement in DMA mode.
2353 * @param htim TIM Input Capture handle
2354 * @param Channel TIM Channels to be enabled
2355 * This parameter can be one of the following values:
2356 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2357 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2358 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2359 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2360 * @param pData The destination Buffer address.
2361 * @param Length The length of data to be transferred from TIM peripheral to memory.
2362 * @retval HAL status
2363 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2364 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2365 {
2366 HAL_StatusTypeDef status = HAL_OK;
2367 uint32_t tmpsmcr;
2368
2369 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2370 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2371
2372 /* Check the parameters */
2373 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2374 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2375
2376 /* Set the TIM channel state */
2377 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2378 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2379 {
2380 return HAL_BUSY;
2381 }
2382 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2383 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2384 {
2385 if ((pData == NULL) || (Length == 0U))
2386 {
2387 return HAL_ERROR;
2388 }
2389 else
2390 {
2391 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2392 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2393 }
2394 }
2395 else
2396 {
2397 return HAL_ERROR;
2398 }
2399
2400 /* Enable the Input Capture channel */
2401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2402
2403 switch (Channel)
2404 {
2405 case TIM_CHANNEL_1:
2406 {
2407 /* Set the DMA capture callbacks */
2408 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2409 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2410
2411 /* Set the DMA error callback */
2412 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2413
2414 /* Enable the DMA stream */
2415 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2416 Length) != HAL_OK)
2417 {
2418 /* Return error status */
2419 return HAL_ERROR;
2420 }
2421 /* Enable the TIM Capture/Compare 1 DMA request */
2422 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2423 break;
2424 }
2425
2426 case TIM_CHANNEL_2:
2427 {
2428 /* Set the DMA capture callbacks */
2429 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2430 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2431
2432 /* Set the DMA error callback */
2433 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2434
2435 /* Enable the DMA stream */
2436 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2437 Length) != HAL_OK)
2438 {
2439 /* Return error status */
2440 return HAL_ERROR;
2441 }
2442 /* Enable the TIM Capture/Compare 2 DMA request */
2443 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2444 break;
2445 }
2446
2447 case TIM_CHANNEL_3:
2448 {
2449 /* Set the DMA capture callbacks */
2450 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2451 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2452
2453 /* Set the DMA error callback */
2454 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2455
2456 /* Enable the DMA stream */
2457 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2458 Length) != HAL_OK)
2459 {
2460 /* Return error status */
2461 return HAL_ERROR;
2462 }
2463 /* Enable the TIM Capture/Compare 3 DMA request */
2464 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2465 break;
2466 }
2467
2468 case TIM_CHANNEL_4:
2469 {
2470 /* Set the DMA capture callbacks */
2471 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2472 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2473
2474 /* Set the DMA error callback */
2475 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2476
2477 /* Enable the DMA stream */
2478 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2479 Length) != HAL_OK)
2480 {
2481 /* Return error status */
2482 return HAL_ERROR;
2483 }
2484 /* Enable the TIM Capture/Compare 4 DMA request */
2485 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2486 break;
2487 }
2488
2489 default:
2490 status = HAL_ERROR;
2491 break;
2492 }
2493
2494 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2495 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2496 {
2497 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2498 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2499 {
2500 __HAL_TIM_ENABLE(htim);
2501 }
2502 }
2503 else
2504 {
2505 __HAL_TIM_ENABLE(htim);
2506 }
2507
2508 /* Return function status */
2509 return status;
2510 }
2511
2512 /**
2513 * @brief Stops the TIM Input Capture measurement in DMA mode.
2514 * @param htim TIM Input Capture handle
2515 * @param Channel TIM Channels to be disabled
2516 * This parameter can be one of the following values:
2517 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2518 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2519 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2520 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2521 * @retval HAL status
2522 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2523 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2524 {
2525 HAL_StatusTypeDef status = HAL_OK;
2526
2527 /* Check the parameters */
2528 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2529 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2530
2531 /* Disable the Input Capture channel */
2532 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2533
2534 switch (Channel)
2535 {
2536 case TIM_CHANNEL_1:
2537 {
2538 /* Disable the TIM Capture/Compare 1 DMA request */
2539 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2540 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2541 break;
2542 }
2543
2544 case TIM_CHANNEL_2:
2545 {
2546 /* Disable the TIM Capture/Compare 2 DMA request */
2547 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2548 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2549 break;
2550 }
2551
2552 case TIM_CHANNEL_3:
2553 {
2554 /* Disable the TIM Capture/Compare 3 DMA request */
2555 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2556 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2557 break;
2558 }
2559
2560 case TIM_CHANNEL_4:
2561 {
2562 /* Disable the TIM Capture/Compare 4 DMA request */
2563 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2564 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2565 break;
2566 }
2567
2568 default:
2569 status = HAL_ERROR;
2570 break;
2571 }
2572
2573 if (status == HAL_OK)
2574 {
2575 /* Disable the Peripheral */
2576 __HAL_TIM_DISABLE(htim);
2577
2578 /* Set the TIM channel state */
2579 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2580 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2581 }
2582
2583 /* Return function status */
2584 return status;
2585 }
2586 /**
2587 * @}
2588 */
2589
2590 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2591 * @brief TIM One Pulse functions
2592 *
2593 @verbatim
2594 ==============================================================================
2595 ##### TIM One Pulse functions #####
2596 ==============================================================================
2597 [..]
2598 This section provides functions allowing to:
2599 (+) Initialize and configure the TIM One Pulse.
2600 (+) De-initialize the TIM One Pulse.
2601 (+) Start the TIM One Pulse.
2602 (+) Stop the TIM One Pulse.
2603 (+) Start the TIM One Pulse and enable interrupt.
2604 (+) Stop the TIM One Pulse and disable interrupt.
2605 (+) Start the TIM One Pulse and enable DMA transfer.
2606 (+) Stop the TIM One Pulse and disable DMA transfer.
2607
2608 @endverbatim
2609 * @{
2610 */
2611 /**
2612 * @brief Initializes the TIM One Pulse Time Base according to the specified
2613 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2614 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2615 * requires a timer reset to avoid unexpected direction
2616 * due to DIR bit readonly in center aligned mode.
2617 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2618 * @note When the timer instance is initialized in One Pulse mode, timer
2619 * channels 1 and channel 2 are reserved and cannot be used for other
2620 * purpose.
2621 * @param htim TIM One Pulse handle
2622 * @param OnePulseMode Select the One pulse mode.
2623 * This parameter can be one of the following values:
2624 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2625 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2626 * @retval HAL status
2627 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2628 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2629 {
2630 /* Check the TIM handle allocation */
2631 if (htim == NULL)
2632 {
2633 return HAL_ERROR;
2634 }
2635
2636 /* Check the parameters */
2637 assert_param(IS_TIM_INSTANCE(htim->Instance));
2638 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2639 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2640 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2641 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2642 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2643
2644 if (htim->State == HAL_TIM_STATE_RESET)
2645 {
2646 /* Allocate lock resource and initialize it */
2647 htim->Lock = HAL_UNLOCKED;
2648
2649 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2650 /* Reset interrupt callbacks to legacy weak callbacks */
2651 TIM_ResetCallback(htim);
2652
2653 if (htim->OnePulse_MspInitCallback == NULL)
2654 {
2655 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2656 }
2657 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2658 htim->OnePulse_MspInitCallback(htim);
2659 #else
2660 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2661 HAL_TIM_OnePulse_MspInit(htim);
2662 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2663 }
2664
2665 /* Set the TIM state */
2666 htim->State = HAL_TIM_STATE_BUSY;
2667
2668 /* Configure the Time base in the One Pulse Mode */
2669 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2670
2671 /* Reset the OPM Bit */
2672 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2673
2674 /* Configure the OPM Mode */
2675 htim->Instance->CR1 |= OnePulseMode;
2676
2677 /* Initialize the DMA burst operation state */
2678 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2679
2680 /* Initialize the TIM channels state */
2681 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2682 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2683 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2684 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2685
2686 /* Initialize the TIM state*/
2687 htim->State = HAL_TIM_STATE_READY;
2688
2689 return HAL_OK;
2690 }
2691
2692 /**
2693 * @brief DeInitializes the TIM One Pulse
2694 * @param htim TIM One Pulse handle
2695 * @retval HAL status
2696 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2697 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2698 {
2699 /* Check the parameters */
2700 assert_param(IS_TIM_INSTANCE(htim->Instance));
2701
2702 htim->State = HAL_TIM_STATE_BUSY;
2703
2704 /* Disable the TIM Peripheral Clock */
2705 __HAL_TIM_DISABLE(htim);
2706
2707 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2708 if (htim->OnePulse_MspDeInitCallback == NULL)
2709 {
2710 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2711 }
2712 /* DeInit the low level hardware */
2713 htim->OnePulse_MspDeInitCallback(htim);
2714 #else
2715 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2716 HAL_TIM_OnePulse_MspDeInit(htim);
2717 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2718
2719 /* Change the DMA burst operation state */
2720 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2721
2722 /* Set the TIM channel state */
2723 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2724 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2725 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2726 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2727
2728 /* Change TIM state */
2729 htim->State = HAL_TIM_STATE_RESET;
2730
2731 /* Release Lock */
2732 __HAL_UNLOCK(htim);
2733
2734 return HAL_OK;
2735 }
2736
2737 /**
2738 * @brief Initializes the TIM One Pulse MSP.
2739 * @param htim TIM One Pulse handle
2740 * @retval None
2741 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2742 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2743 {
2744 /* Prevent unused argument(s) compilation warning */
2745 UNUSED(htim);
2746
2747 /* NOTE : This function should not be modified, when the callback is needed,
2748 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2749 */
2750 }
2751
2752 /**
2753 * @brief DeInitializes TIM One Pulse MSP.
2754 * @param htim TIM One Pulse handle
2755 * @retval None
2756 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2757 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2758 {
2759 /* Prevent unused argument(s) compilation warning */
2760 UNUSED(htim);
2761
2762 /* NOTE : This function should not be modified, when the callback is needed,
2763 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2764 */
2765 }
2766
2767 /**
2768 * @brief Starts the TIM One Pulse signal generation.
2769 * @note Though OutputChannel parameter is deprecated and ignored by the function
2770 * it has been kept to avoid HAL_TIM API compatibility break.
2771 * @note The pulse output channel is determined when calling
2772 * @ref HAL_TIM_OnePulse_ConfigChannel().
2773 * @param htim TIM One Pulse handle
2774 * @param OutputChannel See note above
2775 * @retval HAL status
2776 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2777 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2778 {
2779 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2780 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2781 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2782 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2783
2784 /* Prevent unused argument(s) compilation warning */
2785 UNUSED(OutputChannel);
2786
2787 /* Check the TIM channels state */
2788 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2789 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2790 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2791 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2792 {
2793 return HAL_ERROR;
2794 }
2795
2796 /* Set the TIM channels state */
2797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2800 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2801
2802 /* Enable the Capture compare and the Input Capture channels
2803 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2804 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2805 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2806 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2807
2808 No need to enable the counter, it's enabled automatically by hardware
2809 (the counter starts in response to a stimulus and generate a pulse */
2810
2811 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2812 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2813
2814 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2815 {
2816 /* Enable the main output */
2817 __HAL_TIM_MOE_ENABLE(htim);
2818 }
2819
2820 /* Return function status */
2821 return HAL_OK;
2822 }
2823
2824 /**
2825 * @brief Stops the TIM One Pulse signal generation.
2826 * @note Though OutputChannel parameter is deprecated and ignored by the function
2827 * it has been kept to avoid HAL_TIM API compatibility break.
2828 * @note The pulse output channel is determined when calling
2829 * @ref HAL_TIM_OnePulse_ConfigChannel().
2830 * @param htim TIM One Pulse handle
2831 * @param OutputChannel See note above
2832 * @retval HAL status
2833 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2834 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2835 {
2836 /* Prevent unused argument(s) compilation warning */
2837 UNUSED(OutputChannel);
2838
2839 /* Disable the Capture compare and the Input Capture channels
2840 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2841 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2842 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2843 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2844
2845 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2846 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2847
2848 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2849 {
2850 /* Disable the Main Output */
2851 __HAL_TIM_MOE_DISABLE(htim);
2852 }
2853
2854 /* Disable the Peripheral */
2855 __HAL_TIM_DISABLE(htim);
2856
2857 /* Set the TIM channels state */
2858 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2859 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2860 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2861 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2862
2863 /* Return function status */
2864 return HAL_OK;
2865 }
2866
2867 /**
2868 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2869 * @note Though OutputChannel parameter is deprecated and ignored by the function
2870 * it has been kept to avoid HAL_TIM API compatibility break.
2871 * @note The pulse output channel is determined when calling
2872 * @ref HAL_TIM_OnePulse_ConfigChannel().
2873 * @param htim TIM One Pulse handle
2874 * @param OutputChannel See note above
2875 * @retval HAL status
2876 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2877 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2878 {
2879 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2880 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2881 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2882 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2883
2884 /* Prevent unused argument(s) compilation warning */
2885 UNUSED(OutputChannel);
2886
2887 /* Check the TIM channels state */
2888 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2889 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2890 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2891 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2892 {
2893 return HAL_ERROR;
2894 }
2895
2896 /* Set the TIM channels state */
2897 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2898 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2899 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2900 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2901
2902 /* Enable the Capture compare and the Input Capture channels
2903 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2904 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2905 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2906 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2907
2908 No need to enable the counter, it's enabled automatically by hardware
2909 (the counter starts in response to a stimulus and generate a pulse */
2910
2911 /* Enable the TIM Capture/Compare 1 interrupt */
2912 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2913
2914 /* Enable the TIM Capture/Compare 2 interrupt */
2915 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2916
2917 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2918 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2919
2920 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2921 {
2922 /* Enable the main output */
2923 __HAL_TIM_MOE_ENABLE(htim);
2924 }
2925
2926 /* Return function status */
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2932 * @note Though OutputChannel parameter is deprecated and ignored by the function
2933 * it has been kept to avoid HAL_TIM API compatibility break.
2934 * @note The pulse output channel is determined when calling
2935 * @ref HAL_TIM_OnePulse_ConfigChannel().
2936 * @param htim TIM One Pulse handle
2937 * @param OutputChannel See note above
2938 * @retval HAL status
2939 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2940 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2941 {
2942 /* Prevent unused argument(s) compilation warning */
2943 UNUSED(OutputChannel);
2944
2945 /* Disable the TIM Capture/Compare 1 interrupt */
2946 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2947
2948 /* Disable the TIM Capture/Compare 2 interrupt */
2949 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2950
2951 /* Disable the Capture compare and the Input Capture channels
2952 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2953 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2954 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2955 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2956 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2957 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2958
2959 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2960 {
2961 /* Disable the Main Output */
2962 __HAL_TIM_MOE_DISABLE(htim);
2963 }
2964
2965 /* Disable the Peripheral */
2966 __HAL_TIM_DISABLE(htim);
2967
2968 /* Set the TIM channels state */
2969 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2970 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2971 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2972 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2973
2974 /* Return function status */
2975 return HAL_OK;
2976 }
2977
2978 /**
2979 * @}
2980 */
2981
2982 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2983 * @brief TIM Encoder functions
2984 *
2985 @verbatim
2986 ==============================================================================
2987 ##### TIM Encoder functions #####
2988 ==============================================================================
2989 [..]
2990 This section provides functions allowing to:
2991 (+) Initialize and configure the TIM Encoder.
2992 (+) De-initialize the TIM Encoder.
2993 (+) Start the TIM Encoder.
2994 (+) Stop the TIM Encoder.
2995 (+) Start the TIM Encoder and enable interrupt.
2996 (+) Stop the TIM Encoder and disable interrupt.
2997 (+) Start the TIM Encoder and enable DMA transfer.
2998 (+) Stop the TIM Encoder and disable DMA transfer.
2999
3000 @endverbatim
3001 * @{
3002 */
3003 /**
3004 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3005 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3006 * requires a timer reset to avoid unexpected direction
3007 * due to DIR bit readonly in center aligned mode.
3008 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3009 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3010 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3011 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3012 * @note When the timer instance is initialized in Encoder mode, timer
3013 * channels 1 and channel 2 are reserved and cannot be used for other
3014 * purpose.
3015 * @param htim TIM Encoder Interface handle
3016 * @param sConfig TIM Encoder Interface configuration structure
3017 * @retval HAL status
3018 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3019 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3020 {
3021 uint32_t tmpsmcr;
3022 uint32_t tmpccmr1;
3023 uint32_t tmpccer;
3024
3025 /* Check the TIM handle allocation */
3026 if (htim == NULL)
3027 {
3028 return HAL_ERROR;
3029 }
3030
3031 /* Check the parameters */
3032 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3033 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3034 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3035 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3036 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3037 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3038 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3039 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3040 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3041 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3042 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3043 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3044 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3045 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3046
3047 if (htim->State == HAL_TIM_STATE_RESET)
3048 {
3049 /* Allocate lock resource and initialize it */
3050 htim->Lock = HAL_UNLOCKED;
3051
3052 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3053 /* Reset interrupt callbacks to legacy weak callbacks */
3054 TIM_ResetCallback(htim);
3055
3056 if (htim->Encoder_MspInitCallback == NULL)
3057 {
3058 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3059 }
3060 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3061 htim->Encoder_MspInitCallback(htim);
3062 #else
3063 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3064 HAL_TIM_Encoder_MspInit(htim);
3065 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3066 }
3067
3068 /* Set the TIM state */
3069 htim->State = HAL_TIM_STATE_BUSY;
3070
3071 /* Reset the SMS and ECE bits */
3072 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3073
3074 /* Configure the Time base in the Encoder Mode */
3075 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3076
3077 /* Get the TIMx SMCR register value */
3078 tmpsmcr = htim->Instance->SMCR;
3079
3080 /* Get the TIMx CCMR1 register value */
3081 tmpccmr1 = htim->Instance->CCMR1;
3082
3083 /* Get the TIMx CCER register value */
3084 tmpccer = htim->Instance->CCER;
3085
3086 /* Set the encoder Mode */
3087 tmpsmcr |= sConfig->EncoderMode;
3088
3089 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3090 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3091 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3092
3093 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3094 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3095 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3096 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3097 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3098
3099 /* Set the TI1 and the TI2 Polarities */
3100 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3101 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3102 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3103
3104 /* Write to TIMx SMCR */
3105 htim->Instance->SMCR = tmpsmcr;
3106
3107 /* Write to TIMx CCMR1 */
3108 htim->Instance->CCMR1 = tmpccmr1;
3109
3110 /* Write to TIMx CCER */
3111 htim->Instance->CCER = tmpccer;
3112
3113 /* Initialize the DMA burst operation state */
3114 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3115
3116 /* Set the TIM channels state */
3117 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3118 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3119 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3120 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3121
3122 /* Initialize the TIM state*/
3123 htim->State = HAL_TIM_STATE_READY;
3124
3125 return HAL_OK;
3126 }
3127
3128
3129 /**
3130 * @brief DeInitializes the TIM Encoder interface
3131 * @param htim TIM Encoder Interface handle
3132 * @retval HAL status
3133 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3134 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3135 {
3136 /* Check the parameters */
3137 assert_param(IS_TIM_INSTANCE(htim->Instance));
3138
3139 htim->State = HAL_TIM_STATE_BUSY;
3140
3141 /* Disable the TIM Peripheral Clock */
3142 __HAL_TIM_DISABLE(htim);
3143
3144 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3145 if (htim->Encoder_MspDeInitCallback == NULL)
3146 {
3147 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3148 }
3149 /* DeInit the low level hardware */
3150 htim->Encoder_MspDeInitCallback(htim);
3151 #else
3152 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3153 HAL_TIM_Encoder_MspDeInit(htim);
3154 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3155
3156 /* Change the DMA burst operation state */
3157 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3158
3159 /* Set the TIM channels state */
3160 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3161 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3162 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3163 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3164
3165 /* Change TIM state */
3166 htim->State = HAL_TIM_STATE_RESET;
3167
3168 /* Release Lock */
3169 __HAL_UNLOCK(htim);
3170
3171 return HAL_OK;
3172 }
3173
3174 /**
3175 * @brief Initializes the TIM Encoder Interface MSP.
3176 * @param htim TIM Encoder Interface handle
3177 * @retval None
3178 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3179 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3180 {
3181 /* Prevent unused argument(s) compilation warning */
3182 UNUSED(htim);
3183
3184 /* NOTE : This function should not be modified, when the callback is needed,
3185 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3186 */
3187 }
3188
3189 /**
3190 * @brief DeInitializes TIM Encoder Interface MSP.
3191 * @param htim TIM Encoder Interface handle
3192 * @retval None
3193 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3194 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3195 {
3196 /* Prevent unused argument(s) compilation warning */
3197 UNUSED(htim);
3198
3199 /* NOTE : This function should not be modified, when the callback is needed,
3200 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3201 */
3202 }
3203
3204 /**
3205 * @brief Starts the TIM Encoder Interface.
3206 * @param htim TIM Encoder Interface handle
3207 * @param Channel TIM Channels to be enabled
3208 * This parameter can be one of the following values:
3209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3211 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3212 * @retval HAL status
3213 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3214 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3215 {
3216 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3217 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3218 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3219 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3220
3221 /* Check the parameters */
3222 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3223
3224 /* Set the TIM channel(s) state */
3225 if (Channel == TIM_CHANNEL_1)
3226 {
3227 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3228 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3229 {
3230 return HAL_ERROR;
3231 }
3232 else
3233 {
3234 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3235 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3236 }
3237 }
3238 else if (Channel == TIM_CHANNEL_2)
3239 {
3240 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3241 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3242 {
3243 return HAL_ERROR;
3244 }
3245 else
3246 {
3247 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3248 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3249 }
3250 }
3251 else
3252 {
3253 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3254 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3255 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3256 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3257 {
3258 return HAL_ERROR;
3259 }
3260 else
3261 {
3262 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3263 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3264 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3265 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3266 }
3267 }
3268
3269 /* Enable the encoder interface channels */
3270 switch (Channel)
3271 {
3272 case TIM_CHANNEL_1:
3273 {
3274 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3275 break;
3276 }
3277
3278 case TIM_CHANNEL_2:
3279 {
3280 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3281 break;
3282 }
3283
3284 default :
3285 {
3286 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3287 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3288 break;
3289 }
3290 }
3291 /* Enable the Peripheral */
3292 __HAL_TIM_ENABLE(htim);
3293
3294 /* Return function status */
3295 return HAL_OK;
3296 }
3297
3298 /**
3299 * @brief Stops the TIM Encoder Interface.
3300 * @param htim TIM Encoder Interface handle
3301 * @param Channel TIM Channels to be disabled
3302 * This parameter can be one of the following values:
3303 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3304 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3305 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3306 * @retval HAL status
3307 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3308 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3309 {
3310 /* Check the parameters */
3311 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3312
3313 /* Disable the Input Capture channels 1 and 2
3314 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3315 switch (Channel)
3316 {
3317 case TIM_CHANNEL_1:
3318 {
3319 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3320 break;
3321 }
3322
3323 case TIM_CHANNEL_2:
3324 {
3325 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3326 break;
3327 }
3328
3329 default :
3330 {
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3332 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3333 break;
3334 }
3335 }
3336
3337 /* Disable the Peripheral */
3338 __HAL_TIM_DISABLE(htim);
3339
3340 /* Set the TIM channel(s) state */
3341 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3342 {
3343 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3344 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3345 }
3346 else
3347 {
3348 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3349 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3350 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3351 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3352 }
3353
3354 /* Return function status */
3355 return HAL_OK;
3356 }
3357
3358 /**
3359 * @brief Starts the TIM Encoder Interface in interrupt mode.
3360 * @param htim TIM Encoder Interface handle
3361 * @param Channel TIM Channels to be enabled
3362 * This parameter can be one of the following values:
3363 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3364 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3365 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3366 * @retval HAL status
3367 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3368 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3369 {
3370 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3371 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3372 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3373 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3374
3375 /* Check the parameters */
3376 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3377
3378 /* Set the TIM channel(s) state */
3379 if (Channel == TIM_CHANNEL_1)
3380 {
3381 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3382 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3383 {
3384 return HAL_ERROR;
3385 }
3386 else
3387 {
3388 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3389 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3390 }
3391 }
3392 else if (Channel == TIM_CHANNEL_2)
3393 {
3394 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3395 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3396 {
3397 return HAL_ERROR;
3398 }
3399 else
3400 {
3401 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3402 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3403 }
3404 }
3405 else
3406 {
3407 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3408 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3409 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3410 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3411 {
3412 return HAL_ERROR;
3413 }
3414 else
3415 {
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3417 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3418 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3419 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3420 }
3421 }
3422
3423 /* Enable the encoder interface channels */
3424 /* Enable the capture compare Interrupts 1 and/or 2 */
3425 switch (Channel)
3426 {
3427 case TIM_CHANNEL_1:
3428 {
3429 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3430 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3431 break;
3432 }
3433
3434 case TIM_CHANNEL_2:
3435 {
3436 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3438 break;
3439 }
3440
3441 default :
3442 {
3443 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3446 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3447 break;
3448 }
3449 }
3450
3451 /* Enable the Peripheral */
3452 __HAL_TIM_ENABLE(htim);
3453
3454 /* Return function status */
3455 return HAL_OK;
3456 }
3457
3458 /**
3459 * @brief Stops the TIM Encoder Interface in interrupt mode.
3460 * @param htim TIM Encoder Interface handle
3461 * @param Channel TIM Channels to be disabled
3462 * This parameter can be one of the following values:
3463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3465 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3466 * @retval HAL status
3467 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3468 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3469 {
3470 /* Check the parameters */
3471 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3472
3473 /* Disable the Input Capture channels 1 and 2
3474 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3475 if (Channel == TIM_CHANNEL_1)
3476 {
3477 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3478
3479 /* Disable the capture compare Interrupts 1 */
3480 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3481 }
3482 else if (Channel == TIM_CHANNEL_2)
3483 {
3484 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3485
3486 /* Disable the capture compare Interrupts 2 */
3487 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3488 }
3489 else
3490 {
3491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3493
3494 /* Disable the capture compare Interrupts 1 and 2 */
3495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3496 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3497 }
3498
3499 /* Disable the Peripheral */
3500 __HAL_TIM_DISABLE(htim);
3501
3502 /* Set the TIM channel(s) state */
3503 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3504 {
3505 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3506 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3507 }
3508 else
3509 {
3510 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3511 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3512 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3513 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3514 }
3515
3516 /* Return function status */
3517 return HAL_OK;
3518 }
3519
3520 /**
3521 * @brief Starts the TIM Encoder Interface in DMA mode.
3522 * @param htim TIM Encoder Interface handle
3523 * @param Channel TIM Channels to be enabled
3524 * This parameter can be one of the following values:
3525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3527 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3528 * @param pData1 The destination Buffer address for IC1.
3529 * @param pData2 The destination Buffer address for IC2.
3530 * @param Length The length of data to be transferred from TIM peripheral to memory.
3531 * @retval HAL status
3532 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3533 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3534 uint32_t *pData2, uint16_t Length)
3535 {
3536 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3537 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3538 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3539 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3540
3541 /* Check the parameters */
3542 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3543
3544 /* Set the TIM channel(s) state */
3545 if (Channel == TIM_CHANNEL_1)
3546 {
3547 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3548 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3549 {
3550 return HAL_BUSY;
3551 }
3552 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3553 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3554 {
3555 if ((pData1 == NULL) || (Length == 0U))
3556 {
3557 return HAL_ERROR;
3558 }
3559 else
3560 {
3561 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3562 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3563 }
3564 }
3565 else
3566 {
3567 return HAL_ERROR;
3568 }
3569 }
3570 else if (Channel == TIM_CHANNEL_2)
3571 {
3572 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3573 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3574 {
3575 return HAL_BUSY;
3576 }
3577 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3578 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3579 {
3580 if ((pData2 == NULL) || (Length == 0U))
3581 {
3582 return HAL_ERROR;
3583 }
3584 else
3585 {
3586 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3587 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3588 }
3589 }
3590 else
3591 {
3592 return HAL_ERROR;
3593 }
3594 }
3595 else
3596 {
3597 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3598 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3599 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3600 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3601 {
3602 return HAL_BUSY;
3603 }
3604 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3605 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3606 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3607 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3608 {
3609 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3610 {
3611 return HAL_ERROR;
3612 }
3613 else
3614 {
3615 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3616 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3617 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3618 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3619 }
3620 }
3621 else
3622 {
3623 return HAL_ERROR;
3624 }
3625 }
3626
3627 switch (Channel)
3628 {
3629 case TIM_CHANNEL_1:
3630 {
3631 /* Set the DMA capture callbacks */
3632 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3633 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3634
3635 /* Set the DMA error callback */
3636 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3637
3638 /* Enable the DMA stream */
3639 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3640 Length) != HAL_OK)
3641 {
3642 /* Return error status */
3643 return HAL_ERROR;
3644 }
3645 /* Enable the TIM Input Capture DMA request */
3646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3647
3648 /* Enable the Capture compare channel */
3649 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3650
3651 /* Enable the Peripheral */
3652 __HAL_TIM_ENABLE(htim);
3653
3654 break;
3655 }
3656
3657 case TIM_CHANNEL_2:
3658 {
3659 /* Set the DMA capture callbacks */
3660 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3661 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3662
3663 /* Set the DMA error callback */
3664 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3665 /* Enable the DMA stream */
3666 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3667 Length) != HAL_OK)
3668 {
3669 /* Return error status */
3670 return HAL_ERROR;
3671 }
3672 /* Enable the TIM Input Capture DMA request */
3673 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3674
3675 /* Enable the Capture compare channel */
3676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3677
3678 /* Enable the Peripheral */
3679 __HAL_TIM_ENABLE(htim);
3680
3681 break;
3682 }
3683
3684 default:
3685 {
3686 /* Set the DMA capture callbacks */
3687 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3688 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3689
3690 /* Set the DMA error callback */
3691 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3692
3693 /* Enable the DMA stream */
3694 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3695 Length) != HAL_OK)
3696 {
3697 /* Return error status */
3698 return HAL_ERROR;
3699 }
3700
3701 /* Set the DMA capture callbacks */
3702 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3703 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3704
3705 /* Set the DMA error callback */
3706 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3707
3708 /* Enable the DMA stream */
3709 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3710 Length) != HAL_OK)
3711 {
3712 /* Return error status */
3713 return HAL_ERROR;
3714 }
3715
3716 /* Enable the TIM Input Capture DMA request */
3717 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3718 /* Enable the TIM Input Capture DMA request */
3719 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3720
3721 /* Enable the Capture compare channel */
3722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3723 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3724
3725 /* Enable the Peripheral */
3726 __HAL_TIM_ENABLE(htim);
3727
3728 break;
3729 }
3730 }
3731
3732 /* Return function status */
3733 return HAL_OK;
3734 }
3735
3736 /**
3737 * @brief Stops the TIM Encoder Interface in DMA mode.
3738 * @param htim TIM Encoder Interface handle
3739 * @param Channel TIM Channels to be enabled
3740 * This parameter can be one of the following values:
3741 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3742 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3743 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3744 * @retval HAL status
3745 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3746 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3747 {
3748 /* Check the parameters */
3749 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3750
3751 /* Disable the Input Capture channels 1 and 2
3752 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3753 if (Channel == TIM_CHANNEL_1)
3754 {
3755 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3756
3757 /* Disable the capture compare DMA Request 1 */
3758 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3759 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3760 }
3761 else if (Channel == TIM_CHANNEL_2)
3762 {
3763 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3764
3765 /* Disable the capture compare DMA Request 2 */
3766 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3767 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3768 }
3769 else
3770 {
3771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3772 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3773
3774 /* Disable the capture compare DMA Request 1 and 2 */
3775 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3776 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3777 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3779 }
3780
3781 /* Disable the Peripheral */
3782 __HAL_TIM_DISABLE(htim);
3783
3784 /* Set the TIM channel(s) state */
3785 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3786 {
3787 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3788 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3789 }
3790 else
3791 {
3792 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3793 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3794 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3795 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3796 }
3797
3798 /* Return function status */
3799 return HAL_OK;
3800 }
3801
3802 /**
3803 * @}
3804 */
3805 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3806 * @brief TIM IRQ handler management
3807 *
3808 @verbatim
3809 ==============================================================================
3810 ##### IRQ handler management #####
3811 ==============================================================================
3812 [..]
3813 This section provides Timer IRQ handler function.
3814
3815 @endverbatim
3816 * @{
3817 */
3818 /**
3819 * @brief This function handles TIM interrupts requests.
3820 * @param htim TIM handle
3821 * @retval None
3822 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3823 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3824 {
3825 /* Capture compare 1 event */
3826 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3827 {
3828 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3829 {
3830 {
3831 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3832 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3833
3834 /* Input capture event */
3835 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3836 {
3837 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3838 htim->IC_CaptureCallback(htim);
3839 #else
3840 HAL_TIM_IC_CaptureCallback(htim);
3841 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3842 }
3843 /* Output compare event */
3844 else
3845 {
3846 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3847 htim->OC_DelayElapsedCallback(htim);
3848 htim->PWM_PulseFinishedCallback(htim);
3849 #else
3850 HAL_TIM_OC_DelayElapsedCallback(htim);
3851 HAL_TIM_PWM_PulseFinishedCallback(htim);
3852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3853 }
3854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3855 }
3856 }
3857 }
3858 /* Capture compare 2 event */
3859 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3860 {
3861 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3862 {
3863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3865 /* Input capture event */
3866 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3867 {
3868 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3869 htim->IC_CaptureCallback(htim);
3870 #else
3871 HAL_TIM_IC_CaptureCallback(htim);
3872 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3873 }
3874 /* Output compare event */
3875 else
3876 {
3877 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3878 htim->OC_DelayElapsedCallback(htim);
3879 htim->PWM_PulseFinishedCallback(htim);
3880 #else
3881 HAL_TIM_OC_DelayElapsedCallback(htim);
3882 HAL_TIM_PWM_PulseFinishedCallback(htim);
3883 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3884 }
3885 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3886 }
3887 }
3888 /* Capture compare 3 event */
3889 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3890 {
3891 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3892 {
3893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3894 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3895 /* Input capture event */
3896 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3897 {
3898 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3899 htim->IC_CaptureCallback(htim);
3900 #else
3901 HAL_TIM_IC_CaptureCallback(htim);
3902 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3903 }
3904 /* Output compare event */
3905 else
3906 {
3907 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3908 htim->OC_DelayElapsedCallback(htim);
3909 htim->PWM_PulseFinishedCallback(htim);
3910 #else
3911 HAL_TIM_OC_DelayElapsedCallback(htim);
3912 HAL_TIM_PWM_PulseFinishedCallback(htim);
3913 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3914 }
3915 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3916 }
3917 }
3918 /* Capture compare 4 event */
3919 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3920 {
3921 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3922 {
3923 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3924 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3925 /* Input capture event */
3926 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3927 {
3928 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3929 htim->IC_CaptureCallback(htim);
3930 #else
3931 HAL_TIM_IC_CaptureCallback(htim);
3932 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3933 }
3934 /* Output compare event */
3935 else
3936 {
3937 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3938 htim->OC_DelayElapsedCallback(htim);
3939 htim->PWM_PulseFinishedCallback(htim);
3940 #else
3941 HAL_TIM_OC_DelayElapsedCallback(htim);
3942 HAL_TIM_PWM_PulseFinishedCallback(htim);
3943 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3944 }
3945 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3946 }
3947 }
3948 /* TIM Update event */
3949 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3950 {
3951 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3952 {
3953 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3955 htim->PeriodElapsedCallback(htim);
3956 #else
3957 HAL_TIM_PeriodElapsedCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959 }
3960 }
3961 /* TIM Break input event */
3962 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3963 {
3964 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3965 {
3966 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3967 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3968 htim->BreakCallback(htim);
3969 #else
3970 HAL_TIMEx_BreakCallback(htim);
3971 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3972 }
3973 }
3974 /* TIM Trigger detection event */
3975 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3976 {
3977 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3978 {
3979 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3981 htim->TriggerCallback(htim);
3982 #else
3983 HAL_TIM_TriggerCallback(htim);
3984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3985 }
3986 }
3987 /* TIM commutation event */
3988 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3989 {
3990 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3991 {
3992 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3993 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3994 htim->CommutationCallback(htim);
3995 #else
3996 HAL_TIMEx_CommutCallback(htim);
3997 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3998 }
3999 }
4000 }
4001
4002 /**
4003 * @}
4004 */
4005
4006 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4007 * @brief TIM Peripheral Control functions
4008 *
4009 @verbatim
4010 ==============================================================================
4011 ##### Peripheral Control functions #####
4012 ==============================================================================
4013 [..]
4014 This section provides functions allowing to:
4015 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4016 (+) Configure External Clock source.
4017 (+) Configure Complementary channels, break features and dead time.
4018 (+) Configure Master and the Slave synchronization.
4019 (+) Configure the DMA Burst Mode.
4020
4021 @endverbatim
4022 * @{
4023 */
4024
4025 /**
4026 * @brief Initializes the TIM Output Compare Channels according to the specified
4027 * parameters in the TIM_OC_InitTypeDef.
4028 * @param htim TIM Output Compare handle
4029 * @param sConfig TIM Output Compare configuration structure
4030 * @param Channel TIM Channels to configure
4031 * This parameter can be one of the following values:
4032 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4033 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4034 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4035 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4036 * @retval HAL status
4037 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4038 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4039 const TIM_OC_InitTypeDef *sConfig,
4040 uint32_t Channel)
4041 {
4042 HAL_StatusTypeDef status = HAL_OK;
4043
4044 /* Check the parameters */
4045 assert_param(IS_TIM_CHANNELS(Channel));
4046 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4047 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4048
4049 /* Process Locked */
4050 __HAL_LOCK(htim);
4051
4052 switch (Channel)
4053 {
4054 case TIM_CHANNEL_1:
4055 {
4056 /* Check the parameters */
4057 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4058
4059 /* Configure the TIM Channel 1 in Output Compare */
4060 TIM_OC1_SetConfig(htim->Instance, sConfig);
4061 break;
4062 }
4063
4064 case TIM_CHANNEL_2:
4065 {
4066 /* Check the parameters */
4067 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4068
4069 /* Configure the TIM Channel 2 in Output Compare */
4070 TIM_OC2_SetConfig(htim->Instance, sConfig);
4071 break;
4072 }
4073
4074 case TIM_CHANNEL_3:
4075 {
4076 /* Check the parameters */
4077 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4078
4079 /* Configure the TIM Channel 3 in Output Compare */
4080 TIM_OC3_SetConfig(htim->Instance, sConfig);
4081 break;
4082 }
4083
4084 case TIM_CHANNEL_4:
4085 {
4086 /* Check the parameters */
4087 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4088
4089 /* Configure the TIM Channel 4 in Output Compare */
4090 TIM_OC4_SetConfig(htim->Instance, sConfig);
4091 break;
4092 }
4093
4094 default:
4095 status = HAL_ERROR;
4096 break;
4097 }
4098
4099 __HAL_UNLOCK(htim);
4100
4101 return status;
4102 }
4103
4104 /**
4105 * @brief Initializes the TIM Input Capture Channels according to the specified
4106 * parameters in the TIM_IC_InitTypeDef.
4107 * @param htim TIM IC handle
4108 * @param sConfig TIM Input Capture configuration structure
4109 * @param Channel TIM Channel to configure
4110 * This parameter can be one of the following values:
4111 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4112 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4113 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4114 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4115 * @retval HAL status
4116 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4117 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4118 {
4119 HAL_StatusTypeDef status = HAL_OK;
4120
4121 /* Check the parameters */
4122 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4123 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4124 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4125 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4126 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4127
4128 /* Process Locked */
4129 __HAL_LOCK(htim);
4130
4131 if (Channel == TIM_CHANNEL_1)
4132 {
4133 /* TI1 Configuration */
4134 TIM_TI1_SetConfig(htim->Instance,
4135 sConfig->ICPolarity,
4136 sConfig->ICSelection,
4137 sConfig->ICFilter);
4138
4139 /* Reset the IC1PSC Bits */
4140 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4141
4142 /* Set the IC1PSC value */
4143 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4144 }
4145 else if (Channel == TIM_CHANNEL_2)
4146 {
4147 /* TI2 Configuration */
4148 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4149
4150 TIM_TI2_SetConfig(htim->Instance,
4151 sConfig->ICPolarity,
4152 sConfig->ICSelection,
4153 sConfig->ICFilter);
4154
4155 /* Reset the IC2PSC Bits */
4156 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4157
4158 /* Set the IC2PSC value */
4159 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4160 }
4161 else if (Channel == TIM_CHANNEL_3)
4162 {
4163 /* TI3 Configuration */
4164 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4165
4166 TIM_TI3_SetConfig(htim->Instance,
4167 sConfig->ICPolarity,
4168 sConfig->ICSelection,
4169 sConfig->ICFilter);
4170
4171 /* Reset the IC3PSC Bits */
4172 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4173
4174 /* Set the IC3PSC value */
4175 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4176 }
4177 else if (Channel == TIM_CHANNEL_4)
4178 {
4179 /* TI4 Configuration */
4180 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4181
4182 TIM_TI4_SetConfig(htim->Instance,
4183 sConfig->ICPolarity,
4184 sConfig->ICSelection,
4185 sConfig->ICFilter);
4186
4187 /* Reset the IC4PSC Bits */
4188 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4189
4190 /* Set the IC4PSC value */
4191 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4192 }
4193 else
4194 {
4195 status = HAL_ERROR;
4196 }
4197
4198 __HAL_UNLOCK(htim);
4199
4200 return status;
4201 }
4202
4203 /**
4204 * @brief Initializes the TIM PWM channels according to the specified
4205 * parameters in the TIM_OC_InitTypeDef.
4206 * @param htim TIM PWM handle
4207 * @param sConfig TIM PWM configuration structure
4208 * @param Channel TIM Channels to be configured
4209 * This parameter can be one of the following values:
4210 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4211 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4212 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4213 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4214 * @retval HAL status
4215 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4216 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4217 const TIM_OC_InitTypeDef *sConfig,
4218 uint32_t Channel)
4219 {
4220 HAL_StatusTypeDef status = HAL_OK;
4221
4222 /* Check the parameters */
4223 assert_param(IS_TIM_CHANNELS(Channel));
4224 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4225 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4226 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4227
4228 /* Process Locked */
4229 __HAL_LOCK(htim);
4230
4231 switch (Channel)
4232 {
4233 case TIM_CHANNEL_1:
4234 {
4235 /* Check the parameters */
4236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4237
4238 /* Configure the Channel 1 in PWM mode */
4239 TIM_OC1_SetConfig(htim->Instance, sConfig);
4240
4241 /* Set the Preload enable bit for channel1 */
4242 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4243
4244 /* Configure the Output Fast mode */
4245 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4246 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4247 break;
4248 }
4249
4250 case TIM_CHANNEL_2:
4251 {
4252 /* Check the parameters */
4253 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4254
4255 /* Configure the Channel 2 in PWM mode */
4256 TIM_OC2_SetConfig(htim->Instance, sConfig);
4257
4258 /* Set the Preload enable bit for channel2 */
4259 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4260
4261 /* Configure the Output Fast mode */
4262 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4263 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4264 break;
4265 }
4266
4267 case TIM_CHANNEL_3:
4268 {
4269 /* Check the parameters */
4270 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4271
4272 /* Configure the Channel 3 in PWM mode */
4273 TIM_OC3_SetConfig(htim->Instance, sConfig);
4274
4275 /* Set the Preload enable bit for channel3 */
4276 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4277
4278 /* Configure the Output Fast mode */
4279 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4280 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4281 break;
4282 }
4283
4284 case TIM_CHANNEL_4:
4285 {
4286 /* Check the parameters */
4287 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4288
4289 /* Configure the Channel 4 in PWM mode */
4290 TIM_OC4_SetConfig(htim->Instance, sConfig);
4291
4292 /* Set the Preload enable bit for channel4 */
4293 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4294
4295 /* Configure the Output Fast mode */
4296 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4297 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4298 break;
4299 }
4300
4301 default:
4302 status = HAL_ERROR;
4303 break;
4304 }
4305
4306 __HAL_UNLOCK(htim);
4307
4308 return status;
4309 }
4310
4311 /**
4312 * @brief Initializes the TIM One Pulse Channels according to the specified
4313 * parameters in the TIM_OnePulse_InitTypeDef.
4314 * @param htim TIM One Pulse handle
4315 * @param sConfig TIM One Pulse configuration structure
4316 * @param OutputChannel TIM output channel to configure
4317 * This parameter can be one of the following values:
4318 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4319 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4320 * @param InputChannel TIM input Channel to configure
4321 * This parameter can be one of the following values:
4322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4324 * @note To output a waveform with a minimum delay user can enable the fast
4325 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4326 * output is forced in response to the edge detection on TIx input,
4327 * without taking in account the comparison.
4328 * @retval HAL status
4329 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4330 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4331 uint32_t OutputChannel, uint32_t InputChannel)
4332 {
4333 HAL_StatusTypeDef status = HAL_OK;
4334 TIM_OC_InitTypeDef temp1;
4335
4336 /* Check the parameters */
4337 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4338 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4339
4340 if (OutputChannel != InputChannel)
4341 {
4342 /* Process Locked */
4343 __HAL_LOCK(htim);
4344
4345 htim->State = HAL_TIM_STATE_BUSY;
4346
4347 /* Extract the Output compare configuration from sConfig structure */
4348 temp1.OCMode = sConfig->OCMode;
4349 temp1.Pulse = sConfig->Pulse;
4350 temp1.OCPolarity = sConfig->OCPolarity;
4351 temp1.OCNPolarity = sConfig->OCNPolarity;
4352 temp1.OCIdleState = sConfig->OCIdleState;
4353 temp1.OCNIdleState = sConfig->OCNIdleState;
4354
4355 switch (OutputChannel)
4356 {
4357 case TIM_CHANNEL_1:
4358 {
4359 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4360
4361 TIM_OC1_SetConfig(htim->Instance, &temp1);
4362 break;
4363 }
4364
4365 case TIM_CHANNEL_2:
4366 {
4367 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4368
4369 TIM_OC2_SetConfig(htim->Instance, &temp1);
4370 break;
4371 }
4372
4373 default:
4374 status = HAL_ERROR;
4375 break;
4376 }
4377
4378 if (status == HAL_OK)
4379 {
4380 switch (InputChannel)
4381 {
4382 case TIM_CHANNEL_1:
4383 {
4384 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4385
4386 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4387 sConfig->ICSelection, sConfig->ICFilter);
4388
4389 /* Reset the IC1PSC Bits */
4390 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4391
4392 /* Select the Trigger source */
4393 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4394 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4395
4396 /* Select the Slave Mode */
4397 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4398 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4399 break;
4400 }
4401
4402 case TIM_CHANNEL_2:
4403 {
4404 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4405
4406 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4407 sConfig->ICSelection, sConfig->ICFilter);
4408
4409 /* Reset the IC2PSC Bits */
4410 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4411
4412 /* Select the Trigger source */
4413 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4414 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4415
4416 /* Select the Slave Mode */
4417 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4418 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4419 break;
4420 }
4421
4422 default:
4423 status = HAL_ERROR;
4424 break;
4425 }
4426 }
4427
4428 htim->State = HAL_TIM_STATE_READY;
4429
4430 __HAL_UNLOCK(htim);
4431
4432 return status;
4433 }
4434 else
4435 {
4436 return HAL_ERROR;
4437 }
4438 }
4439
4440 /**
4441 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4442 * @param htim TIM handle
4443 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4444 * This parameter can be one of the following values:
4445 * @arg TIM_DMABASE_CR1
4446 * @arg TIM_DMABASE_CR2
4447 * @arg TIM_DMABASE_SMCR
4448 * @arg TIM_DMABASE_DIER
4449 * @arg TIM_DMABASE_SR
4450 * @arg TIM_DMABASE_EGR
4451 * @arg TIM_DMABASE_CCMR1
4452 * @arg TIM_DMABASE_CCMR2
4453 * @arg TIM_DMABASE_CCER
4454 * @arg TIM_DMABASE_CNT
4455 * @arg TIM_DMABASE_PSC
4456 * @arg TIM_DMABASE_ARR
4457 * @arg TIM_DMABASE_RCR
4458 * @arg TIM_DMABASE_CCR1
4459 * @arg TIM_DMABASE_CCR2
4460 * @arg TIM_DMABASE_CCR3
4461 * @arg TIM_DMABASE_CCR4
4462 * @arg TIM_DMABASE_BDTR
4463 * @param BurstRequestSrc TIM DMA Request sources
4464 * This parameter can be one of the following values:
4465 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4466 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4467 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4468 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4469 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4470 * @arg TIM_DMA_COM: TIM Commutation DMA source
4471 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4472 * @param BurstBuffer The Buffer address.
4473 * @param BurstLength DMA Burst length. This parameter can be one value
4474 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4475 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4476 * @retval HAL status
4477 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4478 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4479 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4480 {
4481 HAL_StatusTypeDef status;
4482
4483 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4484 ((BurstLength) >> 8U) + 1U);
4485
4486
4487
4488 return status;
4489 }
4490
4491 /**
4492 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4493 * @param htim TIM handle
4494 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4495 * This parameter can be one of the following values:
4496 * @arg TIM_DMABASE_CR1
4497 * @arg TIM_DMABASE_CR2
4498 * @arg TIM_DMABASE_SMCR
4499 * @arg TIM_DMABASE_DIER
4500 * @arg TIM_DMABASE_SR
4501 * @arg TIM_DMABASE_EGR
4502 * @arg TIM_DMABASE_CCMR1
4503 * @arg TIM_DMABASE_CCMR2
4504 * @arg TIM_DMABASE_CCER
4505 * @arg TIM_DMABASE_CNT
4506 * @arg TIM_DMABASE_PSC
4507 * @arg TIM_DMABASE_ARR
4508 * @arg TIM_DMABASE_RCR
4509 * @arg TIM_DMABASE_CCR1
4510 * @arg TIM_DMABASE_CCR2
4511 * @arg TIM_DMABASE_CCR3
4512 * @arg TIM_DMABASE_CCR4
4513 * @arg TIM_DMABASE_BDTR
4514 * @param BurstRequestSrc TIM DMA Request sources
4515 * This parameter can be one of the following values:
4516 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4517 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4518 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4519 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4520 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4521 * @arg TIM_DMA_COM: TIM Commutation DMA source
4522 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4523 * @param BurstBuffer The Buffer address.
4524 * @param BurstLength DMA Burst length. This parameter can be one value
4525 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4526 * @param DataLength Data length. This parameter can be one value
4527 * between 1 and 0xFFFF.
4528 * @retval HAL status
4529 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4530 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4531 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4532 uint32_t BurstLength, uint32_t DataLength)
4533 {
4534 HAL_StatusTypeDef status = HAL_OK;
4535
4536 /* Check the parameters */
4537 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4538 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4539 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4540 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4541 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4542
4543 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4544 {
4545 return HAL_BUSY;
4546 }
4547 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4548 {
4549 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4550 {
4551 return HAL_ERROR;
4552 }
4553 else
4554 {
4555 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4556 }
4557 }
4558 else
4559 {
4560 /* nothing to do */
4561 }
4562
4563 switch (BurstRequestSrc)
4564 {
4565 case TIM_DMA_UPDATE:
4566 {
4567 /* Set the DMA Period elapsed callbacks */
4568 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4569 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4570
4571 /* Set the DMA error callback */
4572 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4573
4574 /* Enable the DMA stream */
4575 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4576 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4577 {
4578 /* Return error status */
4579 return HAL_ERROR;
4580 }
4581 break;
4582 }
4583 case TIM_DMA_CC1:
4584 {
4585 /* Set the DMA compare callbacks */
4586 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4587 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4588
4589 /* Set the DMA error callback */
4590 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4591
4592 /* Enable the DMA stream */
4593 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4594 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4595 {
4596 /* Return error status */
4597 return HAL_ERROR;
4598 }
4599 break;
4600 }
4601 case TIM_DMA_CC2:
4602 {
4603 /* Set the DMA compare callbacks */
4604 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4605 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4606
4607 /* Set the DMA error callback */
4608 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4609
4610 /* Enable the DMA stream */
4611 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4612 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4613 {
4614 /* Return error status */
4615 return HAL_ERROR;
4616 }
4617 break;
4618 }
4619 case TIM_DMA_CC3:
4620 {
4621 /* Set the DMA compare callbacks */
4622 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4623 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4624
4625 /* Set the DMA error callback */
4626 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4627
4628 /* Enable the DMA stream */
4629 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4630 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4631 {
4632 /* Return error status */
4633 return HAL_ERROR;
4634 }
4635 break;
4636 }
4637 case TIM_DMA_CC4:
4638 {
4639 /* Set the DMA compare callbacks */
4640 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4641 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4642
4643 /* Set the DMA error callback */
4644 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4645
4646 /* Enable the DMA stream */
4647 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4648 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4649 {
4650 /* Return error status */
4651 return HAL_ERROR;
4652 }
4653 break;
4654 }
4655 case TIM_DMA_COM:
4656 {
4657 /* Set the DMA commutation callbacks */
4658 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4659 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4660
4661 /* Set the DMA error callback */
4662 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4663
4664 /* Enable the DMA stream */
4665 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4666 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4667 {
4668 /* Return error status */
4669 return HAL_ERROR;
4670 }
4671 break;
4672 }
4673 case TIM_DMA_TRIGGER:
4674 {
4675 /* Set the DMA trigger callbacks */
4676 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4677 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4678
4679 /* Set the DMA error callback */
4680 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4681
4682 /* Enable the DMA stream */
4683 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4684 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4685 {
4686 /* Return error status */
4687 return HAL_ERROR;
4688 }
4689 break;
4690 }
4691 default:
4692 status = HAL_ERROR;
4693 break;
4694 }
4695
4696 if (status == HAL_OK)
4697 {
4698 /* Configure the DMA Burst Mode */
4699 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4700 /* Enable the TIM DMA Request */
4701 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4702 }
4703
4704 /* Return function status */
4705 return status;
4706 }
4707
4708 /**
4709 * @brief Stops the TIM DMA Burst mode
4710 * @param htim TIM handle
4711 * @param BurstRequestSrc TIM DMA Request sources to disable
4712 * @retval HAL status
4713 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4714 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4715 {
4716 HAL_StatusTypeDef status = HAL_OK;
4717
4718 /* Check the parameters */
4719 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4720
4721 /* Abort the DMA transfer (at least disable the DMA stream) */
4722 switch (BurstRequestSrc)
4723 {
4724 case TIM_DMA_UPDATE:
4725 {
4726 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4727 break;
4728 }
4729 case TIM_DMA_CC1:
4730 {
4731 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4732 break;
4733 }
4734 case TIM_DMA_CC2:
4735 {
4736 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4737 break;
4738 }
4739 case TIM_DMA_CC3:
4740 {
4741 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4742 break;
4743 }
4744 case TIM_DMA_CC4:
4745 {
4746 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4747 break;
4748 }
4749 case TIM_DMA_COM:
4750 {
4751 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4752 break;
4753 }
4754 case TIM_DMA_TRIGGER:
4755 {
4756 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4757 break;
4758 }
4759 default:
4760 status = HAL_ERROR;
4761 break;
4762 }
4763
4764 if (status == HAL_OK)
4765 {
4766 /* Disable the TIM Update DMA request */
4767 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4768
4769 /* Change the DMA burst operation state */
4770 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4771 }
4772
4773 /* Return function status */
4774 return status;
4775 }
4776
4777 /**
4778 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4779 * @param htim TIM handle
4780 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4781 * This parameter can be one of the following values:
4782 * @arg TIM_DMABASE_CR1
4783 * @arg TIM_DMABASE_CR2
4784 * @arg TIM_DMABASE_SMCR
4785 * @arg TIM_DMABASE_DIER
4786 * @arg TIM_DMABASE_SR
4787 * @arg TIM_DMABASE_EGR
4788 * @arg TIM_DMABASE_CCMR1
4789 * @arg TIM_DMABASE_CCMR2
4790 * @arg TIM_DMABASE_CCER
4791 * @arg TIM_DMABASE_CNT
4792 * @arg TIM_DMABASE_PSC
4793 * @arg TIM_DMABASE_ARR
4794 * @arg TIM_DMABASE_RCR
4795 * @arg TIM_DMABASE_CCR1
4796 * @arg TIM_DMABASE_CCR2
4797 * @arg TIM_DMABASE_CCR3
4798 * @arg TIM_DMABASE_CCR4
4799 * @arg TIM_DMABASE_BDTR
4800 * @param BurstRequestSrc TIM DMA Request sources
4801 * This parameter can be one of the following values:
4802 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4803 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4804 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4805 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4806 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4807 * @arg TIM_DMA_COM: TIM Commutation DMA source
4808 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4809 * @param BurstBuffer The Buffer address.
4810 * @param BurstLength DMA Burst length. This parameter can be one value
4811 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4812 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4813 * @retval HAL status
4814 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4815 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4816 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4817 {
4818 HAL_StatusTypeDef status;
4819
4820 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4821 ((BurstLength) >> 8U) + 1U);
4822
4823
4824 return status;
4825 }
4826
4827 /**
4828 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4829 * @param htim TIM handle
4830 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4831 * This parameter can be one of the following values:
4832 * @arg TIM_DMABASE_CR1
4833 * @arg TIM_DMABASE_CR2
4834 * @arg TIM_DMABASE_SMCR
4835 * @arg TIM_DMABASE_DIER
4836 * @arg TIM_DMABASE_SR
4837 * @arg TIM_DMABASE_EGR
4838 * @arg TIM_DMABASE_CCMR1
4839 * @arg TIM_DMABASE_CCMR2
4840 * @arg TIM_DMABASE_CCER
4841 * @arg TIM_DMABASE_CNT
4842 * @arg TIM_DMABASE_PSC
4843 * @arg TIM_DMABASE_ARR
4844 * @arg TIM_DMABASE_RCR
4845 * @arg TIM_DMABASE_CCR1
4846 * @arg TIM_DMABASE_CCR2
4847 * @arg TIM_DMABASE_CCR3
4848 * @arg TIM_DMABASE_CCR4
4849 * @arg TIM_DMABASE_BDTR
4850 * @param BurstRequestSrc TIM DMA Request sources
4851 * This parameter can be one of the following values:
4852 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4853 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4854 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4855 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4856 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4857 * @arg TIM_DMA_COM: TIM Commutation DMA source
4858 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4859 * @param BurstBuffer The Buffer address.
4860 * @param BurstLength DMA Burst length. This parameter can be one value
4861 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4862 * @param DataLength Data length. This parameter can be one value
4863 * between 1 and 0xFFFF.
4864 * @retval HAL status
4865 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4866 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4867 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4868 uint32_t BurstLength, uint32_t DataLength)
4869 {
4870 HAL_StatusTypeDef status = HAL_OK;
4871
4872 /* Check the parameters */
4873 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4874 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4875 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4876 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4877 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4878
4879 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4880 {
4881 return HAL_BUSY;
4882 }
4883 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4884 {
4885 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4886 {
4887 return HAL_ERROR;
4888 }
4889 else
4890 {
4891 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4892 }
4893 }
4894 else
4895 {
4896 /* nothing to do */
4897 }
4898 switch (BurstRequestSrc)
4899 {
4900 case TIM_DMA_UPDATE:
4901 {
4902 /* Set the DMA Period elapsed callbacks */
4903 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4904 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4905
4906 /* Set the DMA error callback */
4907 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4908
4909 /* Enable the DMA stream */
4910 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4911 DataLength) != HAL_OK)
4912 {
4913 /* Return error status */
4914 return HAL_ERROR;
4915 }
4916 break;
4917 }
4918 case TIM_DMA_CC1:
4919 {
4920 /* Set the DMA capture callbacks */
4921 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4922 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4923
4924 /* Set the DMA error callback */
4925 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4926
4927 /* Enable the DMA stream */
4928 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4929 DataLength) != HAL_OK)
4930 {
4931 /* Return error status */
4932 return HAL_ERROR;
4933 }
4934 break;
4935 }
4936 case TIM_DMA_CC2:
4937 {
4938 /* Set the DMA capture callbacks */
4939 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4940 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4941
4942 /* Set the DMA error callback */
4943 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4944
4945 /* Enable the DMA stream */
4946 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4947 DataLength) != HAL_OK)
4948 {
4949 /* Return error status */
4950 return HAL_ERROR;
4951 }
4952 break;
4953 }
4954 case TIM_DMA_CC3:
4955 {
4956 /* Set the DMA capture callbacks */
4957 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4958 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4959
4960 /* Set the DMA error callback */
4961 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4962
4963 /* Enable the DMA stream */
4964 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4965 DataLength) != HAL_OK)
4966 {
4967 /* Return error status */
4968 return HAL_ERROR;
4969 }
4970 break;
4971 }
4972 case TIM_DMA_CC4:
4973 {
4974 /* Set the DMA capture callbacks */
4975 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4976 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4977
4978 /* Set the DMA error callback */
4979 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4980
4981 /* Enable the DMA stream */
4982 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4983 DataLength) != HAL_OK)
4984 {
4985 /* Return error status */
4986 return HAL_ERROR;
4987 }
4988 break;
4989 }
4990 case TIM_DMA_COM:
4991 {
4992 /* Set the DMA commutation callbacks */
4993 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4994 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4995
4996 /* Set the DMA error callback */
4997 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4998
4999 /* Enable the DMA stream */
5000 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5001 DataLength) != HAL_OK)
5002 {
5003 /* Return error status */
5004 return HAL_ERROR;
5005 }
5006 break;
5007 }
5008 case TIM_DMA_TRIGGER:
5009 {
5010 /* Set the DMA trigger callbacks */
5011 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5012 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5013
5014 /* Set the DMA error callback */
5015 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5016
5017 /* Enable the DMA stream */
5018 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5019 DataLength) != HAL_OK)
5020 {
5021 /* Return error status */
5022 return HAL_ERROR;
5023 }
5024 break;
5025 }
5026 default:
5027 status = HAL_ERROR;
5028 break;
5029 }
5030
5031 if (status == HAL_OK)
5032 {
5033 /* Configure the DMA Burst Mode */
5034 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5035
5036 /* Enable the TIM DMA Request */
5037 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5038 }
5039
5040 /* Return function status */
5041 return status;
5042 }
5043
5044 /**
5045 * @brief Stop the DMA burst reading
5046 * @param htim TIM handle
5047 * @param BurstRequestSrc TIM DMA Request sources to disable.
5048 * @retval HAL status
5049 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5050 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5051 {
5052 HAL_StatusTypeDef status = HAL_OK;
5053
5054 /* Check the parameters */
5055 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5056
5057 /* Abort the DMA transfer (at least disable the DMA stream) */
5058 switch (BurstRequestSrc)
5059 {
5060 case TIM_DMA_UPDATE:
5061 {
5062 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5063 break;
5064 }
5065 case TIM_DMA_CC1:
5066 {
5067 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5068 break;
5069 }
5070 case TIM_DMA_CC2:
5071 {
5072 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5073 break;
5074 }
5075 case TIM_DMA_CC3:
5076 {
5077 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5078 break;
5079 }
5080 case TIM_DMA_CC4:
5081 {
5082 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5083 break;
5084 }
5085 case TIM_DMA_COM:
5086 {
5087 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5088 break;
5089 }
5090 case TIM_DMA_TRIGGER:
5091 {
5092 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5093 break;
5094 }
5095 default:
5096 status = HAL_ERROR;
5097 break;
5098 }
5099
5100 if (status == HAL_OK)
5101 {
5102 /* Disable the TIM Update DMA request */
5103 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5104
5105 /* Change the DMA burst operation state */
5106 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5107 }
5108
5109 /* Return function status */
5110 return status;
5111 }
5112
5113 /**
5114 * @brief Generate a software event
5115 * @param htim TIM handle
5116 * @param EventSource specifies the event source.
5117 * This parameter can be one of the following values:
5118 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5119 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5120 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5121 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5122 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5123 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5124 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5125 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5126 * @note Basic timers can only generate an update event.
5127 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5128 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5129 * supporting a break input.
5130 * @retval HAL status
5131 */
5132
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5133 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5134 {
5135 /* Check the parameters */
5136 assert_param(IS_TIM_INSTANCE(htim->Instance));
5137 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5138
5139 /* Process Locked */
5140 __HAL_LOCK(htim);
5141
5142 /* Change the TIM state */
5143 htim->State = HAL_TIM_STATE_BUSY;
5144
5145 /* Set the event sources */
5146 htim->Instance->EGR = EventSource;
5147
5148 /* Change the TIM state */
5149 htim->State = HAL_TIM_STATE_READY;
5150
5151 __HAL_UNLOCK(htim);
5152
5153 /* Return function status */
5154 return HAL_OK;
5155 }
5156
5157 /**
5158 * @brief Configures the OCRef clear feature
5159 * @param htim TIM handle
5160 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5161 * contains the OCREF clear feature and parameters for the TIM peripheral.
5162 * @param Channel specifies the TIM Channel
5163 * This parameter can be one of the following values:
5164 * @arg TIM_CHANNEL_1: TIM Channel 1
5165 * @arg TIM_CHANNEL_2: TIM Channel 2
5166 * @arg TIM_CHANNEL_3: TIM Channel 3
5167 * @arg TIM_CHANNEL_4: TIM Channel 4
5168 * @retval HAL status
5169 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5170 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5171 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5172 uint32_t Channel)
5173 {
5174 HAL_StatusTypeDef status = HAL_OK;
5175
5176 /* Check the parameters */
5177 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5178 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5179
5180 /* Process Locked */
5181 __HAL_LOCK(htim);
5182
5183 htim->State = HAL_TIM_STATE_BUSY;
5184
5185 switch (sClearInputConfig->ClearInputSource)
5186 {
5187 case TIM_CLEARINPUTSOURCE_NONE:
5188 {
5189 /* Clear the OCREF clear selection bit and the the ETR Bits */
5190 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5191 break;
5192 }
5193
5194 case TIM_CLEARINPUTSOURCE_ETR:
5195 {
5196 /* Check the parameters */
5197 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5198 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5199 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5200
5201 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5202 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5203 {
5204 htim->State = HAL_TIM_STATE_READY;
5205 __HAL_UNLOCK(htim);
5206 return HAL_ERROR;
5207 }
5208
5209 TIM_ETR_SetConfig(htim->Instance,
5210 sClearInputConfig->ClearInputPrescaler,
5211 sClearInputConfig->ClearInputPolarity,
5212 sClearInputConfig->ClearInputFilter);
5213 break;
5214 }
5215
5216 default:
5217 status = HAL_ERROR;
5218 break;
5219 }
5220
5221 if (status == HAL_OK)
5222 {
5223 switch (Channel)
5224 {
5225 case TIM_CHANNEL_1:
5226 {
5227 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5228 {
5229 /* Enable the OCREF clear feature for Channel 1 */
5230 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5231 }
5232 else
5233 {
5234 /* Disable the OCREF clear feature for Channel 1 */
5235 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5236 }
5237 break;
5238 }
5239 case TIM_CHANNEL_2:
5240 {
5241 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5242 {
5243 /* Enable the OCREF clear feature for Channel 2 */
5244 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5245 }
5246 else
5247 {
5248 /* Disable the OCREF clear feature for Channel 2 */
5249 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5250 }
5251 break;
5252 }
5253 case TIM_CHANNEL_3:
5254 {
5255 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5256 {
5257 /* Enable the OCREF clear feature for Channel 3 */
5258 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5259 }
5260 else
5261 {
5262 /* Disable the OCREF clear feature for Channel 3 */
5263 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5264 }
5265 break;
5266 }
5267 case TIM_CHANNEL_4:
5268 {
5269 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5270 {
5271 /* Enable the OCREF clear feature for Channel 4 */
5272 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5273 }
5274 else
5275 {
5276 /* Disable the OCREF clear feature for Channel 4 */
5277 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5278 }
5279 break;
5280 }
5281 default:
5282 break;
5283 }
5284 }
5285
5286 htim->State = HAL_TIM_STATE_READY;
5287
5288 __HAL_UNLOCK(htim);
5289
5290 return status;
5291 }
5292
5293 /**
5294 * @brief Configures the clock source to be used
5295 * @param htim TIM handle
5296 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5297 * contains the clock source information for the TIM peripheral.
5298 * @retval HAL status
5299 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5300 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5301 {
5302 HAL_StatusTypeDef status = HAL_OK;
5303 uint32_t tmpsmcr;
5304
5305 /* Process Locked */
5306 __HAL_LOCK(htim);
5307
5308 htim->State = HAL_TIM_STATE_BUSY;
5309
5310 /* Check the parameters */
5311 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5312
5313 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5314 tmpsmcr = htim->Instance->SMCR;
5315 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5316 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5317 htim->Instance->SMCR = tmpsmcr;
5318
5319 switch (sClockSourceConfig->ClockSource)
5320 {
5321 case TIM_CLOCKSOURCE_INTERNAL:
5322 {
5323 assert_param(IS_TIM_INSTANCE(htim->Instance));
5324 break;
5325 }
5326
5327 case TIM_CLOCKSOURCE_ETRMODE1:
5328 {
5329 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5330 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5331
5332 /* Check ETR input conditioning related parameters */
5333 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5334 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5335 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5336
5337 /* Configure the ETR Clock source */
5338 TIM_ETR_SetConfig(htim->Instance,
5339 sClockSourceConfig->ClockPrescaler,
5340 sClockSourceConfig->ClockPolarity,
5341 sClockSourceConfig->ClockFilter);
5342
5343 /* Select the External clock mode1 and the ETRF trigger */
5344 tmpsmcr = htim->Instance->SMCR;
5345 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5346 /* Write to TIMx SMCR */
5347 htim->Instance->SMCR = tmpsmcr;
5348 break;
5349 }
5350
5351 case TIM_CLOCKSOURCE_ETRMODE2:
5352 {
5353 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5354 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5355
5356 /* Check ETR input conditioning related parameters */
5357 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5358 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5359 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5360
5361 /* Configure the ETR Clock source */
5362 TIM_ETR_SetConfig(htim->Instance,
5363 sClockSourceConfig->ClockPrescaler,
5364 sClockSourceConfig->ClockPolarity,
5365 sClockSourceConfig->ClockFilter);
5366 /* Enable the External clock mode2 */
5367 htim->Instance->SMCR |= TIM_SMCR_ECE;
5368 break;
5369 }
5370
5371 case TIM_CLOCKSOURCE_TI1:
5372 {
5373 /* Check whether or not the timer instance supports external clock mode 1 */
5374 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5375
5376 /* Check TI1 input conditioning related parameters */
5377 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5378 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5379
5380 TIM_TI1_ConfigInputStage(htim->Instance,
5381 sClockSourceConfig->ClockPolarity,
5382 sClockSourceConfig->ClockFilter);
5383 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5384 break;
5385 }
5386
5387 case TIM_CLOCKSOURCE_TI2:
5388 {
5389 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5390 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5391
5392 /* Check TI2 input conditioning related parameters */
5393 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5394 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5395
5396 TIM_TI2_ConfigInputStage(htim->Instance,
5397 sClockSourceConfig->ClockPolarity,
5398 sClockSourceConfig->ClockFilter);
5399 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5400 break;
5401 }
5402
5403 case TIM_CLOCKSOURCE_TI1ED:
5404 {
5405 /* Check whether or not the timer instance supports external clock mode 1 */
5406 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5407
5408 /* Check TI1 input conditioning related parameters */
5409 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5410 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5411
5412 TIM_TI1_ConfigInputStage(htim->Instance,
5413 sClockSourceConfig->ClockPolarity,
5414 sClockSourceConfig->ClockFilter);
5415 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5416 break;
5417 }
5418
5419 case TIM_CLOCKSOURCE_ITR0:
5420 case TIM_CLOCKSOURCE_ITR1:
5421 case TIM_CLOCKSOURCE_ITR2:
5422 case TIM_CLOCKSOURCE_ITR3:
5423 {
5424 /* Check whether or not the timer instance supports internal trigger input */
5425 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5426
5427 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5428 break;
5429 }
5430
5431 default:
5432 status = HAL_ERROR;
5433 break;
5434 }
5435 htim->State = HAL_TIM_STATE_READY;
5436
5437 __HAL_UNLOCK(htim);
5438
5439 return status;
5440 }
5441
5442 /**
5443 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5444 * or a XOR combination between CH1_input, CH2_input & CH3_input
5445 * @param htim TIM handle.
5446 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5447 * output of a XOR gate.
5448 * This parameter can be one of the following values:
5449 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5450 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5451 * pins are connected to the TI1 input (XOR combination)
5452 * @retval HAL status
5453 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5454 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5455 {
5456 uint32_t tmpcr2;
5457
5458 /* Check the parameters */
5459 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5460 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5461
5462 /* Get the TIMx CR2 register value */
5463 tmpcr2 = htim->Instance->CR2;
5464
5465 /* Reset the TI1 selection */
5466 tmpcr2 &= ~TIM_CR2_TI1S;
5467
5468 /* Set the TI1 selection */
5469 tmpcr2 |= TI1_Selection;
5470
5471 /* Write to TIMxCR2 */
5472 htim->Instance->CR2 = tmpcr2;
5473
5474 return HAL_OK;
5475 }
5476
5477 /**
5478 * @brief Configures the TIM in Slave mode
5479 * @param htim TIM handle.
5480 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5481 * contains the selected trigger (internal trigger input, filtered
5482 * timer input or external trigger input) and the Slave mode
5483 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5484 * @retval HAL status
5485 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5486 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5487 {
5488 /* Check the parameters */
5489 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5490 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5491 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5492
5493 __HAL_LOCK(htim);
5494
5495 htim->State = HAL_TIM_STATE_BUSY;
5496
5497 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5498 {
5499 htim->State = HAL_TIM_STATE_READY;
5500 __HAL_UNLOCK(htim);
5501 return HAL_ERROR;
5502 }
5503
5504 /* Disable Trigger Interrupt */
5505 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5506
5507 /* Disable Trigger DMA request */
5508 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5509
5510 htim->State = HAL_TIM_STATE_READY;
5511
5512 __HAL_UNLOCK(htim);
5513
5514 return HAL_OK;
5515 }
5516
5517 /**
5518 * @brief Configures the TIM in Slave mode in interrupt mode
5519 * @param htim TIM handle.
5520 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5521 * contains the selected trigger (internal trigger input, filtered
5522 * timer input or external trigger input) and the Slave mode
5523 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5524 * @retval HAL status
5525 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5526 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5527 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5528 {
5529 /* Check the parameters */
5530 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5531 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5532 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5533
5534 __HAL_LOCK(htim);
5535
5536 htim->State = HAL_TIM_STATE_BUSY;
5537
5538 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5539 {
5540 htim->State = HAL_TIM_STATE_READY;
5541 __HAL_UNLOCK(htim);
5542 return HAL_ERROR;
5543 }
5544
5545 /* Enable Trigger Interrupt */
5546 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5547
5548 /* Disable Trigger DMA request */
5549 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5550
5551 htim->State = HAL_TIM_STATE_READY;
5552
5553 __HAL_UNLOCK(htim);
5554
5555 return HAL_OK;
5556 }
5557
5558 /**
5559 * @brief Read the captured value from Capture Compare unit
5560 * @param htim TIM handle.
5561 * @param Channel TIM Channels to be enabled
5562 * This parameter can be one of the following values:
5563 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5564 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5565 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5566 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5567 * @retval Captured value
5568 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5569 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5570 {
5571 uint32_t tmpreg = 0U;
5572
5573 switch (Channel)
5574 {
5575 case TIM_CHANNEL_1:
5576 {
5577 /* Check the parameters */
5578 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5579
5580 /* Return the capture 1 value */
5581 tmpreg = htim->Instance->CCR1;
5582
5583 break;
5584 }
5585 case TIM_CHANNEL_2:
5586 {
5587 /* Check the parameters */
5588 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5589
5590 /* Return the capture 2 value */
5591 tmpreg = htim->Instance->CCR2;
5592
5593 break;
5594 }
5595
5596 case TIM_CHANNEL_3:
5597 {
5598 /* Check the parameters */
5599 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5600
5601 /* Return the capture 3 value */
5602 tmpreg = htim->Instance->CCR3;
5603
5604 break;
5605 }
5606
5607 case TIM_CHANNEL_4:
5608 {
5609 /* Check the parameters */
5610 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5611
5612 /* Return the capture 4 value */
5613 tmpreg = htim->Instance->CCR4;
5614
5615 break;
5616 }
5617
5618 default:
5619 break;
5620 }
5621
5622 return tmpreg;
5623 }
5624
5625 /**
5626 * @}
5627 */
5628
5629 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5630 * @brief TIM Callbacks functions
5631 *
5632 @verbatim
5633 ==============================================================================
5634 ##### TIM Callbacks functions #####
5635 ==============================================================================
5636 [..]
5637 This section provides TIM callback functions:
5638 (+) TIM Period elapsed callback
5639 (+) TIM Output Compare callback
5640 (+) TIM Input capture callback
5641 (+) TIM Trigger callback
5642 (+) TIM Error callback
5643
5644 @endverbatim
5645 * @{
5646 */
5647
5648 /**
5649 * @brief Period elapsed callback in non-blocking mode
5650 * @param htim TIM handle
5651 * @retval None
5652 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5653 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5654 {
5655 /* Prevent unused argument(s) compilation warning */
5656 UNUSED(htim);
5657
5658 /* NOTE : This function should not be modified, when the callback is needed,
5659 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5660 */
5661 }
5662
5663 /**
5664 * @brief Period elapsed half complete callback in non-blocking mode
5665 * @param htim TIM handle
5666 * @retval None
5667 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5668 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5669 {
5670 /* Prevent unused argument(s) compilation warning */
5671 UNUSED(htim);
5672
5673 /* NOTE : This function should not be modified, when the callback is needed,
5674 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5675 */
5676 }
5677
5678 /**
5679 * @brief Output Compare callback in non-blocking mode
5680 * @param htim TIM OC handle
5681 * @retval None
5682 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5683 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5684 {
5685 /* Prevent unused argument(s) compilation warning */
5686 UNUSED(htim);
5687
5688 /* NOTE : This function should not be modified, when the callback is needed,
5689 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5690 */
5691 }
5692
5693 /**
5694 * @brief Input Capture callback in non-blocking mode
5695 * @param htim TIM IC handle
5696 * @retval None
5697 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5698 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5699 {
5700 /* Prevent unused argument(s) compilation warning */
5701 UNUSED(htim);
5702
5703 /* NOTE : This function should not be modified, when the callback is needed,
5704 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5705 */
5706 }
5707
5708 /**
5709 * @brief Input Capture half complete callback in non-blocking mode
5710 * @param htim TIM IC handle
5711 * @retval None
5712 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5713 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5714 {
5715 /* Prevent unused argument(s) compilation warning */
5716 UNUSED(htim);
5717
5718 /* NOTE : This function should not be modified, when the callback is needed,
5719 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5720 */
5721 }
5722
5723 /**
5724 * @brief PWM Pulse finished callback in non-blocking mode
5725 * @param htim TIM handle
5726 * @retval None
5727 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5728 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5729 {
5730 /* Prevent unused argument(s) compilation warning */
5731 UNUSED(htim);
5732
5733 /* NOTE : This function should not be modified, when the callback is needed,
5734 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5735 */
5736 }
5737
5738 /**
5739 * @brief PWM Pulse finished half complete callback in non-blocking mode
5740 * @param htim TIM handle
5741 * @retval None
5742 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5743 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5744 {
5745 /* Prevent unused argument(s) compilation warning */
5746 UNUSED(htim);
5747
5748 /* NOTE : This function should not be modified, when the callback is needed,
5749 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5750 */
5751 }
5752
5753 /**
5754 * @brief Hall Trigger detection callback in non-blocking mode
5755 * @param htim TIM handle
5756 * @retval None
5757 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5758 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5759 {
5760 /* Prevent unused argument(s) compilation warning */
5761 UNUSED(htim);
5762
5763 /* NOTE : This function should not be modified, when the callback is needed,
5764 the HAL_TIM_TriggerCallback could be implemented in the user file
5765 */
5766 }
5767
5768 /**
5769 * @brief Hall Trigger detection half complete callback in non-blocking mode
5770 * @param htim TIM handle
5771 * @retval None
5772 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5773 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5774 {
5775 /* Prevent unused argument(s) compilation warning */
5776 UNUSED(htim);
5777
5778 /* NOTE : This function should not be modified, when the callback is needed,
5779 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5780 */
5781 }
5782
5783 /**
5784 * @brief Timer error callback in non-blocking mode
5785 * @param htim TIM handle
5786 * @retval None
5787 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5788 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5789 {
5790 /* Prevent unused argument(s) compilation warning */
5791 UNUSED(htim);
5792
5793 /* NOTE : This function should not be modified, when the callback is needed,
5794 the HAL_TIM_ErrorCallback could be implemented in the user file
5795 */
5796 }
5797
5798 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5799 /**
5800 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5801 * @param htim tim handle
5802 * @param CallbackID ID of the callback to be registered
5803 * This parameter can be one of the following values:
5804 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5805 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5806 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5807 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5808 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5809 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5810 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5811 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5812 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5813 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5814 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5815 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5816 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5817 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5818 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5819 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5820 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5821 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5822 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5823 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5824 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5825 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5826 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5827 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5828 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5829 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5830 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5831 * @param pCallback pointer to the callback function
5832 * @retval status
5833 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5834 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5835 pTIM_CallbackTypeDef pCallback)
5836 {
5837 HAL_StatusTypeDef status = HAL_OK;
5838
5839 if (pCallback == NULL)
5840 {
5841 return HAL_ERROR;
5842 }
5843
5844 if (htim->State == HAL_TIM_STATE_READY)
5845 {
5846 switch (CallbackID)
5847 {
5848 case HAL_TIM_BASE_MSPINIT_CB_ID :
5849 htim->Base_MspInitCallback = pCallback;
5850 break;
5851
5852 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5853 htim->Base_MspDeInitCallback = pCallback;
5854 break;
5855
5856 case HAL_TIM_IC_MSPINIT_CB_ID :
5857 htim->IC_MspInitCallback = pCallback;
5858 break;
5859
5860 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5861 htim->IC_MspDeInitCallback = pCallback;
5862 break;
5863
5864 case HAL_TIM_OC_MSPINIT_CB_ID :
5865 htim->OC_MspInitCallback = pCallback;
5866 break;
5867
5868 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5869 htim->OC_MspDeInitCallback = pCallback;
5870 break;
5871
5872 case HAL_TIM_PWM_MSPINIT_CB_ID :
5873 htim->PWM_MspInitCallback = pCallback;
5874 break;
5875
5876 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5877 htim->PWM_MspDeInitCallback = pCallback;
5878 break;
5879
5880 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5881 htim->OnePulse_MspInitCallback = pCallback;
5882 break;
5883
5884 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5885 htim->OnePulse_MspDeInitCallback = pCallback;
5886 break;
5887
5888 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5889 htim->Encoder_MspInitCallback = pCallback;
5890 break;
5891
5892 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5893 htim->Encoder_MspDeInitCallback = pCallback;
5894 break;
5895
5896 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5897 htim->HallSensor_MspInitCallback = pCallback;
5898 break;
5899
5900 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5901 htim->HallSensor_MspDeInitCallback = pCallback;
5902 break;
5903
5904 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5905 htim->PeriodElapsedCallback = pCallback;
5906 break;
5907
5908 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5909 htim->PeriodElapsedHalfCpltCallback = pCallback;
5910 break;
5911
5912 case HAL_TIM_TRIGGER_CB_ID :
5913 htim->TriggerCallback = pCallback;
5914 break;
5915
5916 case HAL_TIM_TRIGGER_HALF_CB_ID :
5917 htim->TriggerHalfCpltCallback = pCallback;
5918 break;
5919
5920 case HAL_TIM_IC_CAPTURE_CB_ID :
5921 htim->IC_CaptureCallback = pCallback;
5922 break;
5923
5924 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5925 htim->IC_CaptureHalfCpltCallback = pCallback;
5926 break;
5927
5928 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5929 htim->OC_DelayElapsedCallback = pCallback;
5930 break;
5931
5932 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5933 htim->PWM_PulseFinishedCallback = pCallback;
5934 break;
5935
5936 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5937 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5938 break;
5939
5940 case HAL_TIM_ERROR_CB_ID :
5941 htim->ErrorCallback = pCallback;
5942 break;
5943
5944 case HAL_TIM_COMMUTATION_CB_ID :
5945 htim->CommutationCallback = pCallback;
5946 break;
5947
5948 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5949 htim->CommutationHalfCpltCallback = pCallback;
5950 break;
5951
5952 case HAL_TIM_BREAK_CB_ID :
5953 htim->BreakCallback = pCallback;
5954 break;
5955
5956 default :
5957 /* Return error status */
5958 status = HAL_ERROR;
5959 break;
5960 }
5961 }
5962 else if (htim->State == HAL_TIM_STATE_RESET)
5963 {
5964 switch (CallbackID)
5965 {
5966 case HAL_TIM_BASE_MSPINIT_CB_ID :
5967 htim->Base_MspInitCallback = pCallback;
5968 break;
5969
5970 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5971 htim->Base_MspDeInitCallback = pCallback;
5972 break;
5973
5974 case HAL_TIM_IC_MSPINIT_CB_ID :
5975 htim->IC_MspInitCallback = pCallback;
5976 break;
5977
5978 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5979 htim->IC_MspDeInitCallback = pCallback;
5980 break;
5981
5982 case HAL_TIM_OC_MSPINIT_CB_ID :
5983 htim->OC_MspInitCallback = pCallback;
5984 break;
5985
5986 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5987 htim->OC_MspDeInitCallback = pCallback;
5988 break;
5989
5990 case HAL_TIM_PWM_MSPINIT_CB_ID :
5991 htim->PWM_MspInitCallback = pCallback;
5992 break;
5993
5994 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5995 htim->PWM_MspDeInitCallback = pCallback;
5996 break;
5997
5998 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5999 htim->OnePulse_MspInitCallback = pCallback;
6000 break;
6001
6002 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6003 htim->OnePulse_MspDeInitCallback = pCallback;
6004 break;
6005
6006 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6007 htim->Encoder_MspInitCallback = pCallback;
6008 break;
6009
6010 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6011 htim->Encoder_MspDeInitCallback = pCallback;
6012 break;
6013
6014 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6015 htim->HallSensor_MspInitCallback = pCallback;
6016 break;
6017
6018 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6019 htim->HallSensor_MspDeInitCallback = pCallback;
6020 break;
6021
6022 default :
6023 /* Return error status */
6024 status = HAL_ERROR;
6025 break;
6026 }
6027 }
6028 else
6029 {
6030 /* Return error status */
6031 status = HAL_ERROR;
6032 }
6033
6034 return status;
6035 }
6036
6037 /**
6038 * @brief Unregister a TIM callback
6039 * TIM callback is redirected to the weak predefined callback
6040 * @param htim tim handle
6041 * @param CallbackID ID of the callback to be unregistered
6042 * This parameter can be one of the following values:
6043 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6044 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6045 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6046 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6047 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6048 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6049 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6050 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6051 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6052 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6053 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6054 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6055 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6056 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6057 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6058 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6059 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6060 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6061 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6062 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6063 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6064 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6065 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6066 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6067 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6068 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6069 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6070 * @retval status
6071 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6072 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6073 {
6074 HAL_StatusTypeDef status = HAL_OK;
6075
6076 if (htim->State == HAL_TIM_STATE_READY)
6077 {
6078 switch (CallbackID)
6079 {
6080 case HAL_TIM_BASE_MSPINIT_CB_ID :
6081 /* Legacy weak Base MspInit Callback */
6082 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6083 break;
6084
6085 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6086 /* Legacy weak Base Msp DeInit Callback */
6087 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6088 break;
6089
6090 case HAL_TIM_IC_MSPINIT_CB_ID :
6091 /* Legacy weak IC Msp Init Callback */
6092 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6093 break;
6094
6095 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6096 /* Legacy weak IC Msp DeInit Callback */
6097 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6098 break;
6099
6100 case HAL_TIM_OC_MSPINIT_CB_ID :
6101 /* Legacy weak OC Msp Init Callback */
6102 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6103 break;
6104
6105 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6106 /* Legacy weak OC Msp DeInit Callback */
6107 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6108 break;
6109
6110 case HAL_TIM_PWM_MSPINIT_CB_ID :
6111 /* Legacy weak PWM Msp Init Callback */
6112 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6113 break;
6114
6115 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6116 /* Legacy weak PWM Msp DeInit Callback */
6117 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6118 break;
6119
6120 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6121 /* Legacy weak One Pulse Msp Init Callback */
6122 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6123 break;
6124
6125 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6126 /* Legacy weak One Pulse Msp DeInit Callback */
6127 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6128 break;
6129
6130 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6131 /* Legacy weak Encoder Msp Init Callback */
6132 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6133 break;
6134
6135 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6136 /* Legacy weak Encoder Msp DeInit Callback */
6137 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6138 break;
6139
6140 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6141 /* Legacy weak Hall Sensor Msp Init Callback */
6142 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6143 break;
6144
6145 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6146 /* Legacy weak Hall Sensor Msp DeInit Callback */
6147 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6148 break;
6149
6150 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6151 /* Legacy weak Period Elapsed Callback */
6152 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6153 break;
6154
6155 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6156 /* Legacy weak Period Elapsed half complete Callback */
6157 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6158 break;
6159
6160 case HAL_TIM_TRIGGER_CB_ID :
6161 /* Legacy weak Trigger Callback */
6162 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6163 break;
6164
6165 case HAL_TIM_TRIGGER_HALF_CB_ID :
6166 /* Legacy weak Trigger half complete Callback */
6167 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6168 break;
6169
6170 case HAL_TIM_IC_CAPTURE_CB_ID :
6171 /* Legacy weak IC Capture Callback */
6172 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6173 break;
6174
6175 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6176 /* Legacy weak IC Capture half complete Callback */
6177 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6178 break;
6179
6180 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6181 /* Legacy weak OC Delay Elapsed Callback */
6182 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6183 break;
6184
6185 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6186 /* Legacy weak PWM Pulse Finished Callback */
6187 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6188 break;
6189
6190 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6191 /* Legacy weak PWM Pulse Finished half complete Callback */
6192 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6193 break;
6194
6195 case HAL_TIM_ERROR_CB_ID :
6196 /* Legacy weak Error Callback */
6197 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6198 break;
6199
6200 case HAL_TIM_COMMUTATION_CB_ID :
6201 /* Legacy weak Commutation Callback */
6202 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6203 break;
6204
6205 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6206 /* Legacy weak Commutation half complete Callback */
6207 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6208 break;
6209
6210 case HAL_TIM_BREAK_CB_ID :
6211 /* Legacy weak Break Callback */
6212 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6213 break;
6214
6215 default :
6216 /* Return error status */
6217 status = HAL_ERROR;
6218 break;
6219 }
6220 }
6221 else if (htim->State == HAL_TIM_STATE_RESET)
6222 {
6223 switch (CallbackID)
6224 {
6225 case HAL_TIM_BASE_MSPINIT_CB_ID :
6226 /* Legacy weak Base MspInit Callback */
6227 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6228 break;
6229
6230 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6231 /* Legacy weak Base Msp DeInit Callback */
6232 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6233 break;
6234
6235 case HAL_TIM_IC_MSPINIT_CB_ID :
6236 /* Legacy weak IC Msp Init Callback */
6237 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6238 break;
6239
6240 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6241 /* Legacy weak IC Msp DeInit Callback */
6242 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6243 break;
6244
6245 case HAL_TIM_OC_MSPINIT_CB_ID :
6246 /* Legacy weak OC Msp Init Callback */
6247 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6248 break;
6249
6250 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6251 /* Legacy weak OC Msp DeInit Callback */
6252 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6253 break;
6254
6255 case HAL_TIM_PWM_MSPINIT_CB_ID :
6256 /* Legacy weak PWM Msp Init Callback */
6257 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6258 break;
6259
6260 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6261 /* Legacy weak PWM Msp DeInit Callback */
6262 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6263 break;
6264
6265 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6266 /* Legacy weak One Pulse Msp Init Callback */
6267 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6268 break;
6269
6270 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6271 /* Legacy weak One Pulse Msp DeInit Callback */
6272 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6273 break;
6274
6275 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6276 /* Legacy weak Encoder Msp Init Callback */
6277 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6278 break;
6279
6280 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6281 /* Legacy weak Encoder Msp DeInit Callback */
6282 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6283 break;
6284
6285 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6286 /* Legacy weak Hall Sensor Msp Init Callback */
6287 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6288 break;
6289
6290 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6291 /* Legacy weak Hall Sensor Msp DeInit Callback */
6292 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6293 break;
6294
6295 default :
6296 /* Return error status */
6297 status = HAL_ERROR;
6298 break;
6299 }
6300 }
6301 else
6302 {
6303 /* Return error status */
6304 status = HAL_ERROR;
6305 }
6306
6307 return status;
6308 }
6309 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6310
6311 /**
6312 * @}
6313 */
6314
6315 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6316 * @brief TIM Peripheral State functions
6317 *
6318 @verbatim
6319 ==============================================================================
6320 ##### Peripheral State functions #####
6321 ==============================================================================
6322 [..]
6323 This subsection permits to get in run-time the status of the peripheral
6324 and the data flow.
6325
6326 @endverbatim
6327 * @{
6328 */
6329
6330 /**
6331 * @brief Return the TIM Base handle state.
6332 * @param htim TIM Base handle
6333 * @retval HAL state
6334 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6335 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6336 {
6337 return htim->State;
6338 }
6339
6340 /**
6341 * @brief Return the TIM OC handle state.
6342 * @param htim TIM Output Compare handle
6343 * @retval HAL state
6344 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6345 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6346 {
6347 return htim->State;
6348 }
6349
6350 /**
6351 * @brief Return the TIM PWM handle state.
6352 * @param htim TIM handle
6353 * @retval HAL state
6354 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6355 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6356 {
6357 return htim->State;
6358 }
6359
6360 /**
6361 * @brief Return the TIM Input Capture handle state.
6362 * @param htim TIM IC handle
6363 * @retval HAL state
6364 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6365 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6366 {
6367 return htim->State;
6368 }
6369
6370 /**
6371 * @brief Return the TIM One Pulse Mode handle state.
6372 * @param htim TIM OPM handle
6373 * @retval HAL state
6374 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6375 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6376 {
6377 return htim->State;
6378 }
6379
6380 /**
6381 * @brief Return the TIM Encoder Mode handle state.
6382 * @param htim TIM Encoder Interface handle
6383 * @retval HAL state
6384 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6385 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6386 {
6387 return htim->State;
6388 }
6389
6390 /**
6391 * @brief Return the TIM Encoder Mode handle state.
6392 * @param htim TIM handle
6393 * @retval Active channel
6394 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6395 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6396 {
6397 return htim->Channel;
6398 }
6399
6400 /**
6401 * @brief Return actual state of the TIM channel.
6402 * @param htim TIM handle
6403 * @param Channel TIM Channel
6404 * This parameter can be one of the following values:
6405 * @arg TIM_CHANNEL_1: TIM Channel 1
6406 * @arg TIM_CHANNEL_2: TIM Channel 2
6407 * @arg TIM_CHANNEL_3: TIM Channel 3
6408 * @arg TIM_CHANNEL_4: TIM Channel 4
6409 * @arg TIM_CHANNEL_5: TIM Channel 5
6410 * @arg TIM_CHANNEL_6: TIM Channel 6
6411 * @retval TIM Channel state
6412 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6413 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6414 {
6415 HAL_TIM_ChannelStateTypeDef channel_state;
6416
6417 /* Check the parameters */
6418 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6419
6420 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6421
6422 return channel_state;
6423 }
6424
6425 /**
6426 * @brief Return actual state of a DMA burst operation.
6427 * @param htim TIM handle
6428 * @retval DMA burst state
6429 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6430 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6431 {
6432 /* Check the parameters */
6433 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6434
6435 return htim->DMABurstState;
6436 }
6437
6438 /**
6439 * @}
6440 */
6441
6442 /**
6443 * @}
6444 */
6445
6446 /** @defgroup TIM_Private_Functions TIM Private Functions
6447 * @{
6448 */
6449
6450 /**
6451 * @brief TIM DMA error callback
6452 * @param hdma pointer to DMA handle.
6453 * @retval None
6454 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6455 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6456 {
6457 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6458
6459 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6460 {
6461 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6462 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6463 }
6464 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6465 {
6466 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6467 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6468 }
6469 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6470 {
6471 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6472 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6473 }
6474 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6475 {
6476 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6477 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6478 }
6479 else
6480 {
6481 htim->State = HAL_TIM_STATE_READY;
6482 }
6483
6484 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6485 htim->ErrorCallback(htim);
6486 #else
6487 HAL_TIM_ErrorCallback(htim);
6488 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6489
6490 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6491 }
6492
6493 /**
6494 * @brief TIM DMA Delay Pulse complete callback.
6495 * @param hdma pointer to DMA handle.
6496 * @retval None
6497 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6498 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6499 {
6500 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6501
6502 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6503 {
6504 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6505
6506 if (hdma->Init.Mode == DMA_NORMAL)
6507 {
6508 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6509 }
6510 }
6511 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6512 {
6513 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6514
6515 if (hdma->Init.Mode == DMA_NORMAL)
6516 {
6517 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6518 }
6519 }
6520 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6521 {
6522 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6523
6524 if (hdma->Init.Mode == DMA_NORMAL)
6525 {
6526 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6527 }
6528 }
6529 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6530 {
6531 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6532
6533 if (hdma->Init.Mode == DMA_NORMAL)
6534 {
6535 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6536 }
6537 }
6538 else
6539 {
6540 /* nothing to do */
6541 }
6542
6543 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6544 htim->PWM_PulseFinishedCallback(htim);
6545 #else
6546 HAL_TIM_PWM_PulseFinishedCallback(htim);
6547 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6548
6549 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6550 }
6551
6552 /**
6553 * @brief TIM DMA Delay Pulse half complete callback.
6554 * @param hdma pointer to DMA handle.
6555 * @retval None
6556 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6557 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6558 {
6559 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6560
6561 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6562 {
6563 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6564 }
6565 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6566 {
6567 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6568 }
6569 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6570 {
6571 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6572 }
6573 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6574 {
6575 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6576 }
6577 else
6578 {
6579 /* nothing to do */
6580 }
6581
6582 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6583 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6584 #else
6585 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6586 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6587
6588 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6589 }
6590
6591 /**
6592 * @brief TIM DMA Capture complete callback.
6593 * @param hdma pointer to DMA handle.
6594 * @retval None
6595 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6596 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6597 {
6598 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6599
6600 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6601 {
6602 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6603
6604 if (hdma->Init.Mode == DMA_NORMAL)
6605 {
6606 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6607 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6608 }
6609 }
6610 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6611 {
6612 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6613
6614 if (hdma->Init.Mode == DMA_NORMAL)
6615 {
6616 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6617 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6618 }
6619 }
6620 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6621 {
6622 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6623
6624 if (hdma->Init.Mode == DMA_NORMAL)
6625 {
6626 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6627 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6628 }
6629 }
6630 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6631 {
6632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6633
6634 if (hdma->Init.Mode == DMA_NORMAL)
6635 {
6636 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6638 }
6639 }
6640 else
6641 {
6642 /* nothing to do */
6643 }
6644
6645 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6646 htim->IC_CaptureCallback(htim);
6647 #else
6648 HAL_TIM_IC_CaptureCallback(htim);
6649 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6650
6651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6652 }
6653
6654 /**
6655 * @brief TIM DMA Capture half complete callback.
6656 * @param hdma pointer to DMA handle.
6657 * @retval None
6658 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6659 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6660 {
6661 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6662
6663 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6664 {
6665 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6666 }
6667 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6668 {
6669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6670 }
6671 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6672 {
6673 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6674 }
6675 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6676 {
6677 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6678 }
6679 else
6680 {
6681 /* nothing to do */
6682 }
6683
6684 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6685 htim->IC_CaptureHalfCpltCallback(htim);
6686 #else
6687 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6688 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6689
6690 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6691 }
6692
6693 /**
6694 * @brief TIM DMA Period Elapse complete callback.
6695 * @param hdma pointer to DMA handle.
6696 * @retval None
6697 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6698 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6699 {
6700 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6701
6702 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6703 {
6704 htim->State = HAL_TIM_STATE_READY;
6705 }
6706
6707 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6708 htim->PeriodElapsedCallback(htim);
6709 #else
6710 HAL_TIM_PeriodElapsedCallback(htim);
6711 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6712 }
6713
6714 /**
6715 * @brief TIM DMA Period Elapse half complete callback.
6716 * @param hdma pointer to DMA handle.
6717 * @retval None
6718 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6719 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6720 {
6721 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6722
6723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6724 htim->PeriodElapsedHalfCpltCallback(htim);
6725 #else
6726 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6727 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6728 }
6729
6730 /**
6731 * @brief TIM DMA Trigger callback.
6732 * @param hdma pointer to DMA handle.
6733 * @retval None
6734 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6735 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6736 {
6737 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6738
6739 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6740 {
6741 htim->State = HAL_TIM_STATE_READY;
6742 }
6743
6744 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6745 htim->TriggerCallback(htim);
6746 #else
6747 HAL_TIM_TriggerCallback(htim);
6748 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6749 }
6750
6751 /**
6752 * @brief TIM DMA Trigger half complete callback.
6753 * @param hdma pointer to DMA handle.
6754 * @retval None
6755 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6756 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6757 {
6758 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6759
6760 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6761 htim->TriggerHalfCpltCallback(htim);
6762 #else
6763 HAL_TIM_TriggerHalfCpltCallback(htim);
6764 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6765 }
6766
6767 /**
6768 * @brief Time Base configuration
6769 * @param TIMx TIM peripheral
6770 * @param Structure TIM Base configuration structure
6771 * @retval None
6772 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6773 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6774 {
6775 uint32_t tmpcr1;
6776 tmpcr1 = TIMx->CR1;
6777
6778 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6779 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6780 {
6781 /* Select the Counter Mode */
6782 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6783 tmpcr1 |= Structure->CounterMode;
6784 }
6785
6786 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6787 {
6788 /* Set the clock division */
6789 tmpcr1 &= ~TIM_CR1_CKD;
6790 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6791 }
6792
6793 /* Set the auto-reload preload */
6794 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6795
6796 TIMx->CR1 = tmpcr1;
6797
6798 /* Set the Autoreload value */
6799 TIMx->ARR = (uint32_t)Structure->Period ;
6800
6801 /* Set the Prescaler value */
6802 TIMx->PSC = Structure->Prescaler;
6803
6804 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6805 {
6806 /* Set the Repetition Counter value */
6807 TIMx->RCR = Structure->RepetitionCounter;
6808 }
6809
6810 /* Generate an update event to reload the Prescaler
6811 and the repetition counter (only for advanced timer) value immediately */
6812 TIMx->EGR = TIM_EGR_UG;
6813 }
6814
6815 /**
6816 * @brief Timer Output Compare 1 configuration
6817 * @param TIMx to select the TIM peripheral
6818 * @param OC_Config The output configuration structure
6819 * @retval None
6820 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6821 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6822 {
6823 uint32_t tmpccmrx;
6824 uint32_t tmpccer;
6825 uint32_t tmpcr2;
6826
6827 /* Get the TIMx CCER register value */
6828 tmpccer = TIMx->CCER;
6829
6830 /* Disable the Channel 1: Reset the CC1E Bit */
6831 TIMx->CCER &= ~TIM_CCER_CC1E;
6832
6833 /* Get the TIMx CR2 register value */
6834 tmpcr2 = TIMx->CR2;
6835
6836 /* Get the TIMx CCMR1 register value */
6837 tmpccmrx = TIMx->CCMR1;
6838
6839 /* Reset the Output Compare Mode Bits */
6840 tmpccmrx &= ~TIM_CCMR1_OC1M;
6841 tmpccmrx &= ~TIM_CCMR1_CC1S;
6842 /* Select the Output Compare Mode */
6843 tmpccmrx |= OC_Config->OCMode;
6844
6845 /* Reset the Output Polarity level */
6846 tmpccer &= ~TIM_CCER_CC1P;
6847 /* Set the Output Compare Polarity */
6848 tmpccer |= OC_Config->OCPolarity;
6849
6850 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6851 {
6852 /* Check parameters */
6853 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6854
6855 /* Reset the Output N Polarity level */
6856 tmpccer &= ~TIM_CCER_CC1NP;
6857 /* Set the Output N Polarity */
6858 tmpccer |= OC_Config->OCNPolarity;
6859 /* Reset the Output N State */
6860 tmpccer &= ~TIM_CCER_CC1NE;
6861 }
6862
6863 if (IS_TIM_BREAK_INSTANCE(TIMx))
6864 {
6865 /* Check parameters */
6866 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6867 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6868
6869 /* Reset the Output Compare and Output Compare N IDLE State */
6870 tmpcr2 &= ~TIM_CR2_OIS1;
6871 tmpcr2 &= ~TIM_CR2_OIS1N;
6872 /* Set the Output Idle state */
6873 tmpcr2 |= OC_Config->OCIdleState;
6874 /* Set the Output N Idle state */
6875 tmpcr2 |= OC_Config->OCNIdleState;
6876 }
6877
6878 /* Write to TIMx CR2 */
6879 TIMx->CR2 = tmpcr2;
6880
6881 /* Write to TIMx CCMR1 */
6882 TIMx->CCMR1 = tmpccmrx;
6883
6884 /* Set the Capture Compare Register value */
6885 TIMx->CCR1 = OC_Config->Pulse;
6886
6887 /* Write to TIMx CCER */
6888 TIMx->CCER = tmpccer;
6889 }
6890
6891 /**
6892 * @brief Timer Output Compare 2 configuration
6893 * @param TIMx to select the TIM peripheral
6894 * @param OC_Config The output configuration structure
6895 * @retval None
6896 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6897 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6898 {
6899 uint32_t tmpccmrx;
6900 uint32_t tmpccer;
6901 uint32_t tmpcr2;
6902
6903 /* Get the TIMx CCER register value */
6904 tmpccer = TIMx->CCER;
6905
6906 /* Disable the Channel 2: Reset the CC2E Bit */
6907 TIMx->CCER &= ~TIM_CCER_CC2E;
6908
6909 /* Get the TIMx CR2 register value */
6910 tmpcr2 = TIMx->CR2;
6911
6912 /* Get the TIMx CCMR1 register value */
6913 tmpccmrx = TIMx->CCMR1;
6914
6915 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6916 tmpccmrx &= ~TIM_CCMR1_OC2M;
6917 tmpccmrx &= ~TIM_CCMR1_CC2S;
6918
6919 /* Select the Output Compare Mode */
6920 tmpccmrx |= (OC_Config->OCMode << 8U);
6921
6922 /* Reset the Output Polarity level */
6923 tmpccer &= ~TIM_CCER_CC2P;
6924 /* Set the Output Compare Polarity */
6925 tmpccer |= (OC_Config->OCPolarity << 4U);
6926
6927 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6928 {
6929 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6930
6931 /* Reset the Output N Polarity level */
6932 tmpccer &= ~TIM_CCER_CC2NP;
6933 /* Set the Output N Polarity */
6934 tmpccer |= (OC_Config->OCNPolarity << 4U);
6935 /* Reset the Output N State */
6936 tmpccer &= ~TIM_CCER_CC2NE;
6937
6938 }
6939
6940 if (IS_TIM_BREAK_INSTANCE(TIMx))
6941 {
6942 /* Check parameters */
6943 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6944 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6945
6946 /* Reset the Output Compare and Output Compare N IDLE State */
6947 tmpcr2 &= ~TIM_CR2_OIS2;
6948 tmpcr2 &= ~TIM_CR2_OIS2N;
6949 /* Set the Output Idle state */
6950 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6951 /* Set the Output N Idle state */
6952 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6953 }
6954
6955 /* Write to TIMx CR2 */
6956 TIMx->CR2 = tmpcr2;
6957
6958 /* Write to TIMx CCMR1 */
6959 TIMx->CCMR1 = tmpccmrx;
6960
6961 /* Set the Capture Compare Register value */
6962 TIMx->CCR2 = OC_Config->Pulse;
6963
6964 /* Write to TIMx CCER */
6965 TIMx->CCER = tmpccer;
6966 }
6967
6968 /**
6969 * @brief Timer Output Compare 3 configuration
6970 * @param TIMx to select the TIM peripheral
6971 * @param OC_Config The output configuration structure
6972 * @retval None
6973 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6974 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6975 {
6976 uint32_t tmpccmrx;
6977 uint32_t tmpccer;
6978 uint32_t tmpcr2;
6979
6980 /* Get the TIMx CCER register value */
6981 tmpccer = TIMx->CCER;
6982
6983 /* Disable the Channel 3: Reset the CC2E Bit */
6984 TIMx->CCER &= ~TIM_CCER_CC3E;
6985
6986 /* Get the TIMx CR2 register value */
6987 tmpcr2 = TIMx->CR2;
6988
6989 /* Get the TIMx CCMR2 register value */
6990 tmpccmrx = TIMx->CCMR2;
6991
6992 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6993 tmpccmrx &= ~TIM_CCMR2_OC3M;
6994 tmpccmrx &= ~TIM_CCMR2_CC3S;
6995 /* Select the Output Compare Mode */
6996 tmpccmrx |= OC_Config->OCMode;
6997
6998 /* Reset the Output Polarity level */
6999 tmpccer &= ~TIM_CCER_CC3P;
7000 /* Set the Output Compare Polarity */
7001 tmpccer |= (OC_Config->OCPolarity << 8U);
7002
7003 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7004 {
7005 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7006
7007 /* Reset the Output N Polarity level */
7008 tmpccer &= ~TIM_CCER_CC3NP;
7009 /* Set the Output N Polarity */
7010 tmpccer |= (OC_Config->OCNPolarity << 8U);
7011 /* Reset the Output N State */
7012 tmpccer &= ~TIM_CCER_CC3NE;
7013 }
7014
7015 if (IS_TIM_BREAK_INSTANCE(TIMx))
7016 {
7017 /* Check parameters */
7018 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7019 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7020
7021 /* Reset the Output Compare and Output Compare N IDLE State */
7022 tmpcr2 &= ~TIM_CR2_OIS3;
7023 tmpcr2 &= ~TIM_CR2_OIS3N;
7024 /* Set the Output Idle state */
7025 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7026 /* Set the Output N Idle state */
7027 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7028 }
7029
7030 /* Write to TIMx CR2 */
7031 TIMx->CR2 = tmpcr2;
7032
7033 /* Write to TIMx CCMR2 */
7034 TIMx->CCMR2 = tmpccmrx;
7035
7036 /* Set the Capture Compare Register value */
7037 TIMx->CCR3 = OC_Config->Pulse;
7038
7039 /* Write to TIMx CCER */
7040 TIMx->CCER = tmpccer;
7041 }
7042
7043 /**
7044 * @brief Timer Output Compare 4 configuration
7045 * @param TIMx to select the TIM peripheral
7046 * @param OC_Config The output configuration structure
7047 * @retval None
7048 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7049 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7050 {
7051 uint32_t tmpccmrx;
7052 uint32_t tmpccer;
7053 uint32_t tmpcr2;
7054
7055 /* Get the TIMx CCER register value */
7056 tmpccer = TIMx->CCER;
7057
7058 /* Disable the Channel 4: Reset the CC4E Bit */
7059 TIMx->CCER &= ~TIM_CCER_CC4E;
7060
7061 /* Get the TIMx CR2 register value */
7062 tmpcr2 = TIMx->CR2;
7063
7064 /* Get the TIMx CCMR2 register value */
7065 tmpccmrx = TIMx->CCMR2;
7066
7067 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7068 tmpccmrx &= ~TIM_CCMR2_OC4M;
7069 tmpccmrx &= ~TIM_CCMR2_CC4S;
7070
7071 /* Select the Output Compare Mode */
7072 tmpccmrx |= (OC_Config->OCMode << 8U);
7073
7074 /* Reset the Output Polarity level */
7075 tmpccer &= ~TIM_CCER_CC4P;
7076 /* Set the Output Compare Polarity */
7077 tmpccer |= (OC_Config->OCPolarity << 12U);
7078
7079 if (IS_TIM_BREAK_INSTANCE(TIMx))
7080 {
7081 /* Check parameters */
7082 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7083
7084 /* Reset the Output Compare IDLE State */
7085 tmpcr2 &= ~TIM_CR2_OIS4;
7086
7087 /* Set the Output Idle state */
7088 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7089 }
7090
7091 /* Write to TIMx CR2 */
7092 TIMx->CR2 = tmpcr2;
7093
7094 /* Write to TIMx CCMR2 */
7095 TIMx->CCMR2 = tmpccmrx;
7096
7097 /* Set the Capture Compare Register value */
7098 TIMx->CCR4 = OC_Config->Pulse;
7099
7100 /* Write to TIMx CCER */
7101 TIMx->CCER = tmpccer;
7102 }
7103
7104 /**
7105 * @brief Slave Timer configuration function
7106 * @param htim TIM handle
7107 * @param sSlaveConfig Slave timer configuration
7108 * @retval None
7109 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7110 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7111 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7112 {
7113 HAL_StatusTypeDef status = HAL_OK;
7114 uint32_t tmpsmcr;
7115 uint32_t tmpccmr1;
7116 uint32_t tmpccer;
7117
7118 /* Get the TIMx SMCR register value */
7119 tmpsmcr = htim->Instance->SMCR;
7120
7121 /* Reset the Trigger Selection Bits */
7122 tmpsmcr &= ~TIM_SMCR_TS;
7123 /* Set the Input Trigger source */
7124 tmpsmcr |= sSlaveConfig->InputTrigger;
7125
7126 /* Reset the slave mode Bits */
7127 tmpsmcr &= ~TIM_SMCR_SMS;
7128 /* Set the slave mode */
7129 tmpsmcr |= sSlaveConfig->SlaveMode;
7130
7131 /* Write to TIMx SMCR */
7132 htim->Instance->SMCR = tmpsmcr;
7133
7134 /* Configure the trigger prescaler, filter, and polarity */
7135 switch (sSlaveConfig->InputTrigger)
7136 {
7137 case TIM_TS_ETRF:
7138 {
7139 /* Check the parameters */
7140 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7141 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7142 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7143 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7144 /* Configure the ETR Trigger source */
7145 TIM_ETR_SetConfig(htim->Instance,
7146 sSlaveConfig->TriggerPrescaler,
7147 sSlaveConfig->TriggerPolarity,
7148 sSlaveConfig->TriggerFilter);
7149 break;
7150 }
7151
7152 case TIM_TS_TI1F_ED:
7153 {
7154 /* Check the parameters */
7155 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7156 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7157
7158 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7159 {
7160 return HAL_ERROR;
7161 }
7162
7163 /* Disable the Channel 1: Reset the CC1E Bit */
7164 tmpccer = htim->Instance->CCER;
7165 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7166 tmpccmr1 = htim->Instance->CCMR1;
7167
7168 /* Set the filter */
7169 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7170 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7171
7172 /* Write to TIMx CCMR1 and CCER registers */
7173 htim->Instance->CCMR1 = tmpccmr1;
7174 htim->Instance->CCER = tmpccer;
7175 break;
7176 }
7177
7178 case TIM_TS_TI1FP1:
7179 {
7180 /* Check the parameters */
7181 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7182 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7183 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7184
7185 /* Configure TI1 Filter and Polarity */
7186 TIM_TI1_ConfigInputStage(htim->Instance,
7187 sSlaveConfig->TriggerPolarity,
7188 sSlaveConfig->TriggerFilter);
7189 break;
7190 }
7191
7192 case TIM_TS_TI2FP2:
7193 {
7194 /* Check the parameters */
7195 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7196 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7197 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7198
7199 /* Configure TI2 Filter and Polarity */
7200 TIM_TI2_ConfigInputStage(htim->Instance,
7201 sSlaveConfig->TriggerPolarity,
7202 sSlaveConfig->TriggerFilter);
7203 break;
7204 }
7205
7206 case TIM_TS_ITR0:
7207 case TIM_TS_ITR1:
7208 case TIM_TS_ITR2:
7209 case TIM_TS_ITR3:
7210 {
7211 /* Check the parameter */
7212 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7213 break;
7214 }
7215
7216 default:
7217 status = HAL_ERROR;
7218 break;
7219 }
7220
7221 return status;
7222 }
7223
7224 /**
7225 * @brief Configure the TI1 as Input.
7226 * @param TIMx to select the TIM peripheral.
7227 * @param TIM_ICPolarity The Input Polarity.
7228 * This parameter can be one of the following values:
7229 * @arg TIM_ICPOLARITY_RISING
7230 * @arg TIM_ICPOLARITY_FALLING
7231 * @arg TIM_ICPOLARITY_BOTHEDGE
7232 * @param TIM_ICSelection specifies the input to be used.
7233 * This parameter can be one of the following values:
7234 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7235 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7236 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7237 * @param TIM_ICFilter Specifies the Input Capture Filter.
7238 * This parameter must be a value between 0x00 and 0x0F.
7239 * @retval None
7240 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7241 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7242 * protected against un-initialized filter and polarity values.
7243 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7244 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7245 uint32_t TIM_ICFilter)
7246 {
7247 uint32_t tmpccmr1;
7248 uint32_t tmpccer;
7249
7250 /* Disable the Channel 1: Reset the CC1E Bit */
7251 tmpccer = TIMx->CCER;
7252 TIMx->CCER &= ~TIM_CCER_CC1E;
7253 tmpccmr1 = TIMx->CCMR1;
7254
7255 /* Select the Input */
7256 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7257 {
7258 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7259 tmpccmr1 |= TIM_ICSelection;
7260 }
7261 else
7262 {
7263 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7264 }
7265
7266 /* Set the filter */
7267 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7268 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7269
7270 /* Select the Polarity and set the CC1E Bit */
7271 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7272 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7273
7274 /* Write to TIMx CCMR1 and CCER registers */
7275 TIMx->CCMR1 = tmpccmr1;
7276 TIMx->CCER = tmpccer;
7277 }
7278
7279 /**
7280 * @brief Configure the Polarity and Filter for TI1.
7281 * @param TIMx to select the TIM peripheral.
7282 * @param TIM_ICPolarity The Input Polarity.
7283 * This parameter can be one of the following values:
7284 * @arg TIM_ICPOLARITY_RISING
7285 * @arg TIM_ICPOLARITY_FALLING
7286 * @arg TIM_ICPOLARITY_BOTHEDGE
7287 * @param TIM_ICFilter Specifies the Input Capture Filter.
7288 * This parameter must be a value between 0x00 and 0x0F.
7289 * @retval None
7290 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7291 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7292 {
7293 uint32_t tmpccmr1;
7294 uint32_t tmpccer;
7295
7296 /* Disable the Channel 1: Reset the CC1E Bit */
7297 tmpccer = TIMx->CCER;
7298 TIMx->CCER &= ~TIM_CCER_CC1E;
7299 tmpccmr1 = TIMx->CCMR1;
7300
7301 /* Set the filter */
7302 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7303 tmpccmr1 |= (TIM_ICFilter << 4U);
7304
7305 /* Select the Polarity and set the CC1E Bit */
7306 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7307 tmpccer |= TIM_ICPolarity;
7308
7309 /* Write to TIMx CCMR1 and CCER registers */
7310 TIMx->CCMR1 = tmpccmr1;
7311 TIMx->CCER = tmpccer;
7312 }
7313
7314 /**
7315 * @brief Configure the TI2 as Input.
7316 * @param TIMx to select the TIM peripheral
7317 * @param TIM_ICPolarity The Input Polarity.
7318 * This parameter can be one of the following values:
7319 * @arg TIM_ICPOLARITY_RISING
7320 * @arg TIM_ICPOLARITY_FALLING
7321 * @arg TIM_ICPOLARITY_BOTHEDGE
7322 * @param TIM_ICSelection specifies the input to be used.
7323 * This parameter can be one of the following values:
7324 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7325 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7326 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7327 * @param TIM_ICFilter Specifies the Input Capture Filter.
7328 * This parameter must be a value between 0x00 and 0x0F.
7329 * @retval None
7330 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7331 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7332 * protected against un-initialized filter and polarity values.
7333 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7334 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7335 uint32_t TIM_ICFilter)
7336 {
7337 uint32_t tmpccmr1;
7338 uint32_t tmpccer;
7339
7340 /* Disable the Channel 2: Reset the CC2E Bit */
7341 tmpccer = TIMx->CCER;
7342 TIMx->CCER &= ~TIM_CCER_CC2E;
7343 tmpccmr1 = TIMx->CCMR1;
7344
7345 /* Select the Input */
7346 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7347 tmpccmr1 |= (TIM_ICSelection << 8U);
7348
7349 /* Set the filter */
7350 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7351 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7352
7353 /* Select the Polarity and set the CC2E Bit */
7354 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7355 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7356
7357 /* Write to TIMx CCMR1 and CCER registers */
7358 TIMx->CCMR1 = tmpccmr1 ;
7359 TIMx->CCER = tmpccer;
7360 }
7361
7362 /**
7363 * @brief Configure the Polarity and Filter for TI2.
7364 * @param TIMx to select the TIM peripheral.
7365 * @param TIM_ICPolarity The Input Polarity.
7366 * This parameter can be one of the following values:
7367 * @arg TIM_ICPOLARITY_RISING
7368 * @arg TIM_ICPOLARITY_FALLING
7369 * @arg TIM_ICPOLARITY_BOTHEDGE
7370 * @param TIM_ICFilter Specifies the Input Capture Filter.
7371 * This parameter must be a value between 0x00 and 0x0F.
7372 * @retval None
7373 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7374 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7375 {
7376 uint32_t tmpccmr1;
7377 uint32_t tmpccer;
7378
7379 /* Disable the Channel 2: Reset the CC2E Bit */
7380 tmpccer = TIMx->CCER;
7381 TIMx->CCER &= ~TIM_CCER_CC2E;
7382 tmpccmr1 = TIMx->CCMR1;
7383
7384 /* Set the filter */
7385 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7386 tmpccmr1 |= (TIM_ICFilter << 12U);
7387
7388 /* Select the Polarity and set the CC2E Bit */
7389 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7390 tmpccer |= (TIM_ICPolarity << 4U);
7391
7392 /* Write to TIMx CCMR1 and CCER registers */
7393 TIMx->CCMR1 = tmpccmr1 ;
7394 TIMx->CCER = tmpccer;
7395 }
7396
7397 /**
7398 * @brief Configure the TI3 as Input.
7399 * @param TIMx to select the TIM peripheral
7400 * @param TIM_ICPolarity The Input Polarity.
7401 * This parameter can be one of the following values:
7402 * @arg TIM_ICPOLARITY_RISING
7403 * @arg TIM_ICPOLARITY_FALLING
7404 * @arg TIM_ICPOLARITY_BOTHEDGE
7405 * @param TIM_ICSelection specifies the input to be used.
7406 * This parameter can be one of the following values:
7407 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7408 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7409 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7410 * @param TIM_ICFilter Specifies the Input Capture Filter.
7411 * This parameter must be a value between 0x00 and 0x0F.
7412 * @retval None
7413 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7414 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7415 * protected against un-initialized filter and polarity values.
7416 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7417 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7418 uint32_t TIM_ICFilter)
7419 {
7420 uint32_t tmpccmr2;
7421 uint32_t tmpccer;
7422
7423 /* Disable the Channel 3: Reset the CC3E Bit */
7424 tmpccer = TIMx->CCER;
7425 TIMx->CCER &= ~TIM_CCER_CC3E;
7426 tmpccmr2 = TIMx->CCMR2;
7427
7428 /* Select the Input */
7429 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7430 tmpccmr2 |= TIM_ICSelection;
7431
7432 /* Set the filter */
7433 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7434 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7435
7436 /* Select the Polarity and set the CC3E Bit */
7437 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7438 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7439
7440 /* Write to TIMx CCMR2 and CCER registers */
7441 TIMx->CCMR2 = tmpccmr2;
7442 TIMx->CCER = tmpccer;
7443 }
7444
7445 /**
7446 * @brief Configure the TI4 as Input.
7447 * @param TIMx to select the TIM peripheral
7448 * @param TIM_ICPolarity The Input Polarity.
7449 * This parameter can be one of the following values:
7450 * @arg TIM_ICPOLARITY_RISING
7451 * @arg TIM_ICPOLARITY_FALLING
7452 * @arg TIM_ICPOLARITY_BOTHEDGE
7453 * @param TIM_ICSelection specifies the input to be used.
7454 * This parameter can be one of the following values:
7455 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7456 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7457 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7458 * @param TIM_ICFilter Specifies the Input Capture Filter.
7459 * This parameter must be a value between 0x00 and 0x0F.
7460 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7461 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7462 * protected against un-initialized filter and polarity values.
7463 * @retval None
7464 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7465 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7466 uint32_t TIM_ICFilter)
7467 {
7468 uint32_t tmpccmr2;
7469 uint32_t tmpccer;
7470
7471 /* Disable the Channel 4: Reset the CC4E Bit */
7472 tmpccer = TIMx->CCER;
7473 TIMx->CCER &= ~TIM_CCER_CC4E;
7474 tmpccmr2 = TIMx->CCMR2;
7475
7476 /* Select the Input */
7477 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7478 tmpccmr2 |= (TIM_ICSelection << 8U);
7479
7480 /* Set the filter */
7481 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7482 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7483
7484 /* Select the Polarity and set the CC4E Bit */
7485 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7486 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7487
7488 /* Write to TIMx CCMR2 and CCER registers */
7489 TIMx->CCMR2 = tmpccmr2;
7490 TIMx->CCER = tmpccer ;
7491 }
7492
7493 /**
7494 * @brief Selects the Input Trigger source
7495 * @param TIMx to select the TIM peripheral
7496 * @param InputTriggerSource The Input Trigger source.
7497 * This parameter can be one of the following values:
7498 * @arg TIM_TS_ITR0: Internal Trigger 0
7499 * @arg TIM_TS_ITR1: Internal Trigger 1
7500 * @arg TIM_TS_ITR2: Internal Trigger 2
7501 * @arg TIM_TS_ITR3: Internal Trigger 3
7502 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7503 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7504 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7505 * @arg TIM_TS_ETRF: External Trigger input
7506 * @retval None
7507 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7508 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7509 {
7510 uint32_t tmpsmcr;
7511
7512 /* Get the TIMx SMCR register value */
7513 tmpsmcr = TIMx->SMCR;
7514 /* Reset the TS Bits */
7515 tmpsmcr &= ~TIM_SMCR_TS;
7516 /* Set the Input Trigger source and the slave mode*/
7517 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7518 /* Write to TIMx SMCR */
7519 TIMx->SMCR = tmpsmcr;
7520 }
7521 /**
7522 * @brief Configures the TIMx External Trigger (ETR).
7523 * @param TIMx to select the TIM peripheral
7524 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7525 * This parameter can be one of the following values:
7526 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7527 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7528 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7529 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7530 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7531 * This parameter can be one of the following values:
7532 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7533 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7534 * @param ExtTRGFilter External Trigger Filter.
7535 * This parameter must be a value between 0x00 and 0x0F
7536 * @retval None
7537 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7538 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7539 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7540 {
7541 uint32_t tmpsmcr;
7542
7543 tmpsmcr = TIMx->SMCR;
7544
7545 /* Reset the ETR Bits */
7546 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7547
7548 /* Set the Prescaler, the Filter value and the Polarity */
7549 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7550
7551 /* Write to TIMx SMCR */
7552 TIMx->SMCR = tmpsmcr;
7553 }
7554
7555 /**
7556 * @brief Enables or disables the TIM Capture Compare Channel x.
7557 * @param TIMx to select the TIM peripheral
7558 * @param Channel specifies the TIM Channel
7559 * This parameter can be one of the following values:
7560 * @arg TIM_CHANNEL_1: TIM Channel 1
7561 * @arg TIM_CHANNEL_2: TIM Channel 2
7562 * @arg TIM_CHANNEL_3: TIM Channel 3
7563 * @arg TIM_CHANNEL_4: TIM Channel 4
7564 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7565 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7566 * @retval None
7567 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7568 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7569 {
7570 uint32_t tmp;
7571
7572 /* Check the parameters */
7573 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7574 assert_param(IS_TIM_CHANNELS(Channel));
7575
7576 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7577
7578 /* Reset the CCxE Bit */
7579 TIMx->CCER &= ~tmp;
7580
7581 /* Set or reset the CCxE Bit */
7582 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7583 }
7584
7585 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7586 /**
7587 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7588 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7589 * the configuration information for TIM module.
7590 * @retval None
7591 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7592 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7593 {
7594 /* Reset the TIM callback to the legacy weak callbacks */
7595 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7596 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7597 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7598 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7599 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7600 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7601 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7602 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7603 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7604 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7605 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7606 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7607 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7608 }
7609 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7610
7611 /**
7612 * @}
7613 */
7614
7615 #endif /* HAL_TIM_MODULE_ENABLED */
7616 /**
7617 * @}
7618 */
7619
7620 /**
7621 * @}
7622 */
7623
