1 /**
2 ******************************************************************************
3 * @file stm32f2xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
43 (+++) Enable the DMAx interface clock using
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx stream
46 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
48 the DMA Tx or Rx stream
49
50 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
51 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
52
53 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
54 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
55
56 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
57
58 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
59
60 *** Polling mode IO operation ***
61 =================================
62 [..]
63 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
64 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
65 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
66 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
67
68 *** Polling mode IO MEM operation ***
69 =====================================
70 [..]
71 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
72 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
73
74
75 *** Interrupt mode IO operation ***
76 ===================================
77 [..]
78 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
79 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
80 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
81 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
82 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
84 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
85 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
86 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
87 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
88 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
89 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
90 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
91 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
92 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
93 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
94 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
95
96 *** Interrupt mode or DMA mode IO sequential operation ***
97 ==========================================================
98 [..]
99 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
100 when a direction change during transfer
101 [..]
102 (+) A specific option field manage the different steps of a sequential transfer
103 (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
104 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
105 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
106 and data to transfer without a final stop condition
107 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
108 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
109 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
110 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
111 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
112 and with new data to transfer if the direction change or manage only the new data to transfer
113 if no direction change and without a final stop condition in both cases
114 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
115 and with new data to transfer if the direction change or manage only the new data to transfer
116 if no direction change and with a final stop condition in both cases
117 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
118 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
119 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
120 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
121 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
122 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
123 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
124 without stopping the communication and so generate a restart condition.
125 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
126 interface.
127 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
128 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
129 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
130 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
131 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
132
133 (+) Different sequential I2C interfaces are listed below:
134 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
135 or using HAL_I2C_Master_Seq_Transmit_DMA()
136 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
137 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
138 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
139 or using HAL_I2C_Master_Seq_Receive_DMA()
140 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
141 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
142 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
143 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
144 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
145 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
146 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
147 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
148 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
149 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
150 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
151 or using HAL_I2C_Slave_Seq_Transmit_DMA()
152 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
153 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
154 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
155 or using HAL_I2C_Slave_Seq_Receive_DMA()
156 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
157 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
158 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
159 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
160
161 *** Interrupt mode IO MEM operation ***
162 =======================================
163 [..]
164 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
165 HAL_I2C_Mem_Write_IT()
166 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
168 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
169 HAL_I2C_Mem_Read_IT()
170 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
171 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
173 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
174
175 *** DMA mode IO operation ***
176 ==============================
177 [..]
178 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
179 HAL_I2C_Master_Transmit_DMA()
180 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
181 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
182 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
183 HAL_I2C_Master_Receive_DMA()
184 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
185 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
186 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
187 HAL_I2C_Slave_Transmit_DMA()
188 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
189 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
190 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
191 HAL_I2C_Slave_Receive_DMA()
192 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
193 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
194 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
195 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
196 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
197 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
198 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
199
200 *** DMA mode IO MEM operation ***
201 =================================
202 [..]
203 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
204 HAL_I2C_Mem_Write_DMA()
205 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
206 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
207 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
208 HAL_I2C_Mem_Read_DMA()
209 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
210 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
211 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
212 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
213
214
215 *** I2C HAL driver macros list ***
216 ==================================
217 [..]
218 Below the list of most used macros in I2C HAL driver.
219
220 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
221 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
222 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
223 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
224 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
225 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
226
227 *** Callback registration ***
228 =============================================
229 [..]
230 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
231 allows the user to configure dynamically the driver callbacks.
232 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
233 to register an interrupt callback.
234 [..]
235 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
236 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
237 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
238 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
239 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
240 (+) ListenCpltCallback : callback for end of listen mode.
241 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
242 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
243 (+) ErrorCallback : callback for error detection.
244 (+) AbortCpltCallback : callback for abort completion process.
245 (+) MspInitCallback : callback for Msp Init.
246 (+) MspDeInitCallback : callback for Msp DeInit.
247 This function takes as parameters the HAL peripheral handle, the Callback ID
248 and a pointer to the user callback function.
249 [..]
250 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
251 [..]
252 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
253 weak function.
254 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
255 and the Callback ID.
256 This function allows to reset following callbacks:
257 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
258 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
259 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
260 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
261 (+) ListenCpltCallback : callback for end of listen mode.
262 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
263 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
264 (+) ErrorCallback : callback for error detection.
265 (+) AbortCpltCallback : callback for abort completion process.
266 (+) MspInitCallback : callback for Msp Init.
267 (+) MspDeInitCallback : callback for Msp DeInit.
268 [..]
269 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
270 [..]
271 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
272 all callbacks are set to the corresponding weak functions:
273 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
274 Exception done for MspInit and MspDeInit functions that are
275 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
276 these callbacks are null (not registered beforehand).
277 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
278 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
279 [..]
280 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
281 Exception done MspInit/MspDeInit functions that can be registered/unregistered
282 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
283 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
284 Then, the user first registers the MspInit/MspDeInit user callbacks
285 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
286 or HAL_I2C_Init() function.
287 [..]
288 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
289 not defined, the callback registration feature is not available and all callbacks
290 are set to the corresponding weak functions.
291
292
293
294 [..]
295 (@) You can refer to the I2C HAL driver header file for more useful macros
296
297 @endverbatim
298 */
299
300 /* Includes ------------------------------------------------------------------*/
301 #include "stm32f2xx_hal.h"
302
303 /** @addtogroup STM32F2xx_HAL_Driver
304 * @{
305 */
306
307 /** @defgroup I2C I2C
308 * @brief I2C HAL module driver
309 * @{
310 */
311
312 #ifdef HAL_I2C_MODULE_ENABLED
313
314 /* Private typedef -----------------------------------------------------------*/
315 /* Private define ------------------------------------------------------------*/
316 /** @defgroup I2C_Private_Define I2C Private Define
317 * @{
318 */
319 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
320 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
321 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
322 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
323
324 /* Private define for @ref PreviousState usage */
325 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
326 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
327 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
328 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
331
332 /**
333 * @}
334 */
335
336 /* Private macro -------------------------------------------------------------*/
337 /** @addtogroup I2C_Private_Macros
338 * @{
339 */
340 /* Macro to get remaining data to transfer on DMA side */
341 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
342 /**
343 * @}
344 */
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347
348 /** @defgroup I2C_Private_Functions I2C Private Functions
349 * @{
350 */
351 /* Private functions to handle DMA transfer */
352 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
353 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
354 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
355
356 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
357
358 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
362
363 /* Private functions to handle flags during polling transfer */
364 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
365 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
366 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
367 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
368 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
369 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
370 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
371 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
372
373 /* Private functions for I2C transfer IRQ handler */
374 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
375 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
376 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
377 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
378 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
379 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
380 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
381
382 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
383 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
384 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
385 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
386 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
387 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
388 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
389
390 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
391
392 /* Private function to Convert Specific options */
393 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
394
395 /* Private function to flush DR register */
396 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
397 /**
398 * @}
399 */
400
401 /* Exported functions --------------------------------------------------------*/
402
403 /** @defgroup I2C_Exported_Functions I2C Exported Functions
404 * @{
405 */
406
407 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
408 * @brief Initialization and Configuration functions
409 *
410 @verbatim
411 ===============================================================================
412 ##### Initialization and de-initialization functions #####
413 ===============================================================================
414 [..] This subsection provides a set of functions allowing to initialize and
415 deinitialize the I2Cx peripheral:
416
417 (+) User must Implement HAL_I2C_MspInit() function in which he configures
418 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
419
420 (+) Call the function HAL_I2C_Init() to configure the selected device with
421 the selected configuration:
422 (++) Communication Speed
423 (++) Duty cycle
424 (++) Addressing mode
425 (++) Own Address 1
426 (++) Dual Addressing mode
427 (++) Own Address 2
428 (++) General call mode
429 (++) Nostretch mode
430
431 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
432 of the selected I2Cx peripheral.
433
434 @endverbatim
435 * @{
436 */
437
438 /**
439 * @brief Initializes the I2C according to the specified parameters
440 * in the I2C_InitTypeDef and initialize the associated handle.
441 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
442 * the configuration information for the specified I2C.
443 * @retval HAL status
444 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)445 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
446 {
447 uint32_t freqrange;
448 uint32_t pclk1;
449
450 /* Check the I2C handle allocation */
451 if (hi2c == NULL)
452 {
453 return HAL_ERROR;
454 }
455
456 /* Check the parameters */
457 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
458 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
459 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
460 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
461 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
462 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
463 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
464 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
465 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
466
467 if (hi2c->State == HAL_I2C_STATE_RESET)
468 {
469 /* Allocate lock resource and initialize it */
470 hi2c->Lock = HAL_UNLOCKED;
471
472 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
473 /* Init the I2C Callback settings */
474 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
475 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
476 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
477 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
478 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
479 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
480 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
481 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
482 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
483 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
484
485 if (hi2c->MspInitCallback == NULL)
486 {
487 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
488 }
489
490 /* Init the low level hardware : GPIO, CLOCK, NVIC */
491 hi2c->MspInitCallback(hi2c);
492 #else
493 /* Init the low level hardware : GPIO, CLOCK, NVIC */
494 HAL_I2C_MspInit(hi2c);
495 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
496 }
497
498 hi2c->State = HAL_I2C_STATE_BUSY;
499
500 /* Disable the selected I2C peripheral */
501 __HAL_I2C_DISABLE(hi2c);
502
503 /*Reset I2C*/
504 hi2c->Instance->CR1 |= I2C_CR1_SWRST;
505 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
506
507 /* Get PCLK1 frequency */
508 pclk1 = HAL_RCC_GetPCLK1Freq();
509
510 /* Check the minimum allowed PCLK1 frequency */
511 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
512 {
513 return HAL_ERROR;
514 }
515
516 /* Calculate frequency range */
517 freqrange = I2C_FREQRANGE(pclk1);
518
519 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
520 /* Configure I2Cx: Frequency range */
521 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
522
523 /*---------------------------- I2Cx TRISE Configuration --------------------*/
524 /* Configure I2Cx: Rise Time */
525 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
526
527 /*---------------------------- I2Cx CCR Configuration ----------------------*/
528 /* Configure I2Cx: Speed */
529 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
530
531 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
532 /* Configure I2Cx: Generalcall and NoStretch mode */
533 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
534
535 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
536 /* Configure I2Cx: Own Address1 and addressing mode */
537 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
538
539 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
540 /* Configure I2Cx: Dual mode and Own Address2 */
541 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
542
543 /* Enable the selected I2C peripheral */
544 __HAL_I2C_ENABLE(hi2c);
545
546 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
547 hi2c->State = HAL_I2C_STATE_READY;
548 hi2c->PreviousState = I2C_STATE_NONE;
549 hi2c->Mode = HAL_I2C_MODE_NONE;
550
551 return HAL_OK;
552 }
553
554 /**
555 * @brief DeInitialize the I2C peripheral.
556 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
557 * the configuration information for the specified I2C.
558 * @retval HAL status
559 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)560 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
561 {
562 /* Check the I2C handle allocation */
563 if (hi2c == NULL)
564 {
565 return HAL_ERROR;
566 }
567
568 /* Check the parameters */
569 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
570
571 hi2c->State = HAL_I2C_STATE_BUSY;
572
573 /* Disable the I2C Peripheral Clock */
574 __HAL_I2C_DISABLE(hi2c);
575
576 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
577 if (hi2c->MspDeInitCallback == NULL)
578 {
579 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
580 }
581
582 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
583 hi2c->MspDeInitCallback(hi2c);
584 #else
585 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
586 HAL_I2C_MspDeInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588
589 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
590 hi2c->State = HAL_I2C_STATE_RESET;
591 hi2c->PreviousState = I2C_STATE_NONE;
592 hi2c->Mode = HAL_I2C_MODE_NONE;
593
594 /* Release Lock */
595 __HAL_UNLOCK(hi2c);
596
597 return HAL_OK;
598 }
599
600 /**
601 * @brief Initialize the I2C MSP.
602 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
603 * the configuration information for the specified I2C.
604 * @retval None
605 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)606 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
607 {
608 /* Prevent unused argument(s) compilation warning */
609 UNUSED(hi2c);
610
611 /* NOTE : This function should not be modified, when the callback is needed,
612 the HAL_I2C_MspInit could be implemented in the user file
613 */
614 }
615
616 /**
617 * @brief DeInitialize the I2C MSP.
618 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
619 * the configuration information for the specified I2C.
620 * @retval None
621 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)622 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
623 {
624 /* Prevent unused argument(s) compilation warning */
625 UNUSED(hi2c);
626
627 /* NOTE : This function should not be modified, when the callback is needed,
628 the HAL_I2C_MspDeInit could be implemented in the user file
629 */
630 }
631
632 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
633 /**
634 * @brief Register a User I2C Callback
635 * To be used instead of the weak predefined callback
636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
637 * the configuration information for the specified I2C.
638 * @param CallbackID ID of the callback to be registered
639 * This parameter can be one of the following values:
640 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
641 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
642 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
643 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
644 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
645 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
646 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
647 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
648 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
649 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
650 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
651 * @param pCallback pointer to the Callback function
652 * @retval HAL status
653 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)654 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
655 {
656 HAL_StatusTypeDef status = HAL_OK;
657
658 if (pCallback == NULL)
659 {
660 /* Update the error code */
661 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
662
663 return HAL_ERROR;
664 }
665 /* Process locked */
666 __HAL_LOCK(hi2c);
667
668 if (HAL_I2C_STATE_READY == hi2c->State)
669 {
670 switch (CallbackID)
671 {
672 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
673 hi2c->MasterTxCpltCallback = pCallback;
674 break;
675
676 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
677 hi2c->MasterRxCpltCallback = pCallback;
678 break;
679
680 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
681 hi2c->SlaveTxCpltCallback = pCallback;
682 break;
683
684 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
685 hi2c->SlaveRxCpltCallback = pCallback;
686 break;
687
688 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
689 hi2c->ListenCpltCallback = pCallback;
690 break;
691
692 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
693 hi2c->MemTxCpltCallback = pCallback;
694 break;
695
696 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
697 hi2c->MemRxCpltCallback = pCallback;
698 break;
699
700 case HAL_I2C_ERROR_CB_ID :
701 hi2c->ErrorCallback = pCallback;
702 break;
703
704 case HAL_I2C_ABORT_CB_ID :
705 hi2c->AbortCpltCallback = pCallback;
706 break;
707
708 case HAL_I2C_MSPINIT_CB_ID :
709 hi2c->MspInitCallback = pCallback;
710 break;
711
712 case HAL_I2C_MSPDEINIT_CB_ID :
713 hi2c->MspDeInitCallback = pCallback;
714 break;
715
716 default :
717 /* Update the error code */
718 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
719
720 /* Return error status */
721 status = HAL_ERROR;
722 break;
723 }
724 }
725 else if (HAL_I2C_STATE_RESET == hi2c->State)
726 {
727 switch (CallbackID)
728 {
729 case HAL_I2C_MSPINIT_CB_ID :
730 hi2c->MspInitCallback = pCallback;
731 break;
732
733 case HAL_I2C_MSPDEINIT_CB_ID :
734 hi2c->MspDeInitCallback = pCallback;
735 break;
736
737 default :
738 /* Update the error code */
739 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
740
741 /* Return error status */
742 status = HAL_ERROR;
743 break;
744 }
745 }
746 else
747 {
748 /* Update the error code */
749 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
750
751 /* Return error status */
752 status = HAL_ERROR;
753 }
754
755 /* Release Lock */
756 __HAL_UNLOCK(hi2c);
757 return status;
758 }
759
760 /**
761 * @brief Unregister an I2C Callback
762 * I2C callback is redirected to the weak predefined callback
763 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
764 * the configuration information for the specified I2C.
765 * @param CallbackID ID of the callback to be unregistered
766 * This parameter can be one of the following values:
767 * This parameter can be one of the following values:
768 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
769 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
770 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
771 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
772 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
773 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
774 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
775 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
776 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
777 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
778 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
779 * @retval HAL status
780 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)781 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
782 {
783 HAL_StatusTypeDef status = HAL_OK;
784
785 /* Process locked */
786 __HAL_LOCK(hi2c);
787
788 if (HAL_I2C_STATE_READY == hi2c->State)
789 {
790 switch (CallbackID)
791 {
792 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
793 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
794 break;
795
796 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
797 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
798 break;
799
800 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
801 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
802 break;
803
804 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
805 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
806 break;
807
808 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
809 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
810 break;
811
812 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
813 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
814 break;
815
816 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
817 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
818 break;
819
820 case HAL_I2C_ERROR_CB_ID :
821 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
822 break;
823
824 case HAL_I2C_ABORT_CB_ID :
825 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
826 break;
827
828 case HAL_I2C_MSPINIT_CB_ID :
829 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
830 break;
831
832 case HAL_I2C_MSPDEINIT_CB_ID :
833 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
834 break;
835
836 default :
837 /* Update the error code */
838 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
839
840 /* Return error status */
841 status = HAL_ERROR;
842 break;
843 }
844 }
845 else if (HAL_I2C_STATE_RESET == hi2c->State)
846 {
847 switch (CallbackID)
848 {
849 case HAL_I2C_MSPINIT_CB_ID :
850 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
851 break;
852
853 case HAL_I2C_MSPDEINIT_CB_ID :
854 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
855 break;
856
857 default :
858 /* Update the error code */
859 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
860
861 /* Return error status */
862 status = HAL_ERROR;
863 break;
864 }
865 }
866 else
867 {
868 /* Update the error code */
869 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
870
871 /* Return error status */
872 status = HAL_ERROR;
873 }
874
875 /* Release Lock */
876 __HAL_UNLOCK(hi2c);
877 return status;
878 }
879
880 /**
881 * @brief Register the Slave Address Match I2C Callback
882 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
883 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
884 * the configuration information for the specified I2C.
885 * @param pCallback pointer to the Address Match Callback function
886 * @retval HAL status
887 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)888 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
889 {
890 HAL_StatusTypeDef status = HAL_OK;
891
892 if (pCallback == NULL)
893 {
894 /* Update the error code */
895 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
896
897 return HAL_ERROR;
898 }
899 /* Process locked */
900 __HAL_LOCK(hi2c);
901
902 if (HAL_I2C_STATE_READY == hi2c->State)
903 {
904 hi2c->AddrCallback = pCallback;
905 }
906 else
907 {
908 /* Update the error code */
909 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
910
911 /* Return error status */
912 status = HAL_ERROR;
913 }
914
915 /* Release Lock */
916 __HAL_UNLOCK(hi2c);
917 return status;
918 }
919
920 /**
921 * @brief UnRegister the Slave Address Match I2C Callback
922 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
923 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
924 * the configuration information for the specified I2C.
925 * @retval HAL status
926 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)927 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
928 {
929 HAL_StatusTypeDef status = HAL_OK;
930
931 /* Process locked */
932 __HAL_LOCK(hi2c);
933
934 if (HAL_I2C_STATE_READY == hi2c->State)
935 {
936 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
937 }
938 else
939 {
940 /* Update the error code */
941 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
942
943 /* Return error status */
944 status = HAL_ERROR;
945 }
946
947 /* Release Lock */
948 __HAL_UNLOCK(hi2c);
949 return status;
950 }
951
952 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
953
954 /**
955 * @brief I2C data register flush process.
956 * @param hi2c I2C handle.
957 * @retval None
958 */
I2C_Flush_DR(I2C_HandleTypeDef * hi2c)959 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
960 {
961 /* Write a dummy data in DR to clear TXE flag */
962 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
963 {
964 hi2c->Instance->DR = 0x00U;
965 }
966 }
967
968 /**
969 * @}
970 */
971
972 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
973 * @brief Data transfers functions
974 *
975 @verbatim
976 ===============================================================================
977 ##### IO operation functions #####
978 ===============================================================================
979 [..]
980 This subsection provides a set of functions allowing to manage the I2C data
981 transfers.
982
983 (#) There are two modes of transfer:
984 (++) Blocking mode : The communication is performed in the polling mode.
985 The status of all data processing is returned by the same function
986 after finishing transfer.
987 (++) No-Blocking mode : The communication is performed using Interrupts
988 or DMA. These functions return the status of the transfer startup.
989 The end of the data processing will be indicated through the
990 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
991 using DMA mode.
992
993 (#) Blocking mode functions are :
994 (++) HAL_I2C_Master_Transmit()
995 (++) HAL_I2C_Master_Receive()
996 (++) HAL_I2C_Slave_Transmit()
997 (++) HAL_I2C_Slave_Receive()
998 (++) HAL_I2C_Mem_Write()
999 (++) HAL_I2C_Mem_Read()
1000 (++) HAL_I2C_IsDeviceReady()
1001
1002 (#) No-Blocking mode functions with Interrupt are :
1003 (++) HAL_I2C_Master_Transmit_IT()
1004 (++) HAL_I2C_Master_Receive_IT()
1005 (++) HAL_I2C_Slave_Transmit_IT()
1006 (++) HAL_I2C_Slave_Receive_IT()
1007 (++) HAL_I2C_Mem_Write_IT()
1008 (++) HAL_I2C_Mem_Read_IT()
1009 (++) HAL_I2C_Master_Seq_Transmit_IT()
1010 (++) HAL_I2C_Master_Seq_Receive_IT()
1011 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1012 (++) HAL_I2C_Slave_Seq_Receive_IT()
1013 (++) HAL_I2C_EnableListen_IT()
1014 (++) HAL_I2C_DisableListen_IT()
1015 (++) HAL_I2C_Master_Abort_IT()
1016
1017 (#) No-Blocking mode functions with DMA are :
1018 (++) HAL_I2C_Master_Transmit_DMA()
1019 (++) HAL_I2C_Master_Receive_DMA()
1020 (++) HAL_I2C_Slave_Transmit_DMA()
1021 (++) HAL_I2C_Slave_Receive_DMA()
1022 (++) HAL_I2C_Mem_Write_DMA()
1023 (++) HAL_I2C_Mem_Read_DMA()
1024 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1025 (++) HAL_I2C_Master_Seq_Receive_DMA()
1026 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1027 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1028
1029 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1030 (++) HAL_I2C_MasterTxCpltCallback()
1031 (++) HAL_I2C_MasterRxCpltCallback()
1032 (++) HAL_I2C_SlaveTxCpltCallback()
1033 (++) HAL_I2C_SlaveRxCpltCallback()
1034 (++) HAL_I2C_MemTxCpltCallback()
1035 (++) HAL_I2C_MemRxCpltCallback()
1036 (++) HAL_I2C_AddrCallback()
1037 (++) HAL_I2C_ListenCpltCallback()
1038 (++) HAL_I2C_ErrorCallback()
1039 (++) HAL_I2C_AbortCpltCallback()
1040
1041 @endverbatim
1042 * @{
1043 */
1044
1045 /**
1046 * @brief Transmits in master mode an amount of data in blocking mode.
1047 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1048 * the configuration information for the specified I2C.
1049 * @param DevAddress Target device address: The device 7 bits address value
1050 * in datasheet must be shifted to the left before calling the interface
1051 * @param pData Pointer to data buffer
1052 * @param Size Amount of data to be sent
1053 * @param Timeout Timeout duration
1054 * @retval HAL status
1055 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1056 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1057 {
1058 /* Init tickstart for timeout management*/
1059 uint32_t tickstart = HAL_GetTick();
1060
1061 if (hi2c->State == HAL_I2C_STATE_READY)
1062 {
1063 /* Wait until BUSY flag is reset */
1064 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1065 {
1066 return HAL_BUSY;
1067 }
1068
1069 /* Process Locked */
1070 __HAL_LOCK(hi2c);
1071
1072 /* Check if the I2C is already enabled */
1073 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1074 {
1075 /* Enable I2C peripheral */
1076 __HAL_I2C_ENABLE(hi2c);
1077 }
1078
1079 /* Disable Pos */
1080 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1081
1082 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1083 hi2c->Mode = HAL_I2C_MODE_MASTER;
1084 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1085
1086 /* Prepare transfer parameters */
1087 hi2c->pBuffPtr = pData;
1088 hi2c->XferCount = Size;
1089 hi2c->XferSize = hi2c->XferCount;
1090 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1091
1092 /* Send Slave Address */
1093 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1094 {
1095 return HAL_ERROR;
1096 }
1097
1098 /* Clear ADDR flag */
1099 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1100
1101 while (hi2c->XferSize > 0U)
1102 {
1103 /* Wait until TXE flag is set */
1104 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1105 {
1106 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1107 {
1108 /* Generate Stop */
1109 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1110 }
1111 return HAL_ERROR;
1112 }
1113
1114 /* Write data to DR */
1115 hi2c->Instance->DR = *hi2c->pBuffPtr;
1116
1117 /* Increment Buffer pointer */
1118 hi2c->pBuffPtr++;
1119
1120 /* Update counter */
1121 hi2c->XferCount--;
1122 hi2c->XferSize--;
1123
1124 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1125 {
1126 /* Write data to DR */
1127 hi2c->Instance->DR = *hi2c->pBuffPtr;
1128
1129 /* Increment Buffer pointer */
1130 hi2c->pBuffPtr++;
1131
1132 /* Update counter */
1133 hi2c->XferCount--;
1134 hi2c->XferSize--;
1135 }
1136
1137 /* Wait until BTF flag is set */
1138 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1139 {
1140 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1141 {
1142 /* Generate Stop */
1143 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1144 }
1145 return HAL_ERROR;
1146 }
1147 }
1148
1149 /* Generate Stop */
1150 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1151
1152 hi2c->State = HAL_I2C_STATE_READY;
1153 hi2c->Mode = HAL_I2C_MODE_NONE;
1154
1155 /* Process Unlocked */
1156 __HAL_UNLOCK(hi2c);
1157
1158 return HAL_OK;
1159 }
1160 else
1161 {
1162 return HAL_BUSY;
1163 }
1164 }
1165
1166 /**
1167 * @brief Receives in master mode an amount of data in blocking mode.
1168 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1169 * the configuration information for the specified I2C.
1170 * @param DevAddress Target device address: The device 7 bits address value
1171 * in datasheet must be shifted to the left before calling the interface
1172 * @param pData Pointer to data buffer
1173 * @param Size Amount of data to be sent
1174 * @param Timeout Timeout duration
1175 * @retval HAL status
1176 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1177 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1178 {
1179 /* Init tickstart for timeout management*/
1180 uint32_t tickstart = HAL_GetTick();
1181
1182 if (hi2c->State == HAL_I2C_STATE_READY)
1183 {
1184 /* Wait until BUSY flag is reset */
1185 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1186 {
1187 return HAL_BUSY;
1188 }
1189
1190 /* Process Locked */
1191 __HAL_LOCK(hi2c);
1192
1193 /* Check if the I2C is already enabled */
1194 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1195 {
1196 /* Enable I2C peripheral */
1197 __HAL_I2C_ENABLE(hi2c);
1198 }
1199
1200 /* Disable Pos */
1201 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1202
1203 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1204 hi2c->Mode = HAL_I2C_MODE_MASTER;
1205 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1206
1207 /* Prepare transfer parameters */
1208 hi2c->pBuffPtr = pData;
1209 hi2c->XferCount = Size;
1210 hi2c->XferSize = hi2c->XferCount;
1211 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1212
1213 /* Send Slave Address */
1214 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1215 {
1216 return HAL_ERROR;
1217 }
1218
1219 if (hi2c->XferSize == 0U)
1220 {
1221 /* Clear ADDR flag */
1222 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1223
1224 /* Generate Stop */
1225 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1226 }
1227 else if (hi2c->XferSize == 1U)
1228 {
1229 /* Disable Acknowledge */
1230 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1231
1232 /* Clear ADDR flag */
1233 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1234
1235 /* Generate Stop */
1236 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1237 }
1238 else if (hi2c->XferSize == 2U)
1239 {
1240 /* Disable Acknowledge */
1241 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1242
1243 /* Enable Pos */
1244 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1245
1246 /* Clear ADDR flag */
1247 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1248 }
1249 else
1250 {
1251 /* Enable Acknowledge */
1252 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1253
1254 /* Clear ADDR flag */
1255 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1256 }
1257
1258 while (hi2c->XferSize > 0U)
1259 {
1260 if (hi2c->XferSize <= 3U)
1261 {
1262 /* One byte */
1263 if (hi2c->XferSize == 1U)
1264 {
1265 /* Wait until RXNE flag is set */
1266 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1267 {
1268 return HAL_ERROR;
1269 }
1270
1271 /* Read data from DR */
1272 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1273
1274 /* Increment Buffer pointer */
1275 hi2c->pBuffPtr++;
1276
1277 /* Update counter */
1278 hi2c->XferSize--;
1279 hi2c->XferCount--;
1280 }
1281 /* Two bytes */
1282 else if (hi2c->XferSize == 2U)
1283 {
1284 /* Wait until BTF flag is set */
1285 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1286 {
1287 return HAL_ERROR;
1288 }
1289
1290 /* Generate Stop */
1291 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1292
1293 /* Read data from DR */
1294 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1295
1296 /* Increment Buffer pointer */
1297 hi2c->pBuffPtr++;
1298
1299 /* Update counter */
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 /* Read data from DR */
1304 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1305
1306 /* Increment Buffer pointer */
1307 hi2c->pBuffPtr++;
1308
1309 /* Update counter */
1310 hi2c->XferSize--;
1311 hi2c->XferCount--;
1312 }
1313 /* 3 Last bytes */
1314 else
1315 {
1316 /* Wait until BTF flag is set */
1317 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1318 {
1319 return HAL_ERROR;
1320 }
1321
1322 /* Disable Acknowledge */
1323 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1324
1325 /* Read data from DR */
1326 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1327
1328 /* Increment Buffer pointer */
1329 hi2c->pBuffPtr++;
1330
1331 /* Update counter */
1332 hi2c->XferSize--;
1333 hi2c->XferCount--;
1334
1335 /* Wait until BTF flag is set */
1336 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1337 {
1338 return HAL_ERROR;
1339 }
1340
1341 /* Generate Stop */
1342 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1343
1344 /* Read data from DR */
1345 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1346
1347 /* Increment Buffer pointer */
1348 hi2c->pBuffPtr++;
1349
1350 /* Update counter */
1351 hi2c->XferSize--;
1352 hi2c->XferCount--;
1353
1354 /* Read data from DR */
1355 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1356
1357 /* Increment Buffer pointer */
1358 hi2c->pBuffPtr++;
1359
1360 /* Update counter */
1361 hi2c->XferSize--;
1362 hi2c->XferCount--;
1363 }
1364 }
1365 else
1366 {
1367 /* Wait until RXNE flag is set */
1368 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1369 {
1370 return HAL_ERROR;
1371 }
1372
1373 /* Read data from DR */
1374 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1375
1376 /* Increment Buffer pointer */
1377 hi2c->pBuffPtr++;
1378
1379 /* Update counter */
1380 hi2c->XferSize--;
1381 hi2c->XferCount--;
1382
1383 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1384 {
1385
1386 if (hi2c->XferSize == 3U)
1387 {
1388 /* Disable Acknowledge */
1389 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1390 }
1391
1392 /* Read data from DR */
1393 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1394
1395 /* Increment Buffer pointer */
1396 hi2c->pBuffPtr++;
1397
1398 /* Update counter */
1399 hi2c->XferSize--;
1400 hi2c->XferCount--;
1401 }
1402 }
1403 }
1404
1405 hi2c->State = HAL_I2C_STATE_READY;
1406 hi2c->Mode = HAL_I2C_MODE_NONE;
1407
1408 /* Process Unlocked */
1409 __HAL_UNLOCK(hi2c);
1410
1411 return HAL_OK;
1412 }
1413 else
1414 {
1415 return HAL_BUSY;
1416 }
1417 }
1418
1419 /**
1420 * @brief Transmits in slave mode an amount of data in blocking mode.
1421 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1422 * the configuration information for the specified I2C.
1423 * @param pData Pointer to data buffer
1424 * @param Size Amount of data to be sent
1425 * @param Timeout Timeout duration
1426 * @retval HAL status
1427 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1428 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1429 {
1430 /* Init tickstart for timeout management*/
1431 uint32_t tickstart = HAL_GetTick();
1432
1433 if (hi2c->State == HAL_I2C_STATE_READY)
1434 {
1435 if ((pData == NULL) || (Size == 0U))
1436 {
1437 return HAL_ERROR;
1438 }
1439
1440 /* Process Locked */
1441 __HAL_LOCK(hi2c);
1442
1443 /* Check if the I2C is already enabled */
1444 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1445 {
1446 /* Enable I2C peripheral */
1447 __HAL_I2C_ENABLE(hi2c);
1448 }
1449
1450 /* Disable Pos */
1451 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1452
1453 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1454 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1455 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1456
1457 /* Prepare transfer parameters */
1458 hi2c->pBuffPtr = pData;
1459 hi2c->XferCount = Size;
1460 hi2c->XferSize = hi2c->XferCount;
1461 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1462
1463 /* Enable Address Acknowledge */
1464 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1465
1466 /* Wait until ADDR flag is set */
1467 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1468 {
1469 return HAL_ERROR;
1470 }
1471
1472 /* Clear ADDR flag */
1473 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1474
1475 /* If 10bit addressing mode is selected */
1476 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1477 {
1478 /* Wait until ADDR flag is set */
1479 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1480 {
1481 return HAL_ERROR;
1482 }
1483
1484 /* Clear ADDR flag */
1485 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1486 }
1487
1488 while (hi2c->XferSize > 0U)
1489 {
1490 /* Wait until TXE flag is set */
1491 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1492 {
1493 /* Disable Address Acknowledge */
1494 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1495
1496 return HAL_ERROR;
1497 }
1498
1499 /* Write data to DR */
1500 hi2c->Instance->DR = *hi2c->pBuffPtr;
1501
1502 /* Increment Buffer pointer */
1503 hi2c->pBuffPtr++;
1504
1505 /* Update counter */
1506 hi2c->XferCount--;
1507 hi2c->XferSize--;
1508
1509 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1510 {
1511 /* Write data to DR */
1512 hi2c->Instance->DR = *hi2c->pBuffPtr;
1513
1514 /* Increment Buffer pointer */
1515 hi2c->pBuffPtr++;
1516
1517 /* Update counter */
1518 hi2c->XferCount--;
1519 hi2c->XferSize--;
1520 }
1521 }
1522
1523 /* Wait until AF flag is set */
1524 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1525 {
1526 return HAL_ERROR;
1527 }
1528
1529 /* Clear AF flag */
1530 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1531
1532 /* Disable Address Acknowledge */
1533 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1534
1535 hi2c->State = HAL_I2C_STATE_READY;
1536 hi2c->Mode = HAL_I2C_MODE_NONE;
1537
1538 /* Process Unlocked */
1539 __HAL_UNLOCK(hi2c);
1540
1541 return HAL_OK;
1542 }
1543 else
1544 {
1545 return HAL_BUSY;
1546 }
1547 }
1548
1549 /**
1550 * @brief Receive in slave mode an amount of data in blocking mode
1551 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1552 * the configuration information for the specified I2C.
1553 * @param pData Pointer to data buffer
1554 * @param Size Amount of data to be sent
1555 * @param Timeout Timeout duration
1556 * @retval HAL status
1557 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1558 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1559 {
1560 /* Init tickstart for timeout management*/
1561 uint32_t tickstart = HAL_GetTick();
1562
1563 if (hi2c->State == HAL_I2C_STATE_READY)
1564 {
1565 if ((pData == NULL) || (Size == (uint16_t)0))
1566 {
1567 return HAL_ERROR;
1568 }
1569
1570 /* Process Locked */
1571 __HAL_LOCK(hi2c);
1572
1573 /* Check if the I2C is already enabled */
1574 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1575 {
1576 /* Enable I2C peripheral */
1577 __HAL_I2C_ENABLE(hi2c);
1578 }
1579
1580 /* Disable Pos */
1581 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1582
1583 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1584 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1585 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1586
1587 /* Prepare transfer parameters */
1588 hi2c->pBuffPtr = pData;
1589 hi2c->XferCount = Size;
1590 hi2c->XferSize = hi2c->XferCount;
1591 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1592
1593 /* Enable Address Acknowledge */
1594 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1595
1596 /* Wait until ADDR flag is set */
1597 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1598 {
1599 return HAL_ERROR;
1600 }
1601
1602 /* Clear ADDR flag */
1603 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1604
1605 while (hi2c->XferSize > 0U)
1606 {
1607 /* Wait until RXNE flag is set */
1608 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1609 {
1610 /* Disable Address Acknowledge */
1611 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1612
1613 return HAL_ERROR;
1614 }
1615
1616 /* Read data from DR */
1617 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1618
1619 /* Increment Buffer pointer */
1620 hi2c->pBuffPtr++;
1621
1622 /* Update counter */
1623 hi2c->XferSize--;
1624 hi2c->XferCount--;
1625
1626 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1627 {
1628 /* Read data from DR */
1629 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1630
1631 /* Increment Buffer pointer */
1632 hi2c->pBuffPtr++;
1633
1634 /* Update counter */
1635 hi2c->XferSize--;
1636 hi2c->XferCount--;
1637 }
1638 }
1639
1640 /* Wait until STOP flag is set */
1641 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1642 {
1643 /* Disable Address Acknowledge */
1644 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1645
1646 return HAL_ERROR;
1647 }
1648
1649 /* Clear STOP flag */
1650 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1651
1652 /* Disable Address Acknowledge */
1653 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1654
1655 hi2c->State = HAL_I2C_STATE_READY;
1656 hi2c->Mode = HAL_I2C_MODE_NONE;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_OK;
1662 }
1663 else
1664 {
1665 return HAL_BUSY;
1666 }
1667 }
1668
1669 /**
1670 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1671 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1672 * the configuration information for the specified I2C.
1673 * @param DevAddress Target device address: The device 7 bits address value
1674 * in datasheet must be shifted to the left before calling the interface
1675 * @param pData Pointer to data buffer
1676 * @param Size Amount of data to be sent
1677 * @retval HAL status
1678 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1679 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1680 {
1681 __IO uint32_t count = 0U;
1682
1683 if (hi2c->State == HAL_I2C_STATE_READY)
1684 {
1685 /* Wait until BUSY flag is reset */
1686 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1687 do
1688 {
1689 count--;
1690 if (count == 0U)
1691 {
1692 hi2c->PreviousState = I2C_STATE_NONE;
1693 hi2c->State = HAL_I2C_STATE_READY;
1694 hi2c->Mode = HAL_I2C_MODE_NONE;
1695 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1696
1697 return HAL_BUSY;
1698 }
1699 }
1700 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1701
1702 /* Process Locked */
1703 __HAL_LOCK(hi2c);
1704
1705 /* Check if the I2C is already enabled */
1706 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1707 {
1708 /* Enable I2C peripheral */
1709 __HAL_I2C_ENABLE(hi2c);
1710 }
1711
1712 /* Disable Pos */
1713 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1714
1715 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1716 hi2c->Mode = HAL_I2C_MODE_MASTER;
1717 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1718
1719 /* Prepare transfer parameters */
1720 hi2c->pBuffPtr = pData;
1721 hi2c->XferCount = Size;
1722 hi2c->XferSize = hi2c->XferCount;
1723 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1724 hi2c->Devaddress = DevAddress;
1725
1726 /* Process Unlocked */
1727 __HAL_UNLOCK(hi2c);
1728
1729 /* Note : The I2C interrupts must be enabled after unlocking current process
1730 to avoid the risk of I2C interrupt handle execution before current
1731 process unlock */
1732 /* Enable EVT, BUF and ERR interrupt */
1733 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1734
1735 /* Generate Start */
1736 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1737
1738 return HAL_OK;
1739 }
1740 else
1741 {
1742 return HAL_BUSY;
1743 }
1744 }
1745
1746 /**
1747 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1748 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1749 * the configuration information for the specified I2C.
1750 * @param DevAddress Target device address: The device 7 bits address value
1751 * in datasheet must be shifted to the left before calling the interface
1752 * @param pData Pointer to data buffer
1753 * @param Size Amount of data to be sent
1754 * @retval HAL status
1755 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1756 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1757 {
1758 __IO uint32_t count = 0U;
1759
1760 if (hi2c->State == HAL_I2C_STATE_READY)
1761 {
1762 /* Wait until BUSY flag is reset */
1763 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1764 do
1765 {
1766 count--;
1767 if (count == 0U)
1768 {
1769 hi2c->PreviousState = I2C_STATE_NONE;
1770 hi2c->State = HAL_I2C_STATE_READY;
1771 hi2c->Mode = HAL_I2C_MODE_NONE;
1772 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1773
1774 return HAL_BUSY;
1775 }
1776 }
1777 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1778
1779 /* Process Locked */
1780 __HAL_LOCK(hi2c);
1781
1782 /* Check if the I2C is already enabled */
1783 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1784 {
1785 /* Enable I2C peripheral */
1786 __HAL_I2C_ENABLE(hi2c);
1787 }
1788
1789 /* Disable Pos */
1790 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1791
1792 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1793 hi2c->Mode = HAL_I2C_MODE_MASTER;
1794 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1795
1796 /* Prepare transfer parameters */
1797 hi2c->pBuffPtr = pData;
1798 hi2c->XferCount = Size;
1799 hi2c->XferSize = hi2c->XferCount;
1800 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1801 hi2c->Devaddress = DevAddress;
1802
1803
1804 /* Process Unlocked */
1805 __HAL_UNLOCK(hi2c);
1806
1807 /* Note : The I2C interrupts must be enabled after unlocking current process
1808 to avoid the risk of I2C interrupt handle execution before current
1809 process unlock */
1810
1811 /* Enable EVT, BUF and ERR interrupt */
1812 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1813
1814 /* Enable Acknowledge */
1815 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1816
1817 /* Generate Start */
1818 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1819
1820 return HAL_OK;
1821 }
1822 else
1823 {
1824 return HAL_BUSY;
1825 }
1826 }
1827
1828 /**
1829 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1830 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1831 * the configuration information for the specified I2C.
1832 * @param pData Pointer to data buffer
1833 * @param Size Amount of data to be sent
1834 * @retval HAL status
1835 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1836 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1837 {
1838
1839 if (hi2c->State == HAL_I2C_STATE_READY)
1840 {
1841 if ((pData == NULL) || (Size == 0U))
1842 {
1843 return HAL_ERROR;
1844 }
1845
1846 /* Process Locked */
1847 __HAL_LOCK(hi2c);
1848
1849 /* Check if the I2C is already enabled */
1850 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1851 {
1852 /* Enable I2C peripheral */
1853 __HAL_I2C_ENABLE(hi2c);
1854 }
1855
1856 /* Disable Pos */
1857 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1858
1859 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1860 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1861 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1862
1863 /* Prepare transfer parameters */
1864 hi2c->pBuffPtr = pData;
1865 hi2c->XferCount = Size;
1866 hi2c->XferSize = hi2c->XferCount;
1867 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1868
1869 /* Enable Address Acknowledge */
1870 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1871
1872 /* Process Unlocked */
1873 __HAL_UNLOCK(hi2c);
1874
1875 /* Note : The I2C interrupts must be enabled after unlocking current process
1876 to avoid the risk of I2C interrupt handle execution before current
1877 process unlock */
1878
1879 /* Enable EVT, BUF and ERR interrupt */
1880 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1881
1882 return HAL_OK;
1883 }
1884 else
1885 {
1886 return HAL_BUSY;
1887 }
1888 }
1889
1890 /**
1891 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1892 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1893 * the configuration information for the specified I2C.
1894 * @param pData Pointer to data buffer
1895 * @param Size Amount of data to be sent
1896 * @retval HAL status
1897 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1898 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1899 {
1900
1901 if (hi2c->State == HAL_I2C_STATE_READY)
1902 {
1903 if ((pData == NULL) || (Size == 0U))
1904 {
1905 return HAL_ERROR;
1906 }
1907
1908 /* Process Locked */
1909 __HAL_LOCK(hi2c);
1910
1911 /* Check if the I2C is already enabled */
1912 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1913 {
1914 /* Enable I2C peripheral */
1915 __HAL_I2C_ENABLE(hi2c);
1916 }
1917
1918 /* Disable Pos */
1919 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1920
1921 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1922 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1923 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1924
1925 /* Prepare transfer parameters */
1926 hi2c->pBuffPtr = pData;
1927 hi2c->XferCount = Size;
1928 hi2c->XferSize = hi2c->XferCount;
1929 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1930
1931 /* Enable Address Acknowledge */
1932 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1933
1934 /* Process Unlocked */
1935 __HAL_UNLOCK(hi2c);
1936
1937 /* Note : The I2C interrupts must be enabled after unlocking current process
1938 to avoid the risk of I2C interrupt handle execution before current
1939 process unlock */
1940
1941 /* Enable EVT, BUF and ERR interrupt */
1942 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1943
1944 return HAL_OK;
1945 }
1946 else
1947 {
1948 return HAL_BUSY;
1949 }
1950 }
1951
1952 /**
1953 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1954 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1955 * the configuration information for the specified I2C.
1956 * @param DevAddress Target device address: The device 7 bits address value
1957 * in datasheet must be shifted to the left before calling the interface
1958 * @param pData Pointer to data buffer
1959 * @param Size Amount of data to be sent
1960 * @retval HAL status
1961 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1962 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1963 {
1964 __IO uint32_t count = 0U;
1965 HAL_StatusTypeDef dmaxferstatus;
1966
1967 if (hi2c->State == HAL_I2C_STATE_READY)
1968 {
1969 /* Wait until BUSY flag is reset */
1970 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1971 do
1972 {
1973 count--;
1974 if (count == 0U)
1975 {
1976 hi2c->PreviousState = I2C_STATE_NONE;
1977 hi2c->State = HAL_I2C_STATE_READY;
1978 hi2c->Mode = HAL_I2C_MODE_NONE;
1979 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1980
1981 return HAL_BUSY;
1982 }
1983 }
1984 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1985
1986 /* Process Locked */
1987 __HAL_LOCK(hi2c);
1988
1989 /* Check if the I2C is already enabled */
1990 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1991 {
1992 /* Enable I2C peripheral */
1993 __HAL_I2C_ENABLE(hi2c);
1994 }
1995
1996 /* Disable Pos */
1997 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1998
1999 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2000 hi2c->Mode = HAL_I2C_MODE_MASTER;
2001 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2002
2003 /* Prepare transfer parameters */
2004 hi2c->pBuffPtr = pData;
2005 hi2c->XferCount = Size;
2006 hi2c->XferSize = hi2c->XferCount;
2007 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2008 hi2c->Devaddress = DevAddress;
2009
2010 if (hi2c->XferSize > 0U)
2011 {
2012 if (hi2c->hdmatx != NULL)
2013 {
2014 /* Set the I2C DMA transfer complete callback */
2015 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2016
2017 /* Set the DMA error callback */
2018 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2019
2020 /* Set the unused DMA callbacks to NULL */
2021 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2022 hi2c->hdmatx->XferM1CpltCallback = NULL;
2023 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2024 hi2c->hdmatx->XferAbortCallback = NULL;
2025
2026 /* Enable the DMA stream */
2027 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2028 }
2029 else
2030 {
2031 /* Update I2C state */
2032 hi2c->State = HAL_I2C_STATE_READY;
2033 hi2c->Mode = HAL_I2C_MODE_NONE;
2034
2035 /* Update I2C error code */
2036 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2037
2038 /* Process Unlocked */
2039 __HAL_UNLOCK(hi2c);
2040
2041 return HAL_ERROR;
2042 }
2043
2044 if (dmaxferstatus == HAL_OK)
2045 {
2046 /* Process Unlocked */
2047 __HAL_UNLOCK(hi2c);
2048
2049 /* Note : The I2C interrupts must be enabled after unlocking current process
2050 to avoid the risk of I2C interrupt handle execution before current
2051 process unlock */
2052
2053 /* Enable EVT and ERR interrupt */
2054 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2055
2056 /* Enable DMA Request */
2057 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2058
2059 /* Enable Acknowledge */
2060 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2061
2062 /* Generate Start */
2063 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2064 }
2065 else
2066 {
2067 /* Update I2C state */
2068 hi2c->State = HAL_I2C_STATE_READY;
2069 hi2c->Mode = HAL_I2C_MODE_NONE;
2070
2071 /* Update I2C error code */
2072 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2073
2074 /* Process Unlocked */
2075 __HAL_UNLOCK(hi2c);
2076
2077 return HAL_ERROR;
2078 }
2079 }
2080 else
2081 {
2082 /* Enable Acknowledge */
2083 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2084
2085 /* Generate Start */
2086 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2087
2088 /* Process Unlocked */
2089 __HAL_UNLOCK(hi2c);
2090
2091 /* Note : The I2C interrupts must be enabled after unlocking current process
2092 to avoid the risk of I2C interrupt handle execution before current
2093 process unlock */
2094
2095 /* Enable EVT, BUF and ERR interrupt */
2096 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2097 }
2098
2099 return HAL_OK;
2100 }
2101 else
2102 {
2103 return HAL_BUSY;
2104 }
2105 }
2106
2107 /**
2108 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2109 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2110 * the configuration information for the specified I2C.
2111 * @param DevAddress Target device address: The device 7 bits address value
2112 * in datasheet must be shifted to the left before calling the interface
2113 * @param pData Pointer to data buffer
2114 * @param Size Amount of data to be sent
2115 * @retval HAL status
2116 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2117 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2118 {
2119 __IO uint32_t count = 0U;
2120 HAL_StatusTypeDef dmaxferstatus;
2121
2122 if (hi2c->State == HAL_I2C_STATE_READY)
2123 {
2124 /* Wait until BUSY flag is reset */
2125 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2126 do
2127 {
2128 count--;
2129 if (count == 0U)
2130 {
2131 hi2c->PreviousState = I2C_STATE_NONE;
2132 hi2c->State = HAL_I2C_STATE_READY;
2133 hi2c->Mode = HAL_I2C_MODE_NONE;
2134 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2135
2136 return HAL_BUSY;
2137 }
2138 }
2139 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2140
2141 /* Process Locked */
2142 __HAL_LOCK(hi2c);
2143
2144 /* Check if the I2C is already enabled */
2145 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2146 {
2147 /* Enable I2C peripheral */
2148 __HAL_I2C_ENABLE(hi2c);
2149 }
2150
2151 /* Disable Pos */
2152 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2153
2154 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2155 hi2c->Mode = HAL_I2C_MODE_MASTER;
2156 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2157
2158 /* Prepare transfer parameters */
2159 hi2c->pBuffPtr = pData;
2160 hi2c->XferCount = Size;
2161 hi2c->XferSize = hi2c->XferCount;
2162 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2163 hi2c->Devaddress = DevAddress;
2164
2165 if (hi2c->XferSize > 0U)
2166 {
2167 if (hi2c->hdmarx != NULL)
2168 {
2169 /* Set the I2C DMA transfer complete callback */
2170 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2171
2172 /* Set the DMA error callback */
2173 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2174
2175 /* Set the unused DMA callbacks to NULL */
2176 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2177 hi2c->hdmarx->XferM1CpltCallback = NULL;
2178 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2179 hi2c->hdmarx->XferAbortCallback = NULL;
2180
2181 /* Enable the DMA stream */
2182 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2183 }
2184 else
2185 {
2186 /* Update I2C state */
2187 hi2c->State = HAL_I2C_STATE_READY;
2188 hi2c->Mode = HAL_I2C_MODE_NONE;
2189
2190 /* Update I2C error code */
2191 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2192
2193 /* Process Unlocked */
2194 __HAL_UNLOCK(hi2c);
2195
2196 return HAL_ERROR;
2197 }
2198
2199 if (dmaxferstatus == HAL_OK)
2200 {
2201 /* Enable Acknowledge */
2202 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2203
2204 /* Generate Start */
2205 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2206
2207 /* Process Unlocked */
2208 __HAL_UNLOCK(hi2c);
2209
2210 /* Note : The I2C interrupts must be enabled after unlocking current process
2211 to avoid the risk of I2C interrupt handle execution before current
2212 process unlock */
2213
2214 /* Enable EVT and ERR interrupt */
2215 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2216
2217 /* Enable DMA Request */
2218 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2219 }
2220 else
2221 {
2222 /* Update I2C state */
2223 hi2c->State = HAL_I2C_STATE_READY;
2224 hi2c->Mode = HAL_I2C_MODE_NONE;
2225
2226 /* Update I2C error code */
2227 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2228
2229 /* Process Unlocked */
2230 __HAL_UNLOCK(hi2c);
2231
2232 return HAL_ERROR;
2233 }
2234 }
2235 else
2236 {
2237 /* Process Unlocked */
2238 __HAL_UNLOCK(hi2c);
2239
2240 /* Note : The I2C interrupts must be enabled after unlocking current process
2241 to avoid the risk of I2C interrupt handle execution before current
2242 process unlock */
2243
2244 /* Enable EVT, BUF and ERR interrupt */
2245 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2246
2247 /* Enable Acknowledge */
2248 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2249
2250 /* Generate Start */
2251 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2252 }
2253
2254 return HAL_OK;
2255 }
2256 else
2257 {
2258 return HAL_BUSY;
2259 }
2260 }
2261
2262 /**
2263 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2264 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2265 * the configuration information for the specified I2C.
2266 * @param pData Pointer to data buffer
2267 * @param Size Amount of data to be sent
2268 * @retval HAL status
2269 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2270 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2271 {
2272 HAL_StatusTypeDef dmaxferstatus;
2273
2274 if (hi2c->State == HAL_I2C_STATE_READY)
2275 {
2276 if ((pData == NULL) || (Size == 0U))
2277 {
2278 return HAL_ERROR;
2279 }
2280
2281 /* Process Locked */
2282 __HAL_LOCK(hi2c);
2283
2284 /* Check if the I2C is already enabled */
2285 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2286 {
2287 /* Enable I2C peripheral */
2288 __HAL_I2C_ENABLE(hi2c);
2289 }
2290
2291 /* Disable Pos */
2292 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2293
2294 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2295 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2296 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2297
2298 /* Prepare transfer parameters */
2299 hi2c->pBuffPtr = pData;
2300 hi2c->XferCount = Size;
2301 hi2c->XferSize = hi2c->XferCount;
2302 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2303
2304 if (hi2c->hdmatx != NULL)
2305 {
2306 /* Set the I2C DMA transfer complete callback */
2307 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2308
2309 /* Set the DMA error callback */
2310 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2311
2312 /* Set the unused DMA callbacks to NULL */
2313 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2314 hi2c->hdmatx->XferM1CpltCallback = NULL;
2315 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2316 hi2c->hdmatx->XferAbortCallback = NULL;
2317
2318 /* Enable the DMA stream */
2319 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2320 }
2321 else
2322 {
2323 /* Update I2C state */
2324 hi2c->State = HAL_I2C_STATE_LISTEN;
2325 hi2c->Mode = HAL_I2C_MODE_NONE;
2326
2327 /* Update I2C error code */
2328 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2329
2330 /* Process Unlocked */
2331 __HAL_UNLOCK(hi2c);
2332
2333 return HAL_ERROR;
2334 }
2335
2336 if (dmaxferstatus == HAL_OK)
2337 {
2338 /* Enable Address Acknowledge */
2339 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2340
2341 /* Process Unlocked */
2342 __HAL_UNLOCK(hi2c);
2343
2344 /* Note : The I2C interrupts must be enabled after unlocking current process
2345 to avoid the risk of I2C interrupt handle execution before current
2346 process unlock */
2347 /* Enable EVT and ERR interrupt */
2348 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2349
2350 /* Enable DMA Request */
2351 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2352
2353 return HAL_OK;
2354 }
2355 else
2356 {
2357 /* Update I2C state */
2358 hi2c->State = HAL_I2C_STATE_READY;
2359 hi2c->Mode = HAL_I2C_MODE_NONE;
2360
2361 /* Update I2C error code */
2362 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2363
2364 /* Process Unlocked */
2365 __HAL_UNLOCK(hi2c);
2366
2367 return HAL_ERROR;
2368 }
2369 }
2370 else
2371 {
2372 return HAL_BUSY;
2373 }
2374 }
2375
2376 /**
2377 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2378 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2379 * the configuration information for the specified I2C.
2380 * @param pData Pointer to data buffer
2381 * @param Size Amount of data to be sent
2382 * @retval HAL status
2383 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2384 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2385 {
2386 HAL_StatusTypeDef dmaxferstatus;
2387
2388 if (hi2c->State == HAL_I2C_STATE_READY)
2389 {
2390 if ((pData == NULL) || (Size == 0U))
2391 {
2392 return HAL_ERROR;
2393 }
2394
2395 /* Process Locked */
2396 __HAL_LOCK(hi2c);
2397
2398 /* Check if the I2C is already enabled */
2399 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2400 {
2401 /* Enable I2C peripheral */
2402 __HAL_I2C_ENABLE(hi2c);
2403 }
2404
2405 /* Disable Pos */
2406 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2407
2408 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2409 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2410 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2411
2412 /* Prepare transfer parameters */
2413 hi2c->pBuffPtr = pData;
2414 hi2c->XferCount = Size;
2415 hi2c->XferSize = hi2c->XferCount;
2416 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2417
2418 if (hi2c->hdmarx != NULL)
2419 {
2420 /* Set the I2C DMA transfer complete callback */
2421 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2422
2423 /* Set the DMA error callback */
2424 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2425
2426 /* Set the unused DMA callbacks to NULL */
2427 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2428 hi2c->hdmarx->XferM1CpltCallback = NULL;
2429 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2430 hi2c->hdmarx->XferAbortCallback = NULL;
2431
2432 /* Enable the DMA stream */
2433 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2434 }
2435 else
2436 {
2437 /* Update I2C state */
2438 hi2c->State = HAL_I2C_STATE_LISTEN;
2439 hi2c->Mode = HAL_I2C_MODE_NONE;
2440
2441 /* Update I2C error code */
2442 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2443
2444 /* Process Unlocked */
2445 __HAL_UNLOCK(hi2c);
2446
2447 return HAL_ERROR;
2448 }
2449
2450 if (dmaxferstatus == HAL_OK)
2451 {
2452 /* Enable Address Acknowledge */
2453 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2454
2455 /* Process Unlocked */
2456 __HAL_UNLOCK(hi2c);
2457
2458 /* Note : The I2C interrupts must be enabled after unlocking current process
2459 to avoid the risk of I2C interrupt handle execution before current
2460 process unlock */
2461 /* Enable EVT and ERR interrupt */
2462 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2463
2464 /* Enable DMA Request */
2465 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2466
2467 return HAL_OK;
2468 }
2469 else
2470 {
2471 /* Update I2C state */
2472 hi2c->State = HAL_I2C_STATE_READY;
2473 hi2c->Mode = HAL_I2C_MODE_NONE;
2474
2475 /* Update I2C error code */
2476 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2477
2478 /* Process Unlocked */
2479 __HAL_UNLOCK(hi2c);
2480
2481 return HAL_ERROR;
2482 }
2483 }
2484 else
2485 {
2486 return HAL_BUSY;
2487 }
2488 }
2489
2490 /**
2491 * @brief Write an amount of data in blocking mode to a specific memory address
2492 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2493 * the configuration information for the specified I2C.
2494 * @param DevAddress Target device address: The device 7 bits address value
2495 * in datasheet must be shifted to the left before calling the interface
2496 * @param MemAddress Internal memory address
2497 * @param MemAddSize Size of internal memory address
2498 * @param pData Pointer to data buffer
2499 * @param Size Amount of data to be sent
2500 * @param Timeout Timeout duration
2501 * @retval HAL status
2502 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2503 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2504 {
2505 /* Init tickstart for timeout management*/
2506 uint32_t tickstart = HAL_GetTick();
2507
2508 /* Check the parameters */
2509 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2510
2511 if (hi2c->State == HAL_I2C_STATE_READY)
2512 {
2513 /* Wait until BUSY flag is reset */
2514 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2515 {
2516 return HAL_BUSY;
2517 }
2518
2519 /* Process Locked */
2520 __HAL_LOCK(hi2c);
2521
2522 /* Check if the I2C is already enabled */
2523 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2524 {
2525 /* Enable I2C peripheral */
2526 __HAL_I2C_ENABLE(hi2c);
2527 }
2528
2529 /* Disable Pos */
2530 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2531
2532 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2533 hi2c->Mode = HAL_I2C_MODE_MEM;
2534 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2535
2536 /* Prepare transfer parameters */
2537 hi2c->pBuffPtr = pData;
2538 hi2c->XferCount = Size;
2539 hi2c->XferSize = hi2c->XferCount;
2540 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2541
2542 /* Send Slave Address and Memory Address */
2543 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2544 {
2545 return HAL_ERROR;
2546 }
2547
2548 while (hi2c->XferSize > 0U)
2549 {
2550 /* Wait until TXE flag is set */
2551 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2552 {
2553 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2554 {
2555 /* Generate Stop */
2556 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2557 }
2558 return HAL_ERROR;
2559 }
2560
2561 /* Write data to DR */
2562 hi2c->Instance->DR = *hi2c->pBuffPtr;
2563
2564 /* Increment Buffer pointer */
2565 hi2c->pBuffPtr++;
2566
2567 /* Update counter */
2568 hi2c->XferSize--;
2569 hi2c->XferCount--;
2570
2571 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2572 {
2573 /* Write data to DR */
2574 hi2c->Instance->DR = *hi2c->pBuffPtr;
2575
2576 /* Increment Buffer pointer */
2577 hi2c->pBuffPtr++;
2578
2579 /* Update counter */
2580 hi2c->XferSize--;
2581 hi2c->XferCount--;
2582 }
2583 }
2584
2585 /* Wait until BTF flag is set */
2586 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2587 {
2588 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2589 {
2590 /* Generate Stop */
2591 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2592 }
2593 return HAL_ERROR;
2594 }
2595
2596 /* Generate Stop */
2597 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2598
2599 hi2c->State = HAL_I2C_STATE_READY;
2600 hi2c->Mode = HAL_I2C_MODE_NONE;
2601
2602 /* Process Unlocked */
2603 __HAL_UNLOCK(hi2c);
2604
2605 return HAL_OK;
2606 }
2607 else
2608 {
2609 return HAL_BUSY;
2610 }
2611 }
2612
2613 /**
2614 * @brief Read an amount of data in blocking mode from a specific memory address
2615 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2616 * the configuration information for the specified I2C.
2617 * @param DevAddress Target device address: The device 7 bits address value
2618 * in datasheet must be shifted to the left before calling the interface
2619 * @param MemAddress Internal memory address
2620 * @param MemAddSize Size of internal memory address
2621 * @param pData Pointer to data buffer
2622 * @param Size Amount of data to be sent
2623 * @param Timeout Timeout duration
2624 * @retval HAL status
2625 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2626 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2627 {
2628 /* Init tickstart for timeout management*/
2629 uint32_t tickstart = HAL_GetTick();
2630
2631 /* Check the parameters */
2632 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2633
2634 if (hi2c->State == HAL_I2C_STATE_READY)
2635 {
2636 /* Wait until BUSY flag is reset */
2637 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2638 {
2639 return HAL_BUSY;
2640 }
2641
2642 /* Process Locked */
2643 __HAL_LOCK(hi2c);
2644
2645 /* Check if the I2C is already enabled */
2646 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2647 {
2648 /* Enable I2C peripheral */
2649 __HAL_I2C_ENABLE(hi2c);
2650 }
2651
2652 /* Disable Pos */
2653 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2654
2655 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2656 hi2c->Mode = HAL_I2C_MODE_MEM;
2657 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2658
2659 /* Prepare transfer parameters */
2660 hi2c->pBuffPtr = pData;
2661 hi2c->XferCount = Size;
2662 hi2c->XferSize = hi2c->XferCount;
2663 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2664
2665 /* Send Slave Address and Memory Address */
2666 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2667 {
2668 return HAL_ERROR;
2669 }
2670
2671 if (hi2c->XferSize == 0U)
2672 {
2673 /* Clear ADDR flag */
2674 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2675
2676 /* Generate Stop */
2677 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2678 }
2679 else if (hi2c->XferSize == 1U)
2680 {
2681 /* Disable Acknowledge */
2682 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2683
2684 /* Clear ADDR flag */
2685 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2686
2687 /* Generate Stop */
2688 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2689 }
2690 else if (hi2c->XferSize == 2U)
2691 {
2692 /* Disable Acknowledge */
2693 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2694
2695 /* Enable Pos */
2696 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2697
2698 /* Clear ADDR flag */
2699 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2700 }
2701 else
2702 {
2703 /* Clear ADDR flag */
2704 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2705 }
2706
2707 while (hi2c->XferSize > 0U)
2708 {
2709 if (hi2c->XferSize <= 3U)
2710 {
2711 /* One byte */
2712 if (hi2c->XferSize == 1U)
2713 {
2714 /* Wait until RXNE flag is set */
2715 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2716 {
2717 return HAL_ERROR;
2718 }
2719
2720 /* Read data from DR */
2721 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2722
2723 /* Increment Buffer pointer */
2724 hi2c->pBuffPtr++;
2725
2726 /* Update counter */
2727 hi2c->XferSize--;
2728 hi2c->XferCount--;
2729 }
2730 /* Two bytes */
2731 else if (hi2c->XferSize == 2U)
2732 {
2733 /* Wait until BTF flag is set */
2734 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2735 {
2736 return HAL_ERROR;
2737 }
2738
2739 /* Generate Stop */
2740 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2741
2742 /* Read data from DR */
2743 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2744
2745 /* Increment Buffer pointer */
2746 hi2c->pBuffPtr++;
2747
2748 /* Update counter */
2749 hi2c->XferSize--;
2750 hi2c->XferCount--;
2751
2752 /* Read data from DR */
2753 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2754
2755 /* Increment Buffer pointer */
2756 hi2c->pBuffPtr++;
2757
2758 /* Update counter */
2759 hi2c->XferSize--;
2760 hi2c->XferCount--;
2761 }
2762 /* 3 Last bytes */
2763 else
2764 {
2765 /* Wait until BTF flag is set */
2766 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2767 {
2768 return HAL_ERROR;
2769 }
2770
2771 /* Disable Acknowledge */
2772 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2773
2774 /* Read data from DR */
2775 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2776
2777 /* Increment Buffer pointer */
2778 hi2c->pBuffPtr++;
2779
2780 /* Update counter */
2781 hi2c->XferSize--;
2782 hi2c->XferCount--;
2783
2784 /* Wait until BTF flag is set */
2785 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2786 {
2787 return HAL_ERROR;
2788 }
2789
2790 /* Generate Stop */
2791 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2792
2793 /* Read data from DR */
2794 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2795
2796 /* Increment Buffer pointer */
2797 hi2c->pBuffPtr++;
2798
2799 /* Update counter */
2800 hi2c->XferSize--;
2801 hi2c->XferCount--;
2802
2803 /* Read data from DR */
2804 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2805
2806 /* Increment Buffer pointer */
2807 hi2c->pBuffPtr++;
2808
2809 /* Update counter */
2810 hi2c->XferSize--;
2811 hi2c->XferCount--;
2812 }
2813 }
2814 else
2815 {
2816 /* Wait until RXNE flag is set */
2817 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2818 {
2819 return HAL_ERROR;
2820 }
2821
2822 /* Read data from DR */
2823 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2824
2825 /* Increment Buffer pointer */
2826 hi2c->pBuffPtr++;
2827
2828 /* Update counter */
2829 hi2c->XferSize--;
2830 hi2c->XferCount--;
2831
2832 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2833 {
2834 /* Read data from DR */
2835 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2836
2837 /* Increment Buffer pointer */
2838 hi2c->pBuffPtr++;
2839
2840 /* Update counter */
2841 hi2c->XferSize--;
2842 hi2c->XferCount--;
2843 }
2844 }
2845 }
2846
2847 hi2c->State = HAL_I2C_STATE_READY;
2848 hi2c->Mode = HAL_I2C_MODE_NONE;
2849
2850 /* Process Unlocked */
2851 __HAL_UNLOCK(hi2c);
2852
2853 return HAL_OK;
2854 }
2855 else
2856 {
2857 return HAL_BUSY;
2858 }
2859 }
2860
2861 /**
2862 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2863 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2864 * the configuration information for the specified I2C.
2865 * @param DevAddress Target device address: The device 7 bits address value
2866 * in datasheet must be shifted to the left before calling the interface
2867 * @param MemAddress Internal memory address
2868 * @param MemAddSize Size of internal memory address
2869 * @param pData Pointer to data buffer
2870 * @param Size Amount of data to be sent
2871 * @retval HAL status
2872 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2873 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2874 {
2875 __IO uint32_t count = 0U;
2876
2877 /* Check the parameters */
2878 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2879
2880 if (hi2c->State == HAL_I2C_STATE_READY)
2881 {
2882 /* Wait until BUSY flag is reset */
2883 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2884 do
2885 {
2886 count--;
2887 if (count == 0U)
2888 {
2889 hi2c->PreviousState = I2C_STATE_NONE;
2890 hi2c->State = HAL_I2C_STATE_READY;
2891 hi2c->Mode = HAL_I2C_MODE_NONE;
2892 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2893
2894 return HAL_BUSY;
2895 }
2896 }
2897 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2898
2899 /* Process Locked */
2900 __HAL_LOCK(hi2c);
2901
2902 /* Check if the I2C is already enabled */
2903 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2904 {
2905 /* Enable I2C peripheral */
2906 __HAL_I2C_ENABLE(hi2c);
2907 }
2908
2909 /* Disable Pos */
2910 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2911
2912 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2913 hi2c->Mode = HAL_I2C_MODE_MEM;
2914 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2915
2916 /* Prepare transfer parameters */
2917 hi2c->pBuffPtr = pData;
2918 hi2c->XferCount = Size;
2919 hi2c->XferSize = hi2c->XferCount;
2920 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2921 hi2c->Devaddress = DevAddress;
2922 hi2c->Memaddress = MemAddress;
2923 hi2c->MemaddSize = MemAddSize;
2924 hi2c->EventCount = 0U;
2925
2926 /* Generate Start */
2927 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2928
2929 /* Process Unlocked */
2930 __HAL_UNLOCK(hi2c);
2931
2932 /* Note : The I2C interrupts must be enabled after unlocking current process
2933 to avoid the risk of I2C interrupt handle execution before current
2934 process unlock */
2935
2936 /* Enable EVT, BUF and ERR interrupt */
2937 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2938
2939 return HAL_OK;
2940 }
2941 else
2942 {
2943 return HAL_BUSY;
2944 }
2945 }
2946
2947 /**
2948 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2950 * the configuration information for the specified I2C.
2951 * @param DevAddress Target device address
2952 * @param MemAddress Internal memory address
2953 * @param MemAddSize Size of internal memory address
2954 * @param pData Pointer to data buffer
2955 * @param Size Amount of data to be sent
2956 * @retval HAL status
2957 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2958 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2959 {
2960 __IO uint32_t count = 0U;
2961
2962 /* Check the parameters */
2963 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2964
2965 if (hi2c->State == HAL_I2C_STATE_READY)
2966 {
2967 /* Wait until BUSY flag is reset */
2968 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2969 do
2970 {
2971 count--;
2972 if (count == 0U)
2973 {
2974 hi2c->PreviousState = I2C_STATE_NONE;
2975 hi2c->State = HAL_I2C_STATE_READY;
2976 hi2c->Mode = HAL_I2C_MODE_NONE;
2977 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2978
2979 return HAL_BUSY;
2980 }
2981 }
2982 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2983
2984 /* Process Locked */
2985 __HAL_LOCK(hi2c);
2986
2987 /* Check if the I2C is already enabled */
2988 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2989 {
2990 /* Enable I2C peripheral */
2991 __HAL_I2C_ENABLE(hi2c);
2992 }
2993
2994 /* Disable Pos */
2995 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2996
2997 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2998 hi2c->Mode = HAL_I2C_MODE_MEM;
2999 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3000
3001 /* Prepare transfer parameters */
3002 hi2c->pBuffPtr = pData;
3003 hi2c->XferCount = Size;
3004 hi2c->XferSize = hi2c->XferCount;
3005 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3006 hi2c->Devaddress = DevAddress;
3007 hi2c->Memaddress = MemAddress;
3008 hi2c->MemaddSize = MemAddSize;
3009 hi2c->EventCount = 0U;
3010
3011 /* Enable Acknowledge */
3012 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3013
3014 /* Generate Start */
3015 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3016
3017 /* Process Unlocked */
3018 __HAL_UNLOCK(hi2c);
3019
3020 if (hi2c->XferSize > 0U)
3021 {
3022 /* Note : The I2C interrupts must be enabled after unlocking current process
3023 to avoid the risk of I2C interrupt handle execution before current
3024 process unlock */
3025
3026 /* Enable EVT, BUF and ERR interrupt */
3027 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3028 }
3029 return HAL_OK;
3030 }
3031 else
3032 {
3033 return HAL_BUSY;
3034 }
3035 }
3036
3037 /**
3038 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3039 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3040 * the configuration information for the specified I2C.
3041 * @param DevAddress Target device address: The device 7 bits address value
3042 * in datasheet must be shifted to the left before calling the interface
3043 * @param MemAddress Internal memory address
3044 * @param MemAddSize Size of internal memory address
3045 * @param pData Pointer to data buffer
3046 * @param Size Amount of data to be sent
3047 * @retval HAL status
3048 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3049 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3050 {
3051 __IO uint32_t count = 0U;
3052 HAL_StatusTypeDef dmaxferstatus;
3053
3054 /* Init tickstart for timeout management*/
3055 uint32_t tickstart = HAL_GetTick();
3056
3057 /* Check the parameters */
3058 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3059
3060 if (hi2c->State == HAL_I2C_STATE_READY)
3061 {
3062 /* Wait until BUSY flag is reset */
3063 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3064 do
3065 {
3066 count--;
3067 if (count == 0U)
3068 {
3069 hi2c->PreviousState = I2C_STATE_NONE;
3070 hi2c->State = HAL_I2C_STATE_READY;
3071 hi2c->Mode = HAL_I2C_MODE_NONE;
3072 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3073
3074 return HAL_BUSY;
3075 }
3076 }
3077 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3078
3079 /* Process Locked */
3080 __HAL_LOCK(hi2c);
3081
3082 /* Check if the I2C is already enabled */
3083 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3084 {
3085 /* Enable I2C peripheral */
3086 __HAL_I2C_ENABLE(hi2c);
3087 }
3088
3089 /* Disable Pos */
3090 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3091
3092 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3093 hi2c->Mode = HAL_I2C_MODE_MEM;
3094 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3095
3096 /* Prepare transfer parameters */
3097 hi2c->pBuffPtr = pData;
3098 hi2c->XferCount = Size;
3099 hi2c->XferSize = hi2c->XferCount;
3100 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3101 hi2c->Devaddress = DevAddress;
3102 hi2c->Memaddress = MemAddress;
3103 hi2c->MemaddSize = MemAddSize;
3104 hi2c->EventCount = 0U;
3105
3106 if (hi2c->XferSize > 0U)
3107 {
3108 if (hi2c->hdmatx != NULL)
3109 {
3110 /* Set the I2C DMA transfer complete callback */
3111 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3112
3113 /* Set the DMA error callback */
3114 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3115
3116 /* Set the unused DMA callbacks to NULL */
3117 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3118 hi2c->hdmatx->XferM1CpltCallback = NULL;
3119 hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3120 hi2c->hdmatx->XferAbortCallback = NULL;
3121
3122 /* Enable the DMA stream */
3123 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3124 }
3125 else
3126 {
3127 /* Update I2C state */
3128 hi2c->State = HAL_I2C_STATE_READY;
3129 hi2c->Mode = HAL_I2C_MODE_NONE;
3130
3131 /* Update I2C error code */
3132 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3133
3134 /* Process Unlocked */
3135 __HAL_UNLOCK(hi2c);
3136
3137 return HAL_ERROR;
3138 }
3139
3140 if (dmaxferstatus == HAL_OK)
3141 {
3142 /* Send Slave Address and Memory Address */
3143 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3144 {
3145 /* Abort the ongoing DMA */
3146 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3147
3148 /* Prevent unused argument(s) compilation and MISRA warning */
3149 UNUSED(dmaxferstatus);
3150
3151 /* Set the unused I2C DMA transfer complete callback to NULL */
3152 hi2c->hdmatx->XferCpltCallback = NULL;
3153
3154 /* Disable Acknowledge */
3155 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3156
3157 hi2c->XferSize = 0U;
3158 hi2c->XferCount = 0U;
3159
3160 /* Disable I2C peripheral to prevent dummy data in buffer */
3161 __HAL_I2C_DISABLE(hi2c);
3162
3163 return HAL_ERROR;
3164 }
3165
3166 /* Clear ADDR flag */
3167 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3168
3169 /* Process Unlocked */
3170 __HAL_UNLOCK(hi2c);
3171
3172 /* Note : The I2C interrupts must be enabled after unlocking current process
3173 to avoid the risk of I2C interrupt handle execution before current
3174 process unlock */
3175 /* Enable ERR interrupt */
3176 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3177
3178 /* Enable DMA Request */
3179 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3180
3181 return HAL_OK;
3182 }
3183 else
3184 {
3185 /* Update I2C state */
3186 hi2c->State = HAL_I2C_STATE_READY;
3187 hi2c->Mode = HAL_I2C_MODE_NONE;
3188
3189 /* Update I2C error code */
3190 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3191
3192 /* Process Unlocked */
3193 __HAL_UNLOCK(hi2c);
3194
3195 return HAL_ERROR;
3196 }
3197 }
3198 else
3199 {
3200 /* Update I2C state */
3201 hi2c->State = HAL_I2C_STATE_READY;
3202 hi2c->Mode = HAL_I2C_MODE_NONE;
3203
3204 /* Update I2C error code */
3205 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3206
3207 /* Process Unlocked */
3208 __HAL_UNLOCK(hi2c);
3209
3210 return HAL_ERROR;
3211 }
3212 }
3213 else
3214 {
3215 return HAL_BUSY;
3216 }
3217 }
3218
3219 /**
3220 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3222 * the configuration information for the specified I2C.
3223 * @param DevAddress Target device address: The device 7 bits address value
3224 * in datasheet must be shifted to the left before calling the interface
3225 * @param MemAddress Internal memory address
3226 * @param MemAddSize Size of internal memory address
3227 * @param pData Pointer to data buffer
3228 * @param Size Amount of data to be read
3229 * @retval HAL status
3230 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3231 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3232 {
3233 /* Init tickstart for timeout management*/
3234 uint32_t tickstart = HAL_GetTick();
3235 __IO uint32_t count = 0U;
3236 HAL_StatusTypeDef dmaxferstatus;
3237
3238 /* Check the parameters */
3239 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3240
3241 if (hi2c->State == HAL_I2C_STATE_READY)
3242 {
3243 /* Wait until BUSY flag is reset */
3244 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3245 do
3246 {
3247 count--;
3248 if (count == 0U)
3249 {
3250 hi2c->PreviousState = I2C_STATE_NONE;
3251 hi2c->State = HAL_I2C_STATE_READY;
3252 hi2c->Mode = HAL_I2C_MODE_NONE;
3253 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3254
3255 return HAL_BUSY;
3256 }
3257 }
3258 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3259
3260 /* Process Locked */
3261 __HAL_LOCK(hi2c);
3262
3263 /* Check if the I2C is already enabled */
3264 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3265 {
3266 /* Enable I2C peripheral */
3267 __HAL_I2C_ENABLE(hi2c);
3268 }
3269
3270 /* Disable Pos */
3271 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3272
3273 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3274 hi2c->Mode = HAL_I2C_MODE_MEM;
3275 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3276
3277 /* Prepare transfer parameters */
3278 hi2c->pBuffPtr = pData;
3279 hi2c->XferCount = Size;
3280 hi2c->XferSize = hi2c->XferCount;
3281 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3282 hi2c->Devaddress = DevAddress;
3283 hi2c->Memaddress = MemAddress;
3284 hi2c->MemaddSize = MemAddSize;
3285 hi2c->EventCount = 0U;
3286
3287 if (hi2c->XferSize > 0U)
3288 {
3289 if (hi2c->hdmarx != NULL)
3290 {
3291 /* Set the I2C DMA transfer complete callback */
3292 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3293
3294 /* Set the DMA error callback */
3295 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3296
3297 /* Set the unused DMA callbacks to NULL */
3298 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3299 hi2c->hdmarx->XferM1CpltCallback = NULL;
3300 hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3301 hi2c->hdmarx->XferAbortCallback = NULL;
3302
3303 /* Enable the DMA stream */
3304 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3305 }
3306 else
3307 {
3308 /* Update I2C state */
3309 hi2c->State = HAL_I2C_STATE_READY;
3310 hi2c->Mode = HAL_I2C_MODE_NONE;
3311
3312 /* Update I2C error code */
3313 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3314
3315 /* Process Unlocked */
3316 __HAL_UNLOCK(hi2c);
3317
3318 return HAL_ERROR;
3319 }
3320
3321 if (dmaxferstatus == HAL_OK)
3322 {
3323 /* Send Slave Address and Memory Address */
3324 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3325 {
3326 /* Abort the ongoing DMA */
3327 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3328
3329 /* Prevent unused argument(s) compilation and MISRA warning */
3330 UNUSED(dmaxferstatus);
3331
3332 /* Set the unused I2C DMA transfer complete callback to NULL */
3333 hi2c->hdmarx->XferCpltCallback = NULL;
3334
3335 /* Disable Acknowledge */
3336 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3337
3338 hi2c->XferSize = 0U;
3339 hi2c->XferCount = 0U;
3340
3341 /* Disable I2C peripheral to prevent dummy data in buffer */
3342 __HAL_I2C_DISABLE(hi2c);
3343
3344 return HAL_ERROR;
3345 }
3346
3347 if (hi2c->XferSize == 1U)
3348 {
3349 /* Disable Acknowledge */
3350 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3351 }
3352 else
3353 {
3354 /* Enable Last DMA bit */
3355 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3356 }
3357
3358 /* Clear ADDR flag */
3359 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3360
3361 /* Process Unlocked */
3362 __HAL_UNLOCK(hi2c);
3363
3364 /* Note : The I2C interrupts must be enabled after unlocking current process
3365 to avoid the risk of I2C interrupt handle execution before current
3366 process unlock */
3367 /* Enable ERR interrupt */
3368 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3369
3370 /* Enable DMA Request */
3371 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3372 }
3373 else
3374 {
3375 /* Update I2C state */
3376 hi2c->State = HAL_I2C_STATE_READY;
3377 hi2c->Mode = HAL_I2C_MODE_NONE;
3378
3379 /* Update I2C error code */
3380 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3381
3382 /* Process Unlocked */
3383 __HAL_UNLOCK(hi2c);
3384
3385 return HAL_ERROR;
3386 }
3387 }
3388 else
3389 {
3390 /* Send Slave Address and Memory Address */
3391 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3392 {
3393 return HAL_ERROR;
3394 }
3395
3396 /* Clear ADDR flag */
3397 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3398
3399 /* Generate Stop */
3400 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3401
3402 hi2c->State = HAL_I2C_STATE_READY;
3403
3404 /* Process Unlocked */
3405 __HAL_UNLOCK(hi2c);
3406 }
3407
3408 return HAL_OK;
3409 }
3410 else
3411 {
3412 return HAL_BUSY;
3413 }
3414 }
3415
3416 /**
3417 * @brief Checks if target device is ready for communication.
3418 * @note This function is used with Memory devices
3419 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3420 * the configuration information for the specified I2C.
3421 * @param DevAddress Target device address: The device 7 bits address value
3422 * in datasheet must be shifted to the left before calling the interface
3423 * @param Trials Number of trials
3424 * @param Timeout Timeout duration
3425 * @retval HAL status
3426 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3427 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3428 {
3429 /* Get tick */
3430 uint32_t tickstart = HAL_GetTick();
3431 uint32_t I2C_Trials = 0U;
3432 FlagStatus tmp1;
3433 FlagStatus tmp2;
3434
3435 if (hi2c->State == HAL_I2C_STATE_READY)
3436 {
3437 /* Wait until BUSY flag is reset */
3438 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3439 {
3440 return HAL_BUSY;
3441 }
3442
3443 /* Process Locked */
3444 __HAL_LOCK(hi2c);
3445
3446 /* Check if the I2C is already enabled */
3447 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3448 {
3449 /* Enable I2C peripheral */
3450 __HAL_I2C_ENABLE(hi2c);
3451 }
3452
3453 /* Disable Pos */
3454 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3455
3456 hi2c->State = HAL_I2C_STATE_BUSY;
3457 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3458 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3459
3460 do
3461 {
3462 /* Generate Start */
3463 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3464
3465 /* Wait until SB flag is set */
3466 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3467 {
3468 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3469 {
3470 hi2c->ErrorCode = HAL_I2C_WRONG_START;
3471 }
3472 return HAL_TIMEOUT;
3473 }
3474
3475 /* Send slave address */
3476 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3477
3478 /* Wait until ADDR or AF flag are set */
3479 /* Get tick */
3480 tickstart = HAL_GetTick();
3481
3482 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3483 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3484 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3485 {
3486 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3487 {
3488 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3489 }
3490 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3491 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3492 }
3493
3494 hi2c->State = HAL_I2C_STATE_READY;
3495
3496 /* Check if the ADDR flag has been set */
3497 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3498 {
3499 /* Generate Stop */
3500 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3501
3502 /* Clear ADDR Flag */
3503 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3504
3505 /* Wait until BUSY flag is reset */
3506 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3507 {
3508 return HAL_ERROR;
3509 }
3510
3511 hi2c->State = HAL_I2C_STATE_READY;
3512
3513 /* Process Unlocked */
3514 __HAL_UNLOCK(hi2c);
3515
3516 return HAL_OK;
3517 }
3518 else
3519 {
3520 /* Generate Stop */
3521 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3522
3523 /* Clear AF Flag */
3524 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3525
3526 /* Wait until BUSY flag is reset */
3527 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3528 {
3529 return HAL_ERROR;
3530 }
3531 }
3532
3533 /* Increment Trials */
3534 I2C_Trials++;
3535 }
3536 while (I2C_Trials < Trials);
3537
3538 hi2c->State = HAL_I2C_STATE_READY;
3539
3540 /* Process Unlocked */
3541 __HAL_UNLOCK(hi2c);
3542
3543 return HAL_ERROR;
3544 }
3545 else
3546 {
3547 return HAL_BUSY;
3548 }
3549 }
3550
3551 /**
3552 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3553 * @note This interface allow to manage repeated start condition when a direction change during transfer
3554 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3555 * the configuration information for the specified I2C.
3556 * @param DevAddress Target device address: The device 7 bits address value
3557 * in datasheet must be shifted to the left before calling the interface
3558 * @param pData Pointer to data buffer
3559 * @param Size Amount of data to be sent
3560 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3561 * @retval HAL status
3562 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3563 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3564 {
3565 __IO uint32_t Prev_State = 0x00U;
3566 __IO uint32_t count = 0x00U;
3567
3568 /* Check the parameters */
3569 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3570
3571 if (hi2c->State == HAL_I2C_STATE_READY)
3572 {
3573 /* Check Busy Flag only if FIRST call of Master interface */
3574 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3575 {
3576 /* Wait until BUSY flag is reset */
3577 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3578 do
3579 {
3580 count--;
3581 if (count == 0U)
3582 {
3583 hi2c->PreviousState = I2C_STATE_NONE;
3584 hi2c->State = HAL_I2C_STATE_READY;
3585 hi2c->Mode = HAL_I2C_MODE_NONE;
3586 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3587
3588 return HAL_BUSY;
3589 }
3590 }
3591 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3592 }
3593
3594 /* Process Locked */
3595 __HAL_LOCK(hi2c);
3596
3597 /* Check if the I2C is already enabled */
3598 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3599 {
3600 /* Enable I2C peripheral */
3601 __HAL_I2C_ENABLE(hi2c);
3602 }
3603
3604 /* Disable Pos */
3605 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3606
3607 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3608 hi2c->Mode = HAL_I2C_MODE_MASTER;
3609 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3610
3611 /* Prepare transfer parameters */
3612 hi2c->pBuffPtr = pData;
3613 hi2c->XferCount = Size;
3614 hi2c->XferSize = hi2c->XferCount;
3615 hi2c->XferOptions = XferOptions;
3616 hi2c->Devaddress = DevAddress;
3617
3618 Prev_State = hi2c->PreviousState;
3619
3620 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3621 /* Mean Previous state is same as current state */
3622 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3623 {
3624 /* Generate Start */
3625 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3626 }
3627
3628 /* Process Unlocked */
3629 __HAL_UNLOCK(hi2c);
3630
3631 /* Note : The I2C interrupts must be enabled after unlocking current process
3632 to avoid the risk of I2C interrupt handle execution before current
3633 process unlock */
3634
3635 /* Enable EVT, BUF and ERR interrupt */
3636 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3637
3638 return HAL_OK;
3639 }
3640 else
3641 {
3642 return HAL_BUSY;
3643 }
3644 }
3645
3646 /**
3647 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3648 * @note This interface allow to manage repeated start condition when a direction change during transfer
3649 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3650 * the configuration information for the specified I2C.
3651 * @param DevAddress Target device address: The device 7 bits address value
3652 * in datasheet must be shifted to the left before calling the interface
3653 * @param pData Pointer to data buffer
3654 * @param Size Amount of data to be sent
3655 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3656 * @retval HAL status
3657 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3658 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3659 {
3660 __IO uint32_t Prev_State = 0x00U;
3661 __IO uint32_t count = 0x00U;
3662 HAL_StatusTypeDef dmaxferstatus;
3663
3664 /* Check the parameters */
3665 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3666
3667 if (hi2c->State == HAL_I2C_STATE_READY)
3668 {
3669 /* Check Busy Flag only if FIRST call of Master interface */
3670 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3671 {
3672 /* Wait until BUSY flag is reset */
3673 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3674 do
3675 {
3676 count--;
3677 if (count == 0U)
3678 {
3679 hi2c->PreviousState = I2C_STATE_NONE;
3680 hi2c->State = HAL_I2C_STATE_READY;
3681 hi2c->Mode = HAL_I2C_MODE_NONE;
3682 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3683
3684 return HAL_BUSY;
3685 }
3686 }
3687 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3688 }
3689
3690 /* Process Locked */
3691 __HAL_LOCK(hi2c);
3692
3693 /* Check if the I2C is already enabled */
3694 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3695 {
3696 /* Enable I2C peripheral */
3697 __HAL_I2C_ENABLE(hi2c);
3698 }
3699
3700 /* Disable Pos */
3701 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3702
3703 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3704 hi2c->Mode = HAL_I2C_MODE_MASTER;
3705 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3706
3707 /* Prepare transfer parameters */
3708 hi2c->pBuffPtr = pData;
3709 hi2c->XferCount = Size;
3710 hi2c->XferSize = hi2c->XferCount;
3711 hi2c->XferOptions = XferOptions;
3712 hi2c->Devaddress = DevAddress;
3713
3714 Prev_State = hi2c->PreviousState;
3715
3716 if (hi2c->XferSize > 0U)
3717 {
3718 if (hi2c->hdmatx != NULL)
3719 {
3720 /* Set the I2C DMA transfer complete callback */
3721 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3722
3723 /* Set the DMA error callback */
3724 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3725
3726 /* Set the unused DMA callbacks to NULL */
3727 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3728 hi2c->hdmatx->XferAbortCallback = NULL;
3729
3730 /* Enable the DMA stream */
3731 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3732 }
3733 else
3734 {
3735 /* Update I2C state */
3736 hi2c->State = HAL_I2C_STATE_READY;
3737 hi2c->Mode = HAL_I2C_MODE_NONE;
3738
3739 /* Update I2C error code */
3740 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3741
3742 /* Process Unlocked */
3743 __HAL_UNLOCK(hi2c);
3744
3745 return HAL_ERROR;
3746 }
3747
3748 if (dmaxferstatus == HAL_OK)
3749 {
3750 /* Enable Acknowledge */
3751 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3752
3753 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3754 /* Mean Previous state is same as current state */
3755 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3756 {
3757 /* Generate Start */
3758 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3759 }
3760
3761 /* Process Unlocked */
3762 __HAL_UNLOCK(hi2c);
3763
3764 /* Note : The I2C interrupts must be enabled after unlocking current process
3765 to avoid the risk of I2C interrupt handle execution before current
3766 process unlock */
3767
3768 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3769 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3770 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3771 {
3772 /* Enable DMA Request */
3773 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3774 }
3775
3776 /* Enable EVT and ERR interrupt */
3777 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3778 }
3779 else
3780 {
3781 /* Update I2C state */
3782 hi2c->State = HAL_I2C_STATE_READY;
3783 hi2c->Mode = HAL_I2C_MODE_NONE;
3784
3785 /* Update I2C error code */
3786 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3787
3788 /* Process Unlocked */
3789 __HAL_UNLOCK(hi2c);
3790
3791 return HAL_ERROR;
3792 }
3793 }
3794 else
3795 {
3796 /* Enable Acknowledge */
3797 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3798
3799 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3800 /* Mean Previous state is same as current state */
3801 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3802 {
3803 /* Generate Start */
3804 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3805 }
3806
3807 /* Process Unlocked */
3808 __HAL_UNLOCK(hi2c);
3809
3810 /* Note : The I2C interrupts must be enabled after unlocking current process
3811 to avoid the risk of I2C interrupt handle execution before current
3812 process unlock */
3813
3814 /* Enable EVT, BUF and ERR interrupt */
3815 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3816 }
3817
3818 return HAL_OK;
3819 }
3820 else
3821 {
3822 return HAL_BUSY;
3823 }
3824 }
3825
3826 /**
3827 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3828 * @note This interface allow to manage repeated start condition when a direction change during transfer
3829 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3830 * the configuration information for the specified I2C.
3831 * @param DevAddress Target device address: The device 7 bits address value
3832 * in datasheet must be shifted to the left before calling the interface
3833 * @param pData Pointer to data buffer
3834 * @param Size Amount of data to be sent
3835 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3836 * @retval HAL status
3837 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3838 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3839 {
3840 __IO uint32_t Prev_State = 0x00U;
3841 __IO uint32_t count = 0U;
3842 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3843
3844 /* Check the parameters */
3845 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3846
3847 if (hi2c->State == HAL_I2C_STATE_READY)
3848 {
3849 /* Check Busy Flag only if FIRST call of Master interface */
3850 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3851 {
3852 /* Wait until BUSY flag is reset */
3853 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3854 do
3855 {
3856 count--;
3857 if (count == 0U)
3858 {
3859 hi2c->PreviousState = I2C_STATE_NONE;
3860 hi2c->State = HAL_I2C_STATE_READY;
3861 hi2c->Mode = HAL_I2C_MODE_NONE;
3862 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3863
3864 return HAL_BUSY;
3865 }
3866 }
3867 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3868 }
3869
3870 /* Process Locked */
3871 __HAL_LOCK(hi2c);
3872
3873 /* Check if the I2C is already enabled */
3874 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3875 {
3876 /* Enable I2C peripheral */
3877 __HAL_I2C_ENABLE(hi2c);
3878 }
3879
3880 /* Disable Pos */
3881 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3882
3883 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3884 hi2c->Mode = HAL_I2C_MODE_MASTER;
3885 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3886
3887 /* Prepare transfer parameters */
3888 hi2c->pBuffPtr = pData;
3889 hi2c->XferCount = Size;
3890 hi2c->XferSize = hi2c->XferCount;
3891 hi2c->XferOptions = XferOptions;
3892 hi2c->Devaddress = DevAddress;
3893
3894 Prev_State = hi2c->PreviousState;
3895
3896 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3897 {
3898 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3899 {
3900 /* Disable Acknowledge */
3901 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3902
3903 /* Enable Pos */
3904 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3905
3906 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3907 enableIT &= ~I2C_IT_BUF;
3908 }
3909 else
3910 {
3911 /* Enable Acknowledge */
3912 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3913 }
3914 }
3915 else
3916 {
3917 /* Enable Acknowledge */
3918 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3919 }
3920
3921 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3922 /* Mean Previous state is same as current state */
3923 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3924 {
3925 /* Generate Start */
3926 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3927 }
3928
3929 /* Process Unlocked */
3930 __HAL_UNLOCK(hi2c);
3931
3932 /* Note : The I2C interrupts must be enabled after unlocking current process
3933 to avoid the risk of I2C interrupt handle execution before current
3934 process unlock */
3935
3936 /* Enable interrupts */
3937 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3938
3939 return HAL_OK;
3940 }
3941 else
3942 {
3943 return HAL_BUSY;
3944 }
3945 }
3946
3947 /**
3948 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3949 * @note This interface allow to manage repeated start condition when a direction change during transfer
3950 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3951 * the configuration information for the specified I2C.
3952 * @param DevAddress Target device address: The device 7 bits address value
3953 * in datasheet must be shifted to the left before calling the interface
3954 * @param pData Pointer to data buffer
3955 * @param Size Amount of data to be sent
3956 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3957 * @retval HAL status
3958 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3959 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3960 {
3961 __IO uint32_t Prev_State = 0x00U;
3962 __IO uint32_t count = 0U;
3963 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3964 HAL_StatusTypeDef dmaxferstatus;
3965
3966 /* Check the parameters */
3967 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3968
3969 if (hi2c->State == HAL_I2C_STATE_READY)
3970 {
3971 /* Check Busy Flag only if FIRST call of Master interface */
3972 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3973 {
3974 /* Wait until BUSY flag is reset */
3975 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3976 do
3977 {
3978 count--;
3979 if (count == 0U)
3980 {
3981 hi2c->PreviousState = I2C_STATE_NONE;
3982 hi2c->State = HAL_I2C_STATE_READY;
3983 hi2c->Mode = HAL_I2C_MODE_NONE;
3984 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3985
3986 return HAL_BUSY;
3987 }
3988 }
3989 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3990 }
3991
3992 /* Process Locked */
3993 __HAL_LOCK(hi2c);
3994
3995 /* Check if the I2C is already enabled */
3996 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3997 {
3998 /* Enable I2C peripheral */
3999 __HAL_I2C_ENABLE(hi2c);
4000 }
4001
4002 /* Disable Pos */
4003 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4004
4005 /* Clear Last DMA bit */
4006 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4007
4008 hi2c->State = HAL_I2C_STATE_BUSY_RX;
4009 hi2c->Mode = HAL_I2C_MODE_MASTER;
4010 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4011
4012 /* Prepare transfer parameters */
4013 hi2c->pBuffPtr = pData;
4014 hi2c->XferCount = Size;
4015 hi2c->XferSize = hi2c->XferCount;
4016 hi2c->XferOptions = XferOptions;
4017 hi2c->Devaddress = DevAddress;
4018
4019 Prev_State = hi2c->PreviousState;
4020
4021 if (hi2c->XferSize > 0U)
4022 {
4023 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4024 {
4025 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4026 {
4027 /* Disable Acknowledge */
4028 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4029
4030 /* Enable Pos */
4031 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4032
4033 /* Enable Last DMA bit */
4034 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4035 }
4036 else
4037 {
4038 /* Enable Acknowledge */
4039 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4040 }
4041 }
4042 else
4043 {
4044 /* Enable Acknowledge */
4045 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4046
4047 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4048 {
4049 /* Enable Last DMA bit */
4050 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4051 }
4052 }
4053 if (hi2c->hdmarx != NULL)
4054 {
4055 /* Set the I2C DMA transfer complete callback */
4056 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4057
4058 /* Set the DMA error callback */
4059 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4060
4061 /* Set the unused DMA callbacks to NULL */
4062 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4063 hi2c->hdmarx->XferAbortCallback = NULL;
4064
4065 /* Enable the DMA stream */
4066 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4067 }
4068 else
4069 {
4070 /* Update I2C state */
4071 hi2c->State = HAL_I2C_STATE_READY;
4072 hi2c->Mode = HAL_I2C_MODE_NONE;
4073
4074 /* Update I2C error code */
4075 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4076
4077 /* Process Unlocked */
4078 __HAL_UNLOCK(hi2c);
4079
4080 return HAL_ERROR;
4081 }
4082 if (dmaxferstatus == HAL_OK)
4083 {
4084 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4085 /* Mean Previous state is same as current state */
4086 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4087 {
4088 /* Generate Start */
4089 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4090
4091 /* Update interrupt for only EVT and ERR */
4092 enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4093 }
4094 else
4095 {
4096 /* Update interrupt for only ERR */
4097 enableIT = I2C_IT_ERR;
4098 }
4099
4100 /* Process Unlocked */
4101 __HAL_UNLOCK(hi2c);
4102
4103 /* Note : The I2C interrupts must be enabled after unlocking current process
4104 to avoid the risk of I2C interrupt handle execution before current
4105 process unlock */
4106
4107 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4108 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4109 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4110 {
4111 /* Enable DMA Request */
4112 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4113 }
4114
4115 /* Enable EVT and ERR interrupt */
4116 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4117 }
4118 else
4119 {
4120 /* Update I2C state */
4121 hi2c->State = HAL_I2C_STATE_READY;
4122 hi2c->Mode = HAL_I2C_MODE_NONE;
4123
4124 /* Update I2C error code */
4125 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4126
4127 /* Process Unlocked */
4128 __HAL_UNLOCK(hi2c);
4129
4130 return HAL_ERROR;
4131 }
4132 }
4133 else
4134 {
4135 /* Enable Acknowledge */
4136 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4137
4138 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4139 /* Mean Previous state is same as current state */
4140 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4141 {
4142 /* Generate Start */
4143 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4144 }
4145
4146 /* Process Unlocked */
4147 __HAL_UNLOCK(hi2c);
4148
4149 /* Note : The I2C interrupts must be enabled after unlocking current process
4150 to avoid the risk of I2C interrupt handle execution before current
4151 process unlock */
4152
4153 /* Enable interrupts */
4154 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4155 }
4156 return HAL_OK;
4157 }
4158 else
4159 {
4160 return HAL_BUSY;
4161 }
4162 }
4163
4164 /**
4165 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4166 * @note This interface allow to manage repeated start condition when a direction change during transfer
4167 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4168 * the configuration information for the specified I2C.
4169 * @param pData Pointer to data buffer
4170 * @param Size Amount of data to be sent
4171 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4172 * @retval HAL status
4173 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4174 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4175 {
4176 /* Check the parameters */
4177 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4178
4179 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4180 {
4181 if ((pData == NULL) || (Size == 0U))
4182 {
4183 return HAL_ERROR;
4184 }
4185
4186 /* Process Locked */
4187 __HAL_LOCK(hi2c);
4188
4189 /* Check if the I2C is already enabled */
4190 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4191 {
4192 /* Enable I2C peripheral */
4193 __HAL_I2C_ENABLE(hi2c);
4194 }
4195
4196 /* Disable Pos */
4197 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4198
4199 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4200 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4201 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4202
4203 /* Prepare transfer parameters */
4204 hi2c->pBuffPtr = pData;
4205 hi2c->XferCount = Size;
4206 hi2c->XferSize = hi2c->XferCount;
4207 hi2c->XferOptions = XferOptions;
4208
4209 /* Clear ADDR flag */
4210 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4211
4212 /* Process Unlocked */
4213 __HAL_UNLOCK(hi2c);
4214
4215 /* Note : The I2C interrupts must be enabled after unlocking current process
4216 to avoid the risk of I2C interrupt handle execution before current
4217 process unlock */
4218
4219 /* Enable EVT, BUF and ERR interrupt */
4220 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4221
4222 return HAL_OK;
4223 }
4224 else
4225 {
4226 return HAL_BUSY;
4227 }
4228 }
4229
4230 /**
4231 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4232 * @note This interface allow to manage repeated start condition when a direction change during transfer
4233 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4234 * the configuration information for the specified I2C.
4235 * @param pData Pointer to data buffer
4236 * @param Size Amount of data to be sent
4237 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4238 * @retval HAL status
4239 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4240 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4241 {
4242 HAL_StatusTypeDef dmaxferstatus;
4243
4244 /* Check the parameters */
4245 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4246
4247 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4248 {
4249 if ((pData == NULL) || (Size == 0U))
4250 {
4251 return HAL_ERROR;
4252 }
4253
4254 /* Process Locked */
4255 __HAL_LOCK(hi2c);
4256
4257 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4258 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4259
4260 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4261 /* and then toggle the HAL slave RX state to TX state */
4262 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4263 {
4264 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4265 {
4266 /* Abort DMA Xfer if any */
4267 if (hi2c->hdmarx != NULL)
4268 {
4269 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4270
4271 /* Set the I2C DMA Abort callback :
4272 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4273 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4274
4275 /* Abort DMA RX */
4276 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4277 {
4278 /* Call Directly XferAbortCallback function in case of error */
4279 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4280 }
4281 }
4282 }
4283 }
4284 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4285 {
4286 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4287 {
4288 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4289
4290 /* Abort DMA Xfer if any */
4291 if (hi2c->hdmatx != NULL)
4292 {
4293 /* Set the I2C DMA Abort callback :
4294 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4295 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4296
4297 /* Abort DMA TX */
4298 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4299 {
4300 /* Call Directly XferAbortCallback function in case of error */
4301 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4302 }
4303 }
4304 }
4305 }
4306 else
4307 {
4308 /* Nothing to do */
4309 }
4310
4311 /* Check if the I2C is already enabled */
4312 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4313 {
4314 /* Enable I2C peripheral */
4315 __HAL_I2C_ENABLE(hi2c);
4316 }
4317
4318 /* Disable Pos */
4319 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4320
4321 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4322 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4323 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4324
4325 /* Prepare transfer parameters */
4326 hi2c->pBuffPtr = pData;
4327 hi2c->XferCount = Size;
4328 hi2c->XferSize = hi2c->XferCount;
4329 hi2c->XferOptions = XferOptions;
4330
4331 if (hi2c->hdmatx != NULL)
4332 {
4333 /* Set the I2C DMA transfer complete callback */
4334 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4335
4336 /* Set the DMA error callback */
4337 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4338
4339 /* Set the unused DMA callbacks to NULL */
4340 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4341 hi2c->hdmatx->XferAbortCallback = NULL;
4342
4343 /* Enable the DMA stream */
4344 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4345 }
4346 else
4347 {
4348 /* Update I2C state */
4349 hi2c->State = HAL_I2C_STATE_LISTEN;
4350 hi2c->Mode = HAL_I2C_MODE_NONE;
4351
4352 /* Update I2C error code */
4353 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4354
4355 /* Process Unlocked */
4356 __HAL_UNLOCK(hi2c);
4357
4358 return HAL_ERROR;
4359 }
4360
4361 if (dmaxferstatus == HAL_OK)
4362 {
4363 /* Enable Address Acknowledge */
4364 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4365
4366 /* Clear ADDR flag */
4367 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4368
4369 /* Process Unlocked */
4370 __HAL_UNLOCK(hi2c);
4371
4372 /* Note : The I2C interrupts must be enabled after unlocking current process
4373 to avoid the risk of I2C interrupt handle execution before current
4374 process unlock */
4375 /* Enable EVT and ERR interrupt */
4376 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4377
4378 /* Enable DMA Request */
4379 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4380
4381 return HAL_OK;
4382 }
4383 else
4384 {
4385 /* Update I2C state */
4386 hi2c->State = HAL_I2C_STATE_READY;
4387 hi2c->Mode = HAL_I2C_MODE_NONE;
4388
4389 /* Update I2C error code */
4390 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4391
4392 /* Process Unlocked */
4393 __HAL_UNLOCK(hi2c);
4394
4395 return HAL_ERROR;
4396 }
4397 }
4398 else
4399 {
4400 return HAL_BUSY;
4401 }
4402 }
4403
4404 /**
4405 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4406 * @note This interface allow to manage repeated start condition when a direction change during transfer
4407 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4408 * the configuration information for the specified I2C.
4409 * @param pData Pointer to data buffer
4410 * @param Size Amount of data to be sent
4411 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4412 * @retval HAL status
4413 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4414 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4415 {
4416 /* Check the parameters */
4417 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4418
4419 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4420 {
4421 if ((pData == NULL) || (Size == 0U))
4422 {
4423 return HAL_ERROR;
4424 }
4425
4426 /* Process Locked */
4427 __HAL_LOCK(hi2c);
4428
4429 /* Check if the I2C is already enabled */
4430 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4431 {
4432 /* Enable I2C peripheral */
4433 __HAL_I2C_ENABLE(hi2c);
4434 }
4435
4436 /* Disable Pos */
4437 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4438
4439 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4440 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4441 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4442
4443 /* Prepare transfer parameters */
4444 hi2c->pBuffPtr = pData;
4445 hi2c->XferCount = Size;
4446 hi2c->XferSize = hi2c->XferCount;
4447 hi2c->XferOptions = XferOptions;
4448
4449 /* Clear ADDR flag */
4450 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4451
4452 /* Process Unlocked */
4453 __HAL_UNLOCK(hi2c);
4454
4455 /* Note : The I2C interrupts must be enabled after unlocking current process
4456 to avoid the risk of I2C interrupt handle execution before current
4457 process unlock */
4458
4459 /* Enable EVT, BUF and ERR interrupt */
4460 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4461
4462 return HAL_OK;
4463 }
4464 else
4465 {
4466 return HAL_BUSY;
4467 }
4468 }
4469
4470 /**
4471 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4472 * @note This interface allow to manage repeated start condition when a direction change during transfer
4473 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4474 * the configuration information for the specified I2C.
4475 * @param pData Pointer to data buffer
4476 * @param Size Amount of data to be sent
4477 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4478 * @retval HAL status
4479 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4480 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4481 {
4482 HAL_StatusTypeDef dmaxferstatus;
4483
4484 /* Check the parameters */
4485 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4486
4487 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4488 {
4489 if ((pData == NULL) || (Size == 0U))
4490 {
4491 return HAL_ERROR;
4492 }
4493
4494 /* Process Locked */
4495 __HAL_LOCK(hi2c);
4496
4497 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4498 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4499
4500 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4501 /* and then toggle the HAL slave RX state to TX state */
4502 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4503 {
4504 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4505 {
4506 /* Abort DMA Xfer if any */
4507 if (hi2c->hdmarx != NULL)
4508 {
4509 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4510
4511 /* Set the I2C DMA Abort callback :
4512 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4513 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4514
4515 /* Abort DMA RX */
4516 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4517 {
4518 /* Call Directly XferAbortCallback function in case of error */
4519 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4520 }
4521 }
4522 }
4523 }
4524 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4525 {
4526 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4527 {
4528 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4529
4530 /* Abort DMA Xfer if any */
4531 if (hi2c->hdmatx != NULL)
4532 {
4533 /* Set the I2C DMA Abort callback :
4534 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4535 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4536
4537 /* Abort DMA TX */
4538 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4539 {
4540 /* Call Directly XferAbortCallback function in case of error */
4541 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4542 }
4543 }
4544 }
4545 }
4546 else
4547 {
4548 /* Nothing to do */
4549 }
4550
4551 /* Check if the I2C is already enabled */
4552 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4553 {
4554 /* Enable I2C peripheral */
4555 __HAL_I2C_ENABLE(hi2c);
4556 }
4557
4558 /* Disable Pos */
4559 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4560
4561 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4562 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4563 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4564
4565 /* Prepare transfer parameters */
4566 hi2c->pBuffPtr = pData;
4567 hi2c->XferCount = Size;
4568 hi2c->XferSize = hi2c->XferCount;
4569 hi2c->XferOptions = XferOptions;
4570
4571 if (hi2c->hdmarx != NULL)
4572 {
4573 /* Set the I2C DMA transfer complete callback */
4574 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4575
4576 /* Set the DMA error callback */
4577 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4578
4579 /* Set the unused DMA callbacks to NULL */
4580 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4581 hi2c->hdmarx->XferAbortCallback = NULL;
4582
4583 /* Enable the DMA stream */
4584 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4585 }
4586 else
4587 {
4588 /* Update I2C state */
4589 hi2c->State = HAL_I2C_STATE_LISTEN;
4590 hi2c->Mode = HAL_I2C_MODE_NONE;
4591
4592 /* Update I2C error code */
4593 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4594
4595 /* Process Unlocked */
4596 __HAL_UNLOCK(hi2c);
4597
4598 return HAL_ERROR;
4599 }
4600
4601 if (dmaxferstatus == HAL_OK)
4602 {
4603 /* Enable Address Acknowledge */
4604 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4605
4606 /* Clear ADDR flag */
4607 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4608
4609 /* Process Unlocked */
4610 __HAL_UNLOCK(hi2c);
4611
4612 /* Enable DMA Request */
4613 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4614
4615 /* Note : The I2C interrupts must be enabled after unlocking current process
4616 to avoid the risk of I2C interrupt handle execution before current
4617 process unlock */
4618 /* Enable EVT and ERR interrupt */
4619 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4620
4621 return HAL_OK;
4622 }
4623 else
4624 {
4625 /* Update I2C state */
4626 hi2c->State = HAL_I2C_STATE_READY;
4627 hi2c->Mode = HAL_I2C_MODE_NONE;
4628
4629 /* Update I2C error code */
4630 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4631
4632 /* Process Unlocked */
4633 __HAL_UNLOCK(hi2c);
4634
4635 return HAL_ERROR;
4636 }
4637 }
4638 else
4639 {
4640 return HAL_BUSY;
4641 }
4642 }
4643
4644 /**
4645 * @brief Enable the Address listen mode with Interrupt.
4646 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4647 * the configuration information for the specified I2C.
4648 * @retval HAL status
4649 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4650 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4651 {
4652 if (hi2c->State == HAL_I2C_STATE_READY)
4653 {
4654 hi2c->State = HAL_I2C_STATE_LISTEN;
4655
4656 /* Check if the I2C is already enabled */
4657 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4658 {
4659 /* Enable I2C peripheral */
4660 __HAL_I2C_ENABLE(hi2c);
4661 }
4662
4663 /* Enable Address Acknowledge */
4664 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4665
4666 /* Enable EVT and ERR interrupt */
4667 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4668
4669 return HAL_OK;
4670 }
4671 else
4672 {
4673 return HAL_BUSY;
4674 }
4675 }
4676
4677 /**
4678 * @brief Disable the Address listen mode with Interrupt.
4679 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4680 * the configuration information for the specified I2C.
4681 * @retval HAL status
4682 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4683 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4684 {
4685 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4686 uint32_t tmp;
4687
4688 /* Disable Address listen mode only if a transfer is not ongoing */
4689 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4690 {
4691 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4692 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4693 hi2c->State = HAL_I2C_STATE_READY;
4694 hi2c->Mode = HAL_I2C_MODE_NONE;
4695
4696 /* Disable Address Acknowledge */
4697 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4698
4699 /* Disable EVT and ERR interrupt */
4700 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4701
4702 return HAL_OK;
4703 }
4704 else
4705 {
4706 return HAL_BUSY;
4707 }
4708 }
4709
4710 /**
4711 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4712 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4713 * the configuration information for the specified I2C.
4714 * @param DevAddress Target device address: The device 7 bits address value
4715 * in datasheet must be shifted to the left before calling the interface
4716 * @retval HAL status
4717 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4718 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4719 {
4720 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4721 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4722
4723 /* Prevent unused argument(s) compilation warning */
4724 UNUSED(DevAddress);
4725
4726 /* Abort Master transfer during Receive or Transmit process */
4727 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4728 {
4729 /* Process Locked */
4730 __HAL_LOCK(hi2c);
4731
4732 hi2c->PreviousState = I2C_STATE_NONE;
4733 hi2c->State = HAL_I2C_STATE_ABORT;
4734
4735 /* Disable Acknowledge */
4736 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4737
4738 /* Generate Stop */
4739 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4740
4741 hi2c->XferCount = 0U;
4742
4743 /* Disable EVT, BUF and ERR interrupt */
4744 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4745
4746 /* Process Unlocked */
4747 __HAL_UNLOCK(hi2c);
4748
4749 /* Call the corresponding callback to inform upper layer of End of Transfer */
4750 I2C_ITError(hi2c);
4751
4752 return HAL_OK;
4753 }
4754 else
4755 {
4756 /* Wrong usage of abort function */
4757 /* This function should be used only in case of abort monitored by master device */
4758 /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4759 return HAL_ERROR;
4760 }
4761 }
4762
4763 /**
4764 * @}
4765 */
4766
4767 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4768 * @{
4769 */
4770
4771 /**
4772 * @brief This function handles I2C event interrupt request.
4773 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4774 * the configuration information for the specified I2C.
4775 * @retval None
4776 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4777 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4778 {
4779 uint32_t sr1itflags;
4780 uint32_t sr2itflags = 0U;
4781 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4782 uint32_t CurrentXferOptions = hi2c->XferOptions;
4783 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4784 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4785
4786 /* Master or Memory mode selected */
4787 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4788 {
4789 sr2itflags = READ_REG(hi2c->Instance->SR2);
4790 sr1itflags = READ_REG(hi2c->Instance->SR1);
4791
4792 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4793 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4794 {
4795 return;
4796 }
4797
4798 /* SB Set ----------------------------------------------------------------*/
4799 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4800 {
4801 /* Convert OTHER_xxx XferOptions if any */
4802 I2C_ConvertOtherXferOptions(hi2c);
4803
4804 I2C_Master_SB(hi2c);
4805 }
4806 /* ADD10 Set -------------------------------------------------------------*/
4807 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4808 {
4809 I2C_Master_ADD10(hi2c);
4810 }
4811 /* ADDR Set --------------------------------------------------------------*/
4812 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4813 {
4814 I2C_Master_ADDR(hi2c);
4815 }
4816 /* I2C in mode Transmitter -----------------------------------------------*/
4817 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4818 {
4819 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4820 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4821 {
4822 /* TXE set and BTF reset -----------------------------------------------*/
4823 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4824 {
4825 I2C_MasterTransmit_TXE(hi2c);
4826 }
4827 /* BTF set -------------------------------------------------------------*/
4828 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4829 {
4830 if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4831 {
4832 I2C_MasterTransmit_BTF(hi2c);
4833 }
4834 else /* HAL_I2C_MODE_MEM */
4835 {
4836 if (CurrentMode == HAL_I2C_MODE_MEM)
4837 {
4838 I2C_MemoryTransmit_TXE_BTF(hi2c);
4839 }
4840 }
4841 }
4842 else
4843 {
4844 /* Do nothing */
4845 }
4846 }
4847 }
4848 /* I2C in mode Receiver --------------------------------------------------*/
4849 else
4850 {
4851 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4852 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4853 {
4854 /* RXNE set and BTF reset -----------------------------------------------*/
4855 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4856 {
4857 I2C_MasterReceive_RXNE(hi2c);
4858 }
4859 /* BTF set -------------------------------------------------------------*/
4860 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4861 {
4862 I2C_MasterReceive_BTF(hi2c);
4863 }
4864 else
4865 {
4866 /* Do nothing */
4867 }
4868 }
4869 }
4870 }
4871 /* Slave mode selected */
4872 else
4873 {
4874 /* If an error is detected, read only SR1 register to prevent */
4875 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4876 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4877 {
4878 sr1itflags = READ_REG(hi2c->Instance->SR1);
4879 }
4880 else
4881 {
4882 sr2itflags = READ_REG(hi2c->Instance->SR2);
4883 sr1itflags = READ_REG(hi2c->Instance->SR1);
4884 }
4885
4886 /* ADDR set --------------------------------------------------------------*/
4887 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4888 {
4889 /* Now time to read SR2, this will clear ADDR flag automatically */
4890 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4891 {
4892 sr2itflags = READ_REG(hi2c->Instance->SR2);
4893 }
4894 I2C_Slave_ADDR(hi2c, sr2itflags);
4895 }
4896 /* STOPF set --------------------------------------------------------------*/
4897 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4898 {
4899 I2C_Slave_STOPF(hi2c);
4900 }
4901 /* I2C in mode Transmitter -----------------------------------------------*/
4902 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4903 {
4904 /* TXE set and BTF reset -----------------------------------------------*/
4905 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4906 {
4907 I2C_SlaveTransmit_TXE(hi2c);
4908 }
4909 /* BTF set -------------------------------------------------------------*/
4910 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4911 {
4912 I2C_SlaveTransmit_BTF(hi2c);
4913 }
4914 else
4915 {
4916 /* Do nothing */
4917 }
4918 }
4919 /* I2C in mode Receiver --------------------------------------------------*/
4920 else
4921 {
4922 /* RXNE set and BTF reset ----------------------------------------------*/
4923 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4924 {
4925 I2C_SlaveReceive_RXNE(hi2c);
4926 }
4927 /* BTF set -------------------------------------------------------------*/
4928 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4929 {
4930 I2C_SlaveReceive_BTF(hi2c);
4931 }
4932 else
4933 {
4934 /* Do nothing */
4935 }
4936 }
4937 }
4938 }
4939
4940 /**
4941 * @brief This function handles I2C error interrupt request.
4942 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4943 * the configuration information for the specified I2C.
4944 * @retval None
4945 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4946 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4947 {
4948 HAL_I2C_ModeTypeDef tmp1;
4949 uint32_t tmp2;
4950 HAL_I2C_StateTypeDef tmp3;
4951 uint32_t tmp4;
4952 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4953 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4954 uint32_t error = HAL_I2C_ERROR_NONE;
4955 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4956
4957 /* I2C Bus error interrupt occurred ----------------------------------------*/
4958 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4959 {
4960 error |= HAL_I2C_ERROR_BERR;
4961
4962 /* Clear BERR flag */
4963 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4964 }
4965
4966 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4967 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4968 {
4969 error |= HAL_I2C_ERROR_ARLO;
4970
4971 /* Clear ARLO flag */
4972 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4973 }
4974
4975 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4976 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4977 {
4978 tmp1 = CurrentMode;
4979 tmp2 = hi2c->XferCount;
4980 tmp3 = hi2c->State;
4981 tmp4 = hi2c->PreviousState;
4982 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4983 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4984 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4985 {
4986 I2C_Slave_AF(hi2c);
4987 }
4988 else
4989 {
4990 /* Clear AF flag */
4991 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4992
4993 error |= HAL_I2C_ERROR_AF;
4994
4995 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
4996 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4997 {
4998 /* Generate Stop */
4999 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5000 }
5001 }
5002 }
5003
5004 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
5005 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5006 {
5007 error |= HAL_I2C_ERROR_OVR;
5008 /* Clear OVR flag */
5009 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
5010 }
5011
5012 /* Call the Error Callback in case of Error detected -----------------------*/
5013 if (error != HAL_I2C_ERROR_NONE)
5014 {
5015 hi2c->ErrorCode |= error;
5016 I2C_ITError(hi2c);
5017 }
5018 }
5019
5020 /**
5021 * @brief Master Tx Transfer completed callback.
5022 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5023 * the configuration information for the specified I2C.
5024 * @retval None
5025 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)5026 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5027 {
5028 /* Prevent unused argument(s) compilation warning */
5029 UNUSED(hi2c);
5030
5031 /* NOTE : This function should not be modified, when the callback is needed,
5032 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5033 */
5034 }
5035
5036 /**
5037 * @brief Master Rx Transfer completed callback.
5038 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5039 * the configuration information for the specified I2C.
5040 * @retval None
5041 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)5042 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5043 {
5044 /* Prevent unused argument(s) compilation warning */
5045 UNUSED(hi2c);
5046
5047 /* NOTE : This function should not be modified, when the callback is needed,
5048 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5049 */
5050 }
5051
5052 /** @brief Slave Tx Transfer completed callback.
5053 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5054 * the configuration information for the specified I2C.
5055 * @retval None
5056 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5057 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5058 {
5059 /* Prevent unused argument(s) compilation warning */
5060 UNUSED(hi2c);
5061
5062 /* NOTE : This function should not be modified, when the callback is needed,
5063 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5064 */
5065 }
5066
5067 /**
5068 * @brief Slave Rx Transfer completed callback.
5069 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5070 * the configuration information for the specified I2C.
5071 * @retval None
5072 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5073 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5074 {
5075 /* Prevent unused argument(s) compilation warning */
5076 UNUSED(hi2c);
5077
5078 /* NOTE : This function should not be modified, when the callback is needed,
5079 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5080 */
5081 }
5082
5083 /**
5084 * @brief Slave Address Match callback.
5085 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5086 * the configuration information for the specified I2C.
5087 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
5088 * @param AddrMatchCode Address Match Code
5089 * @retval None
5090 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5091 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5092 {
5093 /* Prevent unused argument(s) compilation warning */
5094 UNUSED(hi2c);
5095 UNUSED(TransferDirection);
5096 UNUSED(AddrMatchCode);
5097
5098 /* NOTE : This function should not be modified, when the callback is needed,
5099 the HAL_I2C_AddrCallback() could be implemented in the user file
5100 */
5101 }
5102
5103 /**
5104 * @brief Listen Complete callback.
5105 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5106 * the configuration information for the specified I2C.
5107 * @retval None
5108 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5109 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5110 {
5111 /* Prevent unused argument(s) compilation warning */
5112 UNUSED(hi2c);
5113
5114 /* NOTE : This function should not be modified, when the callback is needed,
5115 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5116 */
5117 }
5118
5119 /**
5120 * @brief Memory Tx Transfer completed callback.
5121 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5122 * the configuration information for the specified I2C.
5123 * @retval None
5124 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5125 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5126 {
5127 /* Prevent unused argument(s) compilation warning */
5128 UNUSED(hi2c);
5129
5130 /* NOTE : This function should not be modified, when the callback is needed,
5131 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5132 */
5133 }
5134
5135 /**
5136 * @brief Memory Rx Transfer completed callback.
5137 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5138 * the configuration information for the specified I2C.
5139 * @retval None
5140 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5141 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5142 {
5143 /* Prevent unused argument(s) compilation warning */
5144 UNUSED(hi2c);
5145
5146 /* NOTE : This function should not be modified, when the callback is needed,
5147 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5148 */
5149 }
5150
5151 /**
5152 * @brief I2C error callback.
5153 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5154 * the configuration information for the specified I2C.
5155 * @retval None
5156 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5157 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5158 {
5159 /* Prevent unused argument(s) compilation warning */
5160 UNUSED(hi2c);
5161
5162 /* NOTE : This function should not be modified, when the callback is needed,
5163 the HAL_I2C_ErrorCallback could be implemented in the user file
5164 */
5165 }
5166
5167 /**
5168 * @brief I2C abort callback.
5169 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5170 * the configuration information for the specified I2C.
5171 * @retval None
5172 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5173 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5174 {
5175 /* Prevent unused argument(s) compilation warning */
5176 UNUSED(hi2c);
5177
5178 /* NOTE : This function should not be modified, when the callback is needed,
5179 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5180 */
5181 }
5182
5183 /**
5184 * @}
5185 */
5186
5187 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5188 * @brief Peripheral State, Mode and Error functions
5189 *
5190 @verbatim
5191 ===============================================================================
5192 ##### Peripheral State, Mode and Error functions #####
5193 ===============================================================================
5194 [..]
5195 This subsection permit to get in run-time the status of the peripheral
5196 and the data flow.
5197
5198 @endverbatim
5199 * @{
5200 */
5201
5202 /**
5203 * @brief Return the I2C handle state.
5204 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5205 * the configuration information for the specified I2C.
5206 * @retval HAL state
5207 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5208 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5209 {
5210 /* Return I2C handle state */
5211 return hi2c->State;
5212 }
5213
5214 /**
5215 * @brief Returns the I2C Master, Slave, Memory or no mode.
5216 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5217 * the configuration information for I2C module
5218 * @retval HAL mode
5219 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5220 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5221 {
5222 return hi2c->Mode;
5223 }
5224
5225 /**
5226 * @brief Return the I2C error code.
5227 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5228 * the configuration information for the specified I2C.
5229 * @retval I2C Error Code
5230 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5231 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5232 {
5233 return hi2c->ErrorCode;
5234 }
5235
5236 /**
5237 * @}
5238 */
5239
5240 /**
5241 * @}
5242 */
5243
5244 /** @addtogroup I2C_Private_Functions
5245 * @{
5246 */
5247
5248 /**
5249 * @brief Handle TXE flag for Master
5250 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5251 * the configuration information for I2C module
5252 * @retval None
5253 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)5254 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5255 {
5256 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5257 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5258 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5259 uint32_t CurrentXferOptions = hi2c->XferOptions;
5260
5261 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5262 {
5263 /* Call TxCpltCallback() directly if no stop mode is set */
5264 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5265 {
5266 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5267
5268 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5269 hi2c->Mode = HAL_I2C_MODE_NONE;
5270 hi2c->State = HAL_I2C_STATE_READY;
5271
5272 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5273 hi2c->MasterTxCpltCallback(hi2c);
5274 #else
5275 HAL_I2C_MasterTxCpltCallback(hi2c);
5276 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5277 }
5278 else /* Generate Stop condition then Call TxCpltCallback() */
5279 {
5280 /* Disable EVT, BUF and ERR interrupt */
5281 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5282
5283 /* Generate Stop */
5284 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5285
5286 hi2c->PreviousState = I2C_STATE_NONE;
5287 hi2c->State = HAL_I2C_STATE_READY;
5288
5289 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5290 {
5291 hi2c->Mode = HAL_I2C_MODE_NONE;
5292 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5293 hi2c->MemTxCpltCallback(hi2c);
5294 #else
5295 HAL_I2C_MemTxCpltCallback(hi2c);
5296 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5297 }
5298 else
5299 {
5300 hi2c->Mode = HAL_I2C_MODE_NONE;
5301 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5302 hi2c->MasterTxCpltCallback(hi2c);
5303 #else
5304 HAL_I2C_MasterTxCpltCallback(hi2c);
5305 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5306 }
5307 }
5308 }
5309 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5310 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5311 {
5312 if (hi2c->XferCount == 0U)
5313 {
5314 /* Disable BUF interrupt */
5315 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5316 }
5317 else
5318 {
5319 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5320 {
5321 I2C_MemoryTransmit_TXE_BTF(hi2c);
5322 }
5323 else
5324 {
5325 /* Write data to DR */
5326 hi2c->Instance->DR = *hi2c->pBuffPtr;
5327
5328 /* Increment Buffer pointer */
5329 hi2c->pBuffPtr++;
5330
5331 /* Update counter */
5332 hi2c->XferCount--;
5333 }
5334 }
5335 }
5336 else
5337 {
5338 /* Do nothing */
5339 }
5340 }
5341
5342 /**
5343 * @brief Handle BTF flag for Master transmitter
5344 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5345 * the configuration information for I2C module
5346 * @retval None
5347 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5348 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5349 {
5350 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5351 uint32_t CurrentXferOptions = hi2c->XferOptions;
5352
5353 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5354 {
5355 if (hi2c->XferCount != 0U)
5356 {
5357 /* Write data to DR */
5358 hi2c->Instance->DR = *hi2c->pBuffPtr;
5359
5360 /* Increment Buffer pointer */
5361 hi2c->pBuffPtr++;
5362
5363 /* Update counter */
5364 hi2c->XferCount--;
5365 }
5366 else
5367 {
5368 /* Call TxCpltCallback() directly if no stop mode is set */
5369 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5370 {
5371 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5372
5373 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5374 hi2c->Mode = HAL_I2C_MODE_NONE;
5375 hi2c->State = HAL_I2C_STATE_READY;
5376
5377 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5378 hi2c->MasterTxCpltCallback(hi2c);
5379 #else
5380 HAL_I2C_MasterTxCpltCallback(hi2c);
5381 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5382 }
5383 else /* Generate Stop condition then Call TxCpltCallback() */
5384 {
5385 /* Disable EVT, BUF and ERR interrupt */
5386 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5387
5388 /* Generate Stop */
5389 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5390
5391 hi2c->PreviousState = I2C_STATE_NONE;
5392 hi2c->State = HAL_I2C_STATE_READY;
5393 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5394 {
5395 hi2c->Mode = HAL_I2C_MODE_NONE;
5396 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5397 hi2c->MemTxCpltCallback(hi2c);
5398 #else
5399 HAL_I2C_MemTxCpltCallback(hi2c);
5400 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5401 }
5402 else
5403 {
5404 hi2c->Mode = HAL_I2C_MODE_NONE;
5405
5406 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5407 hi2c->MasterTxCpltCallback(hi2c);
5408 #else
5409 HAL_I2C_MasterTxCpltCallback(hi2c);
5410 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5411 }
5412 }
5413 }
5414 }
5415 else
5416 {
5417 /* Do nothing */
5418 }
5419 }
5420
5421 /**
5422 * @brief Handle TXE and BTF flag for Memory transmitter
5423 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5424 * the configuration information for I2C module
5425 * @retval None
5426 */
I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef * hi2c)5427 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5428 {
5429 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5430 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5431
5432 if (hi2c->EventCount == 0U)
5433 {
5434 /* If Memory address size is 8Bit */
5435 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5436 {
5437 /* Send Memory Address */
5438 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5439
5440 hi2c->EventCount += 2U;
5441 }
5442 /* If Memory address size is 16Bit */
5443 else
5444 {
5445 /* Send MSB of Memory Address */
5446 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5447
5448 hi2c->EventCount++;
5449 }
5450 }
5451 else if (hi2c->EventCount == 1U)
5452 {
5453 /* Send LSB of Memory Address */
5454 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5455
5456 hi2c->EventCount++;
5457 }
5458 else if (hi2c->EventCount == 2U)
5459 {
5460 if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5461 {
5462 /* Generate Restart */
5463 hi2c->Instance->CR1 |= I2C_CR1_START;
5464
5465 hi2c->EventCount++;
5466 }
5467 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5468 {
5469 /* Write data to DR */
5470 hi2c->Instance->DR = *hi2c->pBuffPtr;
5471
5472 /* Increment Buffer pointer */
5473 hi2c->pBuffPtr++;
5474
5475 /* Update counter */
5476 hi2c->XferCount--;
5477 }
5478 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5479 {
5480 /* Generate Stop condition then Call TxCpltCallback() */
5481 /* Disable EVT, BUF and ERR interrupt */
5482 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5483
5484 /* Generate Stop */
5485 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5486
5487 hi2c->PreviousState = I2C_STATE_NONE;
5488 hi2c->State = HAL_I2C_STATE_READY;
5489 hi2c->Mode = HAL_I2C_MODE_NONE;
5490 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5491 hi2c->MemTxCpltCallback(hi2c);
5492 #else
5493 HAL_I2C_MemTxCpltCallback(hi2c);
5494 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5495 }
5496 else
5497 {
5498 /* Do nothing */
5499 }
5500 }
5501 else
5502 {
5503 /* Clear TXE and BTF flags */
5504 I2C_Flush_DR(hi2c);
5505 }
5506 }
5507
5508 /**
5509 * @brief Handle RXNE flag for Master
5510 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5511 * the configuration information for I2C module
5512 * @retval None
5513 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5514 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5515 {
5516 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5517 {
5518 uint32_t tmp;
5519
5520 tmp = hi2c->XferCount;
5521 if (tmp > 3U)
5522 {
5523 /* Read data from DR */
5524 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5525
5526 /* Increment Buffer pointer */
5527 hi2c->pBuffPtr++;
5528
5529 /* Update counter */
5530 hi2c->XferCount--;
5531
5532 if (hi2c->XferCount == (uint16_t)3)
5533 {
5534 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5535 on BTF subroutine */
5536 /* Disable BUF interrupt */
5537 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5538 }
5539 }
5540 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5541 {
5542 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5543 {
5544 /* Disable Acknowledge */
5545 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5546
5547 /* Disable EVT, BUF and ERR interrupt */
5548 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5549
5550 /* Read data from DR */
5551 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5552
5553 /* Increment Buffer pointer */
5554 hi2c->pBuffPtr++;
5555
5556 /* Update counter */
5557 hi2c->XferCount--;
5558
5559 hi2c->State = HAL_I2C_STATE_READY;
5560
5561 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5562 {
5563 hi2c->Mode = HAL_I2C_MODE_NONE;
5564 hi2c->PreviousState = I2C_STATE_NONE;
5565
5566 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5567 hi2c->MemRxCpltCallback(hi2c);
5568 #else
5569 HAL_I2C_MemRxCpltCallback(hi2c);
5570 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5571 }
5572 else
5573 {
5574 hi2c->Mode = HAL_I2C_MODE_NONE;
5575 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5576
5577 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5578 hi2c->MasterRxCpltCallback(hi2c);
5579 #else
5580 HAL_I2C_MasterRxCpltCallback(hi2c);
5581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5582 }
5583 }
5584 else
5585 {
5586 /* Disable EVT, BUF and ERR interrupt */
5587 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5588
5589 /* Read data from DR */
5590 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5591
5592 /* Increment Buffer pointer */
5593 hi2c->pBuffPtr++;
5594
5595 /* Update counter */
5596 hi2c->XferCount--;
5597
5598 hi2c->State = HAL_I2C_STATE_READY;
5599 hi2c->Mode = HAL_I2C_MODE_NONE;
5600
5601 /* Call user error callback */
5602 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5603 hi2c->ErrorCallback(hi2c);
5604 #else
5605 HAL_I2C_ErrorCallback(hi2c);
5606 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5607 }
5608 }
5609 else
5610 {
5611 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5612 on BTF subroutine if there is a reception delay between N-1 and N byte */
5613 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5614 }
5615 }
5616 }
5617
5618 /**
5619 * @brief Handle BTF flag for Master receiver
5620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5621 * the configuration information for I2C module
5622 * @retval None
5623 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5624 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5625 {
5626 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5627 uint32_t CurrentXferOptions = hi2c->XferOptions;
5628
5629 if (hi2c->XferCount == 4U)
5630 {
5631 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5632 on BTF subroutine if there is a reception delay between N-1 and N byte */
5633 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5634
5635 /* Read data from DR */
5636 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5637
5638 /* Increment Buffer pointer */
5639 hi2c->pBuffPtr++;
5640
5641 /* Update counter */
5642 hi2c->XferCount--;
5643 }
5644 else if (hi2c->XferCount == 3U)
5645 {
5646 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5647 on BTF subroutine if there is a reception delay between N-1 and N byte */
5648 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5649
5650 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5651 {
5652 /* Disable Acknowledge */
5653 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5654 }
5655
5656 /* Read data from DR */
5657 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5658
5659 /* Increment Buffer pointer */
5660 hi2c->pBuffPtr++;
5661
5662 /* Update counter */
5663 hi2c->XferCount--;
5664 }
5665 else if (hi2c->XferCount == 2U)
5666 {
5667 /* Prepare next transfer or stop current transfer */
5668 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5669 {
5670 /* Disable Acknowledge */
5671 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5672 }
5673 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5674 {
5675 /* Enable Acknowledge */
5676 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5677 }
5678 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5679 {
5680 /* Generate Stop */
5681 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5682 }
5683 else
5684 {
5685 /* Do nothing */
5686 }
5687
5688 /* Read data from DR */
5689 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5690
5691 /* Increment Buffer pointer */
5692 hi2c->pBuffPtr++;
5693
5694 /* Update counter */
5695 hi2c->XferCount--;
5696
5697 /* Read data from DR */
5698 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5699
5700 /* Increment Buffer pointer */
5701 hi2c->pBuffPtr++;
5702
5703 /* Update counter */
5704 hi2c->XferCount--;
5705
5706 /* Disable EVT and ERR interrupt */
5707 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5708
5709 hi2c->State = HAL_I2C_STATE_READY;
5710 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5711 {
5712 hi2c->Mode = HAL_I2C_MODE_NONE;
5713 hi2c->PreviousState = I2C_STATE_NONE;
5714 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5715 hi2c->MemRxCpltCallback(hi2c);
5716 #else
5717 HAL_I2C_MemRxCpltCallback(hi2c);
5718 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5719 }
5720 else
5721 {
5722 hi2c->Mode = HAL_I2C_MODE_NONE;
5723 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5724 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5725 hi2c->MasterRxCpltCallback(hi2c);
5726 #else
5727 HAL_I2C_MasterRxCpltCallback(hi2c);
5728 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5729 }
5730 }
5731 else
5732 {
5733 /* Read data from DR */
5734 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5735
5736 /* Increment Buffer pointer */
5737 hi2c->pBuffPtr++;
5738
5739 /* Update counter */
5740 hi2c->XferCount--;
5741 }
5742 }
5743
5744 /**
5745 * @brief Handle SB flag for Master
5746 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5747 * the configuration information for I2C module
5748 * @retval None
5749 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5750 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5751 {
5752 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5753 {
5754 if (hi2c->EventCount == 0U)
5755 {
5756 /* Send slave address */
5757 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5758 }
5759 else
5760 {
5761 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5762 }
5763 }
5764 else
5765 {
5766 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5767 {
5768 /* Send slave 7 Bits address */
5769 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5770 {
5771 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5772 }
5773 else
5774 {
5775 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5776 }
5777
5778 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5779 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5780 {
5781 /* Enable DMA Request */
5782 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5783 }
5784 }
5785 else
5786 {
5787 if (hi2c->EventCount == 0U)
5788 {
5789 /* Send header of slave address */
5790 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5791 }
5792 else if (hi2c->EventCount == 1U)
5793 {
5794 /* Send header of slave address */
5795 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5796 }
5797 else
5798 {
5799 /* Do nothing */
5800 }
5801 }
5802 }
5803 }
5804
5805 /**
5806 * @brief Handle ADD10 flag for Master
5807 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5808 * the configuration information for I2C module
5809 * @retval None
5810 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5811 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5812 {
5813 /* Send slave address */
5814 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5815
5816 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5817 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5818 {
5819 /* Enable DMA Request */
5820 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5821 }
5822 }
5823
5824 /**
5825 * @brief Handle ADDR flag for Master
5826 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5827 * the configuration information for I2C module
5828 * @retval None
5829 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5830 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5831 {
5832 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5833 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5834 uint32_t CurrentXferOptions = hi2c->XferOptions;
5835 uint32_t Prev_State = hi2c->PreviousState;
5836
5837 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5838 {
5839 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5840 {
5841 /* Clear ADDR flag */
5842 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5843 }
5844 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5845 {
5846 /* Clear ADDR flag */
5847 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5848
5849 /* Generate Restart */
5850 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5851
5852 hi2c->EventCount++;
5853 }
5854 else
5855 {
5856 if (hi2c->XferCount == 0U)
5857 {
5858 /* Clear ADDR flag */
5859 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5860
5861 /* Generate Stop */
5862 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5863 }
5864 else if (hi2c->XferCount == 1U)
5865 {
5866 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5867 {
5868 /* Disable Acknowledge */
5869 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5870
5871 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5872 {
5873 /* Disable Acknowledge */
5874 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5875
5876 /* Clear ADDR flag */
5877 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5878 }
5879 else
5880 {
5881 /* Clear ADDR flag */
5882 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5883
5884 /* Generate Stop */
5885 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5886 }
5887 }
5888 /* Prepare next transfer or stop current transfer */
5889 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5890 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5891 {
5892 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5893 {
5894 /* Disable Acknowledge */
5895 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5896 }
5897 else
5898 {
5899 /* Enable Acknowledge */
5900 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5901 }
5902
5903 /* Clear ADDR flag */
5904 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5905 }
5906 else
5907 {
5908 /* Disable Acknowledge */
5909 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5910
5911 /* Clear ADDR flag */
5912 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5913
5914 /* Generate Stop */
5915 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5916 }
5917 }
5918 else if (hi2c->XferCount == 2U)
5919 {
5920 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5921 {
5922 /* Disable Acknowledge */
5923 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5924
5925 /* Enable Pos */
5926 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5927 }
5928 else
5929 {
5930 /* Enable Acknowledge */
5931 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5932 }
5933
5934 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5935 {
5936 /* Enable Last DMA bit */
5937 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5938 }
5939
5940 /* Clear ADDR flag */
5941 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5942 }
5943 else
5944 {
5945 /* Enable Acknowledge */
5946 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5947
5948 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5949 {
5950 /* Enable Last DMA bit */
5951 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5952 }
5953
5954 /* Clear ADDR flag */
5955 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5956 }
5957
5958 /* Reset Event counter */
5959 hi2c->EventCount = 0U;
5960 }
5961 }
5962 else
5963 {
5964 /* Clear ADDR flag */
5965 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5966 }
5967 }
5968
5969 /**
5970 * @brief Handle TXE flag for Slave
5971 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5972 * the configuration information for I2C module
5973 * @retval None
5974 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5975 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5976 {
5977 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5978 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5979
5980 if (hi2c->XferCount != 0U)
5981 {
5982 /* Write data to DR */
5983 hi2c->Instance->DR = *hi2c->pBuffPtr;
5984
5985 /* Increment Buffer pointer */
5986 hi2c->pBuffPtr++;
5987
5988 /* Update counter */
5989 hi2c->XferCount--;
5990
5991 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5992 {
5993 /* Last Byte is received, disable Interrupt */
5994 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5995
5996 /* Set state at HAL_I2C_STATE_LISTEN */
5997 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5998 hi2c->State = HAL_I2C_STATE_LISTEN;
5999
6000 /* Call the corresponding callback to inform upper layer of End of Transfer */
6001 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6002 hi2c->SlaveTxCpltCallback(hi2c);
6003 #else
6004 HAL_I2C_SlaveTxCpltCallback(hi2c);
6005 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6006 }
6007 }
6008 }
6009
6010 /**
6011 * @brief Handle BTF flag for Slave transmitter
6012 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6013 * the configuration information for I2C module
6014 * @retval None
6015 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)6016 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6017 {
6018 if (hi2c->XferCount != 0U)
6019 {
6020 /* Write data to DR */
6021 hi2c->Instance->DR = *hi2c->pBuffPtr;
6022
6023 /* Increment Buffer pointer */
6024 hi2c->pBuffPtr++;
6025
6026 /* Update counter */
6027 hi2c->XferCount--;
6028 }
6029 }
6030
6031 /**
6032 * @brief Handle RXNE flag for Slave
6033 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6034 * the configuration information for I2C module
6035 * @retval None
6036 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)6037 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6038 {
6039 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6040 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6041
6042 if (hi2c->XferCount != 0U)
6043 {
6044 /* Read data from DR */
6045 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6046
6047 /* Increment Buffer pointer */
6048 hi2c->pBuffPtr++;
6049
6050 /* Update counter */
6051 hi2c->XferCount--;
6052
6053 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6054 {
6055 /* Last Byte is received, disable Interrupt */
6056 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6057
6058 /* Set state at HAL_I2C_STATE_LISTEN */
6059 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6060 hi2c->State = HAL_I2C_STATE_LISTEN;
6061
6062 /* Call the corresponding callback to inform upper layer of End of Transfer */
6063 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6064 hi2c->SlaveRxCpltCallback(hi2c);
6065 #else
6066 HAL_I2C_SlaveRxCpltCallback(hi2c);
6067 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6068 }
6069 }
6070 }
6071
6072 /**
6073 * @brief Handle BTF flag for Slave receiver
6074 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6075 * the configuration information for I2C module
6076 * @retval None
6077 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)6078 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6079 {
6080 if (hi2c->XferCount != 0U)
6081 {
6082 /* Read data from DR */
6083 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6084
6085 /* Increment Buffer pointer */
6086 hi2c->pBuffPtr++;
6087
6088 /* Update counter */
6089 hi2c->XferCount--;
6090 }
6091 }
6092
6093 /**
6094 * @brief Handle ADD flag for Slave
6095 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6096 * the configuration information for I2C module
6097 * @param IT2Flags Interrupt2 flags to handle.
6098 * @retval None
6099 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)6100 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6101 {
6102 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6103 uint16_t SlaveAddrCode;
6104
6105 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6106 {
6107 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6108 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6109
6110 /* Transfer Direction requested by Master */
6111 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6112 {
6113 TransferDirection = I2C_DIRECTION_TRANSMIT;
6114 }
6115
6116 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6117 {
6118 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6119 }
6120 else
6121 {
6122 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6123 }
6124
6125 /* Process Unlocked */
6126 __HAL_UNLOCK(hi2c);
6127
6128 /* Call Slave Addr callback */
6129 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6130 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6131 #else
6132 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6133 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6134 }
6135 else
6136 {
6137 /* Clear ADDR flag */
6138 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6139
6140 /* Process Unlocked */
6141 __HAL_UNLOCK(hi2c);
6142 }
6143 }
6144
6145 /**
6146 * @brief Handle STOPF flag for Slave
6147 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6148 * the configuration information for I2C module
6149 * @retval None
6150 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)6151 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6152 {
6153 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6154 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6155
6156 /* Disable EVT, BUF and ERR interrupt */
6157 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6158
6159 /* Clear STOPF flag */
6160 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6161
6162 /* Disable Acknowledge */
6163 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6164
6165 /* If a DMA is ongoing, Update handle size context */
6166 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6167 {
6168 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6169 {
6170 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx));
6171
6172 if (hi2c->XferCount != 0U)
6173 {
6174 /* Set ErrorCode corresponding to a Non-Acknowledge */
6175 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6176 }
6177
6178 /* Disable, stop the current DMA */
6179 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6180
6181 /* Abort DMA Xfer if any */
6182 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6183 {
6184 /* Set the I2C DMA Abort callback :
6185 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6186 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6187
6188 /* Abort DMA RX */
6189 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6190 {
6191 /* Call Directly XferAbortCallback function in case of error */
6192 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6193 }
6194 }
6195 }
6196 else
6197 {
6198 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx));
6199
6200 if (hi2c->XferCount != 0U)
6201 {
6202 /* Set ErrorCode corresponding to a Non-Acknowledge */
6203 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6204 }
6205
6206 /* Disable, stop the current DMA */
6207 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6208
6209 /* Abort DMA Xfer if any */
6210 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6211 {
6212 /* Set the I2C DMA Abort callback :
6213 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6214 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6215
6216 /* Abort DMA TX */
6217 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6218 {
6219 /* Call Directly XferAbortCallback function in case of error */
6220 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6221 }
6222 }
6223 }
6224 }
6225
6226 /* All data are not transferred, so set error code accordingly */
6227 if (hi2c->XferCount != 0U)
6228 {
6229 /* Store Last receive data if any */
6230 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6231 {
6232 /* Read data from DR */
6233 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6234
6235 /* Increment Buffer pointer */
6236 hi2c->pBuffPtr++;
6237
6238 /* Update counter */
6239 hi2c->XferCount--;
6240 }
6241
6242 /* Store Last receive data if any */
6243 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6244 {
6245 /* Read data from DR */
6246 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6247
6248 /* Increment Buffer pointer */
6249 hi2c->pBuffPtr++;
6250
6251 /* Update counter */
6252 hi2c->XferCount--;
6253 }
6254
6255 if (hi2c->XferCount != 0U)
6256 {
6257 /* Set ErrorCode corresponding to a Non-Acknowledge */
6258 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6259 }
6260 }
6261
6262 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6263 {
6264 /* Call the corresponding callback to inform upper layer of End of Transfer */
6265 I2C_ITError(hi2c);
6266 }
6267 else
6268 {
6269 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6270 {
6271 /* Set state at HAL_I2C_STATE_LISTEN */
6272 hi2c->PreviousState = I2C_STATE_NONE;
6273 hi2c->State = HAL_I2C_STATE_LISTEN;
6274
6275 /* Call the corresponding callback to inform upper layer of End of Transfer */
6276 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6277 hi2c->SlaveRxCpltCallback(hi2c);
6278 #else
6279 HAL_I2C_SlaveRxCpltCallback(hi2c);
6280 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6281 }
6282
6283 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6284 {
6285 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6286 hi2c->PreviousState = I2C_STATE_NONE;
6287 hi2c->State = HAL_I2C_STATE_READY;
6288 hi2c->Mode = HAL_I2C_MODE_NONE;
6289
6290 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6291 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6292 hi2c->ListenCpltCallback(hi2c);
6293 #else
6294 HAL_I2C_ListenCpltCallback(hi2c);
6295 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6296 }
6297 else
6298 {
6299 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6300 {
6301 hi2c->PreviousState = I2C_STATE_NONE;
6302 hi2c->State = HAL_I2C_STATE_READY;
6303 hi2c->Mode = HAL_I2C_MODE_NONE;
6304
6305 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6306 hi2c->SlaveRxCpltCallback(hi2c);
6307 #else
6308 HAL_I2C_SlaveRxCpltCallback(hi2c);
6309 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6310 }
6311 }
6312 }
6313 }
6314
6315 /**
6316 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6317 * the configuration information for I2C module
6318 * @retval None
6319 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)6320 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6321 {
6322 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6323 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6324 uint32_t CurrentXferOptions = hi2c->XferOptions;
6325
6326 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6327 (CurrentState == HAL_I2C_STATE_LISTEN))
6328 {
6329 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6330
6331 /* Disable EVT, BUF and ERR interrupt */
6332 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6333
6334 /* Clear AF flag */
6335 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6336
6337 /* Disable Acknowledge */
6338 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6339
6340 hi2c->PreviousState = I2C_STATE_NONE;
6341 hi2c->State = HAL_I2C_STATE_READY;
6342 hi2c->Mode = HAL_I2C_MODE_NONE;
6343
6344 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6345 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6346 hi2c->ListenCpltCallback(hi2c);
6347 #else
6348 HAL_I2C_ListenCpltCallback(hi2c);
6349 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6350 }
6351 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6352 {
6353 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6354 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6355 hi2c->State = HAL_I2C_STATE_READY;
6356 hi2c->Mode = HAL_I2C_MODE_NONE;
6357
6358 /* Disable EVT, BUF and ERR interrupt */
6359 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6360
6361 /* Clear AF flag */
6362 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6363
6364 /* Disable Acknowledge */
6365 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6366
6367 /* Clear TXE flag */
6368 I2C_Flush_DR(hi2c);
6369
6370 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6371 hi2c->SlaveTxCpltCallback(hi2c);
6372 #else
6373 HAL_I2C_SlaveTxCpltCallback(hi2c);
6374 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6375 }
6376 else
6377 {
6378 /* Clear AF flag only */
6379 /* State Listen, but XferOptions == FIRST or NEXT */
6380 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6381 }
6382 }
6383
6384 /**
6385 * @brief I2C interrupts error process
6386 * @param hi2c I2C handle.
6387 * @retval None
6388 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6389 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6390 {
6391 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6392 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6393 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6394 uint32_t CurrentError;
6395
6396 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6397 {
6398 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6399 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6400 }
6401
6402 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6403 {
6404 /* keep HAL_I2C_STATE_LISTEN */
6405 hi2c->PreviousState = I2C_STATE_NONE;
6406 hi2c->State = HAL_I2C_STATE_LISTEN;
6407 }
6408 else
6409 {
6410 /* If state is an abort treatment on going, don't change state */
6411 /* This change will be do later */
6412 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6413 {
6414 hi2c->State = HAL_I2C_STATE_READY;
6415 hi2c->Mode = HAL_I2C_MODE_NONE;
6416 }
6417 hi2c->PreviousState = I2C_STATE_NONE;
6418 }
6419
6420 /* Abort DMA transfer */
6421 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6422 {
6423 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6424
6425 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6426 {
6427 /* Set the DMA Abort callback :
6428 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6429 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6430
6431 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6432 {
6433 /* Disable I2C peripheral to prevent dummy data in buffer */
6434 __HAL_I2C_DISABLE(hi2c);
6435
6436 hi2c->State = HAL_I2C_STATE_READY;
6437
6438 /* Call Directly XferAbortCallback function in case of error */
6439 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6440 }
6441 }
6442 else
6443 {
6444 /* Set the DMA Abort callback :
6445 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6446 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6447
6448 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6449 {
6450 /* Store Last receive data if any */
6451 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6452 {
6453 /* Read data from DR */
6454 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6455
6456 /* Increment Buffer pointer */
6457 hi2c->pBuffPtr++;
6458 }
6459
6460 /* Disable I2C peripheral to prevent dummy data in buffer */
6461 __HAL_I2C_DISABLE(hi2c);
6462
6463 hi2c->State = HAL_I2C_STATE_READY;
6464
6465 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6466 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6467 }
6468 }
6469 }
6470 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6471 {
6472 hi2c->State = HAL_I2C_STATE_READY;
6473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6474
6475 /* Store Last receive data if any */
6476 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6477 {
6478 /* Read data from DR */
6479 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6480
6481 /* Increment Buffer pointer */
6482 hi2c->pBuffPtr++;
6483 }
6484
6485 /* Disable I2C peripheral to prevent dummy data in buffer */
6486 __HAL_I2C_DISABLE(hi2c);
6487
6488 /* Call the corresponding callback to inform upper layer of End of Transfer */
6489 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6490 hi2c->AbortCpltCallback(hi2c);
6491 #else
6492 HAL_I2C_AbortCpltCallback(hi2c);
6493 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6494 }
6495 else
6496 {
6497 /* Store Last receive data if any */
6498 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6499 {
6500 /* Read data from DR */
6501 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6502
6503 /* Increment Buffer pointer */
6504 hi2c->pBuffPtr++;
6505 }
6506
6507 /* Call user error callback */
6508 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6509 hi2c->ErrorCallback(hi2c);
6510 #else
6511 HAL_I2C_ErrorCallback(hi2c);
6512 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6513 }
6514
6515 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6516 CurrentError = hi2c->ErrorCode;
6517
6518 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6519 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6520 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6521 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6522 {
6523 /* Disable EVT, BUF and ERR interrupt */
6524 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6525 }
6526
6527 /* So may inform upper layer that listen phase is stopped */
6528 /* during NACK error treatment */
6529 CurrentState = hi2c->State;
6530 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6531 {
6532 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6533 hi2c->PreviousState = I2C_STATE_NONE;
6534 hi2c->State = HAL_I2C_STATE_READY;
6535 hi2c->Mode = HAL_I2C_MODE_NONE;
6536
6537 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6538 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6539 hi2c->ListenCpltCallback(hi2c);
6540 #else
6541 HAL_I2C_ListenCpltCallback(hi2c);
6542 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6543 }
6544 }
6545
6546 /**
6547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6548 * the configuration information for I2C module
6549 * @param DevAddress Target device address: The device 7 bits address value
6550 * in datasheet must be shifted to the left before calling the interface
6551 * @param Timeout Timeout duration
6552 * @param Tickstart Tick start value
6553 * @retval HAL status
6554 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6555 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6556 {
6557 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6558 uint32_t CurrentXferOptions = hi2c->XferOptions;
6559
6560 /* Generate Start condition if first transfer */
6561 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6562 {
6563 /* Generate Start */
6564 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6565 }
6566 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6567 {
6568 /* Generate ReStart */
6569 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6570 }
6571 else
6572 {
6573 /* Do nothing */
6574 }
6575
6576 /* Wait until SB flag is set */
6577 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6578 {
6579 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6580 {
6581 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6582 }
6583 return HAL_TIMEOUT;
6584 }
6585
6586 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6587 {
6588 /* Send slave address */
6589 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6590 }
6591 else
6592 {
6593 /* Send header of slave address */
6594 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6595
6596 /* Wait until ADD10 flag is set */
6597 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6598 {
6599 return HAL_ERROR;
6600 }
6601
6602 /* Send slave address */
6603 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6604 }
6605
6606 /* Wait until ADDR flag is set */
6607 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6608 {
6609 return HAL_ERROR;
6610 }
6611
6612 return HAL_OK;
6613 }
6614
6615 /**
6616 * @brief Master sends target device address for read request.
6617 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6618 * the configuration information for I2C module
6619 * @param DevAddress Target device address: The device 7 bits address value
6620 * in datasheet must be shifted to the left before calling the interface
6621 * @param Timeout Timeout duration
6622 * @param Tickstart Tick start value
6623 * @retval HAL status
6624 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6625 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6626 {
6627 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6628 uint32_t CurrentXferOptions = hi2c->XferOptions;
6629
6630 /* Enable Acknowledge */
6631 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6632
6633 /* Generate Start condition if first transfer */
6634 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6635 {
6636 /* Generate Start */
6637 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6638 }
6639 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6640 {
6641 /* Generate ReStart */
6642 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6643 }
6644 else
6645 {
6646 /* Do nothing */
6647 }
6648
6649 /* Wait until SB flag is set */
6650 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6651 {
6652 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6653 {
6654 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6655 }
6656 return HAL_TIMEOUT;
6657 }
6658
6659 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6660 {
6661 /* Send slave address */
6662 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6663 }
6664 else
6665 {
6666 /* Send header of slave address */
6667 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6668
6669 /* Wait until ADD10 flag is set */
6670 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6671 {
6672 return HAL_ERROR;
6673 }
6674
6675 /* Send slave address */
6676 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6677
6678 /* Wait until ADDR flag is set */
6679 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6680 {
6681 return HAL_ERROR;
6682 }
6683
6684 /* Clear ADDR flag */
6685 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6686
6687 /* Generate Restart */
6688 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6689
6690 /* Wait until SB flag is set */
6691 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6692 {
6693 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6694 {
6695 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6696 }
6697 return HAL_TIMEOUT;
6698 }
6699
6700 /* Send header of slave address */
6701 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6702 }
6703
6704 /* Wait until ADDR flag is set */
6705 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6706 {
6707 return HAL_ERROR;
6708 }
6709
6710 return HAL_OK;
6711 }
6712
6713 /**
6714 * @brief Master sends target device address followed by internal memory address for write request.
6715 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6716 * the configuration information for I2C module
6717 * @param DevAddress Target device address: The device 7 bits address value
6718 * in datasheet must be shifted to the left before calling the interface
6719 * @param MemAddress Internal memory address
6720 * @param MemAddSize Size of internal memory address
6721 * @param Timeout Timeout duration
6722 * @param Tickstart Tick start value
6723 * @retval HAL status
6724 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6725 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6726 {
6727 /* Generate Start */
6728 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6729
6730 /* Wait until SB flag is set */
6731 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6732 {
6733 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6734 {
6735 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6736 }
6737 return HAL_TIMEOUT;
6738 }
6739
6740 /* Send slave address */
6741 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6742
6743 /* Wait until ADDR flag is set */
6744 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6745 {
6746 return HAL_ERROR;
6747 }
6748
6749 /* Clear ADDR flag */
6750 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6751
6752 /* Wait until TXE flag is set */
6753 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6754 {
6755 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6756 {
6757 /* Generate Stop */
6758 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6759 }
6760 return HAL_ERROR;
6761 }
6762
6763 /* If Memory address size is 8Bit */
6764 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6765 {
6766 /* Send Memory Address */
6767 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6768 }
6769 /* If Memory address size is 16Bit */
6770 else
6771 {
6772 /* Send MSB of Memory Address */
6773 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6774
6775 /* Wait until TXE flag is set */
6776 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6777 {
6778 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6779 {
6780 /* Generate Stop */
6781 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6782 }
6783 return HAL_ERROR;
6784 }
6785
6786 /* Send LSB of Memory Address */
6787 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6788 }
6789
6790 return HAL_OK;
6791 }
6792
6793 /**
6794 * @brief Master sends target device address followed by internal memory address for read request.
6795 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6796 * the configuration information for I2C module
6797 * @param DevAddress Target device address: The device 7 bits address value
6798 * in datasheet must be shifted to the left before calling the interface
6799 * @param MemAddress Internal memory address
6800 * @param MemAddSize Size of internal memory address
6801 * @param Timeout Timeout duration
6802 * @param Tickstart Tick start value
6803 * @retval HAL status
6804 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6805 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6806 {
6807 /* Enable Acknowledge */
6808 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6809
6810 /* Generate Start */
6811 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6812
6813 /* Wait until SB flag is set */
6814 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6815 {
6816 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6817 {
6818 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6819 }
6820 return HAL_TIMEOUT;
6821 }
6822
6823 /* Send slave address */
6824 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6825
6826 /* Wait until ADDR flag is set */
6827 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6828 {
6829 return HAL_ERROR;
6830 }
6831
6832 /* Clear ADDR flag */
6833 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6834
6835 /* Wait until TXE flag is set */
6836 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6837 {
6838 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6839 {
6840 /* Generate Stop */
6841 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6842 }
6843 return HAL_ERROR;
6844 }
6845
6846 /* If Memory address size is 8Bit */
6847 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6848 {
6849 /* Send Memory Address */
6850 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6851 }
6852 /* If Memory address size is 16Bit */
6853 else
6854 {
6855 /* Send MSB of Memory Address */
6856 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6857
6858 /* Wait until TXE flag is set */
6859 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6860 {
6861 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6862 {
6863 /* Generate Stop */
6864 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6865 }
6866 return HAL_ERROR;
6867 }
6868
6869 /* Send LSB of Memory Address */
6870 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6871 }
6872
6873 /* Wait until TXE flag is set */
6874 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6875 {
6876 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6877 {
6878 /* Generate Stop */
6879 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6880 }
6881 return HAL_ERROR;
6882 }
6883
6884 /* Generate Restart */
6885 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6886
6887 /* Wait until SB flag is set */
6888 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6889 {
6890 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6891 {
6892 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6893 }
6894 return HAL_TIMEOUT;
6895 }
6896
6897 /* Send slave address */
6898 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6899
6900 /* Wait until ADDR flag is set */
6901 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6902 {
6903 return HAL_ERROR;
6904 }
6905
6906 return HAL_OK;
6907 }
6908
6909 /**
6910 * @brief DMA I2C process complete callback.
6911 * @param hdma DMA handle
6912 * @retval None
6913 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6914 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6915 {
6916 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6917
6918 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6919 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6920 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6921 uint32_t CurrentXferOptions = hi2c->XferOptions;
6922
6923 /* Disable EVT and ERR interrupt */
6924 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6925
6926 /* Clear Complete callback */
6927 if (hi2c->hdmatx != NULL)
6928 {
6929 hi2c->hdmatx->XferCpltCallback = NULL;
6930 }
6931 if (hi2c->hdmarx != NULL)
6932 {
6933 hi2c->hdmarx->XferCpltCallback = NULL;
6934 }
6935
6936 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6937 {
6938 /* Disable DMA Request */
6939 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6940
6941 hi2c->XferCount = 0U;
6942
6943 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6944 {
6945 /* Set state at HAL_I2C_STATE_LISTEN */
6946 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6947 hi2c->State = HAL_I2C_STATE_LISTEN;
6948
6949 /* Call the corresponding callback to inform upper layer of End of Transfer */
6950 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6951 hi2c->SlaveTxCpltCallback(hi2c);
6952 #else
6953 HAL_I2C_SlaveTxCpltCallback(hi2c);
6954 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6955 }
6956 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6957 {
6958 /* Set state at HAL_I2C_STATE_LISTEN */
6959 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6960 hi2c->State = HAL_I2C_STATE_LISTEN;
6961
6962 /* Call the corresponding callback to inform upper layer of End of Transfer */
6963 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6964 hi2c->SlaveRxCpltCallback(hi2c);
6965 #else
6966 HAL_I2C_SlaveRxCpltCallback(hi2c);
6967 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6968 }
6969 else
6970 {
6971 /* Do nothing */
6972 }
6973
6974 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6975 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6976 }
6977 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6978 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6979 {
6980 if (hi2c->XferCount == (uint16_t)1)
6981 {
6982 /* Disable Acknowledge */
6983 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6984 }
6985
6986 /* Disable EVT and ERR interrupt */
6987 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6988
6989 /* Prepare next transfer or stop current transfer */
6990 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6991 {
6992 /* Generate Stop */
6993 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6994 }
6995
6996 /* Disable Last DMA */
6997 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6998
6999 /* Disable DMA Request */
7000 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7001
7002 hi2c->XferCount = 0U;
7003
7004 /* Check if Errors has been detected during transfer */
7005 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
7006 {
7007 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7008 hi2c->ErrorCallback(hi2c);
7009 #else
7010 HAL_I2C_ErrorCallback(hi2c);
7011 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7012 }
7013 else
7014 {
7015 hi2c->State = HAL_I2C_STATE_READY;
7016
7017 if (hi2c->Mode == HAL_I2C_MODE_MEM)
7018 {
7019 hi2c->Mode = HAL_I2C_MODE_NONE;
7020 hi2c->PreviousState = I2C_STATE_NONE;
7021
7022 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7023 hi2c->MemRxCpltCallback(hi2c);
7024 #else
7025 HAL_I2C_MemRxCpltCallback(hi2c);
7026 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7027 }
7028 else
7029 {
7030 hi2c->Mode = HAL_I2C_MODE_NONE;
7031 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7032
7033 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7034 hi2c->MasterRxCpltCallback(hi2c);
7035 #else
7036 HAL_I2C_MasterRxCpltCallback(hi2c);
7037 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7038 }
7039 }
7040 }
7041 else
7042 {
7043 /* Do nothing */
7044 }
7045 }
7046
7047 /**
7048 * @brief DMA I2C communication error callback.
7049 * @param hdma DMA handle
7050 * @retval None
7051 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7052 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7053 {
7054 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7055
7056 /* Clear Complete callback */
7057 if (hi2c->hdmatx != NULL)
7058 {
7059 hi2c->hdmatx->XferCpltCallback = NULL;
7060 }
7061 if (hi2c->hdmarx != NULL)
7062 {
7063 hi2c->hdmarx->XferCpltCallback = NULL;
7064 }
7065
7066 /* Ignore DMA FIFO error */
7067 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
7068 {
7069 /* Disable Acknowledge */
7070 hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
7071
7072 hi2c->XferCount = 0U;
7073
7074 hi2c->State = HAL_I2C_STATE_READY;
7075 hi2c->Mode = HAL_I2C_MODE_NONE;
7076
7077 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
7078
7079 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7080 hi2c->ErrorCallback(hi2c);
7081 #else
7082 HAL_I2C_ErrorCallback(hi2c);
7083 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7084 }
7085 }
7086
7087 /**
7088 * @brief DMA I2C communication abort callback
7089 * (To be called at end of DMA Abort procedure).
7090 * @param hdma DMA handle.
7091 * @retval None
7092 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7093 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7094 {
7095 __IO uint32_t count = 0U;
7096 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7097
7098 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7099 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7100
7101 /* During abort treatment, check that there is no pending STOP request */
7102 /* Wait until STOP flag is reset */
7103 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7104 do
7105 {
7106 if (count == 0U)
7107 {
7108 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7109 break;
7110 }
7111 count--;
7112 }
7113 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7114
7115 /* Clear Complete callback */
7116 if (hi2c->hdmatx != NULL)
7117 {
7118 hi2c->hdmatx->XferCpltCallback = NULL;
7119 }
7120 if (hi2c->hdmarx != NULL)
7121 {
7122 hi2c->hdmarx->XferCpltCallback = NULL;
7123 }
7124
7125 /* Disable Acknowledge */
7126 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7127
7128 hi2c->XferCount = 0U;
7129
7130 /* Reset XferAbortCallback */
7131 if (hi2c->hdmatx != NULL)
7132 {
7133 hi2c->hdmatx->XferAbortCallback = NULL;
7134 }
7135 if (hi2c->hdmarx != NULL)
7136 {
7137 hi2c->hdmarx->XferAbortCallback = NULL;
7138 }
7139
7140 /* Disable I2C peripheral to prevent dummy data in buffer */
7141 __HAL_I2C_DISABLE(hi2c);
7142
7143 /* Check if come from abort from user */
7144 if (hi2c->State == HAL_I2C_STATE_ABORT)
7145 {
7146 hi2c->State = HAL_I2C_STATE_READY;
7147 hi2c->Mode = HAL_I2C_MODE_NONE;
7148 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7149
7150 /* Call the corresponding callback to inform upper layer of End of Transfer */
7151 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7152 hi2c->AbortCpltCallback(hi2c);
7153 #else
7154 HAL_I2C_AbortCpltCallback(hi2c);
7155 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7156 }
7157 else
7158 {
7159 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7160 {
7161 /* Renable I2C peripheral */
7162 __HAL_I2C_ENABLE(hi2c);
7163
7164 /* Enable Acknowledge */
7165 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7166
7167 /* keep HAL_I2C_STATE_LISTEN */
7168 hi2c->PreviousState = I2C_STATE_NONE;
7169 hi2c->State = HAL_I2C_STATE_LISTEN;
7170 }
7171 else
7172 {
7173 hi2c->State = HAL_I2C_STATE_READY;
7174 hi2c->Mode = HAL_I2C_MODE_NONE;
7175 }
7176
7177 /* Call the corresponding callback to inform upper layer of End of Transfer */
7178 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7179 hi2c->ErrorCallback(hi2c);
7180 #else
7181 HAL_I2C_ErrorCallback(hi2c);
7182 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7183 }
7184 }
7185
7186 /**
7187 * @brief This function handles I2C Communication Timeout.
7188 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7189 * the configuration information for I2C module
7190 * @param Flag specifies the I2C flag to check.
7191 * @param Status The new Flag status (SET or RESET).
7192 * @param Timeout Timeout duration
7193 * @param Tickstart Tick start value
7194 * @retval HAL status
7195 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7196 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7197 {
7198 /* Wait until flag is set */
7199 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7200 {
7201 /* Check for the Timeout */
7202 if (Timeout != HAL_MAX_DELAY)
7203 {
7204 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7205 {
7206 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7207 {
7208 hi2c->PreviousState = I2C_STATE_NONE;
7209 hi2c->State = HAL_I2C_STATE_READY;
7210 hi2c->Mode = HAL_I2C_MODE_NONE;
7211 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7212
7213 /* Process Unlocked */
7214 __HAL_UNLOCK(hi2c);
7215
7216 return HAL_ERROR;
7217 }
7218 }
7219 }
7220 }
7221 return HAL_OK;
7222 }
7223
7224 /**
7225 * @brief This function handles I2C Communication Timeout for Master addressing phase.
7226 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7227 * the configuration information for I2C module
7228 * @param Flag specifies the I2C flag to check.
7229 * @param Timeout Timeout duration
7230 * @param Tickstart Tick start value
7231 * @retval HAL status
7232 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)7233 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7234 {
7235 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7236 {
7237 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7238 {
7239 /* Generate Stop */
7240 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7241
7242 /* Clear AF Flag */
7243 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7244
7245 hi2c->PreviousState = I2C_STATE_NONE;
7246 hi2c->State = HAL_I2C_STATE_READY;
7247 hi2c->Mode = HAL_I2C_MODE_NONE;
7248 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7249
7250 /* Process Unlocked */
7251 __HAL_UNLOCK(hi2c);
7252
7253 return HAL_ERROR;
7254 }
7255
7256 /* Check for the Timeout */
7257 if (Timeout != HAL_MAX_DELAY)
7258 {
7259 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7260 {
7261 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
7262 {
7263 hi2c->PreviousState = I2C_STATE_NONE;
7264 hi2c->State = HAL_I2C_STATE_READY;
7265 hi2c->Mode = HAL_I2C_MODE_NONE;
7266 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7267
7268 /* Process Unlocked */
7269 __HAL_UNLOCK(hi2c);
7270
7271 return HAL_ERROR;
7272 }
7273 }
7274 }
7275 }
7276 return HAL_OK;
7277 }
7278
7279 /**
7280 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
7281 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7282 * the configuration information for the specified I2C.
7283 * @param Timeout Timeout duration
7284 * @param Tickstart Tick start value
7285 * @retval HAL status
7286 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7287 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7288 {
7289 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7290 {
7291 /* Check if a NACK is detected */
7292 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7293 {
7294 return HAL_ERROR;
7295 }
7296
7297 /* Check for the Timeout */
7298 if (Timeout != HAL_MAX_DELAY)
7299 {
7300 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7301 {
7302 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
7303 {
7304 hi2c->PreviousState = I2C_STATE_NONE;
7305 hi2c->State = HAL_I2C_STATE_READY;
7306 hi2c->Mode = HAL_I2C_MODE_NONE;
7307 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7308
7309 /* Process Unlocked */
7310 __HAL_UNLOCK(hi2c);
7311
7312 return HAL_ERROR;
7313 }
7314 }
7315 }
7316 }
7317 return HAL_OK;
7318 }
7319
7320 /**
7321 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
7322 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7323 * the configuration information for the specified I2C.
7324 * @param Timeout Timeout duration
7325 * @param Tickstart Tick start value
7326 * @retval HAL status
7327 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7328 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7329 {
7330 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7331 {
7332 /* Check if a NACK is detected */
7333 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7334 {
7335 return HAL_ERROR;
7336 }
7337
7338 /* Check for the Timeout */
7339 if (Timeout != HAL_MAX_DELAY)
7340 {
7341 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7342 {
7343 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
7344 {
7345 hi2c->PreviousState = I2C_STATE_NONE;
7346 hi2c->State = HAL_I2C_STATE_READY;
7347 hi2c->Mode = HAL_I2C_MODE_NONE;
7348 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7349
7350 /* Process Unlocked */
7351 __HAL_UNLOCK(hi2c);
7352
7353 return HAL_ERROR;
7354 }
7355 }
7356 }
7357 }
7358 return HAL_OK;
7359 }
7360
7361 /**
7362 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7363 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7364 * the configuration information for the specified I2C.
7365 * @param Timeout Timeout duration
7366 * @param Tickstart Tick start value
7367 * @retval HAL status
7368 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7369 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7370 {
7371 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7372 {
7373 /* Check if a NACK is detected */
7374 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7375 {
7376 return HAL_ERROR;
7377 }
7378
7379 /* Check for the Timeout */
7380 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7381 {
7382 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7383 {
7384 hi2c->PreviousState = I2C_STATE_NONE;
7385 hi2c->State = HAL_I2C_STATE_READY;
7386 hi2c->Mode = HAL_I2C_MODE_NONE;
7387 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7388
7389 /* Process Unlocked */
7390 __HAL_UNLOCK(hi2c);
7391
7392 return HAL_ERROR;
7393 }
7394 }
7395 }
7396 return HAL_OK;
7397 }
7398
7399 /**
7400 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7401 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7402 * the configuration information for the specified I2C.
7403 * @retval HAL status
7404 */
I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef * hi2c)7405 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7406 {
7407 __IO uint32_t count = 0U;
7408
7409 /* Wait until STOP flag is reset */
7410 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7411 do
7412 {
7413 count--;
7414 if (count == 0U)
7415 {
7416 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7417
7418 return HAL_ERROR;
7419 }
7420 }
7421 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7422
7423 return HAL_OK;
7424 }
7425
7426 /**
7427 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7428 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7429 * the configuration information for the specified I2C.
7430 * @param Timeout Timeout duration
7431 * @param Tickstart Tick start value
7432 * @retval HAL status
7433 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7434 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7435 {
7436
7437 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7438 {
7439 /* Check if a STOPF is detected */
7440 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7441 {
7442 /* Clear STOP Flag */
7443 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7444
7445 hi2c->PreviousState = I2C_STATE_NONE;
7446 hi2c->State = HAL_I2C_STATE_READY;
7447 hi2c->Mode = HAL_I2C_MODE_NONE;
7448 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7449
7450 /* Process Unlocked */
7451 __HAL_UNLOCK(hi2c);
7452
7453 return HAL_ERROR;
7454 }
7455
7456 /* Check for the Timeout */
7457 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7458 {
7459 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7460 {
7461 hi2c->PreviousState = I2C_STATE_NONE;
7462 hi2c->State = HAL_I2C_STATE_READY;
7463 hi2c->Mode = HAL_I2C_MODE_NONE;
7464 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7465
7466 /* Process Unlocked */
7467 __HAL_UNLOCK(hi2c);
7468
7469 return HAL_ERROR;
7470 }
7471 }
7472 }
7473 return HAL_OK;
7474 }
7475
7476 /**
7477 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7478 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7479 * the configuration information for the specified I2C.
7480 * @retval HAL status
7481 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7482 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7483 {
7484 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7485 {
7486 /* Clear NACKF Flag */
7487 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7488
7489 hi2c->PreviousState = I2C_STATE_NONE;
7490 hi2c->State = HAL_I2C_STATE_READY;
7491 hi2c->Mode = HAL_I2C_MODE_NONE;
7492 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7493
7494 /* Process Unlocked */
7495 __HAL_UNLOCK(hi2c);
7496
7497 return HAL_ERROR;
7498 }
7499 return HAL_OK;
7500 }
7501
7502 /**
7503 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7504 * @param hi2c I2C handle.
7505 * @retval None
7506 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7507 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7508 {
7509 /* if user set XferOptions to I2C_OTHER_FRAME */
7510 /* it request implicitly to generate a restart condition */
7511 /* set XferOptions to I2C_FIRST_FRAME */
7512 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7513 {
7514 hi2c->XferOptions = I2C_FIRST_FRAME;
7515 }
7516 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7517 /* it request implicitly to generate a restart condition */
7518 /* then generate a stop condition at the end of transfer */
7519 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7520 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7521 {
7522 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7523 }
7524 else
7525 {
7526 /* Nothing to do */
7527 }
7528 }
7529
7530 /**
7531 * @}
7532 */
7533
7534 #endif /* HAL_I2C_MODULE_ENABLED */
7535 /**
7536 * @}
7537 */
7538
7539 /**
7540 * @}
7541 */
7542
7543
