1 /**
2 ******************************************************************************
3 * @file stm32f2xx_hal_eth.c
4 * @author MCD Application Team
5 * @brief ETH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Ethernet (ETH) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2017 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 (#)Declare a ETH_HandleTypeDef handle structure, for example:
30 ETH_HandleTypeDef heth;
31
32 (#)Fill parameters of Init structure in heth handle
33
34 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
35
36 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
37 (##) Enable the Ethernet interface clock using
38 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
39 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
40 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
41
42 (##) Initialize the related GPIO clocks
43 (##) Configure Ethernet pin-out
44 (##) Configure Ethernet NVIC interrupt (IT mode)
45
46 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
47 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
48 (##) HAL_ETH_DMARxDescListInit(); for Reception process
49
50 (#)Enable MAC and DMA transmission and reception:
51 (##) HAL_ETH_Start();
52
53 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
54 the frame to MAC TX FIFO:
55 (##) HAL_ETH_TransmitFrame();
56
57 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
58 frame parameters
59 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
60
61 (#) Get a received frame when an ETH RX interrupt occurs:
62 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
63
64 (#) Communicate with external PHY device:
65 (##) Read a specific register from the PHY
66 HAL_ETH_ReadPHYRegister();
67 (##) Write data to a specific RHY register:
68 HAL_ETH_WritePHYRegister();
69
70 (#) Configure the Ethernet MAC after ETH peripheral initialization
71 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
72
73 (#) Configure the Ethernet DMA after ETH peripheral initialization
74 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
75
76 *** Callback registration ***
77 =============================================
78
79 The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
80 allows the user to configure dynamically the driver callbacks.
81 Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
82
83 Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
84 (+) TxCpltCallback : Tx Complete Callback.
85 (+) RxCpltCallback : Rx Complete Callback.
86 (+) DMAErrorCallback : DMA Error Callback.
87 (+) MspInitCallback : MspInit Callback.
88 (+) MspDeInitCallback: MspDeInit Callback.
89
90 This function takes as parameters the HAL peripheral handle, the Callback ID
91 and a pointer to the user callback function.
92
93 Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
94 weak function.
95 @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
96 and the Callback ID.
97 This function allows to reset following callbacks:
98 (+) TxCpltCallback : Tx Complete Callback.
99 (+) RxCpltCallback : Rx Complete Callback.
100 (+) DMAErrorCallback : DMA Error Callback.
101 (+) MspInitCallback : MspInit Callback.
102 (+) MspDeInitCallback: MspDeInit Callback.
103
104 By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
105 all callbacks are set to the corresponding weak functions:
106 examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
107 Exception done for MspInit and MspDeInit functions that are
108 reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
109 these callbacks are null (not registered beforehand).
110 if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
111 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
112
113 Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
114 Exception done MspInit/MspDeInit that can be registered/unregistered
115 in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
116 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
117 In that case first register the MspInit/MspDeInit user callbacks
118 using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
119 or HAL_ETH_Init function.
120
121 When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
122 not defined, the callback registration feature is not available and all callbacks
123 are set to the corresponding weak functions.
124
125 @endverbatim
126 ******************************************************************************
127 */
128
129 /* Includes ------------------------------------------------------------------*/
130 #include "stm32f2xx_hal.h"
131
132 /** @addtogroup STM32F2xx_HAL_Driver
133 * @{
134 */
135
136 /** @defgroup ETH ETH
137 * @brief ETH HAL module driver
138 * @{
139 */
140
141 #ifdef HAL_ETH_MODULE_ENABLED
142
143 #if defined (ETH)
144
145 /* Private typedef -----------------------------------------------------------*/
146 /* Private define ------------------------------------------------------------*/
147 /** @defgroup ETH_Private_Constants ETH Private Constants
148 * @{
149 */
150 #define ETH_TIMEOUT_SWRESET 500U
151 #define ETH_TIMEOUT_LINKED_STATE 5000U
152 #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
153
154 /**
155 * @}
156 */
157 /* Private macro -------------------------------------------------------------*/
158 /* Private variables ---------------------------------------------------------*/
159 /* Private function prototypes -----------------------------------------------*/
160 /** @defgroup ETH_Private_Functions ETH Private Functions
161 * @{
162 */
163 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
164 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
165 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
166 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
167 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
168 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
169 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
170 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
171 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
172 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
173 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
174 static void ETH_Delay(uint32_t mdelay);
175 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
176 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
177 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
178
179 /**
180 * @}
181 */
182 /* Private functions ---------------------------------------------------------*/
183
184 /** @defgroup ETH_Exported_Functions ETH Exported Functions
185 * @{
186 */
187
188 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
189 * @brief Initialization and Configuration functions
190 *
191 @verbatim
192 ===============================================================================
193 ##### Initialization and de-initialization functions #####
194 ===============================================================================
195 [..] This section provides functions allowing to:
196 (+) Initialize and configure the Ethernet peripheral
197 (+) De-initialize the Ethernet peripheral
198
199 @endverbatim
200 * @{
201 */
202
203 /**
204 * @brief Initializes the Ethernet MAC and DMA according to default
205 * parameters.
206 * @param heth pointer to a ETH_HandleTypeDef structure that contains
207 * the configuration information for ETHERNET module
208 * @retval HAL status
209 */
HAL_ETH_Init(ETH_HandleTypeDef * heth)210 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
211 {
212 uint32_t tmpreg1 = 0U, phyreg = 0U;
213 uint32_t hclk = 60000000U;
214 uint32_t tickstart = 0U;
215 uint32_t err = ETH_SUCCESS;
216
217 /* Check the ETH peripheral state */
218 if (heth == NULL)
219 {
220 return HAL_ERROR;
221 }
222
223 /* Check parameters */
224 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
225 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
226 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
227 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
228
229 if (heth->State == HAL_ETH_STATE_RESET)
230 {
231 /* Allocate lock resource and initialize it */
232 heth->Lock = HAL_UNLOCKED;
233 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
234 ETH_InitCallbacksToDefault(heth);
235
236 if (heth->MspInitCallback == NULL)
237 {
238 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
239 heth->MspInitCallback = HAL_ETH_MspInit;
240 }
241 heth->MspInitCallback(heth);
242
243 #else
244 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
245 HAL_ETH_MspInit(heth);
246 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
247 }
248
249 /* Enable SYSCFG Clock */
250 __HAL_RCC_SYSCFG_CLK_ENABLE();
251
252 /* Select MII or RMII Mode*/
253 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
254 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
255
256 /* Ethernet Software reset */
257 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
258 /* After reset all the registers holds their respective reset values */
259 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
260
261 /* Get tick */
262 tickstart = HAL_GetTick();
263
264 /* Wait for software reset */
265 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
266 {
267 /* Check for the Timeout */
268 if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_SWRESET)
269 {
270 heth->State = HAL_ETH_STATE_TIMEOUT;
271
272 /* Process Unlocked */
273 __HAL_UNLOCK(heth);
274
275 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
276 not available, please check your external PHY or the IO configuration */
277 return HAL_TIMEOUT;
278 }
279 }
280
281 /*-------------------------------- MAC Initialization ----------------------*/
282 /* Get the ETHERNET MACMIIAR value */
283 tmpreg1 = (heth->Instance)->MACMIIAR;
284 /* Clear CSR Clock Range CR[2:0] bits */
285 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
286
287 /* Get hclk frequency value */
288 hclk = HAL_RCC_GetHCLKFreq();
289
290 /* Set CR bits depending on hclk value */
291 if ((hclk >= 20000000U) && (hclk < 35000000U))
292 {
293 /* CSR Clock Range between 20-35 MHz */
294 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
295 }
296 else if ((hclk >= 35000000U) && (hclk < 60000000U))
297 {
298 /* CSR Clock Range between 35-60 MHz */
299 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
300 }
301 else if ((hclk >= 60000000U) && (hclk < 100000000U))
302 {
303 /* CSR Clock Range between 60-100 MHz */
304 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
305 }
306 else /* ((hclk >= 100000000)&&(hclk < 120000000)) */
307 {
308 /* CSR Clock Range between 100-120 MHz */
309 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
310 }
311
312 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
313 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
314
315 /*-------------------- PHY initialization and configuration ----------------*/
316 /* Put the PHY in reset mode */
317 if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
318 {
319 /* In case of write timeout */
320 err = ETH_ERROR;
321
322 /* Config MAC and DMA */
323 ETH_MACDMAConfig(heth, err);
324
325 /* Set the ETH peripheral state to READY */
326 heth->State = HAL_ETH_STATE_READY;
327
328 /* Return HAL_ERROR */
329 return HAL_ERROR;
330 }
331
332 /* Delay to assure PHY reset */
333 HAL_Delay(PHY_RESET_DELAY);
334
335 if ((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
336 {
337 /* Get tick */
338 tickstart = HAL_GetTick();
339
340 /* We wait for linked status */
341 do
342 {
343 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
344
345 /* Check for the Timeout */
346 if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_LINKED_STATE)
347 {
348 /* In case of write timeout */
349 err = ETH_ERROR;
350
351 /* Config MAC and DMA */
352 ETH_MACDMAConfig(heth, err);
353
354 heth->State = HAL_ETH_STATE_READY;
355
356 /* Process Unlocked */
357 __HAL_UNLOCK(heth);
358
359 return HAL_TIMEOUT;
360 }
361 }
362 while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
363
364
365 /* Enable Auto-Negotiation */
366 if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
367 {
368 /* In case of write timeout */
369 err = ETH_ERROR;
370
371 /* Config MAC and DMA */
372 ETH_MACDMAConfig(heth, err);
373
374 /* Set the ETH peripheral state to READY */
375 heth->State = HAL_ETH_STATE_READY;
376
377 /* Return HAL_ERROR */
378 return HAL_ERROR;
379 }
380
381 /* Get tick */
382 tickstart = HAL_GetTick();
383
384 /* Wait until the auto-negotiation will be completed */
385 do
386 {
387 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
388
389 /* Check for the Timeout */
390 if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
391 {
392 /* In case of write timeout */
393 err = ETH_ERROR;
394
395 /* Config MAC and DMA */
396 ETH_MACDMAConfig(heth, err);
397
398 heth->State = HAL_ETH_STATE_READY;
399
400 /* Process Unlocked */
401 __HAL_UNLOCK(heth);
402
403 return HAL_TIMEOUT;
404 }
405
406 }
407 while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
408
409 /* Read the result of the auto-negotiation */
410 if ((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
411 {
412 /* In case of write timeout */
413 err = ETH_ERROR;
414
415 /* Config MAC and DMA */
416 ETH_MACDMAConfig(heth, err);
417
418 /* Set the ETH peripheral state to READY */
419 heth->State = HAL_ETH_STATE_READY;
420
421 /* Return HAL_ERROR */
422 return HAL_ERROR;
423 }
424
425 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
426 if ((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
427 {
428 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
429 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
430 }
431 else
432 {
433 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
434 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
435 }
436 /* Configure the MAC with the speed fixed by the auto-negotiation process */
437 if ((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
438 {
439 /* Set Ethernet speed to 10M following the auto-negotiation */
440 (heth->Init).Speed = ETH_SPEED_10M;
441 }
442 else
443 {
444 /* Set Ethernet speed to 100M following the auto-negotiation */
445 (heth->Init).Speed = ETH_SPEED_100M;
446 }
447 }
448 else /* AutoNegotiation Disable */
449 {
450 /* Check parameters */
451 assert_param(IS_ETH_SPEED(heth->Init.Speed));
452 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
453
454 /* Set MAC Speed and Duplex Mode */
455 if (HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
456 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
457 {
458 /* In case of write timeout */
459 err = ETH_ERROR;
460
461 /* Config MAC and DMA */
462 ETH_MACDMAConfig(heth, err);
463
464 /* Set the ETH peripheral state to READY */
465 heth->State = HAL_ETH_STATE_READY;
466
467 /* Return HAL_ERROR */
468 return HAL_ERROR;
469 }
470
471 /* Delay to assure PHY configuration */
472 HAL_Delay(PHY_CONFIG_DELAY);
473 }
474
475 /* Config MAC and DMA */
476 ETH_MACDMAConfig(heth, err);
477
478 /* Set ETH HAL State to Ready */
479 heth->State = HAL_ETH_STATE_READY;
480
481 /* Return function status */
482 return HAL_OK;
483 }
484
485 /**
486 * @brief De-Initializes the ETH peripheral.
487 * @param heth pointer to a ETH_HandleTypeDef structure that contains
488 * the configuration information for ETHERNET module
489 * @retval HAL status
490 */
HAL_ETH_DeInit(ETH_HandleTypeDef * heth)491 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
492 {
493 /* Set the ETH peripheral state to BUSY */
494 heth->State = HAL_ETH_STATE_BUSY;
495
496 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
497 if (heth->MspDeInitCallback == NULL)
498 {
499 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
500 }
501 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
502 heth->MspDeInitCallback(heth);
503 #else
504 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
505 HAL_ETH_MspDeInit(heth);
506 #endif
507
508 /* Set ETH HAL state to Disabled */
509 heth->State = HAL_ETH_STATE_RESET;
510
511 /* Release Lock */
512 __HAL_UNLOCK(heth);
513
514 /* Return function status */
515 return HAL_OK;
516 }
517
518 /**
519 * @brief Initializes the DMA Tx descriptors in chain mode.
520 * @param heth pointer to a ETH_HandleTypeDef structure that contains
521 * the configuration information for ETHERNET module
522 * @param DMATxDescTab Pointer to the first Tx desc list
523 * @param TxBuff Pointer to the first TxBuffer list
524 * @param TxBuffCount Number of the used Tx desc in the list
525 * @retval HAL status
526 */
HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef * heth,ETH_DMADescTypeDef * DMATxDescTab,uint8_t * TxBuff,uint32_t TxBuffCount)527 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
528 {
529 uint32_t i = 0U;
530 ETH_DMADescTypeDef *dmatxdesc;
531
532 /* Process Locked */
533 __HAL_LOCK(heth);
534
535 /* Set the ETH peripheral state to BUSY */
536 heth->State = HAL_ETH_STATE_BUSY;
537
538 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
539 heth->TxDesc = DMATxDescTab;
540
541 /* Fill each DMATxDesc descriptor with the right values */
542 for (i = 0U; i < TxBuffCount; i++)
543 {
544 /* Get the pointer on the member (i) of the Tx Desc list */
545 dmatxdesc = DMATxDescTab + i;
546
547 /* Set Second Address Chained bit */
548 dmatxdesc->Status = ETH_DMATXDESC_TCH;
549
550 /* Set Buffer1 address pointer */
551 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_TX_BUF_SIZE]);
552
553 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
554 {
555 /* Set the DMA Tx descriptors checksum insertion */
556 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
557 }
558
559 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
560 if (i < (TxBuffCount - 1))
561 {
562 /* Set next descriptor address register with next descriptor base address */
563 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1);
564 }
565 else
566 {
567 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
568 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
569 }
570 }
571
572 /* Set Transmit Descriptor List Address Register */
573 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
574
575 /* Set ETH HAL State to Ready */
576 heth->State = HAL_ETH_STATE_READY;
577
578 /* Process Unlocked */
579 __HAL_UNLOCK(heth);
580
581 /* Return function status */
582 return HAL_OK;
583 }
584
585 /**
586 * @brief Initializes the DMA Rx descriptors in chain mode.
587 * @param heth pointer to a ETH_HandleTypeDef structure that contains
588 * the configuration information for ETHERNET module
589 * @param DMARxDescTab Pointer to the first Rx desc list
590 * @param RxBuff Pointer to the first RxBuffer list
591 * @param RxBuffCount Number of the used Rx desc in the list
592 * @retval HAL status
593 */
HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef * heth,ETH_DMADescTypeDef * DMARxDescTab,uint8_t * RxBuff,uint32_t RxBuffCount)594 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
595 {
596 uint32_t i = 0U;
597 ETH_DMADescTypeDef *DMARxDesc;
598
599 /* Process Locked */
600 __HAL_LOCK(heth);
601
602 /* Set the ETH peripheral state to BUSY */
603 heth->State = HAL_ETH_STATE_BUSY;
604
605 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
606 heth->RxDesc = DMARxDescTab;
607
608 /* Fill each DMARxDesc descriptor with the right values */
609 for (i = 0U; i < RxBuffCount; i++)
610 {
611 /* Get the pointer on the member (i) of the Rx Desc list */
612 DMARxDesc = DMARxDescTab + i;
613
614 /* Set Own bit of the Rx descriptor Status */
615 DMARxDesc->Status = ETH_DMARXDESC_OWN;
616
617 /* Set Buffer1 size and Second Address Chained bit */
618 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
619
620 /* Set Buffer1 address pointer */
621 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_RX_BUF_SIZE]);
622
623 if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
624 {
625 /* Enable Ethernet DMA Rx Descriptor interrupt */
626 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
627 }
628
629 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
630 if (i < (RxBuffCount - 1U))
631 {
632 /* Set next descriptor address register with next descriptor base address */
633 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1U);
634 }
635 else
636 {
637 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
638 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
639 }
640 }
641
642 /* Set Receive Descriptor List Address Register */
643 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
644
645 /* Set ETH HAL State to Ready */
646 heth->State = HAL_ETH_STATE_READY;
647
648 /* Process Unlocked */
649 __HAL_UNLOCK(heth);
650
651 /* Return function status */
652 return HAL_OK;
653 }
654
655 /**
656 * @brief Initializes the ETH MSP.
657 * @param heth pointer to a ETH_HandleTypeDef structure that contains
658 * the configuration information for ETHERNET module
659 * @retval None
660 */
HAL_ETH_MspInit(ETH_HandleTypeDef * heth)661 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
662 {
663 /* Prevent unused argument(s) compilation warning */
664 UNUSED(heth);
665 /* NOTE : This function Should not be modified, when the callback is needed,
666 the HAL_ETH_MspInit could be implemented in the user file
667 */
668 }
669
670 /**
671 * @brief DeInitializes ETH MSP.
672 * @param heth pointer to a ETH_HandleTypeDef structure that contains
673 * the configuration information for ETHERNET module
674 * @retval None
675 */
HAL_ETH_MspDeInit(ETH_HandleTypeDef * heth)676 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
677 {
678 /* Prevent unused argument(s) compilation warning */
679 UNUSED(heth);
680 /* NOTE : This function Should not be modified, when the callback is needed,
681 the HAL_ETH_MspDeInit could be implemented in the user file
682 */
683 }
684
685 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
686 /**
687 * @brief Register a User ETH Callback
688 * To be used instead of the weak predefined callback
689 * @param heth eth handle
690 * @param CallbackID ID of the callback to be registered
691 * This parameter can be one of the following values:
692 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
693 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
694 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
695 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
696 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
697 * @param pCallback pointer to the Callback function
698 * @retval status
699 */
HAL_ETH_RegisterCallback(ETH_HandleTypeDef * heth,HAL_ETH_CallbackIDTypeDef CallbackID,pETH_CallbackTypeDef pCallback)700 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
701 {
702 HAL_StatusTypeDef status = HAL_OK;
703
704 if (pCallback == NULL)
705 {
706 return HAL_ERROR;
707 }
708 /* Process locked */
709 __HAL_LOCK(heth);
710
711 if (heth->State == HAL_ETH_STATE_READY)
712 {
713 switch (CallbackID)
714 {
715 case HAL_ETH_TX_COMPLETE_CB_ID :
716 heth->TxCpltCallback = pCallback;
717 break;
718
719 case HAL_ETH_RX_COMPLETE_CB_ID :
720 heth->RxCpltCallback = pCallback;
721 break;
722
723 case HAL_ETH_DMA_ERROR_CB_ID :
724 heth->DMAErrorCallback = pCallback;
725 break;
726
727 case HAL_ETH_MSPINIT_CB_ID :
728 heth->MspInitCallback = pCallback;
729 break;
730
731 case HAL_ETH_MSPDEINIT_CB_ID :
732 heth->MspDeInitCallback = pCallback;
733 break;
734
735 default :
736 /* Return error status */
737 status = HAL_ERROR;
738 break;
739 }
740 }
741 else if (heth->State == HAL_ETH_STATE_RESET)
742 {
743 switch (CallbackID)
744 {
745 case HAL_ETH_MSPINIT_CB_ID :
746 heth->MspInitCallback = pCallback;
747 break;
748
749 case HAL_ETH_MSPDEINIT_CB_ID :
750 heth->MspDeInitCallback = pCallback;
751 break;
752
753 default :
754 /* Return error status */
755 status = HAL_ERROR;
756 break;
757 }
758 }
759 else
760 {
761 /* Return error status */
762 status = HAL_ERROR;
763 }
764
765 /* Release Lock */
766 __HAL_UNLOCK(heth);
767
768 return status;
769 }
770
771 /**
772 * @brief Unregister an ETH Callback
773 * ETH callback is redirected to the weak predefined callback
774 * @param heth eth handle
775 * @param CallbackID ID of the callback to be unregistered
776 * This parameter can be one of the following values:
777 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
778 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
779 * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
780 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
781 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
782 * @retval status
783 */
HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef * heth,HAL_ETH_CallbackIDTypeDef CallbackID)784 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
785 {
786 HAL_StatusTypeDef status = HAL_OK;
787
788 /* Process locked */
789 __HAL_LOCK(heth);
790
791 if (heth->State == HAL_ETH_STATE_READY)
792 {
793 switch (CallbackID)
794 {
795 case HAL_ETH_TX_COMPLETE_CB_ID :
796 heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
797 break;
798
799 case HAL_ETH_RX_COMPLETE_CB_ID :
800 heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
801 break;
802
803 case HAL_ETH_DMA_ERROR_CB_ID :
804 heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
805 break;
806
807 case HAL_ETH_MSPINIT_CB_ID :
808 heth->MspInitCallback = HAL_ETH_MspInit;
809 break;
810
811 case HAL_ETH_MSPDEINIT_CB_ID :
812 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
813 break;
814
815 default :
816 /* Return error status */
817 status = HAL_ERROR;
818 break;
819 }
820 }
821 else if (heth->State == HAL_ETH_STATE_RESET)
822 {
823 switch (CallbackID)
824 {
825 case HAL_ETH_MSPINIT_CB_ID :
826 heth->MspInitCallback = HAL_ETH_MspInit;
827 break;
828
829 case HAL_ETH_MSPDEINIT_CB_ID :
830 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
831 break;
832
833 default :
834 /* Return error status */
835 status = HAL_ERROR;
836 break;
837 }
838 }
839 else
840 {
841 /* Return error status */
842 status = HAL_ERROR;
843 }
844
845 /* Release Lock */
846 __HAL_UNLOCK(heth);
847
848 return status;
849 }
850 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
851
852 /**
853 * @}
854 */
855
856 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
857 * @brief Data transfers functions
858 *
859 @verbatim
860 ==============================================================================
861 ##### IO operation functions #####
862 ==============================================================================
863 [..] This section provides functions allowing to:
864 (+) Transmit a frame
865 HAL_ETH_TransmitFrame();
866 (+) Receive a frame
867 HAL_ETH_GetReceivedFrame();
868 HAL_ETH_GetReceivedFrame_IT();
869 (+) Read from an External PHY register
870 HAL_ETH_ReadPHYRegister();
871 (+) Write to an External PHY register
872 HAL_ETH_WritePHYRegister();
873
874 @endverbatim
875
876 * @{
877 */
878
879 /**
880 * @brief Sends an Ethernet frame.
881 * @param heth pointer to a ETH_HandleTypeDef structure that contains
882 * the configuration information for ETHERNET module
883 * @param FrameLength Amount of data to be sent
884 * @retval HAL status
885 */
HAL_ETH_TransmitFrame(ETH_HandleTypeDef * heth,uint32_t FrameLength)886 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
887 {
888 uint32_t bufcount = 0U, size = 0U, i = 0U;
889
890 /* Process Locked */
891 __HAL_LOCK(heth);
892
893 /* Set the ETH peripheral state to BUSY */
894 heth->State = HAL_ETH_STATE_BUSY;
895
896 if (FrameLength == 0U)
897 {
898 /* Set ETH HAL state to READY */
899 heth->State = HAL_ETH_STATE_READY;
900
901 /* Process Unlocked */
902 __HAL_UNLOCK(heth);
903
904 return HAL_ERROR;
905 }
906
907 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
908 if (((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
909 {
910 /* OWN bit set */
911 heth->State = HAL_ETH_STATE_BUSY_TX;
912
913 /* Process Unlocked */
914 __HAL_UNLOCK(heth);
915
916 return HAL_ERROR;
917 }
918
919 /* Get the number of needed Tx buffers for the current frame */
920 if (FrameLength > ETH_TX_BUF_SIZE)
921 {
922 bufcount = FrameLength / ETH_TX_BUF_SIZE;
923 if (FrameLength % ETH_TX_BUF_SIZE)
924 {
925 bufcount++;
926 }
927 }
928 else
929 {
930 bufcount = 1U;
931 }
932 if (bufcount == 1U)
933 {
934 /* Set LAST and FIRST segment */
935 heth->TxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
936 /* Set frame size */
937 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
938 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
939 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
940 /* Point to next descriptor */
941 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
942 }
943 else
944 {
945 for (i = 0U; i < bufcount; i++)
946 {
947 /* Clear FIRST and LAST segment bits */
948 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
949
950 if (i == 0U)
951 {
952 /* Setting the first segment bit */
953 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
954 }
955
956 /* Program size */
957 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
958
959 if (i == (bufcount - 1U))
960 {
961 /* Setting the last segment bit */
962 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
963 size = FrameLength - (bufcount - 1U) * ETH_TX_BUF_SIZE;
964 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
965 }
966
967 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
968 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
969 /* point to next descriptor */
970 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
971 }
972 }
973
974 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
975 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
976 {
977 /* Clear TBUS ETHERNET DMA flag */
978 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
979 /* Resume DMA transmission*/
980 (heth->Instance)->DMATPDR = 0U;
981 }
982
983 /* Set ETH HAL State to Ready */
984 heth->State = HAL_ETH_STATE_READY;
985
986 /* Process Unlocked */
987 __HAL_UNLOCK(heth);
988
989 /* Return function status */
990 return HAL_OK;
991 }
992
993 /**
994 * @brief Checks for received frames.
995 * @param heth pointer to a ETH_HandleTypeDef structure that contains
996 * the configuration information for ETHERNET module
997 * @retval HAL status
998 */
HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef * heth)999 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
1000 {
1001 uint32_t framelength = 0U;
1002
1003 /* Process Locked */
1004 __HAL_LOCK(heth);
1005
1006 /* Check the ETH state to BUSY */
1007 heth->State = HAL_ETH_STATE_BUSY;
1008
1009 /* Check if segment is not owned by DMA */
1010 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
1011 if (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
1012 {
1013 /* Check if last segment */
1014 if (((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
1015 {
1016 /* increment segment count */
1017 (heth->RxFrameInfos).SegCount++;
1018
1019 /* Check if last segment is first segment: one segment contains the frame */
1020 if ((heth->RxFrameInfos).SegCount == 1U)
1021 {
1022 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
1023 }
1024
1025 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1026
1027 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1028 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
1029 heth->RxFrameInfos.length = framelength;
1030
1031 /* Get the address of the buffer start address */
1032 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1033 /* point to next descriptor */
1034 heth->RxDesc = (ETH_DMADescTypeDef *)((heth->RxDesc)->Buffer2NextDescAddr);
1035
1036 /* Set HAL State to Ready */
1037 heth->State = HAL_ETH_STATE_READY;
1038
1039 /* Process Unlocked */
1040 __HAL_UNLOCK(heth);
1041
1042 /* Return function status */
1043 return HAL_OK;
1044 }
1045 /* Check if first segment */
1046 else if ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
1047 {
1048 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
1049 (heth->RxFrameInfos).LSRxDesc = NULL;
1050 (heth->RxFrameInfos).SegCount = 1U;
1051 /* Point to next descriptor */
1052 heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
1053 }
1054 /* Check if intermediate segment */
1055 else
1056 {
1057 (heth->RxFrameInfos).SegCount++;
1058 /* Point to next descriptor */
1059 heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
1060 }
1061 }
1062
1063 /* Set ETH HAL State to Ready */
1064 heth->State = HAL_ETH_STATE_READY;
1065
1066 /* Process Unlocked */
1067 __HAL_UNLOCK(heth);
1068
1069 /* Return function status */
1070 return HAL_ERROR;
1071 }
1072
1073 /**
1074 * @brief Gets the Received frame in interrupt mode.
1075 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1076 * the configuration information for ETHERNET module
1077 * @retval HAL status
1078 */
HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef * heth)1079 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
1080 {
1081 uint32_t descriptorscancounter = 0U;
1082
1083 /* Process Locked */
1084 __HAL_LOCK(heth);
1085
1086 /* Set ETH HAL State to BUSY */
1087 heth->State = HAL_ETH_STATE_BUSY;
1088
1089 /* Scan descriptors owned by CPU */
1090 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
1091 {
1092 /* Just for security */
1093 descriptorscancounter++;
1094
1095 /* Check if first segment in frame */
1096 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
1097 if ((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
1098 {
1099 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1100 heth->RxFrameInfos.SegCount = 1U;
1101 /* Point to next descriptor */
1102 heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
1103 }
1104 /* Check if intermediate segment */
1105 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
1106 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
1107 {
1108 /* Increment segment count */
1109 (heth->RxFrameInfos.SegCount)++;
1110 /* Point to next descriptor */
1111 heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
1112 }
1113 /* Should be last segment */
1114 else
1115 {
1116 /* Last segment */
1117 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
1118
1119 /* Increment segment count */
1120 (heth->RxFrameInfos.SegCount)++;
1121
1122 /* Check if last segment is first segment: one segment contains the frame */
1123 if ((heth->RxFrameInfos.SegCount) == 1U)
1124 {
1125 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
1126 }
1127
1128 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
1129 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
1130
1131 /* Get the address of the buffer start address */
1132 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
1133
1134 /* Point to next descriptor */
1135 heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
1136
1137 /* Set HAL State to Ready */
1138 heth->State = HAL_ETH_STATE_READY;
1139
1140 /* Process Unlocked */
1141 __HAL_UNLOCK(heth);
1142
1143 /* Return function status */
1144 return HAL_OK;
1145 }
1146 }
1147
1148 /* Set HAL State to Ready */
1149 heth->State = HAL_ETH_STATE_READY;
1150
1151 /* Process Unlocked */
1152 __HAL_UNLOCK(heth);
1153
1154 /* Return function status */
1155 return HAL_ERROR;
1156 }
1157
1158 /**
1159 * @brief This function handles ETH interrupt request.
1160 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1161 * the configuration information for ETHERNET module
1162 * @retval HAL status
1163 */
HAL_ETH_IRQHandler(ETH_HandleTypeDef * heth)1164 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
1165 {
1166 /* Frame received */
1167 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
1168 {
1169 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1170 /*Call registered Receive complete callback*/
1171 heth->RxCpltCallback(heth);
1172 #else
1173 /* Receive complete callback */
1174 HAL_ETH_RxCpltCallback(heth);
1175 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1176
1177 /* Clear the Eth DMA Rx IT pending bits */
1178 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
1179
1180 /* Set HAL State to Ready */
1181 heth->State = HAL_ETH_STATE_READY;
1182
1183 /* Process Unlocked */
1184 __HAL_UNLOCK(heth);
1185
1186 }
1187 /* Frame transmitted */
1188 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
1189 {
1190 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1191 /* Call resgistered Transfer complete callback*/
1192 heth->TxCpltCallback(heth);
1193 #else
1194 /* Transfer complete callback */
1195 HAL_ETH_TxCpltCallback(heth);
1196 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1197
1198 /* Clear the Eth DMA Tx IT pending bits */
1199 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
1200
1201 /* Set HAL State to Ready */
1202 heth->State = HAL_ETH_STATE_READY;
1203
1204 /* Process Unlocked */
1205 __HAL_UNLOCK(heth);
1206 }
1207
1208 /* Clear the interrupt flags */
1209 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
1210
1211 /* ETH DMA Error */
1212 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
1213 {
1214 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1215 heth->DMAErrorCallback(heth);
1216 #else
1217 /* Ethernet Error callback */
1218 HAL_ETH_ErrorCallback(heth);
1219 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1220
1221 /* Clear the interrupt flags */
1222 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
1223
1224 /* Set HAL State to Ready */
1225 heth->State = HAL_ETH_STATE_READY;
1226
1227 /* Process Unlocked */
1228 __HAL_UNLOCK(heth);
1229 }
1230 }
1231
1232 /**
1233 * @brief Tx Transfer completed callbacks.
1234 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1235 * the configuration information for ETHERNET module
1236 * @retval None
1237 */
HAL_ETH_TxCpltCallback(ETH_HandleTypeDef * heth)1238 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
1239 {
1240 /* Prevent unused argument(s) compilation warning */
1241 UNUSED(heth);
1242 /* NOTE : This function Should not be modified, when the callback is needed,
1243 the HAL_ETH_TxCpltCallback could be implemented in the user file
1244 */
1245 }
1246
1247 /**
1248 * @brief Rx Transfer completed callbacks.
1249 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1250 * the configuration information for ETHERNET module
1251 * @retval None
1252 */
HAL_ETH_RxCpltCallback(ETH_HandleTypeDef * heth)1253 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
1254 {
1255 /* Prevent unused argument(s) compilation warning */
1256 UNUSED(heth);
1257 /* NOTE : This function Should not be modified, when the callback is needed,
1258 the HAL_ETH_TxCpltCallback could be implemented in the user file
1259 */
1260 }
1261
1262 /**
1263 * @brief Ethernet transfer error callbacks
1264 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1265 * the configuration information for ETHERNET module
1266 * @retval None
1267 */
HAL_ETH_ErrorCallback(ETH_HandleTypeDef * heth)1268 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
1269 {
1270 /* Prevent unused argument(s) compilation warning */
1271 UNUSED(heth);
1272 /* NOTE : This function Should not be modified, when the callback is needed,
1273 the HAL_ETH_TxCpltCallback could be implemented in the user file
1274 */
1275 }
1276
1277 /**
1278 * @brief Reads a PHY register
1279 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1280 * the configuration information for ETHERNET module
1281 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1282 * This parameter can be one of the following values:
1283 * PHY_BCR: Transceiver Basic Control Register,
1284 * PHY_BSR: Transceiver Basic Status Register.
1285 * More PHY register could be read depending on the used PHY
1286 * @param RegValue PHY register value
1287 * @retval HAL status
1288 */
HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef * heth,uint16_t PHYReg,uint32_t * RegValue)1289 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
1290 {
1291 uint32_t tmpreg1 = 0U;
1292 uint32_t tickstart = 0U;
1293
1294 /* Check parameters */
1295 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1296
1297 /* Check the ETH peripheral state */
1298 if (heth->State == HAL_ETH_STATE_BUSY_RD)
1299 {
1300 return HAL_BUSY;
1301 }
1302 /* Set ETH HAL State to BUSY_RD */
1303 heth->State = HAL_ETH_STATE_BUSY_RD;
1304
1305 /* Get the ETHERNET MACMIIAR value */
1306 tmpreg1 = heth->Instance->MACMIIAR;
1307
1308 /* Keep only the CSR Clock Range CR[2:0] bits value */
1309 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1310
1311 /* Prepare the MII address register value */
1312 tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1313 tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1314 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
1315 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1316
1317 /* Write the result value into the MII Address register */
1318 heth->Instance->MACMIIAR = tmpreg1;
1319
1320 /* Get tick */
1321 tickstart = HAL_GetTick();
1322
1323 /* Check for the Busy flag */
1324 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1325 {
1326 /* Check for the Timeout */
1327 if ((HAL_GetTick() - tickstart) > PHY_READ_TO)
1328 {
1329 heth->State = HAL_ETH_STATE_READY;
1330
1331 /* Process Unlocked */
1332 __HAL_UNLOCK(heth);
1333
1334 return HAL_TIMEOUT;
1335 }
1336
1337 tmpreg1 = heth->Instance->MACMIIAR;
1338 }
1339
1340 /* Get MACMIIDR value */
1341 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
1342
1343 /* Set ETH HAL State to READY */
1344 heth->State = HAL_ETH_STATE_READY;
1345
1346 /* Return function status */
1347 return HAL_OK;
1348 }
1349
1350 /**
1351 * @brief Writes to a PHY register.
1352 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1353 * the configuration information for ETHERNET module
1354 * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
1355 * This parameter can be one of the following values:
1356 * PHY_BCR: Transceiver Control Register.
1357 * More PHY register could be written depending on the used PHY
1358 * @param RegValue the value to write
1359 * @retval HAL status
1360 */
HAL_ETH_WritePHYRegister(ETH_HandleTypeDef * heth,uint16_t PHYReg,uint32_t RegValue)1361 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
1362 {
1363 uint32_t tmpreg1 = 0U;
1364 uint32_t tickstart = 0U;
1365
1366 /* Check parameters */
1367 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
1368
1369 /* Check the ETH peripheral state */
1370 if (heth->State == HAL_ETH_STATE_BUSY_WR)
1371 {
1372 return HAL_BUSY;
1373 }
1374 /* Set ETH HAL State to BUSY_WR */
1375 heth->State = HAL_ETH_STATE_BUSY_WR;
1376
1377 /* Get the ETHERNET MACMIIAR value */
1378 tmpreg1 = heth->Instance->MACMIIAR;
1379
1380 /* Keep only the CSR Clock Range CR[2:0] bits value */
1381 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
1382
1383 /* Prepare the MII register address value */
1384 tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
1385 tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
1386 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
1387 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
1388
1389 /* Give the value to the MII data register */
1390 heth->Instance->MACMIIDR = (uint16_t)RegValue;
1391
1392 /* Write the result value into the MII Address register */
1393 heth->Instance->MACMIIAR = tmpreg1;
1394
1395 /* Get tick */
1396 tickstart = HAL_GetTick();
1397
1398 /* Check for the Busy flag */
1399 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
1400 {
1401 /* Check for the Timeout */
1402 if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO)
1403 {
1404 heth->State = HAL_ETH_STATE_READY;
1405
1406 /* Process Unlocked */
1407 __HAL_UNLOCK(heth);
1408
1409 return HAL_TIMEOUT;
1410 }
1411
1412 tmpreg1 = heth->Instance->MACMIIAR;
1413 }
1414
1415 /* Set ETH HAL State to READY */
1416 heth->State = HAL_ETH_STATE_READY;
1417
1418 /* Return function status */
1419 return HAL_OK;
1420 }
1421
1422 /**
1423 * @}
1424 */
1425
1426 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
1427 * @brief Peripheral Control functions
1428 *
1429 @verbatim
1430 ===============================================================================
1431 ##### Peripheral Control functions #####
1432 ===============================================================================
1433 [..] This section provides functions allowing to:
1434 (+) Enable MAC and DMA transmission and reception.
1435 HAL_ETH_Start();
1436 (+) Disable MAC and DMA transmission and reception.
1437 HAL_ETH_Stop();
1438 (+) Set the MAC configuration in runtime mode
1439 HAL_ETH_ConfigMAC();
1440 (+) Set the DMA configuration in runtime mode
1441 HAL_ETH_ConfigDMA();
1442
1443 @endverbatim
1444 * @{
1445 */
1446
1447 /**
1448 * @brief Enables Ethernet MAC and DMA reception/transmission
1449 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1450 * the configuration information for ETHERNET module
1451 * @retval HAL status
1452 */
HAL_ETH_Start(ETH_HandleTypeDef * heth)1453 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
1454 {
1455 /* Process Locked */
1456 __HAL_LOCK(heth);
1457
1458 /* Set the ETH peripheral state to BUSY */
1459 heth->State = HAL_ETH_STATE_BUSY;
1460
1461 /* Enable transmit state machine of the MAC for transmission on the MII */
1462 ETH_MACTransmissionEnable(heth);
1463
1464 /* Enable receive state machine of the MAC for reception from the MII */
1465 ETH_MACReceptionEnable(heth);
1466
1467 /* Flush Transmit FIFO */
1468 ETH_FlushTransmitFIFO(heth);
1469
1470 /* Start DMA transmission */
1471 ETH_DMATransmissionEnable(heth);
1472
1473 /* Start DMA reception */
1474 ETH_DMAReceptionEnable(heth);
1475
1476 /* Set the ETH state to READY*/
1477 heth->State = HAL_ETH_STATE_READY;
1478
1479 /* Process Unlocked */
1480 __HAL_UNLOCK(heth);
1481
1482 /* Return function status */
1483 return HAL_OK;
1484 }
1485
1486 /**
1487 * @brief Stop Ethernet MAC and DMA reception/transmission
1488 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1489 * the configuration information for ETHERNET module
1490 * @retval HAL status
1491 */
HAL_ETH_Stop(ETH_HandleTypeDef * heth)1492 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
1493 {
1494 /* Process Locked */
1495 __HAL_LOCK(heth);
1496
1497 /* Set the ETH peripheral state to BUSY */
1498 heth->State = HAL_ETH_STATE_BUSY;
1499
1500 /* Stop DMA transmission */
1501 ETH_DMATransmissionDisable(heth);
1502
1503 /* Stop DMA reception */
1504 ETH_DMAReceptionDisable(heth);
1505
1506 /* Disable receive state machine of the MAC for reception from the MII */
1507 ETH_MACReceptionDisable(heth);
1508
1509 /* Flush Transmit FIFO */
1510 ETH_FlushTransmitFIFO(heth);
1511
1512 /* Disable transmit state machine of the MAC for transmission on the MII */
1513 ETH_MACTransmissionDisable(heth);
1514
1515 /* Set the ETH state*/
1516 heth->State = HAL_ETH_STATE_READY;
1517
1518 /* Process Unlocked */
1519 __HAL_UNLOCK(heth);
1520
1521 /* Return function status */
1522 return HAL_OK;
1523 }
1524
1525 /**
1526 * @brief Set ETH MAC Configuration.
1527 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1528 * the configuration information for ETHERNET module
1529 * @param macconf MAC Configuration structure
1530 * @retval HAL status
1531 */
HAL_ETH_ConfigMAC(ETH_HandleTypeDef * heth,ETH_MACInitTypeDef * macconf)1532 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
1533 {
1534 uint32_t tmpreg1 = 0U;
1535
1536 /* Process Locked */
1537 __HAL_LOCK(heth);
1538
1539 /* Set the ETH peripheral state to BUSY */
1540 heth->State = HAL_ETH_STATE_BUSY;
1541
1542 assert_param(IS_ETH_SPEED(heth->Init.Speed));
1543 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
1544
1545 if (macconf != NULL)
1546 {
1547 /* Check the parameters */
1548 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
1549 assert_param(IS_ETH_JABBER(macconf->Jabber));
1550 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
1551 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
1552 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
1553 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
1554 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
1555 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
1556 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
1557 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
1558 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
1559 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
1560 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
1561 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
1562 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
1563 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
1564 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
1565 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
1566 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
1567 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
1568 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
1569 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
1570 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
1571 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
1572 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
1573 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
1574 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
1575
1576 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1577 /* Get the ETHERNET MACCR value */
1578 tmpreg1 = (heth->Instance)->MACCR;
1579 /* Clear WD, PCE, PS, TE and RE bits */
1580 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1581
1582 tmpreg1 |= (uint32_t)(macconf->Watchdog |
1583 macconf->Jabber |
1584 macconf->InterFrameGap |
1585 macconf->CarrierSense |
1586 (heth->Init).Speed |
1587 macconf->ReceiveOwn |
1588 macconf->LoopbackMode |
1589 (heth->Init).DuplexMode |
1590 macconf->ChecksumOffload |
1591 macconf->RetryTransmission |
1592 macconf->AutomaticPadCRCStrip |
1593 macconf->BackOffLimit |
1594 macconf->DeferralCheck);
1595
1596 /* Write to ETHERNET MACCR */
1597 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1598
1599 /* Wait until the write operation will be taken into account :
1600 at least four TX_CLK/RX_CLK clock cycles */
1601 tmpreg1 = (heth->Instance)->MACCR;
1602 HAL_Delay(ETH_REG_WRITE_DELAY);
1603 (heth->Instance)->MACCR = tmpreg1;
1604
1605 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1606 /* Write to ETHERNET MACFFR */
1607 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
1608 macconf->SourceAddrFilter |
1609 macconf->PassControlFrames |
1610 macconf->BroadcastFramesReception |
1611 macconf->DestinationAddrFilter |
1612 macconf->PromiscuousMode |
1613 macconf->MulticastFramesFilter |
1614 macconf->UnicastFramesFilter);
1615
1616 /* Wait until the write operation will be taken into account :
1617 at least four TX_CLK/RX_CLK clock cycles */
1618 tmpreg1 = (heth->Instance)->MACFFR;
1619 HAL_Delay(ETH_REG_WRITE_DELAY);
1620 (heth->Instance)->MACFFR = tmpreg1;
1621
1622 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
1623 /* Write to ETHERNET MACHTHR */
1624 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
1625
1626 /* Write to ETHERNET MACHTLR */
1627 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
1628 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
1629
1630 /* Get the ETHERNET MACFCR value */
1631 tmpreg1 = (heth->Instance)->MACFCR;
1632 /* Clear xx bits */
1633 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1634
1635 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
1636 macconf->ZeroQuantaPause |
1637 macconf->PauseLowThreshold |
1638 macconf->UnicastPauseFrameDetect |
1639 macconf->ReceiveFlowControl |
1640 macconf->TransmitFlowControl);
1641
1642 /* Write to ETHERNET MACFCR */
1643 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1644
1645 /* Wait until the write operation will be taken into account :
1646 at least four TX_CLK/RX_CLK clock cycles */
1647 tmpreg1 = (heth->Instance)->MACFCR;
1648 HAL_Delay(ETH_REG_WRITE_DELAY);
1649 (heth->Instance)->MACFCR = tmpreg1;
1650
1651 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
1652 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
1653 macconf->VLANTagIdentifier);
1654
1655 /* Wait until the write operation will be taken into account :
1656 at least four TX_CLK/RX_CLK clock cycles */
1657 tmpreg1 = (heth->Instance)->MACVLANTR;
1658 HAL_Delay(ETH_REG_WRITE_DELAY);
1659 (heth->Instance)->MACVLANTR = tmpreg1;
1660 }
1661 else /* macconf == NULL : here we just configure Speed and Duplex mode */
1662 {
1663 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1664 /* Get the ETHERNET MACCR value */
1665 tmpreg1 = (heth->Instance)->MACCR;
1666
1667 /* Clear FES and DM bits */
1668 tmpreg1 &= ~(0x00004800U);
1669
1670 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
1671
1672 /* Write to ETHERNET MACCR */
1673 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1674
1675 /* Wait until the write operation will be taken into account:
1676 at least four TX_CLK/RX_CLK clock cycles */
1677 tmpreg1 = (heth->Instance)->MACCR;
1678 HAL_Delay(ETH_REG_WRITE_DELAY);
1679 (heth->Instance)->MACCR = tmpreg1;
1680 }
1681
1682 /* Set the ETH state to Ready */
1683 heth->State = HAL_ETH_STATE_READY;
1684
1685 /* Process Unlocked */
1686 __HAL_UNLOCK(heth);
1687
1688 /* Return function status */
1689 return HAL_OK;
1690 }
1691
1692 /**
1693 * @brief Sets ETH DMA Configuration.
1694 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1695 * the configuration information for ETHERNET module
1696 * @param dmaconf DMA Configuration structure
1697 * @retval HAL status
1698 */
HAL_ETH_ConfigDMA(ETH_HandleTypeDef * heth,ETH_DMAInitTypeDef * dmaconf)1699 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
1700 {
1701 uint32_t tmpreg1 = 0U;
1702
1703 /* Process Locked */
1704 __HAL_LOCK(heth);
1705
1706 /* Set the ETH peripheral state to BUSY */
1707 heth->State = HAL_ETH_STATE_BUSY;
1708
1709 /* Check parameters */
1710 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
1711 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
1712 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
1713 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
1714 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
1715 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
1716 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
1717 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
1718 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
1719 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
1720 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
1721 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
1722 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
1723 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
1724 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
1725 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
1726
1727 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
1728 /* Get the ETHERNET DMAOMR value */
1729 tmpreg1 = (heth->Instance)->DMAOMR;
1730 /* Clear xx bits */
1731 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
1732
1733 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
1734 dmaconf->ReceiveStoreForward |
1735 dmaconf->FlushReceivedFrame |
1736 dmaconf->TransmitStoreForward |
1737 dmaconf->TransmitThresholdControl |
1738 dmaconf->ForwardErrorFrames |
1739 dmaconf->ForwardUndersizedGoodFrames |
1740 dmaconf->ReceiveThresholdControl |
1741 dmaconf->SecondFrameOperate);
1742
1743 /* Write to ETHERNET DMAOMR */
1744 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
1745
1746 /* Wait until the write operation will be taken into account:
1747 at least four TX_CLK/RX_CLK clock cycles */
1748 tmpreg1 = (heth->Instance)->DMAOMR;
1749 HAL_Delay(ETH_REG_WRITE_DELAY);
1750 (heth->Instance)->DMAOMR = tmpreg1;
1751
1752 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
1753 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
1754 dmaconf->FixedBurst |
1755 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
1756 dmaconf->TxDMABurstLength |
1757 dmaconf->EnhancedDescriptorFormat |
1758 (dmaconf->DescriptorSkipLength << 2U) |
1759 dmaconf->DMAArbitration |
1760 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
1761
1762 /* Wait until the write operation will be taken into account:
1763 at least four TX_CLK/RX_CLK clock cycles */
1764 tmpreg1 = (heth->Instance)->DMABMR;
1765 HAL_Delay(ETH_REG_WRITE_DELAY);
1766 (heth->Instance)->DMABMR = tmpreg1;
1767
1768 /* Set the ETH state to Ready */
1769 heth->State = HAL_ETH_STATE_READY;
1770
1771 /* Process Unlocked */
1772 __HAL_UNLOCK(heth);
1773
1774 /* Return function status */
1775 return HAL_OK;
1776 }
1777
1778 /**
1779 * @}
1780 */
1781
1782 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
1783 * @brief Peripheral State functions
1784 *
1785 @verbatim
1786 ===============================================================================
1787 ##### Peripheral State functions #####
1788 ===============================================================================
1789 [..]
1790 This subsection permits to get in run-time the status of the peripheral
1791 and the data flow.
1792 (+) Get the ETH handle state:
1793 HAL_ETH_GetState();
1794
1795
1796 @endverbatim
1797 * @{
1798 */
1799
1800 /**
1801 * @brief Return the ETH HAL state
1802 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1803 * the configuration information for ETHERNET module
1804 * @retval HAL state
1805 */
HAL_ETH_GetState(ETH_HandleTypeDef * heth)1806 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
1807 {
1808 /* Return ETH state */
1809 return heth->State;
1810 }
1811
1812 /**
1813 * @}
1814 */
1815
1816 /**
1817 * @}
1818 */
1819
1820 /** @addtogroup ETH_Private_Functions
1821 * @{
1822 */
1823
1824 /**
1825 * @brief Configures Ethernet MAC and DMA with default parameters.
1826 * @param heth pointer to a ETH_HandleTypeDef structure that contains
1827 * the configuration information for ETHERNET module
1828 * @param err Ethernet Init error
1829 * @retval HAL status
1830 */
ETH_MACDMAConfig(ETH_HandleTypeDef * heth,uint32_t err)1831 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
1832 {
1833 ETH_MACInitTypeDef macinit;
1834 ETH_DMAInitTypeDef dmainit;
1835 uint32_t tmpreg1 = 0U;
1836
1837 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
1838 {
1839 /* Set Ethernet duplex mode to Full-duplex */
1840 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
1841
1842 /* Set Ethernet speed to 100M */
1843 (heth->Init).Speed = ETH_SPEED_100M;
1844 }
1845
1846 /* Ethernet MAC default initialization **************************************/
1847 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
1848 macinit.Jabber = ETH_JABBER_ENABLE;
1849 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
1850 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
1851 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
1852 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
1853 if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
1854 {
1855 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
1856 }
1857 else
1858 {
1859 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
1860 }
1861 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
1862 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
1863 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
1864 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
1865 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
1866 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
1867 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
1868 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
1869 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
1870 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
1871 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
1872 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
1873 macinit.HashTableHigh = 0x0U;
1874 macinit.HashTableLow = 0x0U;
1875 macinit.PauseTime = 0x0U;
1876 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
1877 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
1878 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
1879 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
1880 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
1881 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
1882 macinit.VLANTagIdentifier = 0x0U;
1883
1884 /*------------------------ ETHERNET MACCR Configuration --------------------*/
1885 /* Get the ETHERNET MACCR value */
1886 tmpreg1 = (heth->Instance)->MACCR;
1887 /* Clear WD, PCE, PS, TE and RE bits */
1888 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
1889 /* Set the WD bit according to ETH Watchdog value */
1890 /* Set the JD: bit according to ETH Jabber value */
1891 /* Set the IFG bit according to ETH InterFrameGap value */
1892 /* Set the DCRS bit according to ETH CarrierSense value */
1893 /* Set the FES bit according to ETH Speed value */
1894 /* Set the DO bit according to ETH ReceiveOwn value */
1895 /* Set the LM bit according to ETH LoopbackMode value */
1896 /* Set the DM bit according to ETH Mode value */
1897 /* Set the IPCO bit according to ETH ChecksumOffload value */
1898 /* Set the DR bit according to ETH RetryTransmission value */
1899 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
1900 /* Set the BL bit according to ETH BackOffLimit value */
1901 /* Set the DC bit according to ETH DeferralCheck value */
1902 tmpreg1 |= (uint32_t)(macinit.Watchdog |
1903 macinit.Jabber |
1904 macinit.InterFrameGap |
1905 macinit.CarrierSense |
1906 (heth->Init).Speed |
1907 macinit.ReceiveOwn |
1908 macinit.LoopbackMode |
1909 (heth->Init).DuplexMode |
1910 macinit.ChecksumOffload |
1911 macinit.RetryTransmission |
1912 macinit.AutomaticPadCRCStrip |
1913 macinit.BackOffLimit |
1914 macinit.DeferralCheck);
1915
1916 /* Write to ETHERNET MACCR */
1917 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
1918
1919 /* Wait until the write operation will be taken into account:
1920 at least four TX_CLK/RX_CLK clock cycles */
1921 tmpreg1 = (heth->Instance)->MACCR;
1922 HAL_Delay(ETH_REG_WRITE_DELAY);
1923 (heth->Instance)->MACCR = tmpreg1;
1924
1925 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
1926 /* Set the RA bit according to ETH ReceiveAll value */
1927 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
1928 /* Set the PCF bit according to ETH PassControlFrames value */
1929 /* Set the DBF bit according to ETH BroadcastFramesReception value */
1930 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
1931 /* Set the PR bit according to ETH PromiscuousMode value */
1932 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
1933 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
1934 /* Write to ETHERNET MACFFR */
1935 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
1936 macinit.SourceAddrFilter |
1937 macinit.PassControlFrames |
1938 macinit.BroadcastFramesReception |
1939 macinit.DestinationAddrFilter |
1940 macinit.PromiscuousMode |
1941 macinit.MulticastFramesFilter |
1942 macinit.UnicastFramesFilter);
1943
1944 /* Wait until the write operation will be taken into account:
1945 at least four TX_CLK/RX_CLK clock cycles */
1946 tmpreg1 = (heth->Instance)->MACFFR;
1947 HAL_Delay(ETH_REG_WRITE_DELAY);
1948 (heth->Instance)->MACFFR = tmpreg1;
1949
1950 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
1951 /* Write to ETHERNET MACHTHR */
1952 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
1953
1954 /* Write to ETHERNET MACHTLR */
1955 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
1956 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
1957
1958 /* Get the ETHERNET MACFCR value */
1959 tmpreg1 = (heth->Instance)->MACFCR;
1960 /* Clear xx bits */
1961 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
1962
1963 /* Set the PT bit according to ETH PauseTime value */
1964 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
1965 /* Set the PLT bit according to ETH PauseLowThreshold value */
1966 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
1967 /* Set the RFE bit according to ETH ReceiveFlowControl value */
1968 /* Set the TFE bit according to ETH TransmitFlowControl value */
1969 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
1970 macinit.ZeroQuantaPause |
1971 macinit.PauseLowThreshold |
1972 macinit.UnicastPauseFrameDetect |
1973 macinit.ReceiveFlowControl |
1974 macinit.TransmitFlowControl);
1975
1976 /* Write to ETHERNET MACFCR */
1977 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
1978
1979 /* Wait until the write operation will be taken into account:
1980 at least four TX_CLK/RX_CLK clock cycles */
1981 tmpreg1 = (heth->Instance)->MACFCR;
1982 HAL_Delay(ETH_REG_WRITE_DELAY);
1983 (heth->Instance)->MACFCR = tmpreg1;
1984
1985 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
1986 /* Set the ETV bit according to ETH VLANTagComparison value */
1987 /* Set the VL bit according to ETH VLANTagIdentifier value */
1988 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
1989 macinit.VLANTagIdentifier);
1990
1991 /* Wait until the write operation will be taken into account:
1992 at least four TX_CLK/RX_CLK clock cycles */
1993 tmpreg1 = (heth->Instance)->MACVLANTR;
1994 HAL_Delay(ETH_REG_WRITE_DELAY);
1995 (heth->Instance)->MACVLANTR = tmpreg1;
1996
1997 /* Ethernet DMA default initialization ************************************/
1998 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
1999 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
2000 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
2001 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
2002 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
2003 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
2004 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
2005 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
2006 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
2007 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
2008 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
2009 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
2010 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
2011 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
2012 dmainit.DescriptorSkipLength = 0x0U;
2013 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
2014
2015 /* Get the ETHERNET DMAOMR value */
2016 tmpreg1 = (heth->Instance)->DMAOMR;
2017 /* Clear xx bits */
2018 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
2019
2020 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
2021 /* Set the RSF bit according to ETH ReceiveStoreForward value */
2022 /* Set the DFF bit according to ETH FlushReceivedFrame value */
2023 /* Set the TSF bit according to ETH TransmitStoreForward value */
2024 /* Set the TTC bit according to ETH TransmitThresholdControl value */
2025 /* Set the FEF bit according to ETH ForwardErrorFrames value */
2026 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
2027 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
2028 /* Set the OSF bit according to ETH SecondFrameOperate value */
2029 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
2030 dmainit.ReceiveStoreForward |
2031 dmainit.FlushReceivedFrame |
2032 dmainit.TransmitStoreForward |
2033 dmainit.TransmitThresholdControl |
2034 dmainit.ForwardErrorFrames |
2035 dmainit.ForwardUndersizedGoodFrames |
2036 dmainit.ReceiveThresholdControl |
2037 dmainit.SecondFrameOperate);
2038
2039 /* Write to ETHERNET DMAOMR */
2040 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
2041
2042 /* Wait until the write operation will be taken into account:
2043 at least four TX_CLK/RX_CLK clock cycles */
2044 tmpreg1 = (heth->Instance)->DMAOMR;
2045 HAL_Delay(ETH_REG_WRITE_DELAY);
2046 (heth->Instance)->DMAOMR = tmpreg1;
2047
2048 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
2049 /* Set the AAL bit according to ETH AddressAlignedBeats value */
2050 /* Set the FB bit according to ETH FixedBurst value */
2051 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
2052 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
2053 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
2054 /* Set the DSL bit according to ETH DesciptorSkipLength value */
2055 /* Set the PR and DA bits according to ETH DMAArbitration value */
2056 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
2057 dmainit.FixedBurst |
2058 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
2059 dmainit.TxDMABurstLength |
2060 dmainit.EnhancedDescriptorFormat |
2061 (dmainit.DescriptorSkipLength << 2U) |
2062 dmainit.DMAArbitration |
2063 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
2064
2065 /* Wait until the write operation will be taken into account:
2066 at least four TX_CLK/RX_CLK clock cycles */
2067 tmpreg1 = (heth->Instance)->DMABMR;
2068 HAL_Delay(ETH_REG_WRITE_DELAY);
2069 (heth->Instance)->DMABMR = tmpreg1;
2070
2071 if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
2072 {
2073 /* Enable the Ethernet Rx Interrupt */
2074 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
2075 }
2076
2077 /* Initialize MAC address in ethernet MAC */
2078 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
2079 }
2080
2081 /**
2082 * @brief Configures the selected MAC address.
2083 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2084 * the configuration information for ETHERNET module
2085 * @param MacAddr The MAC address to configure
2086 * This parameter can be one of the following values:
2087 * @arg ETH_MAC_Address0: MAC Address0
2088 * @arg ETH_MAC_Address1: MAC Address1
2089 * @arg ETH_MAC_Address2: MAC Address2
2090 * @arg ETH_MAC_Address3: MAC Address3
2091 * @param Addr Pointer to MAC address buffer data (6 bytes)
2092 * @retval HAL status
2093 */
ETH_MACAddressConfig(ETH_HandleTypeDef * heth,uint32_t MacAddr,uint8_t * Addr)2094 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
2095 {
2096 uint32_t tmpreg1;
2097
2098 /* Prevent unused argument(s) compilation warning */
2099 UNUSED(heth);
2100
2101 /* Check the parameters */
2102 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
2103
2104 /* Calculate the selected MAC address high register */
2105 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
2106 /* Load the selected MAC address high register */
2107 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
2108 /* Calculate the selected MAC address low register */
2109 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
2110
2111 /* Load the selected MAC address low register */
2112 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
2113 }
2114
2115 /**
2116 * @brief Enables the MAC transmission.
2117 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2118 * the configuration information for ETHERNET module
2119 * @retval None
2120 */
ETH_MACTransmissionEnable(ETH_HandleTypeDef * heth)2121 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
2122 {
2123 __IO uint32_t tmpreg1 = 0U;
2124
2125 /* Enable the MAC transmission */
2126 (heth->Instance)->MACCR |= ETH_MACCR_TE;
2127
2128 /* Wait until the write operation will be taken into account:
2129 at least four TX_CLK/RX_CLK clock cycles */
2130 tmpreg1 = (heth->Instance)->MACCR;
2131 ETH_Delay(ETH_REG_WRITE_DELAY);
2132 (heth->Instance)->MACCR = tmpreg1;
2133 }
2134
2135 /**
2136 * @brief Disables the MAC transmission.
2137 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2138 * the configuration information for ETHERNET module
2139 * @retval None
2140 */
ETH_MACTransmissionDisable(ETH_HandleTypeDef * heth)2141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
2142 {
2143 __IO uint32_t tmpreg1 = 0U;
2144
2145 /* Disable the MAC transmission */
2146 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
2147
2148 /* Wait until the write operation will be taken into account:
2149 at least four TX_CLK/RX_CLK clock cycles */
2150 tmpreg1 = (heth->Instance)->MACCR;
2151 ETH_Delay(ETH_REG_WRITE_DELAY);
2152 (heth->Instance)->MACCR = tmpreg1;
2153 }
2154
2155 /**
2156 * @brief Enables the MAC reception.
2157 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2158 * the configuration information for ETHERNET module
2159 * @retval None
2160 */
ETH_MACReceptionEnable(ETH_HandleTypeDef * heth)2161 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
2162 {
2163 __IO uint32_t tmpreg1 = 0U;
2164
2165 /* Enable the MAC reception */
2166 (heth->Instance)->MACCR |= ETH_MACCR_RE;
2167
2168 /* Wait until the write operation will be taken into account:
2169 at least four TX_CLK/RX_CLK clock cycles */
2170 tmpreg1 = (heth->Instance)->MACCR;
2171 ETH_Delay(ETH_REG_WRITE_DELAY);
2172 (heth->Instance)->MACCR = tmpreg1;
2173 }
2174
2175 /**
2176 * @brief Disables the MAC reception.
2177 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2178 * the configuration information for ETHERNET module
2179 * @retval None
2180 */
ETH_MACReceptionDisable(ETH_HandleTypeDef * heth)2181 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
2182 {
2183 __IO uint32_t tmpreg1 = 0U;
2184
2185 /* Disable the MAC reception */
2186 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
2187
2188 /* Wait until the write operation will be taken into account:
2189 at least four TX_CLK/RX_CLK clock cycles */
2190 tmpreg1 = (heth->Instance)->MACCR;
2191 ETH_Delay(ETH_REG_WRITE_DELAY);
2192 (heth->Instance)->MACCR = tmpreg1;
2193 }
2194
2195 /**
2196 * @brief Enables the DMA transmission.
2197 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2198 * the configuration information for ETHERNET module
2199 * @retval None
2200 */
ETH_DMATransmissionEnable(ETH_HandleTypeDef * heth)2201 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
2202 {
2203 /* Enable the DMA transmission */
2204 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
2205 }
2206
2207 /**
2208 * @brief Disables the DMA transmission.
2209 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2210 * the configuration information for ETHERNET module
2211 * @retval None
2212 */
ETH_DMATransmissionDisable(ETH_HandleTypeDef * heth)2213 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
2214 {
2215 /* Disable the DMA transmission */
2216 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
2217 }
2218
2219 /**
2220 * @brief Enables the DMA reception.
2221 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2222 * the configuration information for ETHERNET module
2223 * @retval None
2224 */
ETH_DMAReceptionEnable(ETH_HandleTypeDef * heth)2225 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
2226 {
2227 /* Enable the DMA reception */
2228 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
2229 }
2230
2231 /**
2232 * @brief Disables the DMA reception.
2233 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2234 * the configuration information for ETHERNET module
2235 * @retval None
2236 */
ETH_DMAReceptionDisable(ETH_HandleTypeDef * heth)2237 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
2238 {
2239 /* Disable the DMA reception */
2240 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
2241 }
2242
2243 /**
2244 * @brief Clears the ETHERNET transmit FIFO.
2245 * @param heth pointer to a ETH_HandleTypeDef structure that contains
2246 * the configuration information for ETHERNET module
2247 * @retval None
2248 */
ETH_FlushTransmitFIFO(ETH_HandleTypeDef * heth)2249 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
2250 {
2251 __IO uint32_t tmpreg1 = 0U;
2252
2253 /* Set the Flush Transmit FIFO bit */
2254 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
2255
2256 /* Wait until the write operation will be taken into account:
2257 at least four TX_CLK/RX_CLK clock cycles */
2258 tmpreg1 = (heth->Instance)->DMAOMR;
2259 ETH_Delay(ETH_REG_WRITE_DELAY);
2260 (heth->Instance)->DMAOMR = tmpreg1;
2261 }
2262
2263 /**
2264 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
2265 * @param mdelay specifies the delay time length, in milliseconds.
2266 * @retval None
2267 */
ETH_Delay(uint32_t mdelay)2268 static void ETH_Delay(uint32_t mdelay)
2269 {
2270 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
2271 do
2272 {
2273 __NOP();
2274 }
2275 while (Delay --);
2276 }
2277
2278 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
ETH_InitCallbacksToDefault(ETH_HandleTypeDef * heth)2279 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
2280 {
2281 /* Init the ETH Callback settings */
2282 heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
2283 heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
2284 heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
2285 }
2286 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2287
2288 /**
2289 * @}
2290 */
2291
2292 #endif /* ETH */
2293 #endif /* HAL_ETH_MODULE_ENABLED */
2294 /**
2295 * @}
2296 */
2297
2298 /**
2299 * @}
2300 */
2301
