1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F2xx_LL_UTILS_H
34 #define __STM32F2xx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f2xx.h"
42
43 /** @addtogroup STM32F2xx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
78 * @{
79 */
80 /**
81 * @}
82 */
83 /* Exported types ------------------------------------------------------------*/
84 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
85 * @{
86 */
87 /**
88 * @brief UTILS PLL structure definition
89 */
90 typedef struct
91 {
92 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
93 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
94
95 This feature can be modified afterwards using unitary function
96 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
97
98 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
99 This parameter must be a number between Min_Data = 8 and Max_Data = 86
100
101 This feature can be modified afterwards using unitary function
102 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
103
104 uint32_t PLLP; /*!< Division for the main system clock.
105 This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
109 } LL_UTILS_PLLInitTypeDef;
110
111 /**
112 * @brief UTILS System, AHB and APB buses clock configuration structure definition
113 */
114 typedef struct
115 {
116 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
117 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
118
119 This feature can be modified afterwards using unitary function
120 @ref LL_RCC_SetAHBPrescaler(). */
121
122 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
123 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
124
125 This feature can be modified afterwards using unitary function
126 @ref LL_RCC_SetAPB1Prescaler(). */
127
128 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
129 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
130
131 This feature can be modified afterwards using unitary function
132 @ref LL_RCC_SetAPB2Prescaler(). */
133
134 } LL_UTILS_ClkInitTypeDef;
135
136 /**
137 * @}
138 */
139
140 /* Exported constants --------------------------------------------------------*/
141 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
142 * @{
143 */
144
145 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
146 * @{
147 */
148 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
149 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
150 /**
151 * @}
152 */
153
154 /**
155 * @}
156 */
157
158 /* Exported macro ------------------------------------------------------------*/
159
160 /* Exported functions --------------------------------------------------------*/
161 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
162 * @{
163 */
164
165 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
166 * @{
167 */
168
169 /**
170 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
171 * @retval UID[31:0]
172 */
LL_GetUID_Word0(void)173 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
174 {
175 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
176 }
177
178 /**
179 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
180 * @retval UID[63:32]
181 */
LL_GetUID_Word1(void)182 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
183 {
184 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
185 }
186
187 /**
188 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
189 * @retval UID[95:64]
190 */
LL_GetUID_Word2(void)191 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
192 {
193 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
194 }
195
196 /**
197 * @brief Get Flash memory size
198 * @note This bitfield indicates the size of the device Flash memory expressed in
199 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
200 * @retval FLASH_SIZE[15:0]: Flash memory size
201 */
LL_GetFlashSize(void)202 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
203 {
204 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
205 }
206
207
208 /**
209 * @}
210 */
211
212 /** @defgroup UTILS_LL_EF_DELAY DELAY
213 * @{
214 */
215
216 /**
217 * @brief This function configures the Cortex-M SysTick source of the time base.
218 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
219 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
220 * configuration by calling this function, for a delay use rather osDelay RTOS service.
221 * @param Ticks Number of ticks
222 * @retval None
223 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)224 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
225 {
226 /* Configure the SysTick to have interrupt in 1ms time base */
227 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
228 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
229 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
230 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
231 }
232
233 void LL_Init1msTick(uint32_t HCLKFrequency);
234 void LL_mDelay(uint32_t Delay);
235
236 /**
237 * @}
238 */
239
240 /** @defgroup UTILS_EF_SYSTEM SYSTEM
241 * @{
242 */
243
244 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
245 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
246 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
247 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
248 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
249 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
250 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
251
252 /**
253 * @}
254 */
255
256 /**
257 * @}
258 */
259
260 /**
261 * @}
262 */
263
264 /**
265 * @}
266 */
267
268 #ifdef __cplusplus
269 }
270 #endif
271
272 #endif /* __STM32F2xx_LL_UTILS_H */
273
