1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2016 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32F2xx_LL_SYSTEM_H
35 #define __STM32F2xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32f2xx.h"
43
44 /** @addtogroup STM32F2xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @}
64 */
65
66 /* Private macros ------------------------------------------------------------*/
67 /* Exported types ------------------------------------------------------------*/
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
70 * @{
71 */
72
73 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
74 * @{
75 */
76 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */
77 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
78 #define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
79 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
80 /**
81 * @}
82 */
83
84 #if defined(SYSCFG_PMC_MII_RMII_SEL)
85 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
86 * @{
87 */
88 #define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */
89 #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
90
91 /**
92 * @}
93 */
94 #endif /* SYSCFG_PMC_MII_RMII_SEL */
95
96
97
98 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
99 * @{
100 */
101 /**
102 * @}
103 */
104
105 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
106 * @{
107 */
108 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
109 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
110 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
111 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
112 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
113 #if defined(GPIOF)
114 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
115 #endif /* GPIOF */
116 #if defined(GPIOG)
117 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
118 #endif /* GPIOG */
119 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */
120 #if defined(GPIOI)
121 #define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */
122 #endif /* GPIOI */
123 #if defined(GPIOJ)
124 #define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */
125 #endif /* GPIOJ */
126 #if defined(GPIOK)
127 #define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */
128 #endif /* GPIOK */
129 /**
130 * @}
131 */
132
133 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
134 * @{
135 */
136 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
137 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
138 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
139 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
140 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
141 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
142 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
143 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
144 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
145 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
146 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
147 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
148 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
149 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
150 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
151 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
152 /**
153 * @}
154 */
155
156 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
157 * @{
158 */
159 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
160 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
161 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
162 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
163 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
164 /**
165 * @}
166 */
167
168 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
169 * @{
170 */
171 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
172 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
173 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
174 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
175 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
176 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
177 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
178 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
179 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
180 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
181 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
182 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
183 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
184 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
185 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
186 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
187 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
188 /**
189 * @}
190 */
191
192 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
193 * @{
194 */
195 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
196 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
197 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
198 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
199 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
200 /**
201 * @}
202 */
203
204 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
205 * @{
206 */
207 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
208 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
209 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
210 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
211 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
212 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
213 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
214 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
215 /**
216 * @}
217 */
218
219 /**
220 * @}
221 */
222
223 /* Exported macro ------------------------------------------------------------*/
224
225 /* Exported functions --------------------------------------------------------*/
226 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
227 * @{
228 */
229
230 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
231 * @{
232 */
233 /**
234 * @brief Set memory mapping at address 0x00000000
235 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
236 * @param Memory This parameter can be one of the following values:
237 * @arg @ref LL_SYSCFG_REMAP_FLASH
238 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
239 * @arg @ref LL_SYSCFG_REMAP_FSMC
240 * @arg @ref LL_SYSCFG_REMAP_SRAM
241 * @retval None
242 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)243 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
244 {
245 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
246 }
247
248 /**
249 * @brief Get memory mapping at address 0x00000000
250 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
251 * @retval Returned value can be one of the following values:
252 * @arg @ref LL_SYSCFG_REMAP_FLASH
253 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
254 * @arg @ref LL_SYSCFG_REMAP_SRAM
255 * @arg @ref LL_SYSCFG_REMAP_FSMC
256 */
LL_SYSCFG_GetRemapMemory(void)257 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
258 {
259 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
260 }
261
262 /**
263 * @brief Enables the Compensation cell Power Down
264 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
265 * @note The I/O compensation cell can be used only when the device supply
266 * voltage ranges from 2.4 to 3.6 V
267 * @retval None
268 */
LL_SYSCFG_EnableCompensationCell(void)269 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
270 {
271 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
272 }
273
274 /**
275 * @brief Disables the Compensation cell Power Down
276 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
277 * @note The I/O compensation cell can be used only when the device supply
278 * voltage ranges from 2.4 to 3.6 V
279 * @retval None
280 */
LL_SYSCFG_DisableCompensationCell(void)281 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
282 {
283 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
284 }
285
286 /**
287 * @brief Get Compensation Cell ready Flag
288 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
289 * @retval State of bit (1 or 0).
290 */
LL_SYSCFG_IsActiveFlag_CMPCR(void)291 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
292 {
293 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
294 }
295 #if defined(SYSCFG_PMC_MII_RMII_SEL)
296 /**
297 * @brief Select Ethernet PHY interface
298 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
299 * @param Interface This parameter can be one of the following values:
300 * @arg @ref LL_SYSCFG_PMC_ETHMII
301 * @arg @ref LL_SYSCFG_PMC_ETHRMII
302 * @retval None
303 */
LL_SYSCFG_SetPHYInterface(uint32_t Interface)304 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
305 {
306 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
307 }
308
309 /**
310 * @brief Get Ethernet PHY interface
311 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
312 * @retval Returned value can be one of the following values:
313 * @arg @ref LL_SYSCFG_PMC_ETHMII
314 * @arg @ref LL_SYSCFG_PMC_ETHRMII
315 * @retval None
316 */
LL_SYSCFG_GetPHYInterface(void)317 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
318 {
319 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
320 }
321 #endif /* SYSCFG_PMC_MII_RMII_SEL */
322
323
324
325 /**
326 * @brief Configure source input for the EXTI external interrupt.
327 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
328 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
329 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
330 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
331 * @param Port This parameter can be one of the following values:
332 * @arg @ref LL_SYSCFG_EXTI_PORTA
333 * @arg @ref LL_SYSCFG_EXTI_PORTB
334 * @arg @ref LL_SYSCFG_EXTI_PORTC
335 * @arg @ref LL_SYSCFG_EXTI_PORTD
336 * @arg @ref LL_SYSCFG_EXTI_PORTE
337 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
338 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
339 * @arg @ref LL_SYSCFG_EXTI_PORTH
340 *
341 * (*) value not defined in all devices
342 * @param Line This parameter can be one of the following values:
343 * @arg @ref LL_SYSCFG_EXTI_LINE0
344 * @arg @ref LL_SYSCFG_EXTI_LINE1
345 * @arg @ref LL_SYSCFG_EXTI_LINE2
346 * @arg @ref LL_SYSCFG_EXTI_LINE3
347 * @arg @ref LL_SYSCFG_EXTI_LINE4
348 * @arg @ref LL_SYSCFG_EXTI_LINE5
349 * @arg @ref LL_SYSCFG_EXTI_LINE6
350 * @arg @ref LL_SYSCFG_EXTI_LINE7
351 * @arg @ref LL_SYSCFG_EXTI_LINE8
352 * @arg @ref LL_SYSCFG_EXTI_LINE9
353 * @arg @ref LL_SYSCFG_EXTI_LINE10
354 * @arg @ref LL_SYSCFG_EXTI_LINE11
355 * @arg @ref LL_SYSCFG_EXTI_LINE12
356 * @arg @ref LL_SYSCFG_EXTI_LINE13
357 * @arg @ref LL_SYSCFG_EXTI_LINE14
358 * @arg @ref LL_SYSCFG_EXTI_LINE15
359 * @retval None
360 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)361 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
362 {
363 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
364 }
365
366 /**
367 * @brief Get the configured defined for specific EXTI Line
368 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
369 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
370 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
371 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
372 * @param Line This parameter can be one of the following values:
373 * @arg @ref LL_SYSCFG_EXTI_LINE0
374 * @arg @ref LL_SYSCFG_EXTI_LINE1
375 * @arg @ref LL_SYSCFG_EXTI_LINE2
376 * @arg @ref LL_SYSCFG_EXTI_LINE3
377 * @arg @ref LL_SYSCFG_EXTI_LINE4
378 * @arg @ref LL_SYSCFG_EXTI_LINE5
379 * @arg @ref LL_SYSCFG_EXTI_LINE6
380 * @arg @ref LL_SYSCFG_EXTI_LINE7
381 * @arg @ref LL_SYSCFG_EXTI_LINE8
382 * @arg @ref LL_SYSCFG_EXTI_LINE9
383 * @arg @ref LL_SYSCFG_EXTI_LINE10
384 * @arg @ref LL_SYSCFG_EXTI_LINE11
385 * @arg @ref LL_SYSCFG_EXTI_LINE12
386 * @arg @ref LL_SYSCFG_EXTI_LINE13
387 * @arg @ref LL_SYSCFG_EXTI_LINE14
388 * @arg @ref LL_SYSCFG_EXTI_LINE15
389 * @retval Returned value can be one of the following values:
390 * @arg @ref LL_SYSCFG_EXTI_PORTA
391 * @arg @ref LL_SYSCFG_EXTI_PORTB
392 * @arg @ref LL_SYSCFG_EXTI_PORTC
393 * @arg @ref LL_SYSCFG_EXTI_PORTD
394 * @arg @ref LL_SYSCFG_EXTI_PORTE
395 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
396 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
397 * @arg @ref LL_SYSCFG_EXTI_PORTH
398 * (*) value not defined in all devices
399 */
LL_SYSCFG_GetEXTISource(uint32_t Line)400 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
401 {
402 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
403 }
404
405 /**
406 * @}
407 */
408
409
410 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
411 * @{
412 */
413
414 /**
415 * @brief Return the device identifier
416 * @note For STM32F2xxxx ,the device ID is 0x411
417 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
418 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
419 */
LL_DBGMCU_GetDeviceID(void)420 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
421 {
422 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
423 }
424
425 /**
426 * @brief Return the device revision identifier
427 * @note This field indicates the revision of the device.
428 For example, it is read as revA -> 0x1000,revZ -> 0x1001, revB -> 0x2000, revY -> 0x2001, revX -> 0x2003, rev1 -> 0x2007, revV -> 0x200F, rev2 -> 0x201F
429 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
430 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
431 */
LL_DBGMCU_GetRevisionID(void)432 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
433 {
434 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
435 }
436
437 /**
438 * @brief Enable the Debug Module during SLEEP mode
439 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
440 * @retval None
441 */
LL_DBGMCU_EnableDBGSleepMode(void)442 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
443 {
444 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
445 }
446
447 /**
448 * @brief Disable the Debug Module during SLEEP mode
449 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
450 * @retval None
451 */
LL_DBGMCU_DisableDBGSleepMode(void)452 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
453 {
454 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
455 }
456
457 /**
458 * @brief Enable the Debug Module during STOP mode
459 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
460 * @retval None
461 */
LL_DBGMCU_EnableDBGStopMode(void)462 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
463 {
464 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
465 }
466
467 /**
468 * @brief Disable the Debug Module during STOP mode
469 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
470 * @retval None
471 */
LL_DBGMCU_DisableDBGStopMode(void)472 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
473 {
474 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
475 }
476
477 /**
478 * @brief Enable the Debug Module during STANDBY mode
479 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
480 * @retval None
481 */
LL_DBGMCU_EnableDBGStandbyMode(void)482 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
483 {
484 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
485 }
486
487 /**
488 * @brief Disable the Debug Module during STANDBY mode
489 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
490 * @retval None
491 */
LL_DBGMCU_DisableDBGStandbyMode(void)492 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
493 {
494 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
495 }
496
497 /**
498 * @brief Set Trace pin assignment control
499 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
500 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
501 * @param PinAssignment This parameter can be one of the following values:
502 * @arg @ref LL_DBGMCU_TRACE_NONE
503 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
504 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
505 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
506 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
507 * @retval None
508 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)509 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
510 {
511 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
512 }
513
514 /**
515 * @brief Get Trace pin assignment control
516 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
517 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
518 * @retval Returned value can be one of the following values:
519 * @arg @ref LL_DBGMCU_TRACE_NONE
520 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
521 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
522 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
523 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
524 */
LL_DBGMCU_GetTracePinAssignment(void)525 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
526 {
527 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
528 }
529
530 /**
531 * @brief Freeze APB1 peripherals (group1 peripherals)
532 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
533 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
534 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
535 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
536 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
537 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
538 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
539 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
540 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
541 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
542 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
543 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
544 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
545 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
546 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
547 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
548 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
549 * @param Periphs This parameter can be a combination of the following values:
550 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
551 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
552 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
553 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
554 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
555 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
556 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
557 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
558 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
559 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
560 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
561 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
562 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
563 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
564 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
565 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
566 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP
567 *
568 * (*) value not defined in all devices.
569 * @retval None
570 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)571 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
572 {
573 SET_BIT(DBGMCU->APB1FZ, Periphs);
574 }
575
576 /**
577 * @brief Unfreeze APB1 peripherals (group1 peripherals)
578 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
579 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
580 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
581 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
582 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
583 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
584 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
585 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
586 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
587 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
588 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
589 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
590 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
591 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
592 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
593 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
594 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
595 * @param Periphs This parameter can be a combination of the following values:
596 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
597 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
598 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
599 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
600 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
601 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
602 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
603 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
604 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
605 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
606 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
607 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
608 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
609 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
610 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
611 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
612 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP
613 *
614 * (*) value not defined in all devices.
615 * @retval None
616 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)617 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
618 {
619 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
620 }
621
622 /**
623 * @brief Freeze APB2 peripherals
624 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
625 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
626 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
627 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
628 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
629 * @param Periphs This parameter can be a combination of the following values:
630 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
631 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
632 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
633 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
634 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
635 *
636 * (*) value not defined in all devices.
637 * @retval None
638 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)639 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
640 {
641 SET_BIT(DBGMCU->APB2FZ, Periphs);
642 }
643
644 /**
645 * @brief Unfreeze APB2 peripherals
646 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
647 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
648 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
649 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
650 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
651 * @param Periphs This parameter can be a combination of the following values:
652 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
653 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
654 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
655 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
656 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
657 *
658 * (*) value not defined in all devices.
659 * @retval None
660 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)661 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
662 {
663 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
664 }
665 /**
666 * @}
667 */
668
669 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
670 * @{
671 */
672
673 /**
674 * @brief Set FLASH Latency
675 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
676 * @param Latency This parameter can be one of the following values:
677 * @arg @ref LL_FLASH_LATENCY_0
678 * @arg @ref LL_FLASH_LATENCY_1
679 * @arg @ref LL_FLASH_LATENCY_2
680 * @arg @ref LL_FLASH_LATENCY_3
681 * @arg @ref LL_FLASH_LATENCY_4
682 * @arg @ref LL_FLASH_LATENCY_5
683 * @arg @ref LL_FLASH_LATENCY_6
684 * @arg @ref LL_FLASH_LATENCY_7
685 * @retval None
686 */
LL_FLASH_SetLatency(uint32_t Latency)687 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
688 {
689 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
690 }
691
692 /**
693 * @brief Get FLASH Latency
694 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
695 * @retval Returned value can be one of the following values:
696 * @arg @ref LL_FLASH_LATENCY_0
697 * @arg @ref LL_FLASH_LATENCY_1
698 * @arg @ref LL_FLASH_LATENCY_2
699 * @arg @ref LL_FLASH_LATENCY_3
700 * @arg @ref LL_FLASH_LATENCY_4
701 * @arg @ref LL_FLASH_LATENCY_5
702 * @arg @ref LL_FLASH_LATENCY_6
703 * @arg @ref LL_FLASH_LATENCY_7
704 */
LL_FLASH_GetLatency(void)705 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
706 {
707 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
708 }
709
710 /**
711 * @brief Enable Prefetch
712 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
713 * @retval None
714 */
LL_FLASH_EnablePrefetch(void)715 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
716 {
717 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
718 }
719
720 /**
721 * @brief Disable Prefetch
722 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
723 * @retval None
724 */
LL_FLASH_DisablePrefetch(void)725 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
726 {
727 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
728 }
729
730 /**
731 * @brief Check if Prefetch buffer is enabled
732 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
733 * @retval State of bit (1 or 0).
734 */
LL_FLASH_IsPrefetchEnabled(void)735 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
736 {
737 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
738 }
739
740 /**
741 * @brief Enable Instruction cache
742 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
743 * @retval None
744 */
LL_FLASH_EnableInstCache(void)745 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
746 {
747 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
748 }
749
750 /**
751 * @brief Disable Instruction cache
752 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
753 * @retval None
754 */
LL_FLASH_DisableInstCache(void)755 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
756 {
757 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
758 }
759
760 /**
761 * @brief Enable Data cache
762 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
763 * @retval None
764 */
LL_FLASH_EnableDataCache(void)765 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
766 {
767 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
768 }
769
770 /**
771 * @brief Disable Data cache
772 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
773 * @retval None
774 */
LL_FLASH_DisableDataCache(void)775 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
776 {
777 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
778 }
779
780 /**
781 * @brief Enable Instruction cache reset
782 * @note bit can be written only when the instruction cache is disabled
783 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
784 * @retval None
785 */
LL_FLASH_EnableInstCacheReset(void)786 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
787 {
788 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
789 }
790
791 /**
792 * @brief Disable Instruction cache reset
793 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
794 * @retval None
795 */
LL_FLASH_DisableInstCacheReset(void)796 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
797 {
798 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
799 }
800
801 /**
802 * @brief Enable Data cache reset
803 * @note bit can be written only when the data cache is disabled
804 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
805 * @retval None
806 */
LL_FLASH_EnableDataCacheReset(void)807 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
808 {
809 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
810 }
811
812 /**
813 * @brief Disable Data cache reset
814 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
815 * @retval None
816 */
LL_FLASH_DisableDataCacheReset(void)817 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
818 {
819 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
820 }
821
822
823 /**
824 * @}
825 */
826
827 /**
828 * @}
829 */
830
831 /**
832 * @}
833 */
834
835 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
836
837 /**
838 * @}
839 */
840
841 #ifdef __cplusplus
842 }
843 #endif
844
845 #endif /* __STM32F2xx_LL_SYSTEM_H */
846
847
