1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F2xx_LL_RCC_H
20 #define __STM32F2xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f2xx.h"
28
29 /** @addtogroup STM32F2xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 /**
46 * @}
47 */
48 /* Private constants ---------------------------------------------------------*/
49 /* Private macros ------------------------------------------------------------*/
50 #if defined(USE_FULL_LL_DRIVER)
51 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
52 * @{
53 */
54 /**
55 * @}
56 */
57 #endif /*USE_FULL_LL_DRIVER*/
58
59 /* Exported types ------------------------------------------------------------*/
60 #if defined(USE_FULL_LL_DRIVER)
61 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
62 * @{
63 */
64
65 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
66 * @{
67 */
68
69 /**
70 * @brief RCC Clocks Frequency Structure
71 */
72 typedef struct
73 {
74 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
75 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
76 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
77 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
78 } LL_RCC_ClocksTypeDef;
79
80 /**
81 * @}
82 */
83
84 /**
85 * @}
86 */
87 #endif /* USE_FULL_LL_DRIVER */
88
89 /* Exported constants --------------------------------------------------------*/
90 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
91 * @{
92 */
93
94 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
95 * @brief Defines used to adapt values of different oscillators
96 * @note These values could be modified in the user environment according to
97 * HW set-up.
98 * @{
99 */
100 #if !defined (HSE_VALUE)
101 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
102 #endif /* HSE_VALUE */
103
104 #if !defined (HSI_VALUE)
105 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
106 #endif /* HSI_VALUE */
107
108 #if !defined (LSE_VALUE)
109 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
110 #endif /* LSE_VALUE */
111
112 #if !defined (LSI_VALUE)
113 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
114 #endif /* LSI_VALUE */
115
116 #if !defined (EXTERNAL_CLOCK_VALUE)
117 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
118 #endif /* EXTERNAL_CLOCK_VALUE */
119 /**
120 * @}
121 */
122
123 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
124 * @brief Flags defines which can be used with LL_RCC_WriteReg function
125 * @{
126 */
127 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
128 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
129 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
130 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
131 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
132 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
133 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
134 /**
135 * @}
136 */
137
138 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
139 * @brief Flags defines which can be used with LL_RCC_ReadReg function
140 * @{
141 */
142 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
143 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
144 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
145 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
146 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
147 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
148 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
149 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
150 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
151 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
152 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
153 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
154 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
155 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
156 /**
157 * @}
158 */
159
160 /** @defgroup RCC_LL_EC_IT IT Defines
161 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
162 * @{
163 */
164 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
165 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
166 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
167 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
168 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
169 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
170 /**
171 * @}
172 */
173
174 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
175 * @{
176 */
177 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
178 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
179 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
180 /**
181 * @}
182 */
183
184 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
185 * @{
186 */
187 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
188 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
189 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
190 /**
191 * @}
192 */
193
194 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
195 * @{
196 */
197 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
198 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
199 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
200 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
201 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
202 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
203 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
204 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
205 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
206 /**
207 * @}
208 */
209
210 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
211 * @{
212 */
213 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
214 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
215 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
216 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
217 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
218 /**
219 * @}
220 */
221
222 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
223 * @{
224 */
225 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
226 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
227 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
228 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
229 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
230 /**
231 * @}
232 */
233
234 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
235 * @{
236 */
237 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
238 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
239 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
240 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
241 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
242 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
243 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
244 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
245 /**
246 * @}
247 */
248
249 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
250 * @{
251 */
252 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
253 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
254 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
255 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
256 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
257 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
258 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
259 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
260 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
261 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
262 /**
263 * @}
264 */
265
266 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
267 * @{
268 */
269 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
270 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
271 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
272 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
273 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
274 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
275 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
276 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
277 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
278 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
279 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
280 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
281 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
282 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
283 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
284 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
285 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
286 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
287 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
288 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
289 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
290 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
291 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
292 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
293 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
294 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
295 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
296 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
297 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
298 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
299 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
300 /**
301 * @}
302 */
303
304 #if defined(USE_FULL_LL_DRIVER)
305 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
306 * @{
307 */
308 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
309 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
310 /**
311 * @}
312 */
313 #endif /* USE_FULL_LL_DRIVER */
314
315 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
316 * @{
317 */
318 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
319 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
320 /**
321 * @}
322 */
323
324 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
325 * @{
326 */
327 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
328 /**
329 * @}
330 */
331
332 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
333 * @{
334 */
335 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
336 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
337 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
338 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
339 /**
340 * @}
341 */
342
343 /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source
344 * @{
345 */
346 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
347 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
348 /**
349 * @}
350 */
351
352 /** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor
353 * @{
354 */
355 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 2 */
356 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 3 */
357 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 4 */
358 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 5 */
359 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 6 */
360 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 7 */
361 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 8 */
362 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 9 */
363 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 10 */
364 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 11 */
365 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 12 */
366 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 13 */
367 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 14 */
368 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 15 */
369 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 16 */
370 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 17 */
371 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 18 */
372 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 19 */
373 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 20 */
374 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 21 */
375 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 22 */
376 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 23 */
377 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 24 */
378 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 25 */
379 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 26 */
380 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 27 */
381 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 28 */
382 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 29 */
383 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 30 */
384 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 31 */
385 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL and PLLI2S division factor by 32 */
386 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 33 */
387 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 34 */
388 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 35 */
389 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 36 */
390 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 37 */
391 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 38 */
392 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 39 */
393 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 40 */
394 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 41 */
395 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 42 */
396 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 43 */
397 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 44 */
398 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 45 */
399 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 46 */
400 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 47 */
401 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 48 */
402 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 49 */
403 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 50 */
404 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 51 */
405 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 52 */
406 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 53 */
407 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 54 */
408 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 55 */
409 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 56 */
410 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 57 */
411 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 58 */
412 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 59 */
413 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 60 */
414 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 61 */
415 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 62 */
416 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 63 */
417 /**
418 * @}
419 */
420
421 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
422 * @{
423 */
424 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
425 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
426 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
427 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
428 /**
429 * @}
430 */
431
432 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
433 * @{
434 */
435 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
436 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
437 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
438 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
439 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
440 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
441 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
442 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
443 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
444 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
445 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
446 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
447 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
448 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
449 /**
450 * @}
451 */
452
453 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
454 * @{
455 */
456 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
457 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
458 /**
459 * @}
460 */
461
462 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
463 * @{
464 */
465 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
466 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
467 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
468 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
469 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
470 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
471 /**
472 * @}
473 */
474
475 /**
476 * @}
477 */
478
479 /* Exported macro ------------------------------------------------------------*/
480 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
481 * @{
482 */
483
484 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
485 * @{
486 */
487
488 /**
489 * @brief Write a value in RCC register
490 * @param __REG__ Register to be written
491 * @param __VALUE__ Value to be written in the register
492 * @retval None
493 */
494 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
495
496 /**
497 * @brief Read a value in RCC register
498 * @param __REG__ Register to be read
499 * @retval Register value
500 */
501 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
502 /**
503 * @}
504 */
505
506 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
507 * @{
508 */
509
510 /**
511 * @brief Helper macro to calculate the PLLCLK frequency on system domain
512 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
513 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
514 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
515 * @param __PLLM__ This parameter can be one of the following values:
516 * @arg @ref LL_RCC_PLLM_DIV_2
517 * @arg @ref LL_RCC_PLLM_DIV_3
518 * @arg @ref LL_RCC_PLLM_DIV_4
519 * @arg @ref LL_RCC_PLLM_DIV_5
520 * @arg @ref LL_RCC_PLLM_DIV_6
521 * @arg @ref LL_RCC_PLLM_DIV_7
522 * @arg @ref LL_RCC_PLLM_DIV_8
523 * @arg @ref LL_RCC_PLLM_DIV_9
524 * @arg @ref LL_RCC_PLLM_DIV_10
525 * @arg @ref LL_RCC_PLLM_DIV_11
526 * @arg @ref LL_RCC_PLLM_DIV_12
527 * @arg @ref LL_RCC_PLLM_DIV_13
528 * @arg @ref LL_RCC_PLLM_DIV_14
529 * @arg @ref LL_RCC_PLLM_DIV_15
530 * @arg @ref LL_RCC_PLLM_DIV_16
531 * @arg @ref LL_RCC_PLLM_DIV_17
532 * @arg @ref LL_RCC_PLLM_DIV_18
533 * @arg @ref LL_RCC_PLLM_DIV_19
534 * @arg @ref LL_RCC_PLLM_DIV_20
535 * @arg @ref LL_RCC_PLLM_DIV_21
536 * @arg @ref LL_RCC_PLLM_DIV_22
537 * @arg @ref LL_RCC_PLLM_DIV_23
538 * @arg @ref LL_RCC_PLLM_DIV_24
539 * @arg @ref LL_RCC_PLLM_DIV_25
540 * @arg @ref LL_RCC_PLLM_DIV_26
541 * @arg @ref LL_RCC_PLLM_DIV_27
542 * @arg @ref LL_RCC_PLLM_DIV_28
543 * @arg @ref LL_RCC_PLLM_DIV_29
544 * @arg @ref LL_RCC_PLLM_DIV_30
545 * @arg @ref LL_RCC_PLLM_DIV_31
546 * @arg @ref LL_RCC_PLLM_DIV_32
547 * @arg @ref LL_RCC_PLLM_DIV_33
548 * @arg @ref LL_RCC_PLLM_DIV_34
549 * @arg @ref LL_RCC_PLLM_DIV_35
550 * @arg @ref LL_RCC_PLLM_DIV_36
551 * @arg @ref LL_RCC_PLLM_DIV_37
552 * @arg @ref LL_RCC_PLLM_DIV_38
553 * @arg @ref LL_RCC_PLLM_DIV_39
554 * @arg @ref LL_RCC_PLLM_DIV_40
555 * @arg @ref LL_RCC_PLLM_DIV_41
556 * @arg @ref LL_RCC_PLLM_DIV_42
557 * @arg @ref LL_RCC_PLLM_DIV_43
558 * @arg @ref LL_RCC_PLLM_DIV_44
559 * @arg @ref LL_RCC_PLLM_DIV_45
560 * @arg @ref LL_RCC_PLLM_DIV_46
561 * @arg @ref LL_RCC_PLLM_DIV_47
562 * @arg @ref LL_RCC_PLLM_DIV_48
563 * @arg @ref LL_RCC_PLLM_DIV_49
564 * @arg @ref LL_RCC_PLLM_DIV_50
565 * @arg @ref LL_RCC_PLLM_DIV_51
566 * @arg @ref LL_RCC_PLLM_DIV_52
567 * @arg @ref LL_RCC_PLLM_DIV_53
568 * @arg @ref LL_RCC_PLLM_DIV_54
569 * @arg @ref LL_RCC_PLLM_DIV_55
570 * @arg @ref LL_RCC_PLLM_DIV_56
571 * @arg @ref LL_RCC_PLLM_DIV_57
572 * @arg @ref LL_RCC_PLLM_DIV_58
573 * @arg @ref LL_RCC_PLLM_DIV_59
574 * @arg @ref LL_RCC_PLLM_DIV_60
575 * @arg @ref LL_RCC_PLLM_DIV_61
576 * @arg @ref LL_RCC_PLLM_DIV_62
577 * @arg @ref LL_RCC_PLLM_DIV_63
578 * @param __PLLN__ Between 192 and 432
579 * @param __PLLP__ This parameter can be one of the following values:
580 * @arg @ref LL_RCC_PLLP_DIV_2
581 * @arg @ref LL_RCC_PLLP_DIV_4
582 * @arg @ref LL_RCC_PLLP_DIV_6
583 * @arg @ref LL_RCC_PLLP_DIV_8
584 * @retval PLL clock frequency (in Hz)
585 */
586 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
587 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
588
589 /**
590 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
591 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
592 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
593 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
594 * @param __PLLM__ This parameter can be one of the following values:
595 * @arg @ref LL_RCC_PLLM_DIV_2
596 * @arg @ref LL_RCC_PLLM_DIV_3
597 * @arg @ref LL_RCC_PLLM_DIV_4
598 * @arg @ref LL_RCC_PLLM_DIV_5
599 * @arg @ref LL_RCC_PLLM_DIV_6
600 * @arg @ref LL_RCC_PLLM_DIV_7
601 * @arg @ref LL_RCC_PLLM_DIV_8
602 * @arg @ref LL_RCC_PLLM_DIV_9
603 * @arg @ref LL_RCC_PLLM_DIV_10
604 * @arg @ref LL_RCC_PLLM_DIV_11
605 * @arg @ref LL_RCC_PLLM_DIV_12
606 * @arg @ref LL_RCC_PLLM_DIV_13
607 * @arg @ref LL_RCC_PLLM_DIV_14
608 * @arg @ref LL_RCC_PLLM_DIV_15
609 * @arg @ref LL_RCC_PLLM_DIV_16
610 * @arg @ref LL_RCC_PLLM_DIV_17
611 * @arg @ref LL_RCC_PLLM_DIV_18
612 * @arg @ref LL_RCC_PLLM_DIV_19
613 * @arg @ref LL_RCC_PLLM_DIV_20
614 * @arg @ref LL_RCC_PLLM_DIV_21
615 * @arg @ref LL_RCC_PLLM_DIV_22
616 * @arg @ref LL_RCC_PLLM_DIV_23
617 * @arg @ref LL_RCC_PLLM_DIV_24
618 * @arg @ref LL_RCC_PLLM_DIV_25
619 * @arg @ref LL_RCC_PLLM_DIV_26
620 * @arg @ref LL_RCC_PLLM_DIV_27
621 * @arg @ref LL_RCC_PLLM_DIV_28
622 * @arg @ref LL_RCC_PLLM_DIV_29
623 * @arg @ref LL_RCC_PLLM_DIV_30
624 * @arg @ref LL_RCC_PLLM_DIV_31
625 * @arg @ref LL_RCC_PLLM_DIV_32
626 * @arg @ref LL_RCC_PLLM_DIV_33
627 * @arg @ref LL_RCC_PLLM_DIV_34
628 * @arg @ref LL_RCC_PLLM_DIV_35
629 * @arg @ref LL_RCC_PLLM_DIV_36
630 * @arg @ref LL_RCC_PLLM_DIV_37
631 * @arg @ref LL_RCC_PLLM_DIV_38
632 * @arg @ref LL_RCC_PLLM_DIV_39
633 * @arg @ref LL_RCC_PLLM_DIV_40
634 * @arg @ref LL_RCC_PLLM_DIV_41
635 * @arg @ref LL_RCC_PLLM_DIV_42
636 * @arg @ref LL_RCC_PLLM_DIV_43
637 * @arg @ref LL_RCC_PLLM_DIV_44
638 * @arg @ref LL_RCC_PLLM_DIV_45
639 * @arg @ref LL_RCC_PLLM_DIV_46
640 * @arg @ref LL_RCC_PLLM_DIV_47
641 * @arg @ref LL_RCC_PLLM_DIV_48
642 * @arg @ref LL_RCC_PLLM_DIV_49
643 * @arg @ref LL_RCC_PLLM_DIV_50
644 * @arg @ref LL_RCC_PLLM_DIV_51
645 * @arg @ref LL_RCC_PLLM_DIV_52
646 * @arg @ref LL_RCC_PLLM_DIV_53
647 * @arg @ref LL_RCC_PLLM_DIV_54
648 * @arg @ref LL_RCC_PLLM_DIV_55
649 * @arg @ref LL_RCC_PLLM_DIV_56
650 * @arg @ref LL_RCC_PLLM_DIV_57
651 * @arg @ref LL_RCC_PLLM_DIV_58
652 * @arg @ref LL_RCC_PLLM_DIV_59
653 * @arg @ref LL_RCC_PLLM_DIV_60
654 * @arg @ref LL_RCC_PLLM_DIV_61
655 * @arg @ref LL_RCC_PLLM_DIV_62
656 * @arg @ref LL_RCC_PLLM_DIV_63
657 * @param __PLLN__ Between 192 and 432
658 * @param __PLLQ__ This parameter can be one of the following values:
659 * @arg @ref LL_RCC_PLLQ_DIV_2
660 * @arg @ref LL_RCC_PLLQ_DIV_3
661 * @arg @ref LL_RCC_PLLQ_DIV_4
662 * @arg @ref LL_RCC_PLLQ_DIV_5
663 * @arg @ref LL_RCC_PLLQ_DIV_6
664 * @arg @ref LL_RCC_PLLQ_DIV_7
665 * @arg @ref LL_RCC_PLLQ_DIV_8
666 * @arg @ref LL_RCC_PLLQ_DIV_9
667 * @arg @ref LL_RCC_PLLQ_DIV_10
668 * @arg @ref LL_RCC_PLLQ_DIV_11
669 * @arg @ref LL_RCC_PLLQ_DIV_12
670 * @arg @ref LL_RCC_PLLQ_DIV_13
671 * @arg @ref LL_RCC_PLLQ_DIV_14
672 * @arg @ref LL_RCC_PLLQ_DIV_15
673 * @retval PLL clock frequency (in Hz)
674 */
675 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
676 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
677
678 /**
679 * @retval PLLI2S clock frequency (in Hz)
680 */
681
682 /**
683 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
684 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
685 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
686 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
687 * @param __PLLM__ This parameter can be one of the following values:
688 * @param __PLLI2SN__ Between 192 and 432
689 * @param __PLLI2SR__ This parameter can be one of the following values:
690 * @arg @ref LL_RCC_PLLI2SR_DIV_2
691 * @arg @ref LL_RCC_PLLI2SR_DIV_3
692 * @arg @ref LL_RCC_PLLI2SR_DIV_4
693 * @arg @ref LL_RCC_PLLI2SR_DIV_5
694 * @arg @ref LL_RCC_PLLI2SR_DIV_6
695 * @arg @ref LL_RCC_PLLI2SR_DIV_7
696 * @retval PLLI2S clock frequency (in Hz)
697 */
698 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
699 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
700
701 /**
702 * @brief Helper macro to calculate the HCLK frequency
703 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
704 * @param __AHBPRESCALER__ This parameter can be one of the following values:
705 * @arg @ref LL_RCC_SYSCLK_DIV_1
706 * @arg @ref LL_RCC_SYSCLK_DIV_2
707 * @arg @ref LL_RCC_SYSCLK_DIV_4
708 * @arg @ref LL_RCC_SYSCLK_DIV_8
709 * @arg @ref LL_RCC_SYSCLK_DIV_16
710 * @arg @ref LL_RCC_SYSCLK_DIV_64
711 * @arg @ref LL_RCC_SYSCLK_DIV_128
712 * @arg @ref LL_RCC_SYSCLK_DIV_256
713 * @arg @ref LL_RCC_SYSCLK_DIV_512
714 * @retval HCLK clock frequency (in Hz)
715 */
716 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
717
718 /**
719 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
720 * @param __HCLKFREQ__ HCLK frequency
721 * @param __APB1PRESCALER__ This parameter can be one of the following values:
722 * @arg @ref LL_RCC_APB1_DIV_1
723 * @arg @ref LL_RCC_APB1_DIV_2
724 * @arg @ref LL_RCC_APB1_DIV_4
725 * @arg @ref LL_RCC_APB1_DIV_8
726 * @arg @ref LL_RCC_APB1_DIV_16
727 * @retval PCLK1 clock frequency (in Hz)
728 */
729 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
730
731 /**
732 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
733 * @param __HCLKFREQ__ HCLK frequency
734 * @param __APB2PRESCALER__ This parameter can be one of the following values:
735 * @arg @ref LL_RCC_APB2_DIV_1
736 * @arg @ref LL_RCC_APB2_DIV_2
737 * @arg @ref LL_RCC_APB2_DIV_4
738 * @arg @ref LL_RCC_APB2_DIV_8
739 * @arg @ref LL_RCC_APB2_DIV_16
740 * @retval PCLK2 clock frequency (in Hz)
741 */
742 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
743
744 /**
745 * @}
746 */
747
748 /**
749 * @}
750 */
751
752 /* Exported functions --------------------------------------------------------*/
753 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
754 * @{
755 */
756
757 /** @defgroup RCC_LL_EF_HSE HSE
758 * @{
759 */
760
761 /**
762 * @brief Enable the Clock Security System.
763 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
764 * @retval None
765 */
LL_RCC_HSE_EnableCSS(void)766 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
767 {
768 SET_BIT(RCC->CR, RCC_CR_CSSON);
769 }
770
771 /**
772 * @brief Enable HSE external oscillator (HSE Bypass)
773 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
774 * @retval None
775 */
LL_RCC_HSE_EnableBypass(void)776 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
777 {
778 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
779 }
780
781 /**
782 * @brief Disable HSE external oscillator (HSE Bypass)
783 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
784 * @retval None
785 */
LL_RCC_HSE_DisableBypass(void)786 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
787 {
788 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
789 }
790
791 /**
792 * @brief Enable HSE crystal oscillator (HSE ON)
793 * @rmtoll CR HSEON LL_RCC_HSE_Enable
794 * @retval None
795 */
LL_RCC_HSE_Enable(void)796 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
797 {
798 SET_BIT(RCC->CR, RCC_CR_HSEON);
799 }
800
801 /**
802 * @brief Disable HSE crystal oscillator (HSE ON)
803 * @rmtoll CR HSEON LL_RCC_HSE_Disable
804 * @retval None
805 */
LL_RCC_HSE_Disable(void)806 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
807 {
808 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
809 }
810
811 /**
812 * @brief Check if HSE oscillator Ready
813 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
814 * @retval State of bit (1 or 0).
815 */
LL_RCC_HSE_IsReady(void)816 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
817 {
818 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
819 }
820
821 /**
822 * @}
823 */
824
825 /** @defgroup RCC_LL_EF_HSI HSI
826 * @{
827 */
828
829 /**
830 * @brief Enable HSI oscillator
831 * @rmtoll CR HSION LL_RCC_HSI_Enable
832 * @retval None
833 */
LL_RCC_HSI_Enable(void)834 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
835 {
836 SET_BIT(RCC->CR, RCC_CR_HSION);
837 }
838
839 /**
840 * @brief Disable HSI oscillator
841 * @rmtoll CR HSION LL_RCC_HSI_Disable
842 * @retval None
843 */
LL_RCC_HSI_Disable(void)844 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
845 {
846 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
847 }
848
849 /**
850 * @brief Check if HSI clock is ready
851 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
852 * @retval State of bit (1 or 0).
853 */
LL_RCC_HSI_IsReady(void)854 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
855 {
856 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
857 }
858
859 /**
860 * @brief Get HSI Calibration value
861 * @note When HSITRIM is written, HSICAL is updated with the sum of
862 * HSITRIM and the factory trim value
863 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
864 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
865 */
LL_RCC_HSI_GetCalibration(void)866 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
867 {
868 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
869 }
870
871 /**
872 * @brief Set HSI Calibration trimming
873 * @note user-programmable trimming value that is added to the HSICAL
874 * @note Default value is 16, which, when added to the HSICAL value,
875 * should trim the HSI to 16 MHz +/- 1 %
876 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
877 * @param Value Between Min_Data = 0 and Max_Data = 31
878 * @retval None
879 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)880 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
881 {
882 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
883 }
884
885 /**
886 * @brief Get HSI Calibration trimming
887 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
888 * @retval Between Min_Data = 0 and Max_Data = 31
889 */
LL_RCC_HSI_GetCalibTrimming(void)890 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
891 {
892 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
893 }
894
895 /**
896 * @}
897 */
898
899 /** @defgroup RCC_LL_EF_LSE LSE
900 * @{
901 */
902
903 /**
904 * @brief Enable Low Speed External (LSE) crystal.
905 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
906 * @retval None
907 */
LL_RCC_LSE_Enable(void)908 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
909 {
910 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
911 }
912
913 /**
914 * @brief Disable Low Speed External (LSE) crystal.
915 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
916 * @retval None
917 */
LL_RCC_LSE_Disable(void)918 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
919 {
920 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
921 }
922
923 /**
924 * @brief Enable external clock source (LSE bypass).
925 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
926 * @retval None
927 */
LL_RCC_LSE_EnableBypass(void)928 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
929 {
930 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
931 }
932
933 /**
934 * @brief Disable external clock source (LSE bypass).
935 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
936 * @retval None
937 */
LL_RCC_LSE_DisableBypass(void)938 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
939 {
940 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
941 }
942
943 /**
944 * @brief Check if LSE oscillator Ready
945 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
946 * @retval State of bit (1 or 0).
947 */
LL_RCC_LSE_IsReady(void)948 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
949 {
950 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
951 }
952
953 /**
954 * @}
955 */
956
957 /** @defgroup RCC_LL_EF_LSI LSI
958 * @{
959 */
960
961 /**
962 * @brief Enable LSI Oscillator
963 * @rmtoll CSR LSION LL_RCC_LSI_Enable
964 * @retval None
965 */
LL_RCC_LSI_Enable(void)966 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
967 {
968 SET_BIT(RCC->CSR, RCC_CSR_LSION);
969 }
970
971 /**
972 * @brief Disable LSI Oscillator
973 * @rmtoll CSR LSION LL_RCC_LSI_Disable
974 * @retval None
975 */
LL_RCC_LSI_Disable(void)976 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
977 {
978 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
979 }
980
981 /**
982 * @brief Check if LSI is Ready
983 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
984 * @retval State of bit (1 or 0).
985 */
LL_RCC_LSI_IsReady(void)986 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
987 {
988 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
989 }
990
991 /**
992 * @}
993 */
994
995 /** @defgroup RCC_LL_EF_System System
996 * @{
997 */
998
999 /**
1000 * @brief Configure the system clock source
1001 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1002 * @param Source This parameter can be one of the following values:
1003 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1004 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1005 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1006 * @retval None
1007 */
LL_RCC_SetSysClkSource(uint32_t Source)1008 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1009 {
1010 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1011 }
1012
1013 /**
1014 * @brief Get the system clock source
1015 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1016 * @retval Returned value can be one of the following values:
1017 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1018 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1019 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1020 */
LL_RCC_GetSysClkSource(void)1021 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1022 {
1023 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1024 }
1025
1026 /**
1027 * @brief Set AHB prescaler
1028 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1029 * @param Prescaler This parameter can be one of the following values:
1030 * @arg @ref LL_RCC_SYSCLK_DIV_1
1031 * @arg @ref LL_RCC_SYSCLK_DIV_2
1032 * @arg @ref LL_RCC_SYSCLK_DIV_4
1033 * @arg @ref LL_RCC_SYSCLK_DIV_8
1034 * @arg @ref LL_RCC_SYSCLK_DIV_16
1035 * @arg @ref LL_RCC_SYSCLK_DIV_64
1036 * @arg @ref LL_RCC_SYSCLK_DIV_128
1037 * @arg @ref LL_RCC_SYSCLK_DIV_256
1038 * @arg @ref LL_RCC_SYSCLK_DIV_512
1039 * @retval None
1040 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1041 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1042 {
1043 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1044 }
1045
1046 /**
1047 * @brief Set APB1 prescaler
1048 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1049 * @param Prescaler This parameter can be one of the following values:
1050 * @arg @ref LL_RCC_APB1_DIV_1
1051 * @arg @ref LL_RCC_APB1_DIV_2
1052 * @arg @ref LL_RCC_APB1_DIV_4
1053 * @arg @ref LL_RCC_APB1_DIV_8
1054 * @arg @ref LL_RCC_APB1_DIV_16
1055 * @retval None
1056 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1057 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1058 {
1059 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1060 }
1061
1062 /**
1063 * @brief Set APB2 prescaler
1064 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1065 * @param Prescaler This parameter can be one of the following values:
1066 * @arg @ref LL_RCC_APB2_DIV_1
1067 * @arg @ref LL_RCC_APB2_DIV_2
1068 * @arg @ref LL_RCC_APB2_DIV_4
1069 * @arg @ref LL_RCC_APB2_DIV_8
1070 * @arg @ref LL_RCC_APB2_DIV_16
1071 * @retval None
1072 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1073 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1074 {
1075 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1076 }
1077
1078 /**
1079 * @brief Get AHB prescaler
1080 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1081 * @retval Returned value can be one of the following values:
1082 * @arg @ref LL_RCC_SYSCLK_DIV_1
1083 * @arg @ref LL_RCC_SYSCLK_DIV_2
1084 * @arg @ref LL_RCC_SYSCLK_DIV_4
1085 * @arg @ref LL_RCC_SYSCLK_DIV_8
1086 * @arg @ref LL_RCC_SYSCLK_DIV_16
1087 * @arg @ref LL_RCC_SYSCLK_DIV_64
1088 * @arg @ref LL_RCC_SYSCLK_DIV_128
1089 * @arg @ref LL_RCC_SYSCLK_DIV_256
1090 * @arg @ref LL_RCC_SYSCLK_DIV_512
1091 */
LL_RCC_GetAHBPrescaler(void)1092 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1093 {
1094 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1095 }
1096
1097 /**
1098 * @brief Get APB1 prescaler
1099 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1100 * @retval Returned value can be one of the following values:
1101 * @arg @ref LL_RCC_APB1_DIV_1
1102 * @arg @ref LL_RCC_APB1_DIV_2
1103 * @arg @ref LL_RCC_APB1_DIV_4
1104 * @arg @ref LL_RCC_APB1_DIV_8
1105 * @arg @ref LL_RCC_APB1_DIV_16
1106 */
LL_RCC_GetAPB1Prescaler(void)1107 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1108 {
1109 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1110 }
1111
1112 /**
1113 * @brief Get APB2 prescaler
1114 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_RCC_APB2_DIV_1
1117 * @arg @ref LL_RCC_APB2_DIV_2
1118 * @arg @ref LL_RCC_APB2_DIV_4
1119 * @arg @ref LL_RCC_APB2_DIV_8
1120 * @arg @ref LL_RCC_APB2_DIV_16
1121 */
LL_RCC_GetAPB2Prescaler(void)1122 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1123 {
1124 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1125 }
1126
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup RCC_LL_EF_MCO MCO
1132 * @{
1133 */
1134
1135 /**
1136 * @brief Configure MCOx
1137 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
1138 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
1139 * CFGR MCO2 LL_RCC_ConfigMCO\n
1140 * CFGR MCO2PRE LL_RCC_ConfigMCO
1141 * @param MCOxSource This parameter can be one of the following values:
1142 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1143 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1144 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1145 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1146 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
1147 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
1148 * @arg @ref LL_RCC_MCO2SOURCE_HSE
1149 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
1150 * @param MCOxPrescaler This parameter can be one of the following values:
1151 * @arg @ref LL_RCC_MCO1_DIV_1
1152 * @arg @ref LL_RCC_MCO1_DIV_2
1153 * @arg @ref LL_RCC_MCO1_DIV_3
1154 * @arg @ref LL_RCC_MCO1_DIV_4
1155 * @arg @ref LL_RCC_MCO1_DIV_5
1156 * @arg @ref LL_RCC_MCO2_DIV_1
1157 * @arg @ref LL_RCC_MCO2_DIV_2
1158 * @arg @ref LL_RCC_MCO2_DIV_3
1159 * @arg @ref LL_RCC_MCO2_DIV_4
1160 * @arg @ref LL_RCC_MCO2_DIV_5
1161 * @retval None
1162 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1163 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1164 {
1165 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
1166 }
1167
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1173 * @{
1174 */
1175
1176 /**
1177 * @brief Configure I2S clock source
1178 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
1179 * @param Source This parameter can be one of the following values:
1180 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
1181 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1182 * @retval None
1183 */
LL_RCC_SetI2SClockSource(uint32_t Source)1184 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
1185 {
1186 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
1187 }
1188
1189 /**
1190 * @brief Get I2S Clock Source
1191 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
1192 * @param I2Sx This parameter can be one of the following values:
1193 * @arg @ref LL_RCC_I2S1_CLKSOURCE
1194 * @retval Returned value can be one of the following values:
1195 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
1196 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
1197 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1198 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1199 {
1200 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
1201 }
1202
1203 /**
1204 * @}
1205 */
1206
1207 /** @defgroup RCC_LL_EF_RTC RTC
1208 * @{
1209 */
1210
1211 /**
1212 * @brief Set RTC Clock Source
1213 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1214 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1215 * set). The BDRST bit can be used to reset them.
1216 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
1217 * @param Source This parameter can be one of the following values:
1218 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1219 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1220 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1221 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1222 * @retval None
1223 */
LL_RCC_SetRTCClockSource(uint32_t Source)1224 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1225 {
1226 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
1227 }
1228
1229 /**
1230 * @brief Get RTC Clock Source
1231 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
1232 * @retval Returned value can be one of the following values:
1233 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1234 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1235 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1236 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1237 */
LL_RCC_GetRTCClockSource(void)1238 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1239 {
1240 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
1241 }
1242
1243 /**
1244 * @brief Enable RTC
1245 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
1246 * @retval None
1247 */
LL_RCC_EnableRTC(void)1248 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1249 {
1250 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1251 }
1252
1253 /**
1254 * @brief Disable RTC
1255 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
1256 * @retval None
1257 */
LL_RCC_DisableRTC(void)1258 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1259 {
1260 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1261 }
1262
1263 /**
1264 * @brief Check if RTC has been enabled or not
1265 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
1266 * @retval State of bit (1 or 0).
1267 */
LL_RCC_IsEnabledRTC(void)1268 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1269 {
1270 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
1271 }
1272
1273 /**
1274 * @brief Force the Backup domain reset
1275 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
1276 * @retval None
1277 */
LL_RCC_ForceBackupDomainReset(void)1278 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1279 {
1280 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
1281 }
1282
1283 /**
1284 * @brief Release the Backup domain reset
1285 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
1286 * @retval None
1287 */
LL_RCC_ReleaseBackupDomainReset(void)1288 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1289 {
1290 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
1291 }
1292
1293 /**
1294 * @brief Set HSE Prescalers for RTC Clock
1295 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
1296 * @param Prescaler This parameter can be one of the following values:
1297 * @arg @ref LL_RCC_RTC_NOCLOCK
1298 * @arg @ref LL_RCC_RTC_HSE_DIV_2
1299 * @arg @ref LL_RCC_RTC_HSE_DIV_3
1300 * @arg @ref LL_RCC_RTC_HSE_DIV_4
1301 * @arg @ref LL_RCC_RTC_HSE_DIV_5
1302 * @arg @ref LL_RCC_RTC_HSE_DIV_6
1303 * @arg @ref LL_RCC_RTC_HSE_DIV_7
1304 * @arg @ref LL_RCC_RTC_HSE_DIV_8
1305 * @arg @ref LL_RCC_RTC_HSE_DIV_9
1306 * @arg @ref LL_RCC_RTC_HSE_DIV_10
1307 * @arg @ref LL_RCC_RTC_HSE_DIV_11
1308 * @arg @ref LL_RCC_RTC_HSE_DIV_12
1309 * @arg @ref LL_RCC_RTC_HSE_DIV_13
1310 * @arg @ref LL_RCC_RTC_HSE_DIV_14
1311 * @arg @ref LL_RCC_RTC_HSE_DIV_15
1312 * @arg @ref LL_RCC_RTC_HSE_DIV_16
1313 * @arg @ref LL_RCC_RTC_HSE_DIV_17
1314 * @arg @ref LL_RCC_RTC_HSE_DIV_18
1315 * @arg @ref LL_RCC_RTC_HSE_DIV_19
1316 * @arg @ref LL_RCC_RTC_HSE_DIV_20
1317 * @arg @ref LL_RCC_RTC_HSE_DIV_21
1318 * @arg @ref LL_RCC_RTC_HSE_DIV_22
1319 * @arg @ref LL_RCC_RTC_HSE_DIV_23
1320 * @arg @ref LL_RCC_RTC_HSE_DIV_24
1321 * @arg @ref LL_RCC_RTC_HSE_DIV_25
1322 * @arg @ref LL_RCC_RTC_HSE_DIV_26
1323 * @arg @ref LL_RCC_RTC_HSE_DIV_27
1324 * @arg @ref LL_RCC_RTC_HSE_DIV_28
1325 * @arg @ref LL_RCC_RTC_HSE_DIV_29
1326 * @arg @ref LL_RCC_RTC_HSE_DIV_30
1327 * @arg @ref LL_RCC_RTC_HSE_DIV_31
1328 * @retval None
1329 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)1330 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
1331 {
1332 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
1333 }
1334
1335 /**
1336 * @brief Get HSE Prescalers for RTC Clock
1337 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
1338 * @retval Returned value can be one of the following values:
1339 * @arg @ref LL_RCC_RTC_NOCLOCK
1340 * @arg @ref LL_RCC_RTC_HSE_DIV_2
1341 * @arg @ref LL_RCC_RTC_HSE_DIV_3
1342 * @arg @ref LL_RCC_RTC_HSE_DIV_4
1343 * @arg @ref LL_RCC_RTC_HSE_DIV_5
1344 * @arg @ref LL_RCC_RTC_HSE_DIV_6
1345 * @arg @ref LL_RCC_RTC_HSE_DIV_7
1346 * @arg @ref LL_RCC_RTC_HSE_DIV_8
1347 * @arg @ref LL_RCC_RTC_HSE_DIV_9
1348 * @arg @ref LL_RCC_RTC_HSE_DIV_10
1349 * @arg @ref LL_RCC_RTC_HSE_DIV_11
1350 * @arg @ref LL_RCC_RTC_HSE_DIV_12
1351 * @arg @ref LL_RCC_RTC_HSE_DIV_13
1352 * @arg @ref LL_RCC_RTC_HSE_DIV_14
1353 * @arg @ref LL_RCC_RTC_HSE_DIV_15
1354 * @arg @ref LL_RCC_RTC_HSE_DIV_16
1355 * @arg @ref LL_RCC_RTC_HSE_DIV_17
1356 * @arg @ref LL_RCC_RTC_HSE_DIV_18
1357 * @arg @ref LL_RCC_RTC_HSE_DIV_19
1358 * @arg @ref LL_RCC_RTC_HSE_DIV_20
1359 * @arg @ref LL_RCC_RTC_HSE_DIV_21
1360 * @arg @ref LL_RCC_RTC_HSE_DIV_22
1361 * @arg @ref LL_RCC_RTC_HSE_DIV_23
1362 * @arg @ref LL_RCC_RTC_HSE_DIV_24
1363 * @arg @ref LL_RCC_RTC_HSE_DIV_25
1364 * @arg @ref LL_RCC_RTC_HSE_DIV_26
1365 * @arg @ref LL_RCC_RTC_HSE_DIV_27
1366 * @arg @ref LL_RCC_RTC_HSE_DIV_28
1367 * @arg @ref LL_RCC_RTC_HSE_DIV_29
1368 * @arg @ref LL_RCC_RTC_HSE_DIV_30
1369 * @arg @ref LL_RCC_RTC_HSE_DIV_31
1370 */
LL_RCC_GetRTC_HSEPrescaler(void)1371 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
1372 {
1373 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
1374 }
1375
1376 /**
1377 * @}
1378 */
1379
1380 /** @defgroup RCC_LL_EF_PLL PLL
1381 * @{
1382 */
1383
1384 /**
1385 * @brief Enable PLL
1386 * @rmtoll CR PLLON LL_RCC_PLL_Enable
1387 * @retval None
1388 */
LL_RCC_PLL_Enable(void)1389 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
1390 {
1391 SET_BIT(RCC->CR, RCC_CR_PLLON);
1392 }
1393
1394 /**
1395 * @brief Disable PLL
1396 * @note Cannot be disabled if the PLL clock is used as the system clock
1397 * @rmtoll CR PLLON LL_RCC_PLL_Disable
1398 * @retval None
1399 */
LL_RCC_PLL_Disable(void)1400 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
1401 {
1402 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
1403 }
1404
1405 /**
1406 * @brief Check if PLL Ready
1407 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
1408 * @retval State of bit (1 or 0).
1409 */
LL_RCC_PLL_IsReady(void)1410 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
1411 {
1412 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
1413 }
1414
1415 /**
1416 * @brief Configure PLL used for SYSCLK Domain
1417 * @note PLL Source and PLLM Divider can be written only when PLL,
1418 * PLLI2S are disabled
1419 * @note PLLN/PLLP can be written only when PLL is disabled
1420 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
1421 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
1422 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
1423 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
1424 * @param Source This parameter can be one of the following values:
1425 * @arg @ref LL_RCC_PLLSOURCE_HSI
1426 * @arg @ref LL_RCC_PLLSOURCE_HSE
1427 * @param PLLM This parameter can be one of the following values:
1428 * @arg @ref LL_RCC_PLLM_DIV_2
1429 * @arg @ref LL_RCC_PLLM_DIV_3
1430 * @arg @ref LL_RCC_PLLM_DIV_4
1431 * @arg @ref LL_RCC_PLLM_DIV_5
1432 * @arg @ref LL_RCC_PLLM_DIV_6
1433 * @arg @ref LL_RCC_PLLM_DIV_7
1434 * @arg @ref LL_RCC_PLLM_DIV_8
1435 * @arg @ref LL_RCC_PLLM_DIV_9
1436 * @arg @ref LL_RCC_PLLM_DIV_10
1437 * @arg @ref LL_RCC_PLLM_DIV_11
1438 * @arg @ref LL_RCC_PLLM_DIV_12
1439 * @arg @ref LL_RCC_PLLM_DIV_13
1440 * @arg @ref LL_RCC_PLLM_DIV_14
1441 * @arg @ref LL_RCC_PLLM_DIV_15
1442 * @arg @ref LL_RCC_PLLM_DIV_16
1443 * @arg @ref LL_RCC_PLLM_DIV_17
1444 * @arg @ref LL_RCC_PLLM_DIV_18
1445 * @arg @ref LL_RCC_PLLM_DIV_19
1446 * @arg @ref LL_RCC_PLLM_DIV_20
1447 * @arg @ref LL_RCC_PLLM_DIV_21
1448 * @arg @ref LL_RCC_PLLM_DIV_22
1449 * @arg @ref LL_RCC_PLLM_DIV_23
1450 * @arg @ref LL_RCC_PLLM_DIV_24
1451 * @arg @ref LL_RCC_PLLM_DIV_25
1452 * @arg @ref LL_RCC_PLLM_DIV_26
1453 * @arg @ref LL_RCC_PLLM_DIV_27
1454 * @arg @ref LL_RCC_PLLM_DIV_28
1455 * @arg @ref LL_RCC_PLLM_DIV_29
1456 * @arg @ref LL_RCC_PLLM_DIV_30
1457 * @arg @ref LL_RCC_PLLM_DIV_31
1458 * @arg @ref LL_RCC_PLLM_DIV_32
1459 * @arg @ref LL_RCC_PLLM_DIV_33
1460 * @arg @ref LL_RCC_PLLM_DIV_34
1461 * @arg @ref LL_RCC_PLLM_DIV_35
1462 * @arg @ref LL_RCC_PLLM_DIV_36
1463 * @arg @ref LL_RCC_PLLM_DIV_37
1464 * @arg @ref LL_RCC_PLLM_DIV_38
1465 * @arg @ref LL_RCC_PLLM_DIV_39
1466 * @arg @ref LL_RCC_PLLM_DIV_40
1467 * @arg @ref LL_RCC_PLLM_DIV_41
1468 * @arg @ref LL_RCC_PLLM_DIV_42
1469 * @arg @ref LL_RCC_PLLM_DIV_43
1470 * @arg @ref LL_RCC_PLLM_DIV_44
1471 * @arg @ref LL_RCC_PLLM_DIV_45
1472 * @arg @ref LL_RCC_PLLM_DIV_46
1473 * @arg @ref LL_RCC_PLLM_DIV_47
1474 * @arg @ref LL_RCC_PLLM_DIV_48
1475 * @arg @ref LL_RCC_PLLM_DIV_49
1476 * @arg @ref LL_RCC_PLLM_DIV_50
1477 * @arg @ref LL_RCC_PLLM_DIV_51
1478 * @arg @ref LL_RCC_PLLM_DIV_52
1479 * @arg @ref LL_RCC_PLLM_DIV_53
1480 * @arg @ref LL_RCC_PLLM_DIV_54
1481 * @arg @ref LL_RCC_PLLM_DIV_55
1482 * @arg @ref LL_RCC_PLLM_DIV_56
1483 * @arg @ref LL_RCC_PLLM_DIV_57
1484 * @arg @ref LL_RCC_PLLM_DIV_58
1485 * @arg @ref LL_RCC_PLLM_DIV_59
1486 * @arg @ref LL_RCC_PLLM_DIV_60
1487 * @arg @ref LL_RCC_PLLM_DIV_61
1488 * @arg @ref LL_RCC_PLLM_DIV_62
1489 * @arg @ref LL_RCC_PLLM_DIV_63
1490 * @param PLLN Between 192 and 432
1491 * @param PLLP This parameter can be one of the following values:
1492 * @arg @ref LL_RCC_PLLP_DIV_2
1493 * @arg @ref LL_RCC_PLLP_DIV_4
1494 * @arg @ref LL_RCC_PLLP_DIV_6
1495 * @arg @ref LL_RCC_PLLP_DIV_8
1496 * @retval None
1497 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)1498 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
1499 {
1500 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
1501 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
1502 }
1503
1504 /**
1505 * @brief Configure PLL used for 48Mhz domain clock
1506 * @note PLL Source and PLLM Divider can be written only when PLL,
1507 * PLLI2S are disabled
1508 * @note PLLN/PLLQ can be written only when PLL is disabled
1509 * @note This can be selected for USB, RNG, SDIO
1510 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
1511 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
1512 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
1513 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
1514 * @param Source This parameter can be one of the following values:
1515 * @arg @ref LL_RCC_PLLSOURCE_HSI
1516 * @arg @ref LL_RCC_PLLSOURCE_HSE
1517 * @param PLLM This parameter can be one of the following values:
1518 * @arg @ref LL_RCC_PLLM_DIV_2
1519 * @arg @ref LL_RCC_PLLM_DIV_3
1520 * @arg @ref LL_RCC_PLLM_DIV_4
1521 * @arg @ref LL_RCC_PLLM_DIV_5
1522 * @arg @ref LL_RCC_PLLM_DIV_6
1523 * @arg @ref LL_RCC_PLLM_DIV_7
1524 * @arg @ref LL_RCC_PLLM_DIV_8
1525 * @arg @ref LL_RCC_PLLM_DIV_9
1526 * @arg @ref LL_RCC_PLLM_DIV_10
1527 * @arg @ref LL_RCC_PLLM_DIV_11
1528 * @arg @ref LL_RCC_PLLM_DIV_12
1529 * @arg @ref LL_RCC_PLLM_DIV_13
1530 * @arg @ref LL_RCC_PLLM_DIV_14
1531 * @arg @ref LL_RCC_PLLM_DIV_15
1532 * @arg @ref LL_RCC_PLLM_DIV_16
1533 * @arg @ref LL_RCC_PLLM_DIV_17
1534 * @arg @ref LL_RCC_PLLM_DIV_18
1535 * @arg @ref LL_RCC_PLLM_DIV_19
1536 * @arg @ref LL_RCC_PLLM_DIV_20
1537 * @arg @ref LL_RCC_PLLM_DIV_21
1538 * @arg @ref LL_RCC_PLLM_DIV_22
1539 * @arg @ref LL_RCC_PLLM_DIV_23
1540 * @arg @ref LL_RCC_PLLM_DIV_24
1541 * @arg @ref LL_RCC_PLLM_DIV_25
1542 * @arg @ref LL_RCC_PLLM_DIV_26
1543 * @arg @ref LL_RCC_PLLM_DIV_27
1544 * @arg @ref LL_RCC_PLLM_DIV_28
1545 * @arg @ref LL_RCC_PLLM_DIV_29
1546 * @arg @ref LL_RCC_PLLM_DIV_30
1547 * @arg @ref LL_RCC_PLLM_DIV_31
1548 * @arg @ref LL_RCC_PLLM_DIV_32
1549 * @arg @ref LL_RCC_PLLM_DIV_33
1550 * @arg @ref LL_RCC_PLLM_DIV_34
1551 * @arg @ref LL_RCC_PLLM_DIV_35
1552 * @arg @ref LL_RCC_PLLM_DIV_36
1553 * @arg @ref LL_RCC_PLLM_DIV_37
1554 * @arg @ref LL_RCC_PLLM_DIV_38
1555 * @arg @ref LL_RCC_PLLM_DIV_39
1556 * @arg @ref LL_RCC_PLLM_DIV_40
1557 * @arg @ref LL_RCC_PLLM_DIV_41
1558 * @arg @ref LL_RCC_PLLM_DIV_42
1559 * @arg @ref LL_RCC_PLLM_DIV_43
1560 * @arg @ref LL_RCC_PLLM_DIV_44
1561 * @arg @ref LL_RCC_PLLM_DIV_45
1562 * @arg @ref LL_RCC_PLLM_DIV_46
1563 * @arg @ref LL_RCC_PLLM_DIV_47
1564 * @arg @ref LL_RCC_PLLM_DIV_48
1565 * @arg @ref LL_RCC_PLLM_DIV_49
1566 * @arg @ref LL_RCC_PLLM_DIV_50
1567 * @arg @ref LL_RCC_PLLM_DIV_51
1568 * @arg @ref LL_RCC_PLLM_DIV_52
1569 * @arg @ref LL_RCC_PLLM_DIV_53
1570 * @arg @ref LL_RCC_PLLM_DIV_54
1571 * @arg @ref LL_RCC_PLLM_DIV_55
1572 * @arg @ref LL_RCC_PLLM_DIV_56
1573 * @arg @ref LL_RCC_PLLM_DIV_57
1574 * @arg @ref LL_RCC_PLLM_DIV_58
1575 * @arg @ref LL_RCC_PLLM_DIV_59
1576 * @arg @ref LL_RCC_PLLM_DIV_60
1577 * @arg @ref LL_RCC_PLLM_DIV_61
1578 * @arg @ref LL_RCC_PLLM_DIV_62
1579 * @arg @ref LL_RCC_PLLM_DIV_63
1580 * @param PLLN Between 192 and 432
1581 * @param PLLQ This parameter can be one of the following values:
1582 * @arg @ref LL_RCC_PLLQ_DIV_2
1583 * @arg @ref LL_RCC_PLLQ_DIV_3
1584 * @arg @ref LL_RCC_PLLQ_DIV_4
1585 * @arg @ref LL_RCC_PLLQ_DIV_5
1586 * @arg @ref LL_RCC_PLLQ_DIV_6
1587 * @arg @ref LL_RCC_PLLQ_DIV_7
1588 * @arg @ref LL_RCC_PLLQ_DIV_8
1589 * @arg @ref LL_RCC_PLLQ_DIV_9
1590 * @arg @ref LL_RCC_PLLQ_DIV_10
1591 * @arg @ref LL_RCC_PLLQ_DIV_11
1592 * @arg @ref LL_RCC_PLLQ_DIV_12
1593 * @arg @ref LL_RCC_PLLQ_DIV_13
1594 * @arg @ref LL_RCC_PLLQ_DIV_14
1595 * @arg @ref LL_RCC_PLLQ_DIV_15
1596 * @retval None
1597 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)1598 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
1599 {
1600 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
1601 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
1602 }
1603
1604 /**
1605 * @brief Get Main PLL multiplication factor for VCO
1606 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
1607 * @retval Between 192 and 432
1608 */
LL_RCC_PLL_GetN(void)1609 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
1610 {
1611 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
1612 }
1613
1614 /**
1615 * @brief Get Main PLL division factor for PLLP
1616 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
1617 * @retval Returned value can be one of the following values:
1618 * @arg @ref LL_RCC_PLLP_DIV_2
1619 * @arg @ref LL_RCC_PLLP_DIV_4
1620 * @arg @ref LL_RCC_PLLP_DIV_6
1621 * @arg @ref LL_RCC_PLLP_DIV_8
1622 */
LL_RCC_PLL_GetP(void)1623 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
1624 {
1625 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
1626 }
1627
1628 /**
1629 * @brief Get Main PLL division factor for PLLQ
1630 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
1631 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
1632 * @retval Returned value can be one of the following values:
1633 * @arg @ref LL_RCC_PLLQ_DIV_2
1634 * @arg @ref LL_RCC_PLLQ_DIV_3
1635 * @arg @ref LL_RCC_PLLQ_DIV_4
1636 * @arg @ref LL_RCC_PLLQ_DIV_5
1637 * @arg @ref LL_RCC_PLLQ_DIV_6
1638 * @arg @ref LL_RCC_PLLQ_DIV_7
1639 * @arg @ref LL_RCC_PLLQ_DIV_8
1640 * @arg @ref LL_RCC_PLLQ_DIV_9
1641 * @arg @ref LL_RCC_PLLQ_DIV_10
1642 * @arg @ref LL_RCC_PLLQ_DIV_11
1643 * @arg @ref LL_RCC_PLLQ_DIV_12
1644 * @arg @ref LL_RCC_PLLQ_DIV_13
1645 * @arg @ref LL_RCC_PLLQ_DIV_14
1646 * @arg @ref LL_RCC_PLLQ_DIV_15
1647 */
LL_RCC_PLL_GetQ(void)1648 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
1649 {
1650 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
1651 }
1652
1653 /**
1654 * @brief Configure PLL clock source
1655 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
1656 * @param PLLSource This parameter can be one of the following values:
1657 * @arg @ref LL_RCC_PLLSOURCE_HSI
1658 * @arg @ref LL_RCC_PLLSOURCE_HSE
1659 * @retval None
1660 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)1661 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
1662 {
1663 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
1664 }
1665
1666 /**
1667 * @brief Get the oscillator used as PLL clock source.
1668 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
1669 * @retval Returned value can be one of the following values:
1670 * @arg @ref LL_RCC_PLLSOURCE_HSI
1671 * @arg @ref LL_RCC_PLLSOURCE_HSE
1672 */
LL_RCC_PLL_GetMainSource(void)1673 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
1674 {
1675 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
1676 }
1677
1678 /**
1679 * @brief Get Division factor for the main PLL and other PLL
1680 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
1681 * @retval Returned value can be one of the following values:
1682 * @arg @ref LL_RCC_PLLM_DIV_2
1683 * @arg @ref LL_RCC_PLLM_DIV_3
1684 * @arg @ref LL_RCC_PLLM_DIV_4
1685 * @arg @ref LL_RCC_PLLM_DIV_5
1686 * @arg @ref LL_RCC_PLLM_DIV_6
1687 * @arg @ref LL_RCC_PLLM_DIV_7
1688 * @arg @ref LL_RCC_PLLM_DIV_8
1689 * @arg @ref LL_RCC_PLLM_DIV_9
1690 * @arg @ref LL_RCC_PLLM_DIV_10
1691 * @arg @ref LL_RCC_PLLM_DIV_11
1692 * @arg @ref LL_RCC_PLLM_DIV_12
1693 * @arg @ref LL_RCC_PLLM_DIV_13
1694 * @arg @ref LL_RCC_PLLM_DIV_14
1695 * @arg @ref LL_RCC_PLLM_DIV_15
1696 * @arg @ref LL_RCC_PLLM_DIV_16
1697 * @arg @ref LL_RCC_PLLM_DIV_17
1698 * @arg @ref LL_RCC_PLLM_DIV_18
1699 * @arg @ref LL_RCC_PLLM_DIV_19
1700 * @arg @ref LL_RCC_PLLM_DIV_20
1701 * @arg @ref LL_RCC_PLLM_DIV_21
1702 * @arg @ref LL_RCC_PLLM_DIV_22
1703 * @arg @ref LL_RCC_PLLM_DIV_23
1704 * @arg @ref LL_RCC_PLLM_DIV_24
1705 * @arg @ref LL_RCC_PLLM_DIV_25
1706 * @arg @ref LL_RCC_PLLM_DIV_26
1707 * @arg @ref LL_RCC_PLLM_DIV_27
1708 * @arg @ref LL_RCC_PLLM_DIV_28
1709 * @arg @ref LL_RCC_PLLM_DIV_29
1710 * @arg @ref LL_RCC_PLLM_DIV_30
1711 * @arg @ref LL_RCC_PLLM_DIV_31
1712 * @arg @ref LL_RCC_PLLM_DIV_32
1713 * @arg @ref LL_RCC_PLLM_DIV_33
1714 * @arg @ref LL_RCC_PLLM_DIV_34
1715 * @arg @ref LL_RCC_PLLM_DIV_35
1716 * @arg @ref LL_RCC_PLLM_DIV_36
1717 * @arg @ref LL_RCC_PLLM_DIV_37
1718 * @arg @ref LL_RCC_PLLM_DIV_38
1719 * @arg @ref LL_RCC_PLLM_DIV_39
1720 * @arg @ref LL_RCC_PLLM_DIV_40
1721 * @arg @ref LL_RCC_PLLM_DIV_41
1722 * @arg @ref LL_RCC_PLLM_DIV_42
1723 * @arg @ref LL_RCC_PLLM_DIV_43
1724 * @arg @ref LL_RCC_PLLM_DIV_44
1725 * @arg @ref LL_RCC_PLLM_DIV_45
1726 * @arg @ref LL_RCC_PLLM_DIV_46
1727 * @arg @ref LL_RCC_PLLM_DIV_47
1728 * @arg @ref LL_RCC_PLLM_DIV_48
1729 * @arg @ref LL_RCC_PLLM_DIV_49
1730 * @arg @ref LL_RCC_PLLM_DIV_50
1731 * @arg @ref LL_RCC_PLLM_DIV_51
1732 * @arg @ref LL_RCC_PLLM_DIV_52
1733 * @arg @ref LL_RCC_PLLM_DIV_53
1734 * @arg @ref LL_RCC_PLLM_DIV_54
1735 * @arg @ref LL_RCC_PLLM_DIV_55
1736 * @arg @ref LL_RCC_PLLM_DIV_56
1737 * @arg @ref LL_RCC_PLLM_DIV_57
1738 * @arg @ref LL_RCC_PLLM_DIV_58
1739 * @arg @ref LL_RCC_PLLM_DIV_59
1740 * @arg @ref LL_RCC_PLLM_DIV_60
1741 * @arg @ref LL_RCC_PLLM_DIV_61
1742 * @arg @ref LL_RCC_PLLM_DIV_62
1743 * @arg @ref LL_RCC_PLLM_DIV_63
1744 */
LL_RCC_PLL_GetDivider(void)1745 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
1746 {
1747 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
1748 }
1749
1750 /**
1751 * @brief Configure Spread Spectrum used for PLL
1752 * @note These bits must be written before enabling PLL
1753 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
1754 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
1755 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
1756 * @param Mod Between Min_Data=0 and Max_Data=8191
1757 * @param Inc Between Min_Data=0 and Max_Data=32767
1758 * @param Sel This parameter can be one of the following values:
1759 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
1760 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
1761 * @retval None
1762 */
LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod,uint32_t Inc,uint32_t Sel)1763 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
1764 {
1765 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
1766 }
1767
1768 /**
1769 * @brief Get Spread Spectrum Modulation Period for PLL
1770 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
1771 * @retval Between Min_Data=0 and Max_Data=8191
1772 */
LL_RCC_PLL_GetPeriodModulation(void)1773 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
1774 {
1775 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
1776 }
1777
1778 /**
1779 * @brief Get Spread Spectrum Incrementation Step for PLL
1780 * @note Must be written before enabling PLL
1781 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
1782 * @retval Between Min_Data=0 and Max_Data=32767
1783 */
LL_RCC_PLL_GetStepIncrementation(void)1784 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
1785 {
1786 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
1787 }
1788
1789 /**
1790 * @brief Get Spread Spectrum Selection for PLL
1791 * @note Must be written before enabling PLL
1792 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
1793 * @retval Returned value can be one of the following values:
1794 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
1795 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
1796 */
LL_RCC_PLL_GetSpreadSelection(void)1797 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
1798 {
1799 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
1800 }
1801
1802 /**
1803 * @brief Enable Spread Spectrum for PLL.
1804 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
1805 * @retval None
1806 */
LL_RCC_PLL_SpreadSpectrum_Enable(void)1807 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
1808 {
1809 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
1810 }
1811
1812 /**
1813 * @brief Disable Spread Spectrum for PLL.
1814 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
1815 * @retval None
1816 */
LL_RCC_PLL_SpreadSpectrum_Disable(void)1817 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
1818 {
1819 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
1820 }
1821
1822 /**
1823 * @}
1824 */
1825
1826 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
1827 * @{
1828 */
1829
1830 /**
1831 * @brief Enable PLLI2S
1832 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
1833 * @retval None
1834 */
LL_RCC_PLLI2S_Enable(void)1835 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
1836 {
1837 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
1838 }
1839
1840 /**
1841 * @brief Disable PLLI2S
1842 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
1843 * @retval None
1844 */
LL_RCC_PLLI2S_Disable(void)1845 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
1846 {
1847 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
1848 }
1849
1850 /**
1851 * @brief Check if PLLI2S Ready
1852 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
1853 * @retval State of bit (1 or 0).
1854 */
LL_RCC_PLLI2S_IsReady(void)1855 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
1856 {
1857 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
1858 }
1859
1860 /**
1861 * @brief Configure PLLI2S used for I2S1 domain clock
1862 * @note PLL Source and PLLM Divider can be written only when PLL,
1863 * PLLI2S are disabled
1864 * @note PLLN/PLLR can be written only when PLLI2S is disabled
1865 * @note This can be selected for I2S
1866 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
1867 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
1868 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
1869 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
1870 * @param Source This parameter can be one of the following values:
1871 * @arg @ref LL_RCC_PLLSOURCE_HSI
1872 * @arg @ref LL_RCC_PLLSOURCE_HSE
1873 * @param PLLM This parameter can be one of the following values:
1874 * @arg @ref LL_RCC_PLLM_DIV_2
1875 * @arg @ref LL_RCC_PLLM_DIV_3
1876 * @arg @ref LL_RCC_PLLM_DIV_4
1877 * @arg @ref LL_RCC_PLLM_DIV_5
1878 * @arg @ref LL_RCC_PLLM_DIV_6
1879 * @arg @ref LL_RCC_PLLM_DIV_7
1880 * @arg @ref LL_RCC_PLLM_DIV_8
1881 * @arg @ref LL_RCC_PLLM_DIV_9
1882 * @arg @ref LL_RCC_PLLM_DIV_10
1883 * @arg @ref LL_RCC_PLLM_DIV_11
1884 * @arg @ref LL_RCC_PLLM_DIV_12
1885 * @arg @ref LL_RCC_PLLM_DIV_13
1886 * @arg @ref LL_RCC_PLLM_DIV_14
1887 * @arg @ref LL_RCC_PLLM_DIV_15
1888 * @arg @ref LL_RCC_PLLM_DIV_16
1889 * @arg @ref LL_RCC_PLLM_DIV_17
1890 * @arg @ref LL_RCC_PLLM_DIV_18
1891 * @arg @ref LL_RCC_PLLM_DIV_19
1892 * @arg @ref LL_RCC_PLLM_DIV_20
1893 * @arg @ref LL_RCC_PLLM_DIV_21
1894 * @arg @ref LL_RCC_PLLM_DIV_22
1895 * @arg @ref LL_RCC_PLLM_DIV_23
1896 * @arg @ref LL_RCC_PLLM_DIV_24
1897 * @arg @ref LL_RCC_PLLM_DIV_25
1898 * @arg @ref LL_RCC_PLLM_DIV_26
1899 * @arg @ref LL_RCC_PLLM_DIV_27
1900 * @arg @ref LL_RCC_PLLM_DIV_28
1901 * @arg @ref LL_RCC_PLLM_DIV_29
1902 * @arg @ref LL_RCC_PLLM_DIV_30
1903 * @arg @ref LL_RCC_PLLM_DIV_31
1904 * @arg @ref LL_RCC_PLLM_DIV_32
1905 * @arg @ref LL_RCC_PLLM_DIV_33
1906 * @arg @ref LL_RCC_PLLM_DIV_34
1907 * @arg @ref LL_RCC_PLLM_DIV_35
1908 * @arg @ref LL_RCC_PLLM_DIV_36
1909 * @arg @ref LL_RCC_PLLM_DIV_37
1910 * @arg @ref LL_RCC_PLLM_DIV_38
1911 * @arg @ref LL_RCC_PLLM_DIV_39
1912 * @arg @ref LL_RCC_PLLM_DIV_40
1913 * @arg @ref LL_RCC_PLLM_DIV_41
1914 * @arg @ref LL_RCC_PLLM_DIV_42
1915 * @arg @ref LL_RCC_PLLM_DIV_43
1916 * @arg @ref LL_RCC_PLLM_DIV_44
1917 * @arg @ref LL_RCC_PLLM_DIV_45
1918 * @arg @ref LL_RCC_PLLM_DIV_46
1919 * @arg @ref LL_RCC_PLLM_DIV_47
1920 * @arg @ref LL_RCC_PLLM_DIV_48
1921 * @arg @ref LL_RCC_PLLM_DIV_49
1922 * @arg @ref LL_RCC_PLLM_DIV_50
1923 * @arg @ref LL_RCC_PLLM_DIV_51
1924 * @arg @ref LL_RCC_PLLM_DIV_52
1925 * @arg @ref LL_RCC_PLLM_DIV_53
1926 * @arg @ref LL_RCC_PLLM_DIV_54
1927 * @arg @ref LL_RCC_PLLM_DIV_55
1928 * @arg @ref LL_RCC_PLLM_DIV_56
1929 * @arg @ref LL_RCC_PLLM_DIV_57
1930 * @arg @ref LL_RCC_PLLM_DIV_58
1931 * @arg @ref LL_RCC_PLLM_DIV_59
1932 * @arg @ref LL_RCC_PLLM_DIV_60
1933 * @arg @ref LL_RCC_PLLM_DIV_61
1934 * @arg @ref LL_RCC_PLLM_DIV_62
1935 * @arg @ref LL_RCC_PLLM_DIV_63
1936 * @param PLLN Between 192 and 432
1937 * @param PLLR This parameter can be one of the following values:
1938 * @arg @ref LL_RCC_PLLI2SR_DIV_2
1939 * @arg @ref LL_RCC_PLLI2SR_DIV_3
1940 * @arg @ref LL_RCC_PLLI2SR_DIV_4
1941 * @arg @ref LL_RCC_PLLI2SR_DIV_5
1942 * @arg @ref LL_RCC_PLLI2SR_DIV_6
1943 * @arg @ref LL_RCC_PLLI2SR_DIV_7
1944 * @retval None
1945 */
LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)1946 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
1947 {
1948 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
1949 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
1950 }
1951
1952 /**
1953 * @brief Get I2SPLL multiplication factor for VCO
1954 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
1955 * @retval Between 192 and 432
1956 */
LL_RCC_PLLI2S_GetN(void)1957 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
1958 {
1959 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
1960 }
1961
1962 /**
1963 * @brief Get I2SPLL division factor for PLLI2SR
1964 * @note used for PLLI2SCLK (I2S clock)
1965 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
1966 * @retval Returned value can be one of the following values:
1967 * @arg @ref LL_RCC_PLLI2SR_DIV_2
1968 * @arg @ref LL_RCC_PLLI2SR_DIV_3
1969 * @arg @ref LL_RCC_PLLI2SR_DIV_4
1970 * @arg @ref LL_RCC_PLLI2SR_DIV_5
1971 * @arg @ref LL_RCC_PLLI2SR_DIV_6
1972 * @arg @ref LL_RCC_PLLI2SR_DIV_7
1973 */
LL_RCC_PLLI2S_GetR(void)1974 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
1975 {
1976 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
1977 }
1978
1979 /**
1980 * @}
1981 */
1982
1983 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1984 * @{
1985 */
1986
1987 /**
1988 * @brief Clear LSI ready interrupt flag
1989 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1990 * @retval None
1991 */
LL_RCC_ClearFlag_LSIRDY(void)1992 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1993 {
1994 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
1995 }
1996
1997 /**
1998 * @brief Clear LSE ready interrupt flag
1999 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
2000 * @retval None
2001 */
LL_RCC_ClearFlag_LSERDY(void)2002 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2003 {
2004 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
2005 }
2006
2007 /**
2008 * @brief Clear HSI ready interrupt flag
2009 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2010 * @retval None
2011 */
LL_RCC_ClearFlag_HSIRDY(void)2012 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2013 {
2014 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
2015 }
2016
2017 /**
2018 * @brief Clear HSE ready interrupt flag
2019 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
2020 * @retval None
2021 */
LL_RCC_ClearFlag_HSERDY(void)2022 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2023 {
2024 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
2025 }
2026
2027 /**
2028 * @brief Clear PLL ready interrupt flag
2029 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2030 * @retval None
2031 */
LL_RCC_ClearFlag_PLLRDY(void)2032 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2033 {
2034 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
2035 }
2036
2037 /**
2038 * @brief Clear PLLI2S ready interrupt flag
2039 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
2040 * @retval None
2041 */
LL_RCC_ClearFlag_PLLI2SRDY(void)2042 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
2043 {
2044 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
2045 }
2046
2047 /**
2048 * @brief Clear Clock security system interrupt flag
2049 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
2050 * @retval None
2051 */
LL_RCC_ClearFlag_HSECSS(void)2052 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2053 {
2054 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
2055 }
2056
2057 /**
2058 * @brief Check if LSI ready interrupt occurred or not
2059 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2060 * @retval State of bit (1 or 0).
2061 */
LL_RCC_IsActiveFlag_LSIRDY(void)2062 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2063 {
2064 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
2065 }
2066
2067 /**
2068 * @brief Check if LSE ready interrupt occurred or not
2069 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2070 * @retval State of bit (1 or 0).
2071 */
LL_RCC_IsActiveFlag_LSERDY(void)2072 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2073 {
2074 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
2075 }
2076
2077 /**
2078 * @brief Check if HSI ready interrupt occurred or not
2079 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2080 * @retval State of bit (1 or 0).
2081 */
LL_RCC_IsActiveFlag_HSIRDY(void)2082 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2083 {
2084 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
2085 }
2086
2087 /**
2088 * @brief Check if HSE ready interrupt occurred or not
2089 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2090 * @retval State of bit (1 or 0).
2091 */
LL_RCC_IsActiveFlag_HSERDY(void)2092 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2093 {
2094 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
2095 }
2096
2097 /**
2098 * @brief Check if PLL ready interrupt occurred or not
2099 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2100 * @retval State of bit (1 or 0).
2101 */
LL_RCC_IsActiveFlag_PLLRDY(void)2102 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2103 {
2104 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
2105 }
2106
2107 /**
2108 * @brief Check if PLLI2S ready interrupt occurred or not
2109 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
2110 * @retval State of bit (1 or 0).
2111 */
LL_RCC_IsActiveFlag_PLLI2SRDY(void)2112 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
2113 {
2114 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
2115 }
2116
2117 /**
2118 * @brief Check if Clock security system interrupt occurred or not
2119 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
2120 * @retval State of bit (1 or 0).
2121 */
LL_RCC_IsActiveFlag_HSECSS(void)2122 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2123 {
2124 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
2125 }
2126
2127 /**
2128 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2129 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2130 * @retval State of bit (1 or 0).
2131 */
LL_RCC_IsActiveFlag_IWDGRST(void)2132 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2133 {
2134 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
2135 }
2136
2137 /**
2138 * @brief Check if RCC flag Low Power reset is set or not.
2139 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2140 * @retval State of bit (1 or 0).
2141 */
LL_RCC_IsActiveFlag_LPWRRST(void)2142 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2143 {
2144 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
2145 }
2146
2147 /**
2148 * @brief Check if RCC flag Pin reset is set or not.
2149 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2150 * @retval State of bit (1 or 0).
2151 */
LL_RCC_IsActiveFlag_PINRST(void)2152 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2153 {
2154 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
2155 }
2156
2157 /**
2158 * @brief Check if RCC flag POR/PDR reset is set or not.
2159 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
2160 * @retval State of bit (1 or 0).
2161 */
LL_RCC_IsActiveFlag_PORRST(void)2162 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
2163 {
2164 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
2165 }
2166
2167 /**
2168 * @brief Check if RCC flag Software reset is set or not.
2169 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2170 * @retval State of bit (1 or 0).
2171 */
LL_RCC_IsActiveFlag_SFTRST(void)2172 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2173 {
2174 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
2175 }
2176
2177 /**
2178 * @brief Check if RCC flag Window Watchdog reset is set or not.
2179 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2180 * @retval State of bit (1 or 0).
2181 */
LL_RCC_IsActiveFlag_WWDGRST(void)2182 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2183 {
2184 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
2185 }
2186
2187 /**
2188 * @brief Check if RCC flag BOR reset is set or not.
2189 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2190 * @retval State of bit (1 or 0).
2191 */
LL_RCC_IsActiveFlag_BORRST(void)2192 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2193 {
2194 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
2195 }
2196
2197 /**
2198 * @brief Set RMVF bit to clear the reset flags.
2199 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2200 * @retval None
2201 */
LL_RCC_ClearResetFlags(void)2202 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2203 {
2204 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2205 }
2206
2207 /**
2208 * @}
2209 */
2210
2211 /** @defgroup RCC_LL_EF_IT_Management IT Management
2212 * @{
2213 */
2214
2215 /**
2216 * @brief Enable LSI ready interrupt
2217 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
2218 * @retval None
2219 */
LL_RCC_EnableIT_LSIRDY(void)2220 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2221 {
2222 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2223 }
2224
2225 /**
2226 * @brief Enable LSE ready interrupt
2227 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
2228 * @retval None
2229 */
LL_RCC_EnableIT_LSERDY(void)2230 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2231 {
2232 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2233 }
2234
2235 /**
2236 * @brief Enable HSI ready interrupt
2237 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
2238 * @retval None
2239 */
LL_RCC_EnableIT_HSIRDY(void)2240 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2241 {
2242 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2243 }
2244
2245 /**
2246 * @brief Enable HSE ready interrupt
2247 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
2248 * @retval None
2249 */
LL_RCC_EnableIT_HSERDY(void)2250 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2251 {
2252 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2253 }
2254
2255 /**
2256 * @brief Enable PLL ready interrupt
2257 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
2258 * @retval None
2259 */
LL_RCC_EnableIT_PLLRDY(void)2260 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2261 {
2262 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2263 }
2264
2265 /**
2266 * @brief Enable PLLI2S ready interrupt
2267 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
2268 * @retval None
2269 */
LL_RCC_EnableIT_PLLI2SRDY(void)2270 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
2271 {
2272 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
2273 }
2274
2275 /**
2276 * @brief Disable LSI ready interrupt
2277 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
2278 * @retval None
2279 */
LL_RCC_DisableIT_LSIRDY(void)2280 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2281 {
2282 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2283 }
2284
2285 /**
2286 * @brief Disable LSE ready interrupt
2287 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
2288 * @retval None
2289 */
LL_RCC_DisableIT_LSERDY(void)2290 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2291 {
2292 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2293 }
2294
2295 /**
2296 * @brief Disable HSI ready interrupt
2297 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
2298 * @retval None
2299 */
LL_RCC_DisableIT_HSIRDY(void)2300 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2301 {
2302 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2303 }
2304
2305 /**
2306 * @brief Disable HSE ready interrupt
2307 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
2308 * @retval None
2309 */
LL_RCC_DisableIT_HSERDY(void)2310 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2311 {
2312 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2313 }
2314
2315 /**
2316 * @brief Disable PLL ready interrupt
2317 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
2318 * @retval None
2319 */
LL_RCC_DisableIT_PLLRDY(void)2320 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2321 {
2322 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2323 }
2324
2325 /**
2326 * @brief Disable PLLI2S ready interrupt
2327 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
2328 * @retval None
2329 */
LL_RCC_DisableIT_PLLI2SRDY(void)2330 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
2331 {
2332 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
2333 }
2334
2335 /**
2336 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2337 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2338 * @retval State of bit (1 or 0).
2339 */
LL_RCC_IsEnabledIT_LSIRDY(void)2340 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2341 {
2342 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
2343 }
2344
2345 /**
2346 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2347 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2348 * @retval State of bit (1 or 0).
2349 */
LL_RCC_IsEnabledIT_LSERDY(void)2350 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2351 {
2352 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
2353 }
2354
2355 /**
2356 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2357 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2358 * @retval State of bit (1 or 0).
2359 */
LL_RCC_IsEnabledIT_HSIRDY(void)2360 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2361 {
2362 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
2363 }
2364
2365 /**
2366 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2367 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2368 * @retval State of bit (1 or 0).
2369 */
LL_RCC_IsEnabledIT_HSERDY(void)2370 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2371 {
2372 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
2373 }
2374
2375 /**
2376 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2377 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2378 * @retval State of bit (1 or 0).
2379 */
LL_RCC_IsEnabledIT_PLLRDY(void)2380 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2381 {
2382 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
2383 }
2384
2385 /**
2386 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
2387 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
2388 * @retval State of bit (1 or 0).
2389 */
LL_RCC_IsEnabledIT_PLLI2SRDY(void)2390 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
2391 {
2392 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
2393 }
2394
2395 /**
2396 * @}
2397 */
2398
2399 #if defined(USE_FULL_LL_DRIVER)
2400 /** @defgroup RCC_LL_EF_Init De-initialization function
2401 * @{
2402 */
2403 ErrorStatus LL_RCC_DeInit(void);
2404 /**
2405 * @}
2406 */
2407
2408 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2409 * @{
2410 */
2411 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2412 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2413 /**
2414 * @}
2415 */
2416 #endif /* USE_FULL_LL_DRIVER */
2417
2418 /**
2419 * @}
2420 */
2421
2422 /**
2423 * @}
2424 */
2425
2426 #endif /* defined(RCC) */
2427
2428 /**
2429 * @}
2430 */
2431
2432 #ifdef __cplusplus
2433 }
2434 #endif
2435
2436 #endif /* __STM32F2xx_LL_RCC_H */
2437
2438
