1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F2xx_LL_I2C_H
21 #define __STM32F2xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47
48 /* Defines used to perform compute and check in the macros */
49 #define LL_I2C_MAX_SPEED_STANDARD 100000U
50 #define LL_I2C_MAX_SPEED_FAST 400000U
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
58 * @{
59 */
60 /**
61 * @}
62 */
63 #endif /*USE_FULL_LL_DRIVER*/
64
65 /* Exported types ------------------------------------------------------------*/
66 #if defined(USE_FULL_LL_DRIVER)
67 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
68 * @{
69 */
70 typedef struct
71 {
72 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
73 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
74
75 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
76
77 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
78 This parameter must be set to a value lower than 400kHz (in Hz)
79
80 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
81 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
82
83 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
84 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
85
86 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
87
88 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
89 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
90
91 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
92
93 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
94 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
95
96 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
97
98 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
99 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
100
101 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
102 } LL_I2C_InitTypeDef;
103 /**
104 * @}
105 */
106 #endif /*USE_FULL_LL_DRIVER*/
107
108 /* Exported constants --------------------------------------------------------*/
109 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
110 * @{
111 */
112
113 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
114 * @brief Flags defines which can be used with LL_I2C_ReadReg function
115 * @{
116 */
117 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
118 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
119 Address matched flag (slave mode) */
120 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
121 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
122 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
123 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
124 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
125 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
126 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
127 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
128 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
129 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
130 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
131 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
132 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
133 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
134 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
135 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
136 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
137 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
138 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
139 /**
140 * @}
141 */
142
143 /** @defgroup I2C_LL_EC_IT IT Defines
144 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
145 * @{
146 */
147 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
148 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
149 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
150 /**
151 * @}
152 */
153
154 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
155 * @{
156 */
157 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
158 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
159 /**
160 * @}
161 */
162
163 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
164 * @{
165 */
166 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
167 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
168 /**
169 * @}
170 */
171
172 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
173 * @{
174 */
175 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
176 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
177 /**
178 * @}
179 */
180
181 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
182 * @{
183 */
184 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
185 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
186 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
187 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
188 /**
189 * @}
190 */
191
192 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
193 * @{
194 */
195 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
196 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
197 /**
198 * @}
199 */
200
201 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
202 * @{
203 */
204 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
205 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
206 /**
207 * @}
208 */
209
210 /**
211 * @}
212 */
213
214 /* Exported macro ------------------------------------------------------------*/
215 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
216 * @{
217 */
218
219 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
220 * @{
221 */
222
223 /**
224 * @brief Write a value in I2C register
225 * @param __INSTANCE__ I2C Instance
226 * @param __REG__ Register to be written
227 * @param __VALUE__ Value to be written in the register
228 * @retval None
229 */
230 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
231
232 /**
233 * @brief Read a value in I2C register
234 * @param __INSTANCE__ I2C Instance
235 * @param __REG__ Register to be read
236 * @retval Register value
237 */
238 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
239 /**
240 * @}
241 */
242
243 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper
244 * @{
245 */
246
247 /**
248 * @brief Convert Peripheral Clock Frequency in Mhz.
249 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
250 * @retval Value of peripheral clock (in Mhz)
251 */
252 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
253
254 /**
255 * @brief Convert Peripheral Clock Frequency in Hz.
256 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
257 * @retval Value of peripheral clock (in Hz)
258 */
259 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
260
261 /**
262 * @brief Compute I2C Clock rising time.
263 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
264 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
265 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
266 */
267 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
268
269 /**
270 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
271 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
272 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
273 * @param __DUTYCYCLE__ This parameter can be one of the following values:
274 * @arg @ref LL_I2C_DUTYCYCLE_2
275 * @arg @ref LL_I2C_DUTYCYCLE_16_9
276 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
277 */
278 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
279 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
280 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
281
282 /**
283 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
284 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
285 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
286 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
287 */
288 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
289
290 /**
291 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
292 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
293 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
294 * @param __DUTYCYCLE__ This parameter can be one of the following values:
295 * @arg @ref LL_I2C_DUTYCYCLE_2
296 * @arg @ref LL_I2C_DUTYCYCLE_16_9
297 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
298 */
299 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
300 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
301 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
302
303 /**
304 * @brief Get the Least significant bits of a 10-Bits address.
305 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
306 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
307 */
308 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
309
310 /**
311 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
312 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
313 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
314 */
315 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
316
317 /**
318 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
319 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
320 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
321 */
322 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
323
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /* Exported functions --------------------------------------------------------*/
333
334 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
335 * @{
336 */
337
338 /** @defgroup I2C_LL_EF_Configuration Configuration
339 * @{
340 */
341
342 /**
343 * @brief Enable I2C peripheral (PE = 1).
344 * @rmtoll CR1 PE LL_I2C_Enable
345 * @param I2Cx I2C Instance.
346 * @retval None
347 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)348 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
349 {
350 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
351 }
352
353 /**
354 * @brief Disable I2C peripheral (PE = 0).
355 * @rmtoll CR1 PE LL_I2C_Disable
356 * @param I2Cx I2C Instance.
357 * @retval None
358 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)359 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
360 {
361 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
362 }
363
364 /**
365 * @brief Check if the I2C peripheral is enabled or disabled.
366 * @rmtoll CR1 PE LL_I2C_IsEnabled
367 * @param I2Cx I2C Instance.
368 * @retval State of bit (1 or 0).
369 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)370 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
371 {
372 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
373 }
374
375
376 /**
377 * @brief Enable DMA transmission requests.
378 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
379 * @param I2Cx I2C Instance.
380 * @retval None
381 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)382 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
383 {
384 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
385 }
386
387 /**
388 * @brief Disable DMA transmission requests.
389 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
390 * @param I2Cx I2C Instance.
391 * @retval None
392 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)393 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
394 {
395 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
396 }
397
398 /**
399 * @brief Check if DMA transmission requests are enabled or disabled.
400 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
401 * @param I2Cx I2C Instance.
402 * @retval State of bit (1 or 0).
403 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)404 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
405 {
406 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
407 }
408
409 /**
410 * @brief Enable DMA reception requests.
411 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
412 * @param I2Cx I2C Instance.
413 * @retval None
414 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)415 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
416 {
417 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
418 }
419
420 /**
421 * @brief Disable DMA reception requests.
422 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
423 * @param I2Cx I2C Instance.
424 * @retval None
425 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)426 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
427 {
428 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
429 }
430
431 /**
432 * @brief Check if DMA reception requests are enabled or disabled.
433 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
434 * @param I2Cx I2C Instance.
435 * @retval State of bit (1 or 0).
436 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)437 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
438 {
439 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
440 }
441
442 /**
443 * @brief Get the data register address used for DMA transfer.
444 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
445 * @param I2Cx I2C Instance.
446 * @retval Address of data register
447 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx)448 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
449 {
450 return (uint32_t) & (I2Cx->DR);
451 }
452
453 /**
454 * @brief Enable Clock stretching.
455 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
456 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
457 * @param I2Cx I2C Instance.
458 * @retval None
459 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)460 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
461 {
462 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
463 }
464
465 /**
466 * @brief Disable Clock stretching.
467 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
468 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
469 * @param I2Cx I2C Instance.
470 * @retval None
471 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)472 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
473 {
474 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
475 }
476
477 /**
478 * @brief Check if Clock stretching is enabled or disabled.
479 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
480 * @param I2Cx I2C Instance.
481 * @retval State of bit (1 or 0).
482 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)483 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
484 {
485 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
486 }
487
488 /**
489 * @brief Enable General Call.
490 * @note When enabled the Address 0x00 is ACKed.
491 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
492 * @param I2Cx I2C Instance.
493 * @retval None
494 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)495 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
496 {
497 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
498 }
499
500 /**
501 * @brief Disable General Call.
502 * @note When disabled the Address 0x00 is NACKed.
503 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
504 * @param I2Cx I2C Instance.
505 * @retval None
506 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)507 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
508 {
509 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
510 }
511
512 /**
513 * @brief Check if General Call is enabled or disabled.
514 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
515 * @param I2Cx I2C Instance.
516 * @retval State of bit (1 or 0).
517 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)518 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
519 {
520 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
521 }
522
523 /**
524 * @brief Set the Own Address1.
525 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
526 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
527 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
528 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
529 * @param I2Cx I2C Instance.
530 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
531 * @param OwnAddrSize This parameter can be one of the following values:
532 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
533 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
534 * @retval None
535 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)536 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
537 {
538 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
539 }
540
541 /**
542 * @brief Set the 7bits Own Address2.
543 * @note This action has no effect if own address2 is enabled.
544 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
545 * @param I2Cx I2C Instance.
546 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
547 * @retval None
548 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2)549 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
550 {
551 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
552 }
553
554 /**
555 * @brief Enable acknowledge on Own Address2 match address.
556 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)560 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
561 {
562 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
563 }
564
565 /**
566 * @brief Disable acknowledge on Own Address2 match address.
567 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
568 * @param I2Cx I2C Instance.
569 * @retval None
570 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)571 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
572 {
573 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
574 }
575
576 /**
577 * @brief Check if Own Address1 acknowledge is enabled or disabled.
578 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
579 * @param I2Cx I2C Instance.
580 * @retval State of bit (1 or 0).
581 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)582 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
583 {
584 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
585 }
586
587 /**
588 * @brief Configure the Peripheral clock frequency.
589 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
590 * @param I2Cx I2C Instance.
591 * @param PeriphClock Peripheral Clock (in Hz)
592 * @retval None
593 */
LL_I2C_SetPeriphClock(I2C_TypeDef * I2Cx,uint32_t PeriphClock)594 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
595 {
596 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
597 }
598
599 /**
600 * @brief Get the Peripheral clock frequency.
601 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
602 * @param I2Cx I2C Instance.
603 * @retval Value of Peripheral Clock (in Hz)
604 */
LL_I2C_GetPeriphClock(I2C_TypeDef * I2Cx)605 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
606 {
607 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
608 }
609
610 /**
611 * @brief Configure the Duty cycle (Fast mode only).
612 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
613 * @param I2Cx I2C Instance.
614 * @param DutyCycle This parameter can be one of the following values:
615 * @arg @ref LL_I2C_DUTYCYCLE_2
616 * @arg @ref LL_I2C_DUTYCYCLE_16_9
617 * @retval None
618 */
LL_I2C_SetDutyCycle(I2C_TypeDef * I2Cx,uint32_t DutyCycle)619 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
620 {
621 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
622 }
623
624 /**
625 * @brief Get the Duty cycle (Fast mode only).
626 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
627 * @param I2Cx I2C Instance.
628 * @retval Returned value can be one of the following values:
629 * @arg @ref LL_I2C_DUTYCYCLE_2
630 * @arg @ref LL_I2C_DUTYCYCLE_16_9
631 */
LL_I2C_GetDutyCycle(I2C_TypeDef * I2Cx)632 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
633 {
634 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
635 }
636
637 /**
638 * @brief Configure the I2C master clock speed mode.
639 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
640 * @param I2Cx I2C Instance.
641 * @param ClockSpeedMode This parameter can be one of the following values:
642 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
643 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
644 * @retval None
645 */
LL_I2C_SetClockSpeedMode(I2C_TypeDef * I2Cx,uint32_t ClockSpeedMode)646 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
647 {
648 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
649 }
650
651 /**
652 * @brief Get the the I2C master speed mode.
653 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
654 * @param I2Cx I2C Instance.
655 * @retval Returned value can be one of the following values:
656 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
657 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
658 */
LL_I2C_GetClockSpeedMode(I2C_TypeDef * I2Cx)659 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
660 {
661 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
662 }
663
664 /**
665 * @brief Configure the SCL, SDA rising time.
666 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
667 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
668 * @param I2Cx I2C Instance.
669 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
670 * @retval None
671 */
LL_I2C_SetRiseTime(I2C_TypeDef * I2Cx,uint32_t RiseTime)672 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
673 {
674 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
675 }
676
677 /**
678 * @brief Get the SCL, SDA rising time.
679 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
680 * @param I2Cx I2C Instance.
681 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
682 */
LL_I2C_GetRiseTime(I2C_TypeDef * I2Cx)683 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
684 {
685 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
686 }
687
688 /**
689 * @brief Configure the SCL high and low period.
690 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
691 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
692 * @param I2Cx I2C Instance.
693 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
694 * @retval None
695 */
LL_I2C_SetClockPeriod(I2C_TypeDef * I2Cx,uint32_t ClockPeriod)696 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
697 {
698 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
699 }
700
701 /**
702 * @brief Get the SCL high and low period.
703 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
704 * @param I2Cx I2C Instance.
705 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
706 */
LL_I2C_GetClockPeriod(I2C_TypeDef * I2Cx)707 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
708 {
709 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
710 }
711
712 /**
713 * @brief Configure the SCL speed.
714 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
715 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
716 * TRISE TRISE LL_I2C_ConfigSpeed\n
717 * CCR FS LL_I2C_ConfigSpeed\n
718 * CCR DUTY LL_I2C_ConfigSpeed\n
719 * CCR CCR LL_I2C_ConfigSpeed
720 * @param I2Cx I2C Instance.
721 * @param PeriphClock Peripheral Clock (in Hz)
722 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
723 * @param DutyCycle This parameter can be one of the following values:
724 * @arg @ref LL_I2C_DUTYCYCLE_2
725 * @arg @ref LL_I2C_DUTYCYCLE_16_9
726 * @retval None
727 */
LL_I2C_ConfigSpeed(I2C_TypeDef * I2Cx,uint32_t PeriphClock,uint32_t ClockSpeed,uint32_t DutyCycle)728 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
729 uint32_t DutyCycle)
730 {
731 uint32_t freqrange = 0x0U;
732 uint32_t clockconfig = 0x0U;
733
734 /* Compute frequency range */
735 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
736
737 /* Configure I2Cx: Frequency range register */
738 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
739
740 /* Configure I2Cx: Rise Time register */
741 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
742
743 /* Configure Speed mode, Duty Cycle and Clock control register value */
744 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
745 {
746 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
747 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
748 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
749 DutyCycle;
750 }
751 else
752 {
753 /* Set Speed mode at standard for Clock Speed request in standard clock range */
754 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
755 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
756 }
757
758 /* Configure I2Cx: Clock control register */
759 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
760 }
761
762 /**
763 * @brief Configure peripheral mode.
764 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
765 * SMBus feature is supported by the I2Cx Instance.
766 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
767 * CR1 SMBTYPE LL_I2C_SetMode\n
768 * CR1 ENARP LL_I2C_SetMode
769 * @param I2Cx I2C Instance.
770 * @param PeripheralMode This parameter can be one of the following values:
771 * @arg @ref LL_I2C_MODE_I2C
772 * @arg @ref LL_I2C_MODE_SMBUS_HOST
773 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
774 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
775 * @retval None
776 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)777 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
778 {
779 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
780 }
781
782 /**
783 * @brief Get peripheral mode.
784 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
785 * SMBus feature is supported by the I2Cx Instance.
786 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
787 * CR1 SMBTYPE LL_I2C_GetMode\n
788 * CR1 ENARP LL_I2C_GetMode
789 * @param I2Cx I2C Instance.
790 * @retval Returned value can be one of the following values:
791 * @arg @ref LL_I2C_MODE_I2C
792 * @arg @ref LL_I2C_MODE_SMBUS_HOST
793 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
794 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
795 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)796 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
797 {
798 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
799 }
800
801 /**
802 * @brief Enable SMBus alert (Host or Device mode)
803 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
804 * SMBus feature is supported by the I2Cx Instance.
805 * @note SMBus Device mode:
806 * - SMBus Alert pin is drived low and
807 * Alert Response Address Header acknowledge is enabled.
808 * SMBus Host mode:
809 * - SMBus Alert pin management is supported.
810 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
811 * @param I2Cx I2C Instance.
812 * @retval None
813 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)814 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
815 {
816 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
817 }
818
819 /**
820 * @brief Disable SMBus alert (Host or Device mode)
821 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
822 * SMBus feature is supported by the I2Cx Instance.
823 * @note SMBus Device mode:
824 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
825 * Alert Response Address Header acknowledge is disabled.
826 * SMBus Host mode:
827 * - SMBus Alert pin management is not supported.
828 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
829 * @param I2Cx I2C Instance.
830 * @retval None
831 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)832 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
833 {
834 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
835 }
836
837 /**
838 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
839 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
840 * SMBus feature is supported by the I2Cx Instance.
841 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
842 * @param I2Cx I2C Instance.
843 * @retval State of bit (1 or 0).
844 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)845 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
846 {
847 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
848 }
849
850 /**
851 * @brief Enable SMBus Packet Error Calculation (PEC).
852 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
853 * SMBus feature is supported by the I2Cx Instance.
854 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
855 * @param I2Cx I2C Instance.
856 * @retval None
857 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)858 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
859 {
860 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
861 }
862
863 /**
864 * @brief Disable SMBus Packet Error Calculation (PEC).
865 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
866 * SMBus feature is supported by the I2Cx Instance.
867 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
868 * @param I2Cx I2C Instance.
869 * @retval None
870 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)871 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
872 {
873 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
874 }
875
876 /**
877 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
878 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
879 * SMBus feature is supported by the I2Cx Instance.
880 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
881 * @param I2Cx I2C Instance.
882 * @retval State of bit (1 or 0).
883 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)884 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
885 {
886 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
887 }
888
889 /**
890 * @}
891 */
892
893 /** @defgroup I2C_LL_EF_IT_Management IT_Management
894 * @{
895 */
896
897 /**
898 * @brief Enable TXE interrupt.
899 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
900 * CR2 ITBUFEN LL_I2C_EnableIT_TX
901 * @param I2Cx I2C Instance.
902 * @retval None
903 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)904 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
905 {
906 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
907 }
908
909 /**
910 * @brief Disable TXE interrupt.
911 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
912 * CR2 ITBUFEN LL_I2C_DisableIT_TX
913 * @param I2Cx I2C Instance.
914 * @retval None
915 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)916 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
917 {
918 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
919 }
920
921 /**
922 * @brief Check if the TXE Interrupt is enabled or disabled.
923 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
924 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
925 * @param I2Cx I2C Instance.
926 * @retval State of bit (1 or 0).
927 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)928 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
929 {
930 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
931 }
932
933 /**
934 * @brief Enable RXNE interrupt.
935 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
936 * CR2 ITBUFEN LL_I2C_EnableIT_RX
937 * @param I2Cx I2C Instance.
938 * @retval None
939 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)940 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
941 {
942 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
943 }
944
945 /**
946 * @brief Disable RXNE interrupt.
947 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
948 * CR2 ITBUFEN LL_I2C_DisableIT_RX
949 * @param I2Cx I2C Instance.
950 * @retval None
951 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)952 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
953 {
954 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
955 }
956
957 /**
958 * @brief Check if the RXNE Interrupt is enabled or disabled.
959 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
960 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
961 * @param I2Cx I2C Instance.
962 * @retval State of bit (1 or 0).
963 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)964 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
965 {
966 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
967 }
968
969 /**
970 * @brief Enable Events interrupts.
971 * @note Any of these events will generate interrupt :
972 * Start Bit (SB)
973 * Address sent, Address matched (ADDR)
974 * 10-bit header sent (ADD10)
975 * Stop detection (STOPF)
976 * Byte transfer finished (BTF)
977 *
978 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
979 * Receive buffer not empty (RXNE)
980 * Transmit buffer empty (TXE)
981 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
982 * @param I2Cx I2C Instance.
983 * @retval None
984 */
LL_I2C_EnableIT_EVT(I2C_TypeDef * I2Cx)985 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
986 {
987 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
988 }
989
990 /**
991 * @brief Disable Events interrupts.
992 * @note Any of these events will generate interrupt :
993 * Start Bit (SB)
994 * Address sent, Address matched (ADDR)
995 * 10-bit header sent (ADD10)
996 * Stop detection (STOPF)
997 * Byte transfer finished (BTF)
998 * Receive buffer not empty (RXNE)
999 * Transmit buffer empty (TXE)
1000 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
1001 * @param I2Cx I2C Instance.
1002 * @retval None
1003 */
LL_I2C_DisableIT_EVT(I2C_TypeDef * I2Cx)1004 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
1005 {
1006 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1007 }
1008
1009 /**
1010 * @brief Check if Events interrupts are enabled or disabled.
1011 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
1012 * @param I2Cx I2C Instance.
1013 * @retval State of bit (1 or 0).
1014 */
LL_I2C_IsEnabledIT_EVT(I2C_TypeDef * I2Cx)1015 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
1016 {
1017 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
1018 }
1019
1020 /**
1021 * @brief Enable Buffer interrupts.
1022 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
1023 * Receive buffer not empty (RXNE)
1024 * Transmit buffer empty (TXE)
1025 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
1026 * @param I2Cx I2C Instance.
1027 * @retval None
1028 */
LL_I2C_EnableIT_BUF(I2C_TypeDef * I2Cx)1029 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
1030 {
1031 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1032 }
1033
1034 /**
1035 * @brief Disable Buffer interrupts.
1036 * @note Any of these Buffer events will generate interrupt :
1037 * Receive buffer not empty (RXNE)
1038 * Transmit buffer empty (TXE)
1039 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
1040 * @param I2Cx I2C Instance.
1041 * @retval None
1042 */
LL_I2C_DisableIT_BUF(I2C_TypeDef * I2Cx)1043 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
1044 {
1045 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1046 }
1047
1048 /**
1049 * @brief Check if Buffer interrupts are enabled or disabled.
1050 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
1051 * @param I2Cx I2C Instance.
1052 * @retval State of bit (1 or 0).
1053 */
LL_I2C_IsEnabledIT_BUF(I2C_TypeDef * I2Cx)1054 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
1055 {
1056 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
1057 }
1058
1059 /**
1060 * @brief Enable Error interrupts.
1061 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1062 * SMBus feature is supported by the I2Cx Instance.
1063 * @note Any of these errors will generate interrupt :
1064 * Bus Error detection (BERR)
1065 * Arbitration Loss (ARLO)
1066 * Acknowledge Failure(AF)
1067 * Overrun/Underrun (OVR)
1068 * SMBus Timeout detection (TIMEOUT)
1069 * SMBus PEC error detection (PECERR)
1070 * SMBus Alert pin event detection (SMBALERT)
1071 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
1072 * @param I2Cx I2C Instance.
1073 * @retval None
1074 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1075 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1076 {
1077 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1078 }
1079
1080 /**
1081 * @brief Disable Error interrupts.
1082 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1083 * SMBus feature is supported by the I2Cx Instance.
1084 * @note Any of these errors will generate interrupt :
1085 * Bus Error detection (BERR)
1086 * Arbitration Loss (ARLO)
1087 * Acknowledge Failure(AF)
1088 * Overrun/Underrun (OVR)
1089 * SMBus Timeout detection (TIMEOUT)
1090 * SMBus PEC error detection (PECERR)
1091 * SMBus Alert pin event detection (SMBALERT)
1092 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
1093 * @param I2Cx I2C Instance.
1094 * @retval None
1095 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1096 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1097 {
1098 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1099 }
1100
1101 /**
1102 * @brief Check if Error interrupts are enabled or disabled.
1103 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
1104 * @param I2Cx I2C Instance.
1105 * @retval State of bit (1 or 0).
1106 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1107 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1108 {
1109 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
1110 }
1111
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1117 * @{
1118 */
1119
1120 /**
1121 * @brief Indicate the status of Transmit data register empty flag.
1122 * @note RESET: When next data is written in Transmit data register.
1123 * SET: When Transmit data register is empty.
1124 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
1125 * @param I2Cx I2C Instance.
1126 * @retval State of bit (1 or 0).
1127 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1128 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1129 {
1130 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
1131 }
1132
1133 /**
1134 * @brief Indicate the status of Byte Transfer Finished flag.
1135 * RESET: When Data byte transfer not done.
1136 * SET: When Data byte transfer succeeded.
1137 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
1138 * @param I2Cx I2C Instance.
1139 * @retval State of bit (1 or 0).
1140 */
LL_I2C_IsActiveFlag_BTF(I2C_TypeDef * I2Cx)1141 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
1142 {
1143 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
1144 }
1145
1146 /**
1147 * @brief Indicate the status of Receive data register not empty flag.
1148 * @note RESET: When Receive data register is read.
1149 * SET: When the received data is copied in Receive data register.
1150 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
1151 * @param I2Cx I2C Instance.
1152 * @retval State of bit (1 or 0).
1153 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1154 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1155 {
1156 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
1157 }
1158
1159 /**
1160 * @brief Indicate the status of Start Bit (master mode).
1161 * @note RESET: When No Start condition.
1162 * SET: When Start condition is generated.
1163 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
1164 * @param I2Cx I2C Instance.
1165 * @retval State of bit (1 or 0).
1166 */
LL_I2C_IsActiveFlag_SB(I2C_TypeDef * I2Cx)1167 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
1168 {
1169 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
1170 }
1171
1172 /**
1173 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
1174 * @note RESET: Clear default value.
1175 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
1176 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
1177 * @param I2Cx I2C Instance.
1178 * @retval State of bit (1 or 0).
1179 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1180 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1181 {
1182 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
1183 }
1184
1185 /**
1186 * @brief Indicate the status of 10-bit header sent (master mode).
1187 * @note RESET: When no ADD10 event occurred.
1188 * SET: When the master has sent the first address byte (header).
1189 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
1190 * @param I2Cx I2C Instance.
1191 * @retval State of bit (1 or 0).
1192 */
LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef * I2Cx)1193 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
1194 {
1195 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
1196 }
1197
1198 /**
1199 * @brief Indicate the status of Acknowledge failure flag.
1200 * @note RESET: No acknowledge failure.
1201 * SET: When an acknowledge failure is received after a byte transmission.
1202 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
1203 * @param I2Cx I2C Instance.
1204 * @retval State of bit (1 or 0).
1205 */
LL_I2C_IsActiveFlag_AF(I2C_TypeDef * I2Cx)1206 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
1207 {
1208 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
1209 }
1210
1211 /**
1212 * @brief Indicate the status of Stop detection flag (slave mode).
1213 * @note RESET: Clear default value.
1214 * SET: When a Stop condition is detected.
1215 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
1216 * @param I2Cx I2C Instance.
1217 * @retval State of bit (1 or 0).
1218 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1219 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1220 {
1221 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
1222 }
1223
1224 /**
1225 * @brief Indicate the status of Bus error flag.
1226 * @note RESET: Clear default value.
1227 * SET: When a misplaced Start or Stop condition is detected.
1228 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
1229 * @param I2Cx I2C Instance.
1230 * @retval State of bit (1 or 0).
1231 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1232 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1233 {
1234 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
1235 }
1236
1237 /**
1238 * @brief Indicate the status of Arbitration lost flag.
1239 * @note RESET: Clear default value.
1240 * SET: When arbitration lost.
1241 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
1242 * @param I2Cx I2C Instance.
1243 * @retval State of bit (1 or 0).
1244 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1245 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1246 {
1247 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
1248 }
1249
1250 /**
1251 * @brief Indicate the status of Overrun/Underrun flag.
1252 * @note RESET: Clear default value.
1253 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1254 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
1255 * @param I2Cx I2C Instance.
1256 * @retval State of bit (1 or 0).
1257 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1258 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1259 {
1260 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
1261 }
1262
1263 /**
1264 * @brief Indicate the status of SMBus PEC error flag in reception.
1265 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1266 * SMBus feature is supported by the I2Cx Instance.
1267 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1268 * @param I2Cx I2C Instance.
1269 * @retval State of bit (1 or 0).
1270 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1271 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1272 {
1273 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
1274 }
1275
1276 /**
1277 * @brief Indicate the status of SMBus Timeout detection flag.
1278 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1279 * SMBus feature is supported by the I2Cx Instance.
1280 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1281 * @param I2Cx I2C Instance.
1282 * @retval State of bit (1 or 0).
1283 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1284 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1285 {
1286 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
1287 }
1288
1289 /**
1290 * @brief Indicate the status of SMBus alert flag.
1291 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1292 * SMBus feature is supported by the I2Cx Instance.
1293 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
1294 * @param I2Cx I2C Instance.
1295 * @retval State of bit (1 or 0).
1296 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1297 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1298 {
1299 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
1300 }
1301
1302 /**
1303 * @brief Indicate the status of Bus Busy flag.
1304 * @note RESET: Clear default value.
1305 * SET: When a Start condition is detected.
1306 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
1307 * @param I2Cx I2C Instance.
1308 * @retval State of bit (1 or 0).
1309 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1310 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1311 {
1312 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
1313 }
1314
1315 /**
1316 * @brief Indicate the status of Dual flag.
1317 * @note RESET: Received address matched with OAR1.
1318 * SET: Received address matched with OAR2.
1319 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
1320 * @param I2Cx I2C Instance.
1321 * @retval State of bit (1 or 0).
1322 */
LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef * I2Cx)1323 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
1324 {
1325 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
1326 }
1327
1328 /**
1329 * @brief Indicate the status of SMBus Host address reception (Slave mode).
1330 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1331 * SMBus feature is supported by the I2Cx Instance.
1332 * @note RESET: No SMBus Host address
1333 * SET: SMBus Host address received.
1334 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1335 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
1336 * @param I2Cx I2C Instance.
1337 * @retval State of bit (1 or 0).
1338 */
LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef * I2Cx)1339 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
1340 {
1341 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
1342 }
1343
1344 /**
1345 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
1346 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1347 * SMBus feature is supported by the I2Cx Instance.
1348 * @note RESET: No SMBus Device default address
1349 * SET: SMBus Device default address received.
1350 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1351 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
1352 * @param I2Cx I2C Instance.
1353 * @retval State of bit (1 or 0).
1354 */
LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef * I2Cx)1355 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
1356 {
1357 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
1358 }
1359
1360 /**
1361 * @brief Indicate the status of General call address reception (Slave mode).
1362 * @note RESET: No General call address
1363 * SET: General call address received.
1364 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
1365 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
1366 * @param I2Cx I2C Instance.
1367 * @retval State of bit (1 or 0).
1368 */
LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef * I2Cx)1369 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
1370 {
1371 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
1372 }
1373
1374 /**
1375 * @brief Indicate the status of Master/Slave flag.
1376 * @note RESET: Slave Mode.
1377 * SET: Master Mode.
1378 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
1379 * @param I2Cx I2C Instance.
1380 * @retval State of bit (1 or 0).
1381 */
LL_I2C_IsActiveFlag_MSL(I2C_TypeDef * I2Cx)1382 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
1383 {
1384 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
1385 }
1386
1387 /**
1388 * @brief Clear Address Matched flag.
1389 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1390 * register followed by a read access to the I2Cx_SR2 register.
1391 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
1392 * @param I2Cx I2C Instance.
1393 * @retval None
1394 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1395 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1396 {
1397 __IO uint32_t tmpreg;
1398 tmpreg = I2Cx->SR1;
1399 (void) tmpreg;
1400 tmpreg = I2Cx->SR2;
1401 (void) tmpreg;
1402 }
1403
1404 /**
1405 * @brief Clear Acknowledge failure flag.
1406 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
1407 * @param I2Cx I2C Instance.
1408 * @retval None
1409 */
LL_I2C_ClearFlag_AF(I2C_TypeDef * I2Cx)1410 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
1411 {
1412 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
1413 }
1414
1415 /**
1416 * @brief Clear Stop detection flag.
1417 * @note Clearing this flag is done by a read access to the I2Cx_SR1
1418 * register followed by a write access to I2Cx_CR1 register.
1419 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
1420 * CR1 PE LL_I2C_ClearFlag_STOP
1421 * @param I2Cx I2C Instance.
1422 * @retval None
1423 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1424 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1425 {
1426 __IO uint32_t tmpreg;
1427 tmpreg = I2Cx->SR1;
1428 (void) tmpreg;
1429 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
1430 }
1431
1432 /**
1433 * @brief Clear Bus error flag.
1434 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
1435 * @param I2Cx I2C Instance.
1436 * @retval None
1437 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1438 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1439 {
1440 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
1441 }
1442
1443 /**
1444 * @brief Clear Arbitration lost flag.
1445 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
1446 * @param I2Cx I2C Instance.
1447 * @retval None
1448 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1449 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1450 {
1451 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
1452 }
1453
1454 /**
1455 * @brief Clear Overrun/Underrun flag.
1456 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
1457 * @param I2Cx I2C Instance.
1458 * @retval None
1459 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1460 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1461 {
1462 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
1463 }
1464
1465 /**
1466 * @brief Clear SMBus PEC error flag.
1467 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
1468 * @param I2Cx I2C Instance.
1469 * @retval None
1470 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1471 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1472 {
1473 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
1474 }
1475
1476 /**
1477 * @brief Clear SMBus Timeout detection flag.
1478 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1479 * SMBus feature is supported by the I2Cx Instance.
1480 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
1481 * @param I2Cx I2C Instance.
1482 * @retval None
1483 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1484 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1485 {
1486 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
1487 }
1488
1489 /**
1490 * @brief Clear SMBus Alert flag.
1491 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1492 * SMBus feature is supported by the I2Cx Instance.
1493 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
1494 * @param I2Cx I2C Instance.
1495 * @retval None
1496 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1497 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1498 {
1499 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
1500 }
1501
1502 /**
1503 * @}
1504 */
1505
1506 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1507 * @{
1508 */
1509
1510 /**
1511 * @brief Enable Reset of I2C peripheral.
1512 * @rmtoll CR1 SWRST LL_I2C_EnableReset
1513 * @param I2Cx I2C Instance.
1514 * @retval None
1515 */
LL_I2C_EnableReset(I2C_TypeDef * I2Cx)1516 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
1517 {
1518 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1519 }
1520
1521 /**
1522 * @brief Disable Reset of I2C peripheral.
1523 * @rmtoll CR1 SWRST LL_I2C_DisableReset
1524 * @param I2Cx I2C Instance.
1525 * @retval None
1526 */
LL_I2C_DisableReset(I2C_TypeDef * I2Cx)1527 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
1528 {
1529 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1530 }
1531
1532 /**
1533 * @brief Check if the I2C peripheral is under reset state or not.
1534 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
1535 * @param I2Cx I2C Instance.
1536 * @retval State of bit (1 or 0).
1537 */
LL_I2C_IsResetEnabled(I2C_TypeDef * I2Cx)1538 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
1539 {
1540 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
1541 }
1542
1543 /**
1544 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1545 * @note Usage in Slave or Master mode.
1546 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
1547 * @param I2Cx I2C Instance.
1548 * @param TypeAcknowledge This parameter can be one of the following values:
1549 * @arg @ref LL_I2C_ACK
1550 * @arg @ref LL_I2C_NACK
1551 * @retval None
1552 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1553 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1554 {
1555 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
1556 }
1557
1558 /**
1559 * @brief Generate a START or RESTART condition
1560 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1561 * This action has no effect when RELOAD is set.
1562 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
1563 * @param I2Cx I2C Instance.
1564 * @retval None
1565 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1566 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1567 {
1568 SET_BIT(I2Cx->CR1, I2C_CR1_START);
1569 }
1570
1571 /**
1572 * @brief Generate a STOP condition after the current byte transfer (master mode).
1573 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
1574 * @param I2Cx I2C Instance.
1575 * @retval None
1576 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)1577 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1578 {
1579 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
1580 }
1581
1582 /**
1583 * @brief Enable bit POS (master/host mode).
1584 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
1585 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
1586 * @param I2Cx I2C Instance.
1587 * @retval None
1588 */
LL_I2C_EnableBitPOS(I2C_TypeDef * I2Cx)1589 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
1590 {
1591 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
1592 }
1593
1594 /**
1595 * @brief Disable bit POS (master/host mode).
1596 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
1597 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
1598 * @param I2Cx I2C Instance.
1599 * @retval None
1600 */
LL_I2C_DisableBitPOS(I2C_TypeDef * I2Cx)1601 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
1602 {
1603 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
1604 }
1605
1606 /**
1607 * @brief Check if bit POS is enabled or disabled.
1608 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
1609 * @param I2Cx I2C Instance.
1610 * @retval State of bit (1 or 0).
1611 */
LL_I2C_IsEnabledBitPOS(I2C_TypeDef * I2Cx)1612 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
1613 {
1614 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
1615 }
1616
1617 /**
1618 * @brief Indicate the value of transfer direction.
1619 * @note RESET: Bus is in read transfer (peripheral point of view).
1620 * SET: Bus is in write transfer (peripheral point of view).
1621 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
1622 * @param I2Cx I2C Instance.
1623 * @retval Returned value can be one of the following values:
1624 * @arg @ref LL_I2C_DIRECTION_WRITE
1625 * @arg @ref LL_I2C_DIRECTION_READ
1626 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)1627 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
1628 {
1629 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
1630 }
1631
1632 /**
1633 * @brief Enable DMA last transfer.
1634 * @note This action mean that next DMA EOT is the last transfer.
1635 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
1636 * @param I2Cx I2C Instance.
1637 * @retval None
1638 */
LL_I2C_EnableLastDMA(I2C_TypeDef * I2Cx)1639 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
1640 {
1641 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
1642 }
1643
1644 /**
1645 * @brief Disable DMA last transfer.
1646 * @note This action mean that next DMA EOT is not the last transfer.
1647 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
1648 * @param I2Cx I2C Instance.
1649 * @retval None
1650 */
LL_I2C_DisableLastDMA(I2C_TypeDef * I2Cx)1651 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
1652 {
1653 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
1654 }
1655
1656 /**
1657 * @brief Check if DMA last transfer is enabled or disabled.
1658 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
1659 * @param I2Cx I2C Instance.
1660 * @retval State of bit (1 or 0).
1661 */
LL_I2C_IsEnabledLastDMA(I2C_TypeDef * I2Cx)1662 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
1663 {
1664 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
1665 }
1666
1667 /**
1668 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1669 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1670 * SMBus feature is supported by the I2Cx Instance.
1671 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
1672 * or by a START or STOP condition, it is also cleared by software.
1673 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
1674 * @param I2Cx I2C Instance.
1675 * @retval None
1676 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)1677 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
1678 {
1679 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
1680 }
1681
1682 /**
1683 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
1684 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1685 * SMBus feature is supported by the I2Cx Instance.
1686 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
1687 * @param I2Cx I2C Instance.
1688 * @retval None
1689 */
LL_I2C_DisableSMBusPECCompare(I2C_TypeDef * I2Cx)1690 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
1691 {
1692 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
1693 }
1694
1695 /**
1696 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
1697 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1698 * SMBus feature is supported by the I2Cx Instance.
1699 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
1700 * @param I2Cx I2C Instance.
1701 * @retval State of bit (1 or 0).
1702 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)1703 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
1704 {
1705 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
1706 }
1707
1708 /**
1709 * @brief Get the SMBus Packet Error byte calculated.
1710 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1711 * SMBus feature is supported by the I2Cx Instance.
1712 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
1713 * @param I2Cx I2C Instance.
1714 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1715 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)1716 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
1717 {
1718 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
1719 }
1720
1721 /**
1722 * @brief Read Receive Data register.
1723 * @rmtoll DR DR LL_I2C_ReceiveData8
1724 * @param I2Cx I2C Instance.
1725 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1726 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)1727 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
1728 {
1729 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
1730 }
1731
1732 /**
1733 * @brief Write in Transmit Data Register .
1734 * @rmtoll DR DR LL_I2C_TransmitData8
1735 * @param I2Cx I2C Instance.
1736 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
1737 * @retval None
1738 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)1739 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1740 {
1741 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
1742 }
1743
1744 /**
1745 * @}
1746 */
1747
1748 #if defined(USE_FULL_LL_DRIVER)
1749 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
1750 * @{
1751 */
1752
1753 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
1754 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
1755 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1756
1757
1758 /**
1759 * @}
1760 */
1761 #endif /* USE_FULL_LL_DRIVER */
1762
1763 /**
1764 * @}
1765 */
1766
1767 /**
1768 * @}
1769 */
1770
1771 #endif /* I2C1 || I2C2 || I2C3 */
1772
1773 /**
1774 * @}
1775 */
1776
1777 #ifdef __cplusplus
1778 }
1779 #endif
1780
1781 #endif /* __STM32F2xx_LL_I2C_H */
1782
1783
