1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F2xx_LL_DMA_H
21 #define __STM32F2xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
46 static const uint8_t STREAM_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
56 };
57
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
64 * @{
65 */
66 /**
67 * @}
68 */
69
70
71 /* Private macros ------------------------------------------------------------*/
72 /* Exported types ------------------------------------------------------------*/
73 #if defined(USE_FULL_LL_DRIVER)
74 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
75 * @{
76 */
77 typedef struct
78 {
79 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
80 or as Source base address in case of memory to memory transfer direction.
81
82 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
83
84 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
85 or as Destination base address in case of memory to memory transfer direction.
86
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
88
89 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
90 from memory to memory or from peripheral to memory.
91 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
92
93 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
94
95 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
96 This parameter can be a value of @ref DMA_LL_EC_MODE
97 @note The circular buffer mode cannot be used if the memory to memory
98 data transfer direction is configured on the selected Stream
99
100 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
101
102 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
103 is incremented or not.
104 This parameter can be a value of @ref DMA_LL_EC_PERIPH
105
106 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
107
108 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
109 is incremented or not.
110 This parameter can be a value of @ref DMA_LL_EC_MEMORY
111
112 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
113
114 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
115 in case of memory to memory transfer direction.
116 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
117
118 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
119
120 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
121 in case of memory to memory transfer direction.
122 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
123
124 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
125
126 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
127 The data unit is equal to the source buffer configuration set in PeripheralSize
128 or MemorySize parameters depending in the transfer direction.
129 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
132
133 uint32_t Channel; /*!< Specifies the peripheral channel.
134 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
135
136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
137
138 uint32_t Priority; /*!< Specifies the channel priority level.
139 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
140
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
142
143 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
144 This parameter can be a value of @ref DMA_LL_FIFOMODE
145 @note The Direct mode (FIFO mode disabled) cannot be used if the
146 memory-to-memory data transfer is configured on the selected stream
147
148 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
149
150 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
151 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
152
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
154
155 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
156 It specifies the amount of data to be transferred in a single non interruptible
157 transaction.
158 This parameter can be a value of @ref DMA_LL_EC_MBURST
159 @note The burst mode is possible only if the address Increment mode is enabled.
160
161 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
162
163 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
164 It specifies the amount of data to be transferred in a single non interruptible
165 transaction.
166 This parameter can be a value of @ref DMA_LL_EC_PBURST
167 @note The burst mode is possible only if the address Increment mode is enabled.
168
169 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
170
171 } LL_DMA_InitTypeDef;
172 /**
173 * @}
174 */
175 #endif /*USE_FULL_LL_DRIVER*/
176 /* Exported constants --------------------------------------------------------*/
177 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
178 * @{
179 */
180
181 /** @defgroup DMA_LL_EC_STREAM STREAM
182 * @{
183 */
184 #define LL_DMA_STREAM_0 0x00000000U
185 #define LL_DMA_STREAM_1 0x00000001U
186 #define LL_DMA_STREAM_2 0x00000002U
187 #define LL_DMA_STREAM_3 0x00000003U
188 #define LL_DMA_STREAM_4 0x00000004U
189 #define LL_DMA_STREAM_5 0x00000005U
190 #define LL_DMA_STREAM_6 0x00000006U
191 #define LL_DMA_STREAM_7 0x00000007U
192 #define LL_DMA_STREAM_ALL 0xFFFF0000U
193 /**
194 * @}
195 */
196
197 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
198 * @{
199 */
200 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
201 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
202 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
203 /**
204 * @}
205 */
206
207 /** @defgroup DMA_LL_EC_MODE MODE
208 * @{
209 */
210 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
211 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
212 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
213 /**
214 * @}
215 */
216
217 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
218 * @{
219 */
220 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
221 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
222 /**
223 * @}
224 */
225
226 /** @defgroup DMA_LL_EC_PERIPH PERIPH
227 * @{
228 */
229 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
230 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
231 /**
232 * @}
233 */
234
235 /** @defgroup DMA_LL_EC_MEMORY MEMORY
236 * @{
237 */
238 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
239 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
240 /**
241 * @}
242 */
243
244 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
245 * @{
246 */
247 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
248 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
249 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
250 /**
251 * @}
252 */
253
254 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
255 * @{
256 */
257 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
258 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
259 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
260 /**
261 * @}
262 */
263
264 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
265 * @{
266 */
267 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
268 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
269 /**
270 * @}
271 */
272
273 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
274 * @{
275 */
276 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
277 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
278 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
279 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
280 /**
281 * @}
282 */
283
284 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
285 * @{
286 */
287 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
288 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
289 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
290 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
291 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
292 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
293 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
294 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
295 /**
296 * @}
297 */
298
299 /** @defgroup DMA_LL_EC_MBURST MBURST
300 * @{
301 */
302 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
303 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
304 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
305 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
306 /**
307 * @}
308 */
309
310 /** @defgroup DMA_LL_EC_PBURST PBURST
311 * @{
312 */
313 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
314 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
315 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
316 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
317 /**
318 * @}
319 */
320
321 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
322 * @{
323 */
324 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
325 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
326 /**
327 * @}
328 */
329
330 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
331 * @{
332 */
333 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
334 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
335 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
336 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
337 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
338 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
339 /**
340 * @}
341 */
342
343 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
344 * @{
345 */
346 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
347 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
348 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
349 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
350 /**
351 * @}
352 */
353
354 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
355 * @{
356 */
357 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
358 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
359 /**
360 * @}
361 */
362
363 /**
364 * @}
365 */
366
367 /* Exported macro ------------------------------------------------------------*/
368 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
369 * @{
370 */
371
372 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
373 * @{
374 */
375 /**
376 * @brief Write a value in DMA register
377 * @param __INSTANCE__ DMA Instance
378 * @param __REG__ Register to be written
379 * @param __VALUE__ Value to be written in the register
380 * @retval None
381 */
382 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
383
384 /**
385 * @brief Read a value in DMA register
386 * @param __INSTANCE__ DMA Instance
387 * @param __REG__ Register to be read
388 * @retval Register value
389 */
390 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
391 /**
392 * @}
393 */
394
395 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
396 * @{
397 */
398 /**
399 * @brief Convert DMAx_Streamy into DMAx
400 * @param __STREAM_INSTANCE__ DMAx_Streamy
401 * @retval DMAx
402 */
403 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
404 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
405
406 /**
407 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
408 * @param __STREAM_INSTANCE__ DMAx_Streamy
409 * @retval LL_DMA_CHANNEL_y
410 */
411 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
412 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
417 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
418 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
419 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
420 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
421 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
422 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
423 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
424 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
425 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
426 LL_DMA_STREAM_7)
427
428 /**
429 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
430 * @param __DMA_INSTANCE__ DMAx
431 * @param __STREAM__ LL_DMA_STREAM_y
432 * @retval DMAx_Streamy
433 */
434 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
435 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
450 DMA2_Stream7)
451
452 /**
453 * @}
454 */
455
456 /**
457 * @}
458 */
459
460
461 /* Exported functions --------------------------------------------------------*/
462 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
463 * @{
464 */
465
466 /** @defgroup DMA_LL_EF_Configuration Configuration
467 * @{
468 */
469 /**
470 * @brief Enable DMA stream.
471 * @rmtoll CR EN LL_DMA_EnableStream
472 * @param DMAx DMAx Instance
473 * @param Stream This parameter can be one of the following values:
474 * @arg @ref LL_DMA_STREAM_0
475 * @arg @ref LL_DMA_STREAM_1
476 * @arg @ref LL_DMA_STREAM_2
477 * @arg @ref LL_DMA_STREAM_3
478 * @arg @ref LL_DMA_STREAM_4
479 * @arg @ref LL_DMA_STREAM_5
480 * @arg @ref LL_DMA_STREAM_6
481 * @arg @ref LL_DMA_STREAM_7
482 * @retval None
483 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)484 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
485 {
486 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
487 }
488
489 /**
490 * @brief Disable DMA stream.
491 * @rmtoll CR EN LL_DMA_DisableStream
492 * @param DMAx DMAx Instance
493 * @param Stream This parameter can be one of the following values:
494 * @arg @ref LL_DMA_STREAM_0
495 * @arg @ref LL_DMA_STREAM_1
496 * @arg @ref LL_DMA_STREAM_2
497 * @arg @ref LL_DMA_STREAM_3
498 * @arg @ref LL_DMA_STREAM_4
499 * @arg @ref LL_DMA_STREAM_5
500 * @arg @ref LL_DMA_STREAM_6
501 * @arg @ref LL_DMA_STREAM_7
502 * @retval None
503 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)504 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
505 {
506 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
507 }
508
509 /**
510 * @brief Check if DMA stream is enabled or disabled.
511 * @rmtoll CR EN LL_DMA_IsEnabledStream
512 * @param DMAx DMAx Instance
513 * @param Stream This parameter can be one of the following values:
514 * @arg @ref LL_DMA_STREAM_0
515 * @arg @ref LL_DMA_STREAM_1
516 * @arg @ref LL_DMA_STREAM_2
517 * @arg @ref LL_DMA_STREAM_3
518 * @arg @ref LL_DMA_STREAM_4
519 * @arg @ref LL_DMA_STREAM_5
520 * @arg @ref LL_DMA_STREAM_6
521 * @arg @ref LL_DMA_STREAM_7
522 * @retval State of bit (1 or 0).
523 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)524 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
525 {
526 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
527 }
528
529 /**
530 * @brief Configure all parameters linked to DMA transfer.
531 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
532 * CR CIRC LL_DMA_ConfigTransfer\n
533 * CR PINC LL_DMA_ConfigTransfer\n
534 * CR MINC LL_DMA_ConfigTransfer\n
535 * CR PSIZE LL_DMA_ConfigTransfer\n
536 * CR MSIZE LL_DMA_ConfigTransfer\n
537 * CR PL LL_DMA_ConfigTransfer\n
538 * CR PFCTRL LL_DMA_ConfigTransfer
539 * @param DMAx DMAx Instance
540 * @param Stream This parameter can be one of the following values:
541 * @arg @ref LL_DMA_STREAM_0
542 * @arg @ref LL_DMA_STREAM_1
543 * @arg @ref LL_DMA_STREAM_2
544 * @arg @ref LL_DMA_STREAM_3
545 * @arg @ref LL_DMA_STREAM_4
546 * @arg @ref LL_DMA_STREAM_5
547 * @arg @ref LL_DMA_STREAM_6
548 * @arg @ref LL_DMA_STREAM_7
549 * @param Configuration This parameter must be a combination of all the following values:
550 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
551 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
552 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
553 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
554 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
555 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
556 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
557 *@retval None
558 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)559 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
560 {
561 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
562 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
563 Configuration);
564 }
565
566 /**
567 * @brief Set Data transfer direction (read from peripheral or from memory).
568 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
569 * @param DMAx DMAx Instance
570 * @param Stream This parameter can be one of the following values:
571 * @arg @ref LL_DMA_STREAM_0
572 * @arg @ref LL_DMA_STREAM_1
573 * @arg @ref LL_DMA_STREAM_2
574 * @arg @ref LL_DMA_STREAM_3
575 * @arg @ref LL_DMA_STREAM_4
576 * @arg @ref LL_DMA_STREAM_5
577 * @arg @ref LL_DMA_STREAM_6
578 * @arg @ref LL_DMA_STREAM_7
579 * @param Direction This parameter can be one of the following values:
580 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
581 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
582 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
583 * @retval None
584 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)585 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
586 {
587 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
588 }
589
590 /**
591 * @brief Get Data transfer direction (read from peripheral or from memory).
592 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
593 * @param DMAx DMAx Instance
594 * @param Stream This parameter can be one of the following values:
595 * @arg @ref LL_DMA_STREAM_0
596 * @arg @ref LL_DMA_STREAM_1
597 * @arg @ref LL_DMA_STREAM_2
598 * @arg @ref LL_DMA_STREAM_3
599 * @arg @ref LL_DMA_STREAM_4
600 * @arg @ref LL_DMA_STREAM_5
601 * @arg @ref LL_DMA_STREAM_6
602 * @arg @ref LL_DMA_STREAM_7
603 * @retval Returned value can be one of the following values:
604 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
605 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
606 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
607 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)608 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
609 {
610 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
611 }
612
613 /**
614 * @brief Set DMA mode normal, circular or peripheral flow control.
615 * @rmtoll CR CIRC LL_DMA_SetMode\n
616 * CR PFCTRL LL_DMA_SetMode
617 * @param DMAx DMAx Instance
618 * @param Stream This parameter can be one of the following values:
619 * @arg @ref LL_DMA_STREAM_0
620 * @arg @ref LL_DMA_STREAM_1
621 * @arg @ref LL_DMA_STREAM_2
622 * @arg @ref LL_DMA_STREAM_3
623 * @arg @ref LL_DMA_STREAM_4
624 * @arg @ref LL_DMA_STREAM_5
625 * @arg @ref LL_DMA_STREAM_6
626 * @arg @ref LL_DMA_STREAM_7
627 * @param Mode This parameter can be one of the following values:
628 * @arg @ref LL_DMA_MODE_NORMAL
629 * @arg @ref LL_DMA_MODE_CIRCULAR
630 * @arg @ref LL_DMA_MODE_PFCTRL
631 * @retval None
632 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)633 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
634 {
635 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
636 }
637
638 /**
639 * @brief Get DMA mode normal, circular or peripheral flow control.
640 * @rmtoll CR CIRC LL_DMA_GetMode\n
641 * CR PFCTRL LL_DMA_GetMode
642 * @param DMAx DMAx Instance
643 * @param Stream This parameter can be one of the following values:
644 * @arg @ref LL_DMA_STREAM_0
645 * @arg @ref LL_DMA_STREAM_1
646 * @arg @ref LL_DMA_STREAM_2
647 * @arg @ref LL_DMA_STREAM_3
648 * @arg @ref LL_DMA_STREAM_4
649 * @arg @ref LL_DMA_STREAM_5
650 * @arg @ref LL_DMA_STREAM_6
651 * @arg @ref LL_DMA_STREAM_7
652 * @retval Returned value can be one of the following values:
653 * @arg @ref LL_DMA_MODE_NORMAL
654 * @arg @ref LL_DMA_MODE_CIRCULAR
655 * @arg @ref LL_DMA_MODE_PFCTRL
656 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)657 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
658 {
659 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
660 }
661
662 /**
663 * @brief Set Peripheral increment mode.
664 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
665 * @param DMAx DMAx Instance
666 * @param Stream This parameter can be one of the following values:
667 * @arg @ref LL_DMA_STREAM_0
668 * @arg @ref LL_DMA_STREAM_1
669 * @arg @ref LL_DMA_STREAM_2
670 * @arg @ref LL_DMA_STREAM_3
671 * @arg @ref LL_DMA_STREAM_4
672 * @arg @ref LL_DMA_STREAM_5
673 * @arg @ref LL_DMA_STREAM_6
674 * @arg @ref LL_DMA_STREAM_7
675 * @param IncrementMode This parameter can be one of the following values:
676 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
677 * @arg @ref LL_DMA_PERIPH_INCREMENT
678 * @retval None
679 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)680 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
681 {
682 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
683 }
684
685 /**
686 * @brief Get Peripheral increment mode.
687 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
688 * @param DMAx DMAx Instance
689 * @param Stream This parameter can be one of the following values:
690 * @arg @ref LL_DMA_STREAM_0
691 * @arg @ref LL_DMA_STREAM_1
692 * @arg @ref LL_DMA_STREAM_2
693 * @arg @ref LL_DMA_STREAM_3
694 * @arg @ref LL_DMA_STREAM_4
695 * @arg @ref LL_DMA_STREAM_5
696 * @arg @ref LL_DMA_STREAM_6
697 * @arg @ref LL_DMA_STREAM_7
698 * @retval Returned value can be one of the following values:
699 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
700 * @arg @ref LL_DMA_PERIPH_INCREMENT
701 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)702 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
703 {
704 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
705 }
706
707 /**
708 * @brief Set Memory increment mode.
709 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
710 * @param DMAx DMAx Instance
711 * @param Stream This parameter can be one of the following values:
712 * @arg @ref LL_DMA_STREAM_0
713 * @arg @ref LL_DMA_STREAM_1
714 * @arg @ref LL_DMA_STREAM_2
715 * @arg @ref LL_DMA_STREAM_3
716 * @arg @ref LL_DMA_STREAM_4
717 * @arg @ref LL_DMA_STREAM_5
718 * @arg @ref LL_DMA_STREAM_6
719 * @arg @ref LL_DMA_STREAM_7
720 * @param IncrementMode This parameter can be one of the following values:
721 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
722 * @arg @ref LL_DMA_MEMORY_INCREMENT
723 * @retval None
724 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)725 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
726 {
727 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
728 }
729
730 /**
731 * @brief Get Memory increment mode.
732 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
733 * @param DMAx DMAx Instance
734 * @param Stream This parameter can be one of the following values:
735 * @arg @ref LL_DMA_STREAM_0
736 * @arg @ref LL_DMA_STREAM_1
737 * @arg @ref LL_DMA_STREAM_2
738 * @arg @ref LL_DMA_STREAM_3
739 * @arg @ref LL_DMA_STREAM_4
740 * @arg @ref LL_DMA_STREAM_5
741 * @arg @ref LL_DMA_STREAM_6
742 * @arg @ref LL_DMA_STREAM_7
743 * @retval Returned value can be one of the following values:
744 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
745 * @arg @ref LL_DMA_MEMORY_INCREMENT
746 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)747 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
748 {
749 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
750 }
751
752 /**
753 * @brief Set Peripheral size.
754 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
755 * @param DMAx DMAx Instance
756 * @param Stream This parameter can be one of the following values:
757 * @arg @ref LL_DMA_STREAM_0
758 * @arg @ref LL_DMA_STREAM_1
759 * @arg @ref LL_DMA_STREAM_2
760 * @arg @ref LL_DMA_STREAM_3
761 * @arg @ref LL_DMA_STREAM_4
762 * @arg @ref LL_DMA_STREAM_5
763 * @arg @ref LL_DMA_STREAM_6
764 * @arg @ref LL_DMA_STREAM_7
765 * @param Size This parameter can be one of the following values:
766 * @arg @ref LL_DMA_PDATAALIGN_BYTE
767 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
768 * @arg @ref LL_DMA_PDATAALIGN_WORD
769 * @retval None
770 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)771 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
772 {
773 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
774 }
775
776 /**
777 * @brief Get Peripheral size.
778 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
779 * @param DMAx DMAx Instance
780 * @param Stream This parameter can be one of the following values:
781 * @arg @ref LL_DMA_STREAM_0
782 * @arg @ref LL_DMA_STREAM_1
783 * @arg @ref LL_DMA_STREAM_2
784 * @arg @ref LL_DMA_STREAM_3
785 * @arg @ref LL_DMA_STREAM_4
786 * @arg @ref LL_DMA_STREAM_5
787 * @arg @ref LL_DMA_STREAM_6
788 * @arg @ref LL_DMA_STREAM_7
789 * @retval Returned value can be one of the following values:
790 * @arg @ref LL_DMA_PDATAALIGN_BYTE
791 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
792 * @arg @ref LL_DMA_PDATAALIGN_WORD
793 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)794 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
795 {
796 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
797 }
798
799 /**
800 * @brief Set Memory size.
801 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
802 * @param DMAx DMAx Instance
803 * @param Stream This parameter can be one of the following values:
804 * @arg @ref LL_DMA_STREAM_0
805 * @arg @ref LL_DMA_STREAM_1
806 * @arg @ref LL_DMA_STREAM_2
807 * @arg @ref LL_DMA_STREAM_3
808 * @arg @ref LL_DMA_STREAM_4
809 * @arg @ref LL_DMA_STREAM_5
810 * @arg @ref LL_DMA_STREAM_6
811 * @arg @ref LL_DMA_STREAM_7
812 * @param Size This parameter can be one of the following values:
813 * @arg @ref LL_DMA_MDATAALIGN_BYTE
814 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
815 * @arg @ref LL_DMA_MDATAALIGN_WORD
816 * @retval None
817 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)818 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
819 {
820 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
821 }
822
823 /**
824 * @brief Get Memory size.
825 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
826 * @param DMAx DMAx Instance
827 * @param Stream This parameter can be one of the following values:
828 * @arg @ref LL_DMA_STREAM_0
829 * @arg @ref LL_DMA_STREAM_1
830 * @arg @ref LL_DMA_STREAM_2
831 * @arg @ref LL_DMA_STREAM_3
832 * @arg @ref LL_DMA_STREAM_4
833 * @arg @ref LL_DMA_STREAM_5
834 * @arg @ref LL_DMA_STREAM_6
835 * @arg @ref LL_DMA_STREAM_7
836 * @retval Returned value can be one of the following values:
837 * @arg @ref LL_DMA_MDATAALIGN_BYTE
838 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
839 * @arg @ref LL_DMA_MDATAALIGN_WORD
840 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)841 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
842 {
843 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
844 }
845
846 /**
847 * @brief Set Peripheral increment offset size.
848 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
849 * @param DMAx DMAx Instance
850 * @param Stream This parameter can be one of the following values:
851 * @arg @ref LL_DMA_STREAM_0
852 * @arg @ref LL_DMA_STREAM_1
853 * @arg @ref LL_DMA_STREAM_2
854 * @arg @ref LL_DMA_STREAM_3
855 * @arg @ref LL_DMA_STREAM_4
856 * @arg @ref LL_DMA_STREAM_5
857 * @arg @ref LL_DMA_STREAM_6
858 * @arg @ref LL_DMA_STREAM_7
859 * @param OffsetSize This parameter can be one of the following values:
860 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
861 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
862 * @retval None
863 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)864 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
865 {
866 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
867 }
868
869 /**
870 * @brief Get Peripheral increment offset size.
871 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
872 * @param DMAx DMAx Instance
873 * @param Stream This parameter can be one of the following values:
874 * @arg @ref LL_DMA_STREAM_0
875 * @arg @ref LL_DMA_STREAM_1
876 * @arg @ref LL_DMA_STREAM_2
877 * @arg @ref LL_DMA_STREAM_3
878 * @arg @ref LL_DMA_STREAM_4
879 * @arg @ref LL_DMA_STREAM_5
880 * @arg @ref LL_DMA_STREAM_6
881 * @arg @ref LL_DMA_STREAM_7
882 * @retval Returned value can be one of the following values:
883 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
884 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
885 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)886 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
887 {
888 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
889 }
890
891 /**
892 * @brief Set Stream priority level.
893 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
894 * @param DMAx DMAx Instance
895 * @param Stream This parameter can be one of the following values:
896 * @arg @ref LL_DMA_STREAM_0
897 * @arg @ref LL_DMA_STREAM_1
898 * @arg @ref LL_DMA_STREAM_2
899 * @arg @ref LL_DMA_STREAM_3
900 * @arg @ref LL_DMA_STREAM_4
901 * @arg @ref LL_DMA_STREAM_5
902 * @arg @ref LL_DMA_STREAM_6
903 * @arg @ref LL_DMA_STREAM_7
904 * @param Priority This parameter can be one of the following values:
905 * @arg @ref LL_DMA_PRIORITY_LOW
906 * @arg @ref LL_DMA_PRIORITY_MEDIUM
907 * @arg @ref LL_DMA_PRIORITY_HIGH
908 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
909 * @retval None
910 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)911 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
912 {
913 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
914 }
915
916 /**
917 * @brief Get Stream priority level.
918 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
919 * @param DMAx DMAx Instance
920 * @param Stream This parameter can be one of the following values:
921 * @arg @ref LL_DMA_STREAM_0
922 * @arg @ref LL_DMA_STREAM_1
923 * @arg @ref LL_DMA_STREAM_2
924 * @arg @ref LL_DMA_STREAM_3
925 * @arg @ref LL_DMA_STREAM_4
926 * @arg @ref LL_DMA_STREAM_5
927 * @arg @ref LL_DMA_STREAM_6
928 * @arg @ref LL_DMA_STREAM_7
929 * @retval Returned value can be one of the following values:
930 * @arg @ref LL_DMA_PRIORITY_LOW
931 * @arg @ref LL_DMA_PRIORITY_MEDIUM
932 * @arg @ref LL_DMA_PRIORITY_HIGH
933 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
934 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)935 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
936 {
937 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
938 }
939
940 /**
941 * @brief Set Number of data to transfer.
942 * @rmtoll NDTR NDT LL_DMA_SetDataLength
943 * @note This action has no effect if
944 * stream is enabled.
945 * @param DMAx DMAx Instance
946 * @param Stream This parameter can be one of the following values:
947 * @arg @ref LL_DMA_STREAM_0
948 * @arg @ref LL_DMA_STREAM_1
949 * @arg @ref LL_DMA_STREAM_2
950 * @arg @ref LL_DMA_STREAM_3
951 * @arg @ref LL_DMA_STREAM_4
952 * @arg @ref LL_DMA_STREAM_5
953 * @arg @ref LL_DMA_STREAM_6
954 * @arg @ref LL_DMA_STREAM_7
955 * @param NbData Between 0 to 0xFFFFFFFF
956 * @retval None
957 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)958 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
959 {
960 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
961 }
962
963 /**
964 * @brief Get Number of data to transfer.
965 * @rmtoll NDTR NDT LL_DMA_GetDataLength
966 * @note Once the stream is enabled, the return value indicate the
967 * remaining bytes to be transmitted.
968 * @param DMAx DMAx Instance
969 * @param Stream This parameter can be one of the following values:
970 * @arg @ref LL_DMA_STREAM_0
971 * @arg @ref LL_DMA_STREAM_1
972 * @arg @ref LL_DMA_STREAM_2
973 * @arg @ref LL_DMA_STREAM_3
974 * @arg @ref LL_DMA_STREAM_4
975 * @arg @ref LL_DMA_STREAM_5
976 * @arg @ref LL_DMA_STREAM_6
977 * @arg @ref LL_DMA_STREAM_7
978 * @retval Between 0 to 0xFFFFFFFF
979 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)980 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
981 {
982 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
983 }
984
985 /**
986 * @brief Select Channel number associated to the Stream.
987 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
988 * @param DMAx DMAx Instance
989 * @param Stream This parameter can be one of the following values:
990 * @arg @ref LL_DMA_STREAM_0
991 * @arg @ref LL_DMA_STREAM_1
992 * @arg @ref LL_DMA_STREAM_2
993 * @arg @ref LL_DMA_STREAM_3
994 * @arg @ref LL_DMA_STREAM_4
995 * @arg @ref LL_DMA_STREAM_5
996 * @arg @ref LL_DMA_STREAM_6
997 * @arg @ref LL_DMA_STREAM_7
998 * @param Channel This parameter can be one of the following values:
999 * @arg @ref LL_DMA_CHANNEL_0
1000 * @arg @ref LL_DMA_CHANNEL_1
1001 * @arg @ref LL_DMA_CHANNEL_2
1002 * @arg @ref LL_DMA_CHANNEL_3
1003 * @arg @ref LL_DMA_CHANNEL_4
1004 * @arg @ref LL_DMA_CHANNEL_5
1005 * @arg @ref LL_DMA_CHANNEL_6
1006 * @arg @ref LL_DMA_CHANNEL_7
1007 * @retval None
1008 */
LL_DMA_SetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Channel)1009 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1010 {
1011 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1012 }
1013
1014 /**
1015 * @brief Get the Channel number associated to the Stream.
1016 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1017 * @param DMAx DMAx Instance
1018 * @param Stream This parameter can be one of the following values:
1019 * @arg @ref LL_DMA_STREAM_0
1020 * @arg @ref LL_DMA_STREAM_1
1021 * @arg @ref LL_DMA_STREAM_2
1022 * @arg @ref LL_DMA_STREAM_3
1023 * @arg @ref LL_DMA_STREAM_4
1024 * @arg @ref LL_DMA_STREAM_5
1025 * @arg @ref LL_DMA_STREAM_6
1026 * @arg @ref LL_DMA_STREAM_7
1027 * @retval Returned value can be one of the following values:
1028 * @arg @ref LL_DMA_CHANNEL_0
1029 * @arg @ref LL_DMA_CHANNEL_1
1030 * @arg @ref LL_DMA_CHANNEL_2
1031 * @arg @ref LL_DMA_CHANNEL_3
1032 * @arg @ref LL_DMA_CHANNEL_4
1033 * @arg @ref LL_DMA_CHANNEL_5
1034 * @arg @ref LL_DMA_CHANNEL_6
1035 * @arg @ref LL_DMA_CHANNEL_7
1036 */
LL_DMA_GetChannelSelection(DMA_TypeDef * DMAx,uint32_t Stream)1037 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1038 {
1039 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1040 }
1041
1042 /**
1043 * @brief Set Memory burst transfer configuration.
1044 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1045 * @param DMAx DMAx Instance
1046 * @param Stream This parameter can be one of the following values:
1047 * @arg @ref LL_DMA_STREAM_0
1048 * @arg @ref LL_DMA_STREAM_1
1049 * @arg @ref LL_DMA_STREAM_2
1050 * @arg @ref LL_DMA_STREAM_3
1051 * @arg @ref LL_DMA_STREAM_4
1052 * @arg @ref LL_DMA_STREAM_5
1053 * @arg @ref LL_DMA_STREAM_6
1054 * @arg @ref LL_DMA_STREAM_7
1055 * @param Mburst This parameter can be one of the following values:
1056 * @arg @ref LL_DMA_MBURST_SINGLE
1057 * @arg @ref LL_DMA_MBURST_INC4
1058 * @arg @ref LL_DMA_MBURST_INC8
1059 * @arg @ref LL_DMA_MBURST_INC16
1060 * @retval None
1061 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1062 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1063 {
1064 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1065 }
1066
1067 /**
1068 * @brief Get Memory burst transfer configuration.
1069 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1070 * @param DMAx DMAx Instance
1071 * @param Stream This parameter can be one of the following values:
1072 * @arg @ref LL_DMA_STREAM_0
1073 * @arg @ref LL_DMA_STREAM_1
1074 * @arg @ref LL_DMA_STREAM_2
1075 * @arg @ref LL_DMA_STREAM_3
1076 * @arg @ref LL_DMA_STREAM_4
1077 * @arg @ref LL_DMA_STREAM_5
1078 * @arg @ref LL_DMA_STREAM_6
1079 * @arg @ref LL_DMA_STREAM_7
1080 * @retval Returned value can be one of the following values:
1081 * @arg @ref LL_DMA_MBURST_SINGLE
1082 * @arg @ref LL_DMA_MBURST_INC4
1083 * @arg @ref LL_DMA_MBURST_INC8
1084 * @arg @ref LL_DMA_MBURST_INC16
1085 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1086 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1087 {
1088 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1089 }
1090
1091 /**
1092 * @brief Set Peripheral burst transfer configuration.
1093 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1094 * @param DMAx DMAx Instance
1095 * @param Stream This parameter can be one of the following values:
1096 * @arg @ref LL_DMA_STREAM_0
1097 * @arg @ref LL_DMA_STREAM_1
1098 * @arg @ref LL_DMA_STREAM_2
1099 * @arg @ref LL_DMA_STREAM_3
1100 * @arg @ref LL_DMA_STREAM_4
1101 * @arg @ref LL_DMA_STREAM_5
1102 * @arg @ref LL_DMA_STREAM_6
1103 * @arg @ref LL_DMA_STREAM_7
1104 * @param Pburst This parameter can be one of the following values:
1105 * @arg @ref LL_DMA_PBURST_SINGLE
1106 * @arg @ref LL_DMA_PBURST_INC4
1107 * @arg @ref LL_DMA_PBURST_INC8
1108 * @arg @ref LL_DMA_PBURST_INC16
1109 * @retval None
1110 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1111 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1112 {
1113 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1114 }
1115
1116 /**
1117 * @brief Get Peripheral burst transfer configuration.
1118 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1119 * @param DMAx DMAx Instance
1120 * @param Stream This parameter can be one of the following values:
1121 * @arg @ref LL_DMA_STREAM_0
1122 * @arg @ref LL_DMA_STREAM_1
1123 * @arg @ref LL_DMA_STREAM_2
1124 * @arg @ref LL_DMA_STREAM_3
1125 * @arg @ref LL_DMA_STREAM_4
1126 * @arg @ref LL_DMA_STREAM_5
1127 * @arg @ref LL_DMA_STREAM_6
1128 * @arg @ref LL_DMA_STREAM_7
1129 * @retval Returned value can be one of the following values:
1130 * @arg @ref LL_DMA_PBURST_SINGLE
1131 * @arg @ref LL_DMA_PBURST_INC4
1132 * @arg @ref LL_DMA_PBURST_INC8
1133 * @arg @ref LL_DMA_PBURST_INC16
1134 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1135 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1136 {
1137 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1138 }
1139
1140 /**
1141 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1142 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1143 * @param DMAx DMAx Instance
1144 * @param Stream This parameter can be one of the following values:
1145 * @arg @ref LL_DMA_STREAM_0
1146 * @arg @ref LL_DMA_STREAM_1
1147 * @arg @ref LL_DMA_STREAM_2
1148 * @arg @ref LL_DMA_STREAM_3
1149 * @arg @ref LL_DMA_STREAM_4
1150 * @arg @ref LL_DMA_STREAM_5
1151 * @arg @ref LL_DMA_STREAM_6
1152 * @arg @ref LL_DMA_STREAM_7
1153 * @param CurrentMemory This parameter can be one of the following values:
1154 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1155 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1156 * @retval None
1157 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1158 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1159 {
1160 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1161 }
1162
1163 /**
1164 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1165 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1166 * @param DMAx DMAx Instance
1167 * @param Stream This parameter can be one of the following values:
1168 * @arg @ref LL_DMA_STREAM_0
1169 * @arg @ref LL_DMA_STREAM_1
1170 * @arg @ref LL_DMA_STREAM_2
1171 * @arg @ref LL_DMA_STREAM_3
1172 * @arg @ref LL_DMA_STREAM_4
1173 * @arg @ref LL_DMA_STREAM_5
1174 * @arg @ref LL_DMA_STREAM_6
1175 * @arg @ref LL_DMA_STREAM_7
1176 * @retval Returned value can be one of the following values:
1177 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1178 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1179 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1180 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1181 {
1182 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1183 }
1184
1185 /**
1186 * @brief Enable the double buffer mode.
1187 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1188 * @param DMAx DMAx Instance
1189 * @param Stream This parameter can be one of the following values:
1190 * @arg @ref LL_DMA_STREAM_0
1191 * @arg @ref LL_DMA_STREAM_1
1192 * @arg @ref LL_DMA_STREAM_2
1193 * @arg @ref LL_DMA_STREAM_3
1194 * @arg @ref LL_DMA_STREAM_4
1195 * @arg @ref LL_DMA_STREAM_5
1196 * @arg @ref LL_DMA_STREAM_6
1197 * @arg @ref LL_DMA_STREAM_7
1198 * @retval None
1199 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1200 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1201 {
1202 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1203 }
1204
1205 /**
1206 * @brief Disable the double buffer mode.
1207 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1208 * @param DMAx DMAx Instance
1209 * @param Stream This parameter can be one of the following values:
1210 * @arg @ref LL_DMA_STREAM_0
1211 * @arg @ref LL_DMA_STREAM_1
1212 * @arg @ref LL_DMA_STREAM_2
1213 * @arg @ref LL_DMA_STREAM_3
1214 * @arg @ref LL_DMA_STREAM_4
1215 * @arg @ref LL_DMA_STREAM_5
1216 * @arg @ref LL_DMA_STREAM_6
1217 * @arg @ref LL_DMA_STREAM_7
1218 * @retval None
1219 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1220 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1221 {
1222 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1223 }
1224
1225 /**
1226 * @brief Get FIFO status.
1227 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1228 * @param DMAx DMAx Instance
1229 * @param Stream This parameter can be one of the following values:
1230 * @arg @ref LL_DMA_STREAM_0
1231 * @arg @ref LL_DMA_STREAM_1
1232 * @arg @ref LL_DMA_STREAM_2
1233 * @arg @ref LL_DMA_STREAM_3
1234 * @arg @ref LL_DMA_STREAM_4
1235 * @arg @ref LL_DMA_STREAM_5
1236 * @arg @ref LL_DMA_STREAM_6
1237 * @arg @ref LL_DMA_STREAM_7
1238 * @retval Returned value can be one of the following values:
1239 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1240 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1241 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1242 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1243 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1244 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1245 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1246 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1247 {
1248 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1249 }
1250
1251 /**
1252 * @brief Disable Fifo mode.
1253 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1254 * @param DMAx DMAx Instance
1255 * @param Stream This parameter can be one of the following values:
1256 * @arg @ref LL_DMA_STREAM_0
1257 * @arg @ref LL_DMA_STREAM_1
1258 * @arg @ref LL_DMA_STREAM_2
1259 * @arg @ref LL_DMA_STREAM_3
1260 * @arg @ref LL_DMA_STREAM_4
1261 * @arg @ref LL_DMA_STREAM_5
1262 * @arg @ref LL_DMA_STREAM_6
1263 * @arg @ref LL_DMA_STREAM_7
1264 * @retval None
1265 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1266 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1267 {
1268 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1269 }
1270
1271 /**
1272 * @brief Enable Fifo mode.
1273 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1274 * @param DMAx DMAx Instance
1275 * @param Stream This parameter can be one of the following values:
1276 * @arg @ref LL_DMA_STREAM_0
1277 * @arg @ref LL_DMA_STREAM_1
1278 * @arg @ref LL_DMA_STREAM_2
1279 * @arg @ref LL_DMA_STREAM_3
1280 * @arg @ref LL_DMA_STREAM_4
1281 * @arg @ref LL_DMA_STREAM_5
1282 * @arg @ref LL_DMA_STREAM_6
1283 * @arg @ref LL_DMA_STREAM_7
1284 * @retval None
1285 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1286 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1287 {
1288 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1289 }
1290
1291 /**
1292 * @brief Select FIFO threshold.
1293 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1294 * @param DMAx DMAx Instance
1295 * @param Stream This parameter can be one of the following values:
1296 * @arg @ref LL_DMA_STREAM_0
1297 * @arg @ref LL_DMA_STREAM_1
1298 * @arg @ref LL_DMA_STREAM_2
1299 * @arg @ref LL_DMA_STREAM_3
1300 * @arg @ref LL_DMA_STREAM_4
1301 * @arg @ref LL_DMA_STREAM_5
1302 * @arg @ref LL_DMA_STREAM_6
1303 * @arg @ref LL_DMA_STREAM_7
1304 * @param Threshold This parameter can be one of the following values:
1305 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1306 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1307 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1308 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1309 * @retval None
1310 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1311 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1312 {
1313 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1314 }
1315
1316 /**
1317 * @brief Get FIFO threshold.
1318 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1319 * @param DMAx DMAx Instance
1320 * @param Stream This parameter can be one of the following values:
1321 * @arg @ref LL_DMA_STREAM_0
1322 * @arg @ref LL_DMA_STREAM_1
1323 * @arg @ref LL_DMA_STREAM_2
1324 * @arg @ref LL_DMA_STREAM_3
1325 * @arg @ref LL_DMA_STREAM_4
1326 * @arg @ref LL_DMA_STREAM_5
1327 * @arg @ref LL_DMA_STREAM_6
1328 * @arg @ref LL_DMA_STREAM_7
1329 * @retval Returned value can be one of the following values:
1330 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1331 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1332 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1333 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1334 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1335 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1336 {
1337 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1338 }
1339
1340 /**
1341 * @brief Configure the FIFO .
1342 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1343 * FCR DMDIS LL_DMA_ConfigFifo
1344 * @param DMAx DMAx Instance
1345 * @param Stream This parameter can be one of the following values:
1346 * @arg @ref LL_DMA_STREAM_0
1347 * @arg @ref LL_DMA_STREAM_1
1348 * @arg @ref LL_DMA_STREAM_2
1349 * @arg @ref LL_DMA_STREAM_3
1350 * @arg @ref LL_DMA_STREAM_4
1351 * @arg @ref LL_DMA_STREAM_5
1352 * @arg @ref LL_DMA_STREAM_6
1353 * @arg @ref LL_DMA_STREAM_7
1354 * @param FifoMode This parameter can be one of the following values:
1355 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1356 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1357 * @param FifoThreshold This parameter can be one of the following values:
1358 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1359 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1360 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1361 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1362 * @retval None
1363 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1364 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1365 {
1366 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1367 }
1368
1369 /**
1370 * @brief Configure the Source and Destination addresses.
1371 * @note This API must not be called when the DMA stream is enabled.
1372 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1373 * PAR PA LL_DMA_ConfigAddresses
1374 * @param DMAx DMAx Instance
1375 * @param Stream This parameter can be one of the following values:
1376 * @arg @ref LL_DMA_STREAM_0
1377 * @arg @ref LL_DMA_STREAM_1
1378 * @arg @ref LL_DMA_STREAM_2
1379 * @arg @ref LL_DMA_STREAM_3
1380 * @arg @ref LL_DMA_STREAM_4
1381 * @arg @ref LL_DMA_STREAM_5
1382 * @arg @ref LL_DMA_STREAM_6
1383 * @arg @ref LL_DMA_STREAM_7
1384 * @param SrcAddress Between 0 to 0xFFFFFFFF
1385 * @param DstAddress Between 0 to 0xFFFFFFFF
1386 * @param Direction This parameter can be one of the following values:
1387 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1388 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1389 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1390 * @retval None
1391 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1392 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1393 {
1394 /* Direction Memory to Periph */
1395 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1396 {
1397 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1398 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1399 }
1400 /* Direction Periph to Memory and Memory to Memory */
1401 else
1402 {
1403 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1404 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1405 }
1406 }
1407
1408 /**
1409 * @brief Set the Memory address.
1410 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1411 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1412 * @note This API must not be called when the DMA channel is enabled.
1413 * @param DMAx DMAx Instance
1414 * @param Stream This parameter can be one of the following values:
1415 * @arg @ref LL_DMA_STREAM_0
1416 * @arg @ref LL_DMA_STREAM_1
1417 * @arg @ref LL_DMA_STREAM_2
1418 * @arg @ref LL_DMA_STREAM_3
1419 * @arg @ref LL_DMA_STREAM_4
1420 * @arg @ref LL_DMA_STREAM_5
1421 * @arg @ref LL_DMA_STREAM_6
1422 * @arg @ref LL_DMA_STREAM_7
1423 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1424 * @retval None
1425 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1426 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1427 {
1428 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1429 }
1430
1431 /**
1432 * @brief Set the Peripheral address.
1433 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1434 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1435 * @note This API must not be called when the DMA channel is enabled.
1436 * @param DMAx DMAx Instance
1437 * @param Stream This parameter can be one of the following values:
1438 * @arg @ref LL_DMA_STREAM_0
1439 * @arg @ref LL_DMA_STREAM_1
1440 * @arg @ref LL_DMA_STREAM_2
1441 * @arg @ref LL_DMA_STREAM_3
1442 * @arg @ref LL_DMA_STREAM_4
1443 * @arg @ref LL_DMA_STREAM_5
1444 * @arg @ref LL_DMA_STREAM_6
1445 * @arg @ref LL_DMA_STREAM_7
1446 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1447 * @retval None
1448 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1449 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1450 {
1451 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1452 }
1453
1454 /**
1455 * @brief Get the Memory address.
1456 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1457 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1458 * @param DMAx DMAx Instance
1459 * @param Stream This parameter can be one of the following values:
1460 * @arg @ref LL_DMA_STREAM_0
1461 * @arg @ref LL_DMA_STREAM_1
1462 * @arg @ref LL_DMA_STREAM_2
1463 * @arg @ref LL_DMA_STREAM_3
1464 * @arg @ref LL_DMA_STREAM_4
1465 * @arg @ref LL_DMA_STREAM_5
1466 * @arg @ref LL_DMA_STREAM_6
1467 * @arg @ref LL_DMA_STREAM_7
1468 * @retval Between 0 to 0xFFFFFFFF
1469 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1470 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1471 {
1472 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1473 }
1474
1475 /**
1476 * @brief Get the Peripheral address.
1477 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1478 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1479 * @param DMAx DMAx Instance
1480 * @param Stream This parameter can be one of the following values:
1481 * @arg @ref LL_DMA_STREAM_0
1482 * @arg @ref LL_DMA_STREAM_1
1483 * @arg @ref LL_DMA_STREAM_2
1484 * @arg @ref LL_DMA_STREAM_3
1485 * @arg @ref LL_DMA_STREAM_4
1486 * @arg @ref LL_DMA_STREAM_5
1487 * @arg @ref LL_DMA_STREAM_6
1488 * @arg @ref LL_DMA_STREAM_7
1489 * @retval Between 0 to 0xFFFFFFFF
1490 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1491 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1492 {
1493 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1494 }
1495
1496 /**
1497 * @brief Set the Memory to Memory Source address.
1498 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1499 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1500 * @note This API must not be called when the DMA channel is enabled.
1501 * @param DMAx DMAx Instance
1502 * @param Stream This parameter can be one of the following values:
1503 * @arg @ref LL_DMA_STREAM_0
1504 * @arg @ref LL_DMA_STREAM_1
1505 * @arg @ref LL_DMA_STREAM_2
1506 * @arg @ref LL_DMA_STREAM_3
1507 * @arg @ref LL_DMA_STREAM_4
1508 * @arg @ref LL_DMA_STREAM_5
1509 * @arg @ref LL_DMA_STREAM_6
1510 * @arg @ref LL_DMA_STREAM_7
1511 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1512 * @retval None
1513 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1514 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1515 {
1516 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1517 }
1518
1519 /**
1520 * @brief Set the Memory to Memory Destination address.
1521 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1522 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1523 * @note This API must not be called when the DMA channel is enabled.
1524 * @param DMAx DMAx Instance
1525 * @param Stream This parameter can be one of the following values:
1526 * @arg @ref LL_DMA_STREAM_0
1527 * @arg @ref LL_DMA_STREAM_1
1528 * @arg @ref LL_DMA_STREAM_2
1529 * @arg @ref LL_DMA_STREAM_3
1530 * @arg @ref LL_DMA_STREAM_4
1531 * @arg @ref LL_DMA_STREAM_5
1532 * @arg @ref LL_DMA_STREAM_6
1533 * @arg @ref LL_DMA_STREAM_7
1534 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1535 * @retval None
1536 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1537 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1538 {
1539 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1540 }
1541
1542 /**
1543 * @brief Get the Memory to Memory Source address.
1544 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1545 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1546 * @param DMAx DMAx Instance
1547 * @param Stream This parameter can be one of the following values:
1548 * @arg @ref LL_DMA_STREAM_0
1549 * @arg @ref LL_DMA_STREAM_1
1550 * @arg @ref LL_DMA_STREAM_2
1551 * @arg @ref LL_DMA_STREAM_3
1552 * @arg @ref LL_DMA_STREAM_4
1553 * @arg @ref LL_DMA_STREAM_5
1554 * @arg @ref LL_DMA_STREAM_6
1555 * @arg @ref LL_DMA_STREAM_7
1556 * @retval Between 0 to 0xFFFFFFFF
1557 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1558 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1559 {
1560 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1561 }
1562
1563 /**
1564 * @brief Get the Memory to Memory Destination address.
1565 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1566 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1567 * @param DMAx DMAx Instance
1568 * @param Stream This parameter can be one of the following values:
1569 * @arg @ref LL_DMA_STREAM_0
1570 * @arg @ref LL_DMA_STREAM_1
1571 * @arg @ref LL_DMA_STREAM_2
1572 * @arg @ref LL_DMA_STREAM_3
1573 * @arg @ref LL_DMA_STREAM_4
1574 * @arg @ref LL_DMA_STREAM_5
1575 * @arg @ref LL_DMA_STREAM_6
1576 * @arg @ref LL_DMA_STREAM_7
1577 * @retval Between 0 to 0xFFFFFFFF
1578 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1579 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1580 {
1581 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1582 }
1583
1584 /**
1585 * @brief Set Memory 1 address (used in case of Double buffer mode).
1586 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1587 * @param DMAx DMAx Instance
1588 * @param Stream This parameter can be one of the following values:
1589 * @arg @ref LL_DMA_STREAM_0
1590 * @arg @ref LL_DMA_STREAM_1
1591 * @arg @ref LL_DMA_STREAM_2
1592 * @arg @ref LL_DMA_STREAM_3
1593 * @arg @ref LL_DMA_STREAM_4
1594 * @arg @ref LL_DMA_STREAM_5
1595 * @arg @ref LL_DMA_STREAM_6
1596 * @arg @ref LL_DMA_STREAM_7
1597 * @param Address Between 0 to 0xFFFFFFFF
1598 * @retval None
1599 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1600 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1601 {
1602 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1603 }
1604
1605 /**
1606 * @brief Get Memory 1 address (used in case of Double buffer mode).
1607 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1608 * @param DMAx DMAx Instance
1609 * @param Stream This parameter can be one of the following values:
1610 * @arg @ref LL_DMA_STREAM_0
1611 * @arg @ref LL_DMA_STREAM_1
1612 * @arg @ref LL_DMA_STREAM_2
1613 * @arg @ref LL_DMA_STREAM_3
1614 * @arg @ref LL_DMA_STREAM_4
1615 * @arg @ref LL_DMA_STREAM_5
1616 * @arg @ref LL_DMA_STREAM_6
1617 * @arg @ref LL_DMA_STREAM_7
1618 * @retval Between 0 to 0xFFFFFFFF
1619 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)1620 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1621 {
1622 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1623 }
1624
1625 /**
1626 * @}
1627 */
1628
1629 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1630 * @{
1631 */
1632
1633 /**
1634 * @brief Get Stream 0 half transfer flag.
1635 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1636 * @param DMAx DMAx Instance
1637 * @retval State of bit (1 or 0).
1638 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)1639 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1640 {
1641 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1642 }
1643
1644 /**
1645 * @brief Get Stream 1 half transfer flag.
1646 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1647 * @param DMAx DMAx Instance
1648 * @retval State of bit (1 or 0).
1649 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1650 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1651 {
1652 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1653 }
1654
1655 /**
1656 * @brief Get Stream 2 half transfer flag.
1657 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1658 * @param DMAx DMAx Instance
1659 * @retval State of bit (1 or 0).
1660 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1661 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1662 {
1663 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1664 }
1665
1666 /**
1667 * @brief Get Stream 3 half transfer flag.
1668 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1669 * @param DMAx DMAx Instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1672 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1673 {
1674 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1675 }
1676
1677 /**
1678 * @brief Get Stream 4 half transfer flag.
1679 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1680 * @param DMAx DMAx Instance
1681 * @retval State of bit (1 or 0).
1682 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1683 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1684 {
1685 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1686 }
1687
1688 /**
1689 * @brief Get Stream 5 half transfer flag.
1690 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1691 * @param DMAx DMAx Instance
1692 * @retval State of bit (1 or 0).
1693 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1694 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1695 {
1696 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1697 }
1698
1699 /**
1700 * @brief Get Stream 6 half transfer flag.
1701 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1702 * @param DMAx DMAx Instance
1703 * @retval State of bit (1 or 0).
1704 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1705 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1706 {
1707 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1708 }
1709
1710 /**
1711 * @brief Get Stream 7 half transfer flag.
1712 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1713 * @param DMAx DMAx Instance
1714 * @retval State of bit (1 or 0).
1715 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1716 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1717 {
1718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1719 }
1720
1721 /**
1722 * @brief Get Stream 0 transfer complete flag.
1723 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1724 * @param DMAx DMAx Instance
1725 * @retval State of bit (1 or 0).
1726 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)1727 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1728 {
1729 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1730 }
1731
1732 /**
1733 * @brief Get Stream 1 transfer complete flag.
1734 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1735 * @param DMAx DMAx Instance
1736 * @retval State of bit (1 or 0).
1737 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1738 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1739 {
1740 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1741 }
1742
1743 /**
1744 * @brief Get Stream 2 transfer complete flag.
1745 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1746 * @param DMAx DMAx Instance
1747 * @retval State of bit (1 or 0).
1748 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1749 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1750 {
1751 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1752 }
1753
1754 /**
1755 * @brief Get Stream 3 transfer complete flag.
1756 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1757 * @param DMAx DMAx Instance
1758 * @retval State of bit (1 or 0).
1759 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1760 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1761 {
1762 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1763 }
1764
1765 /**
1766 * @brief Get Stream 4 transfer complete flag.
1767 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1768 * @param DMAx DMAx Instance
1769 * @retval State of bit (1 or 0).
1770 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1771 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1772 {
1773 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1774 }
1775
1776 /**
1777 * @brief Get Stream 5 transfer complete flag.
1778 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1779 * @param DMAx DMAx Instance
1780 * @retval State of bit (1 or 0).
1781 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1782 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1783 {
1784 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1785 }
1786
1787 /**
1788 * @brief Get Stream 6 transfer complete flag.
1789 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1790 * @param DMAx DMAx Instance
1791 * @retval State of bit (1 or 0).
1792 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1793 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1794 {
1795 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1796 }
1797
1798 /**
1799 * @brief Get Stream 7 transfer complete flag.
1800 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1801 * @param DMAx DMAx Instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1804 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1805 {
1806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1807 }
1808
1809 /**
1810 * @brief Get Stream 0 transfer error flag.
1811 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1812 * @param DMAx DMAx Instance
1813 * @retval State of bit (1 or 0).
1814 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)1815 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1816 {
1817 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1818 }
1819
1820 /**
1821 * @brief Get Stream 1 transfer error flag.
1822 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1823 * @param DMAx DMAx Instance
1824 * @retval State of bit (1 or 0).
1825 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1826 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1827 {
1828 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1829 }
1830
1831 /**
1832 * @brief Get Stream 2 transfer error flag.
1833 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1834 * @param DMAx DMAx Instance
1835 * @retval State of bit (1 or 0).
1836 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1837 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1838 {
1839 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1840 }
1841
1842 /**
1843 * @brief Get Stream 3 transfer error flag.
1844 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1845 * @param DMAx DMAx Instance
1846 * @retval State of bit (1 or 0).
1847 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1848 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1849 {
1850 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1851 }
1852
1853 /**
1854 * @brief Get Stream 4 transfer error flag.
1855 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1856 * @param DMAx DMAx Instance
1857 * @retval State of bit (1 or 0).
1858 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1859 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1860 {
1861 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1862 }
1863
1864 /**
1865 * @brief Get Stream 5 transfer error flag.
1866 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1867 * @param DMAx DMAx Instance
1868 * @retval State of bit (1 or 0).
1869 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1870 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1871 {
1872 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1873 }
1874
1875 /**
1876 * @brief Get Stream 6 transfer error flag.
1877 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1878 * @param DMAx DMAx Instance
1879 * @retval State of bit (1 or 0).
1880 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1881 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1882 {
1883 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1884 }
1885
1886 /**
1887 * @brief Get Stream 7 transfer error flag.
1888 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1889 * @param DMAx DMAx Instance
1890 * @retval State of bit (1 or 0).
1891 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1892 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1893 {
1894 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1895 }
1896
1897 /**
1898 * @brief Get Stream 0 direct mode error flag.
1899 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1900 * @param DMAx DMAx Instance
1901 * @retval State of bit (1 or 0).
1902 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)1903 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1904 {
1905 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1906 }
1907
1908 /**
1909 * @brief Get Stream 1 direct mode error flag.
1910 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1911 * @param DMAx DMAx Instance
1912 * @retval State of bit (1 or 0).
1913 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)1914 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1915 {
1916 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1917 }
1918
1919 /**
1920 * @brief Get Stream 2 direct mode error flag.
1921 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1922 * @param DMAx DMAx Instance
1923 * @retval State of bit (1 or 0).
1924 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)1925 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1926 {
1927 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1928 }
1929
1930 /**
1931 * @brief Get Stream 3 direct mode error flag.
1932 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1933 * @param DMAx DMAx Instance
1934 * @retval State of bit (1 or 0).
1935 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)1936 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1937 {
1938 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1939 }
1940
1941 /**
1942 * @brief Get Stream 4 direct mode error flag.
1943 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1944 * @param DMAx DMAx Instance
1945 * @retval State of bit (1 or 0).
1946 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)1947 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
1948 {
1949 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
1950 }
1951
1952 /**
1953 * @brief Get Stream 5 direct mode error flag.
1954 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
1955 * @param DMAx DMAx Instance
1956 * @retval State of bit (1 or 0).
1957 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)1958 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
1959 {
1960 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
1961 }
1962
1963 /**
1964 * @brief Get Stream 6 direct mode error flag.
1965 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
1966 * @param DMAx DMAx Instance
1967 * @retval State of bit (1 or 0).
1968 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)1969 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
1970 {
1971 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
1972 }
1973
1974 /**
1975 * @brief Get Stream 7 direct mode error flag.
1976 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
1977 * @param DMAx DMAx Instance
1978 * @retval State of bit (1 or 0).
1979 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)1980 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
1981 {
1982 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
1983 }
1984
1985 /**
1986 * @brief Get Stream 0 FIFO error flag.
1987 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
1988 * @param DMAx DMAx Instance
1989 * @retval State of bit (1 or 0).
1990 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)1991 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
1992 {
1993 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
1994 }
1995
1996 /**
1997 * @brief Get Stream 1 FIFO error flag.
1998 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
1999 * @param DMAx DMAx Instance
2000 * @retval State of bit (1 or 0).
2001 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2002 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2003 {
2004 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2005 }
2006
2007 /**
2008 * @brief Get Stream 2 FIFO error flag.
2009 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2010 * @param DMAx DMAx Instance
2011 * @retval State of bit (1 or 0).
2012 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2013 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2014 {
2015 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2016 }
2017
2018 /**
2019 * @brief Get Stream 3 FIFO error flag.
2020 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2021 * @param DMAx DMAx Instance
2022 * @retval State of bit (1 or 0).
2023 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2024 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2025 {
2026 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2027 }
2028
2029 /**
2030 * @brief Get Stream 4 FIFO error flag.
2031 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2032 * @param DMAx DMAx Instance
2033 * @retval State of bit (1 or 0).
2034 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2035 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2036 {
2037 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2038 }
2039
2040 /**
2041 * @brief Get Stream 5 FIFO error flag.
2042 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2043 * @param DMAx DMAx Instance
2044 * @retval State of bit (1 or 0).
2045 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2046 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2047 {
2048 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2049 }
2050
2051 /**
2052 * @brief Get Stream 6 FIFO error flag.
2053 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2054 * @param DMAx DMAx Instance
2055 * @retval State of bit (1 or 0).
2056 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2057 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2058 {
2059 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2060 }
2061
2062 /**
2063 * @brief Get Stream 7 FIFO error flag.
2064 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2065 * @param DMAx DMAx Instance
2066 * @retval State of bit (1 or 0).
2067 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2068 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2069 {
2070 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2071 }
2072
2073 /**
2074 * @brief Clear Stream 0 half transfer flag.
2075 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2076 * @param DMAx DMAx Instance
2077 * @retval None
2078 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2079 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2080 {
2081 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2082 }
2083
2084 /**
2085 * @brief Clear Stream 1 half transfer flag.
2086 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2087 * @param DMAx DMAx Instance
2088 * @retval None
2089 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2090 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2091 {
2092 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2093 }
2094
2095 /**
2096 * @brief Clear Stream 2 half transfer flag.
2097 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2098 * @param DMAx DMAx Instance
2099 * @retval None
2100 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2101 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2102 {
2103 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2104 }
2105
2106 /**
2107 * @brief Clear Stream 3 half transfer flag.
2108 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2109 * @param DMAx DMAx Instance
2110 * @retval None
2111 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2112 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2113 {
2114 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2115 }
2116
2117 /**
2118 * @brief Clear Stream 4 half transfer flag.
2119 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2120 * @param DMAx DMAx Instance
2121 * @retval None
2122 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2123 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2124 {
2125 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2126 }
2127
2128 /**
2129 * @brief Clear Stream 5 half transfer flag.
2130 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2131 * @param DMAx DMAx Instance
2132 * @retval None
2133 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2134 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2135 {
2136 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2137 }
2138
2139 /**
2140 * @brief Clear Stream 6 half transfer flag.
2141 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2142 * @param DMAx DMAx Instance
2143 * @retval None
2144 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2145 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2146 {
2147 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2148 }
2149
2150 /**
2151 * @brief Clear Stream 7 half transfer flag.
2152 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2153 * @param DMAx DMAx Instance
2154 * @retval None
2155 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2156 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2157 {
2158 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2159 }
2160
2161 /**
2162 * @brief Clear Stream 0 transfer complete flag.
2163 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2164 * @param DMAx DMAx Instance
2165 * @retval None
2166 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2167 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2168 {
2169 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2170 }
2171
2172 /**
2173 * @brief Clear Stream 1 transfer complete flag.
2174 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2175 * @param DMAx DMAx Instance
2176 * @retval None
2177 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2178 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2179 {
2180 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2181 }
2182
2183 /**
2184 * @brief Clear Stream 2 transfer complete flag.
2185 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2186 * @param DMAx DMAx Instance
2187 * @retval None
2188 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2189 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2190 {
2191 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2192 }
2193
2194 /**
2195 * @brief Clear Stream 3 transfer complete flag.
2196 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2197 * @param DMAx DMAx Instance
2198 * @retval None
2199 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2200 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2201 {
2202 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2203 }
2204
2205 /**
2206 * @brief Clear Stream 4 transfer complete flag.
2207 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2208 * @param DMAx DMAx Instance
2209 * @retval None
2210 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2211 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2212 {
2213 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2214 }
2215
2216 /**
2217 * @brief Clear Stream 5 transfer complete flag.
2218 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2219 * @param DMAx DMAx Instance
2220 * @retval None
2221 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2222 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2223 {
2224 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2225 }
2226
2227 /**
2228 * @brief Clear Stream 6 transfer complete flag.
2229 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2230 * @param DMAx DMAx Instance
2231 * @retval None
2232 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2233 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2234 {
2235 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2236 }
2237
2238 /**
2239 * @brief Clear Stream 7 transfer complete flag.
2240 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2241 * @param DMAx DMAx Instance
2242 * @retval None
2243 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2244 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2245 {
2246 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2247 }
2248
2249 /**
2250 * @brief Clear Stream 0 transfer error flag.
2251 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2252 * @param DMAx DMAx Instance
2253 * @retval None
2254 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2255 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2256 {
2257 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2258 }
2259
2260 /**
2261 * @brief Clear Stream 1 transfer error flag.
2262 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2263 * @param DMAx DMAx Instance
2264 * @retval None
2265 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2266 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2267 {
2268 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2269 }
2270
2271 /**
2272 * @brief Clear Stream 2 transfer error flag.
2273 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2274 * @param DMAx DMAx Instance
2275 * @retval None
2276 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2277 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2278 {
2279 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2280 }
2281
2282 /**
2283 * @brief Clear Stream 3 transfer error flag.
2284 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2285 * @param DMAx DMAx Instance
2286 * @retval None
2287 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2288 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2289 {
2290 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2291 }
2292
2293 /**
2294 * @brief Clear Stream 4 transfer error flag.
2295 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2296 * @param DMAx DMAx Instance
2297 * @retval None
2298 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2299 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2300 {
2301 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2302 }
2303
2304 /**
2305 * @brief Clear Stream 5 transfer error flag.
2306 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2307 * @param DMAx DMAx Instance
2308 * @retval None
2309 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2310 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2311 {
2312 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2313 }
2314
2315 /**
2316 * @brief Clear Stream 6 transfer error flag.
2317 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2318 * @param DMAx DMAx Instance
2319 * @retval None
2320 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2321 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2322 {
2323 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2324 }
2325
2326 /**
2327 * @brief Clear Stream 7 transfer error flag.
2328 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2329 * @param DMAx DMAx Instance
2330 * @retval None
2331 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2332 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2333 {
2334 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2335 }
2336
2337 /**
2338 * @brief Clear Stream 0 direct mode error flag.
2339 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2340 * @param DMAx DMAx Instance
2341 * @retval None
2342 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2343 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2344 {
2345 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2346 }
2347
2348 /**
2349 * @brief Clear Stream 1 direct mode error flag.
2350 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2351 * @param DMAx DMAx Instance
2352 * @retval None
2353 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2354 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2355 {
2356 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2357 }
2358
2359 /**
2360 * @brief Clear Stream 2 direct mode error flag.
2361 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2362 * @param DMAx DMAx Instance
2363 * @retval None
2364 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2365 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2366 {
2367 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2368 }
2369
2370 /**
2371 * @brief Clear Stream 3 direct mode error flag.
2372 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2373 * @param DMAx DMAx Instance
2374 * @retval None
2375 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2376 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2377 {
2378 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2379 }
2380
2381 /**
2382 * @brief Clear Stream 4 direct mode error flag.
2383 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2384 * @param DMAx DMAx Instance
2385 * @retval None
2386 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2387 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2388 {
2389 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2390 }
2391
2392 /**
2393 * @brief Clear Stream 5 direct mode error flag.
2394 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2395 * @param DMAx DMAx Instance
2396 * @retval None
2397 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2398 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2399 {
2400 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2401 }
2402
2403 /**
2404 * @brief Clear Stream 6 direct mode error flag.
2405 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2406 * @param DMAx DMAx Instance
2407 * @retval None
2408 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2409 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2410 {
2411 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2412 }
2413
2414 /**
2415 * @brief Clear Stream 7 direct mode error flag.
2416 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2417 * @param DMAx DMAx Instance
2418 * @retval None
2419 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2420 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2421 {
2422 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2423 }
2424
2425 /**
2426 * @brief Clear Stream 0 FIFO error flag.
2427 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2428 * @param DMAx DMAx Instance
2429 * @retval None
2430 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2431 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2432 {
2433 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2434 }
2435
2436 /**
2437 * @brief Clear Stream 1 FIFO error flag.
2438 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2439 * @param DMAx DMAx Instance
2440 * @retval None
2441 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2442 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2443 {
2444 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2445 }
2446
2447 /**
2448 * @brief Clear Stream 2 FIFO error flag.
2449 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2450 * @param DMAx DMAx Instance
2451 * @retval None
2452 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2453 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2454 {
2455 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2456 }
2457
2458 /**
2459 * @brief Clear Stream 3 FIFO error flag.
2460 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2461 * @param DMAx DMAx Instance
2462 * @retval None
2463 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2464 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2465 {
2466 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2467 }
2468
2469 /**
2470 * @brief Clear Stream 4 FIFO error flag.
2471 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2472 * @param DMAx DMAx Instance
2473 * @retval None
2474 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2475 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2476 {
2477 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2478 }
2479
2480 /**
2481 * @brief Clear Stream 5 FIFO error flag.
2482 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2483 * @param DMAx DMAx Instance
2484 * @retval None
2485 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2486 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2487 {
2488 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2489 }
2490
2491 /**
2492 * @brief Clear Stream 6 FIFO error flag.
2493 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2494 * @param DMAx DMAx Instance
2495 * @retval None
2496 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2497 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2498 {
2499 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2500 }
2501
2502 /**
2503 * @brief Clear Stream 7 FIFO error flag.
2504 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2505 * @param DMAx DMAx Instance
2506 * @retval None
2507 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2508 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2509 {
2510 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2511 }
2512
2513 /**
2514 * @}
2515 */
2516
2517 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2518 * @{
2519 */
2520
2521 /**
2522 * @brief Enable Half transfer interrupt.
2523 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2524 * @param DMAx DMAx Instance
2525 * @param Stream This parameter can be one of the following values:
2526 * @arg @ref LL_DMA_STREAM_0
2527 * @arg @ref LL_DMA_STREAM_1
2528 * @arg @ref LL_DMA_STREAM_2
2529 * @arg @ref LL_DMA_STREAM_3
2530 * @arg @ref LL_DMA_STREAM_4
2531 * @arg @ref LL_DMA_STREAM_5
2532 * @arg @ref LL_DMA_STREAM_6
2533 * @arg @ref LL_DMA_STREAM_7
2534 * @retval None
2535 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2536 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2537 {
2538 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2539 }
2540
2541 /**
2542 * @brief Enable Transfer error interrupt.
2543 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2544 * @param DMAx DMAx Instance
2545 * @param Stream This parameter can be one of the following values:
2546 * @arg @ref LL_DMA_STREAM_0
2547 * @arg @ref LL_DMA_STREAM_1
2548 * @arg @ref LL_DMA_STREAM_2
2549 * @arg @ref LL_DMA_STREAM_3
2550 * @arg @ref LL_DMA_STREAM_4
2551 * @arg @ref LL_DMA_STREAM_5
2552 * @arg @ref LL_DMA_STREAM_6
2553 * @arg @ref LL_DMA_STREAM_7
2554 * @retval None
2555 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2556 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2557 {
2558 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2559 }
2560
2561 /**
2562 * @brief Enable Transfer complete interrupt.
2563 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2564 * @param DMAx DMAx Instance
2565 * @param Stream This parameter can be one of the following values:
2566 * @arg @ref LL_DMA_STREAM_0
2567 * @arg @ref LL_DMA_STREAM_1
2568 * @arg @ref LL_DMA_STREAM_2
2569 * @arg @ref LL_DMA_STREAM_3
2570 * @arg @ref LL_DMA_STREAM_4
2571 * @arg @ref LL_DMA_STREAM_5
2572 * @arg @ref LL_DMA_STREAM_6
2573 * @arg @ref LL_DMA_STREAM_7
2574 * @retval None
2575 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2576 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2577 {
2578 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2579 }
2580
2581 /**
2582 * @brief Enable Direct mode error interrupt.
2583 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2584 * @param DMAx DMAx Instance
2585 * @param Stream This parameter can be one of the following values:
2586 * @arg @ref LL_DMA_STREAM_0
2587 * @arg @ref LL_DMA_STREAM_1
2588 * @arg @ref LL_DMA_STREAM_2
2589 * @arg @ref LL_DMA_STREAM_3
2590 * @arg @ref LL_DMA_STREAM_4
2591 * @arg @ref LL_DMA_STREAM_5
2592 * @arg @ref LL_DMA_STREAM_6
2593 * @arg @ref LL_DMA_STREAM_7
2594 * @retval None
2595 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2596 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2597 {
2598 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2599 }
2600
2601 /**
2602 * @brief Enable FIFO error interrupt.
2603 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2604 * @param DMAx DMAx Instance
2605 * @param Stream This parameter can be one of the following values:
2606 * @arg @ref LL_DMA_STREAM_0
2607 * @arg @ref LL_DMA_STREAM_1
2608 * @arg @ref LL_DMA_STREAM_2
2609 * @arg @ref LL_DMA_STREAM_3
2610 * @arg @ref LL_DMA_STREAM_4
2611 * @arg @ref LL_DMA_STREAM_5
2612 * @arg @ref LL_DMA_STREAM_6
2613 * @arg @ref LL_DMA_STREAM_7
2614 * @retval None
2615 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2616 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2617 {
2618 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2619 }
2620
2621 /**
2622 * @brief Disable Half transfer interrupt.
2623 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2624 * @param DMAx DMAx Instance
2625 * @param Stream This parameter can be one of the following values:
2626 * @arg @ref LL_DMA_STREAM_0
2627 * @arg @ref LL_DMA_STREAM_1
2628 * @arg @ref LL_DMA_STREAM_2
2629 * @arg @ref LL_DMA_STREAM_3
2630 * @arg @ref LL_DMA_STREAM_4
2631 * @arg @ref LL_DMA_STREAM_5
2632 * @arg @ref LL_DMA_STREAM_6
2633 * @arg @ref LL_DMA_STREAM_7
2634 * @retval None
2635 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2636 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2637 {
2638 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2639 }
2640
2641 /**
2642 * @brief Disable Transfer error interrupt.
2643 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2644 * @param DMAx DMAx Instance
2645 * @param Stream This parameter can be one of the following values:
2646 * @arg @ref LL_DMA_STREAM_0
2647 * @arg @ref LL_DMA_STREAM_1
2648 * @arg @ref LL_DMA_STREAM_2
2649 * @arg @ref LL_DMA_STREAM_3
2650 * @arg @ref LL_DMA_STREAM_4
2651 * @arg @ref LL_DMA_STREAM_5
2652 * @arg @ref LL_DMA_STREAM_6
2653 * @arg @ref LL_DMA_STREAM_7
2654 * @retval None
2655 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2656 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2657 {
2658 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2659 }
2660
2661 /**
2662 * @brief Disable Transfer complete interrupt.
2663 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2664 * @param DMAx DMAx Instance
2665 * @param Stream This parameter can be one of the following values:
2666 * @arg @ref LL_DMA_STREAM_0
2667 * @arg @ref LL_DMA_STREAM_1
2668 * @arg @ref LL_DMA_STREAM_2
2669 * @arg @ref LL_DMA_STREAM_3
2670 * @arg @ref LL_DMA_STREAM_4
2671 * @arg @ref LL_DMA_STREAM_5
2672 * @arg @ref LL_DMA_STREAM_6
2673 * @arg @ref LL_DMA_STREAM_7
2674 * @retval None
2675 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2676 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2677 {
2678 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2679 }
2680
2681 /**
2682 * @brief Disable Direct mode error interrupt.
2683 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2684 * @param DMAx DMAx Instance
2685 * @param Stream This parameter can be one of the following values:
2686 * @arg @ref LL_DMA_STREAM_0
2687 * @arg @ref LL_DMA_STREAM_1
2688 * @arg @ref LL_DMA_STREAM_2
2689 * @arg @ref LL_DMA_STREAM_3
2690 * @arg @ref LL_DMA_STREAM_4
2691 * @arg @ref LL_DMA_STREAM_5
2692 * @arg @ref LL_DMA_STREAM_6
2693 * @arg @ref LL_DMA_STREAM_7
2694 * @retval None
2695 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2696 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2697 {
2698 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2699 }
2700
2701 /**
2702 * @brief Disable FIFO error interrupt.
2703 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2704 * @param DMAx DMAx Instance
2705 * @param Stream This parameter can be one of the following values:
2706 * @arg @ref LL_DMA_STREAM_0
2707 * @arg @ref LL_DMA_STREAM_1
2708 * @arg @ref LL_DMA_STREAM_2
2709 * @arg @ref LL_DMA_STREAM_3
2710 * @arg @ref LL_DMA_STREAM_4
2711 * @arg @ref LL_DMA_STREAM_5
2712 * @arg @ref LL_DMA_STREAM_6
2713 * @arg @ref LL_DMA_STREAM_7
2714 * @retval None
2715 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2716 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2717 {
2718 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2719 }
2720
2721 /**
2722 * @brief Check if Half transfer interrupt is enabled.
2723 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2724 * @param DMAx DMAx Instance
2725 * @param Stream This parameter can be one of the following values:
2726 * @arg @ref LL_DMA_STREAM_0
2727 * @arg @ref LL_DMA_STREAM_1
2728 * @arg @ref LL_DMA_STREAM_2
2729 * @arg @ref LL_DMA_STREAM_3
2730 * @arg @ref LL_DMA_STREAM_4
2731 * @arg @ref LL_DMA_STREAM_5
2732 * @arg @ref LL_DMA_STREAM_6
2733 * @arg @ref LL_DMA_STREAM_7
2734 * @retval State of bit (1 or 0).
2735 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2736 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2737 {
2738 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2739 }
2740
2741 /**
2742 * @brief Check if Transfer error nterrup is enabled.
2743 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2744 * @param DMAx DMAx Instance
2745 * @param Stream This parameter can be one of the following values:
2746 * @arg @ref LL_DMA_STREAM_0
2747 * @arg @ref LL_DMA_STREAM_1
2748 * @arg @ref LL_DMA_STREAM_2
2749 * @arg @ref LL_DMA_STREAM_3
2750 * @arg @ref LL_DMA_STREAM_4
2751 * @arg @ref LL_DMA_STREAM_5
2752 * @arg @ref LL_DMA_STREAM_6
2753 * @arg @ref LL_DMA_STREAM_7
2754 * @retval State of bit (1 or 0).
2755 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2756 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2757 {
2758 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2759 }
2760
2761 /**
2762 * @brief Check if Transfer complete interrupt is enabled.
2763 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2764 * @param DMAx DMAx Instance
2765 * @param Stream This parameter can be one of the following values:
2766 * @arg @ref LL_DMA_STREAM_0
2767 * @arg @ref LL_DMA_STREAM_1
2768 * @arg @ref LL_DMA_STREAM_2
2769 * @arg @ref LL_DMA_STREAM_3
2770 * @arg @ref LL_DMA_STREAM_4
2771 * @arg @ref LL_DMA_STREAM_5
2772 * @arg @ref LL_DMA_STREAM_6
2773 * @arg @ref LL_DMA_STREAM_7
2774 * @retval State of bit (1 or 0).
2775 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2776 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2777 {
2778 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2779 }
2780
2781 /**
2782 * @brief Check if Direct mode error interrupt is enabled.
2783 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2784 * @param DMAx DMAx Instance
2785 * @param Stream This parameter can be one of the following values:
2786 * @arg @ref LL_DMA_STREAM_0
2787 * @arg @ref LL_DMA_STREAM_1
2788 * @arg @ref LL_DMA_STREAM_2
2789 * @arg @ref LL_DMA_STREAM_3
2790 * @arg @ref LL_DMA_STREAM_4
2791 * @arg @ref LL_DMA_STREAM_5
2792 * @arg @ref LL_DMA_STREAM_6
2793 * @arg @ref LL_DMA_STREAM_7
2794 * @retval State of bit (1 or 0).
2795 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2796 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2797 {
2798 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2799 }
2800
2801 /**
2802 * @brief Check if FIFO error interrupt is enabled.
2803 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2804 * @param DMAx DMAx Instance
2805 * @param Stream This parameter can be one of the following values:
2806 * @arg @ref LL_DMA_STREAM_0
2807 * @arg @ref LL_DMA_STREAM_1
2808 * @arg @ref LL_DMA_STREAM_2
2809 * @arg @ref LL_DMA_STREAM_3
2810 * @arg @ref LL_DMA_STREAM_4
2811 * @arg @ref LL_DMA_STREAM_5
2812 * @arg @ref LL_DMA_STREAM_6
2813 * @arg @ref LL_DMA_STREAM_7
2814 * @retval State of bit (1 or 0).
2815 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2816 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2817 {
2818 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2819 }
2820
2821 /**
2822 * @}
2823 */
2824
2825 #if defined(USE_FULL_LL_DRIVER)
2826 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2827 * @{
2828 */
2829
2830 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2831 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2832 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2833
2834 /**
2835 * @}
2836 */
2837 #endif /* USE_FULL_LL_DRIVER */
2838
2839 /**
2840 * @}
2841 */
2842
2843 /**
2844 * @}
2845 */
2846
2847 #endif /* DMA1 || DMA2 */
2848
2849 /**
2850 * @}
2851 */
2852
2853 #ifdef __cplusplus
2854 }
2855 #endif
2856
2857 #endif /* __STM32F2xx_LL_DMA_H */
2858
2859
