1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F2xx_HAL_RCC_EX_H 20 #define __STM32F2xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f2xx_hal_def.h" 28 29 /** @addtogroup STM32F2xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 39 * @{ 40 */ 41 /** 42 * @brief PLLI2S Clock structure definition 43 */ 44 typedef struct 45 { 46 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 47 This parameter must be a number between Min_Data = 192 and Max_Data = 432. 48 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 49 50 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 51 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 52 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 53 54 }RCC_PLLI2SInitTypeDef; 55 56 /** 57 * @brief RCC extended clocks structure definition 58 */ 59 typedef struct 60 { 61 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 62 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 63 64 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 65 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 66 67 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 68 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 69 70 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 71 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 72 73 }RCC_PeriphCLKInitTypeDef; 74 /** 75 * @} 76 */ 77 78 /* Exported constants --------------------------------------------------------*/ 79 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 80 * @{ 81 */ 82 83 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 84 * @{ 85 */ 86 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) 87 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002) 88 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004) 89 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008) 90 91 /** 92 * @} 93 */ 94 95 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 96 * @{ 97 */ 98 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 99 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 100 /** 101 * @} 102 */ 103 104 /** 105 * @} 106 */ 107 108 /* Exported macro ------------------------------------------------------------*/ 109 /** @defgroup RCCEx_Exported_Macros RCC Exported Macros 110 * @{ 111 */ 112 113 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 114 * @brief Enables or disables the AHB1 peripheral clock. 115 * @note After reset, the peripheral clock (used for registers read/write access) 116 * is disabled and the application software has to enable this clock before 117 * using it. 118 * @{ 119 */ 120 #if defined(STM32F207xx) || defined(STM32F217xx) 121 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 122 __IO uint32_t tmpreg = 0x00; \ 123 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 124 /* Delay after an RCC peripheral clock enabling */ \ 125 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 126 UNUSED(tmpreg); \ 127 } while(0) 128 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 129 __IO uint32_t tmpreg = 0x00; \ 130 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 131 /* Delay after an RCC peripheral clock enabling */ \ 132 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 133 UNUSED(tmpreg); \ 134 } while(0) 135 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 136 __IO uint32_t tmpreg = 0x00; \ 137 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 138 /* Delay after an RCC peripheral clock enabling */ \ 139 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 140 UNUSED(tmpreg); \ 141 } while(0) 142 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 143 __IO uint32_t tmpreg = 0x00; \ 144 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 145 /* Delay after an RCC peripheral clock enabling */ \ 146 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 147 UNUSED(tmpreg); \ 148 } while(0) 149 150 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 151 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 152 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 153 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 154 155 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 156 * @brief Get the enable or disable status of the AHB1 peripheral clock. 157 * @note After reset, the peripheral clock (used for registers read/write access) 158 * is disabled and the application software has to enable this clock before 159 * using it. 160 * @{ 161 */ 162 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET) 163 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET) 164 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET) 165 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET) 166 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 167 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 168 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 169 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET) 170 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET) 171 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET) 172 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET) 173 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 174 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 175 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 176 /** 177 * @} 178 */ 179 180 /** 181 * @brief Enable ETHERNET clock. 182 */ 183 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 184 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 185 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 186 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 187 } while(0) 188 /** 189 * @brief Disable ETHERNET clock. 190 */ 191 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 192 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 193 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 194 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 195 } while(0) 196 #endif /* STM32F207xx || STM32F217xx */ 197 /** 198 * @} 199 */ 200 201 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 202 * @brief Enable or disable the AHB2 peripheral clock. 203 * @note After reset, the peripheral clock (used for registers read/write access) 204 * is disabled and the application software has to enable this clock before 205 * using it. 206 * @{ 207 */ 208 #if defined(STM32F207xx) || defined(STM32F217xx) 209 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 210 __IO uint32_t tmpreg = 0x00; \ 211 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 212 /* Delay after an RCC peripheral clock enabling */ \ 213 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 214 UNUSED(tmpreg); \ 215 } while(0) 216 217 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 218 #endif /* STM32F207xx || STM32F217xx */ 219 220 #if defined(STM32F215xx) || defined(STM32F217xx) 221 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 222 __IO uint32_t tmpreg = 0x00; \ 223 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 224 /* Delay after an RCC peripheral clock enabling */ \ 225 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 226 UNUSED(tmpreg); \ 227 } while(0) 228 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 229 __IO uint32_t tmpreg = 0x00; \ 230 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 231 /* Delay after an RCC peripheral clock enabling */ \ 232 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 233 UNUSED(tmpreg); \ 234 } while(0) 235 236 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 237 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 238 #endif /* STM32F215xx || STM32F217xx */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 244 * @brief Get the enable or disable status of the AHB2 peripheral clock. 245 * @note After reset, the peripheral clock (used for registers read/write access) 246 * is disabled and the application software has to enable this clock before 247 * using it. 248 * @{ 249 */ 250 #if defined(STM32F207xx) || defined(STM32F217xx) 251 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET) 252 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET) 253 #endif /* defined(STM32F207xx) || defined(STM32F217xx) */ 254 #if defined(STM32F215xx) || defined(STM32F217xx) 255 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET) 256 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET) 257 258 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET) 259 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET) 260 #endif /* defined(STM32F215xx) || defined(STM32F217xx) */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 266 * @brief Force or release AHB1 peripheral reset. 267 * @{ 268 */ 269 #if defined(STM32F207xx) || defined(STM32F217xx) 270 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 271 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 272 #endif /* STM32F207xx || STM32F217xx */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 278 * @brief Force or release AHB2 peripheral reset. 279 * @{ 280 */ 281 #if defined(STM32F207xx) || defined(STM32F217xx) 282 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 283 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 284 #endif /* STM32F207xx || STM32F217xx */ 285 286 #if defined(STM32F215xx) || defined(STM32F217xx) 287 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 288 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 289 290 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 291 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 292 #endif /* STM32F215xx || STM32F217xx */ 293 294 /** 295 * @} 296 */ 297 298 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 299 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 300 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 301 * power consumption. 302 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 303 * @note By default, all peripheral clocks are enabled during SLEEP mode. 304 * @{ 305 */ 306 #if defined(STM32F207xx) || defined(STM32F217xx) 307 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 308 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 309 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 310 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 311 312 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 313 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 314 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 315 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 316 #endif /* STM32F207xx || STM32F217xx */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 322 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 323 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 324 * power consumption. 325 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 326 * @note By default, all peripheral clocks are enabled during SLEEP mode. 327 * @{ 328 */ 329 #if defined(STM32F207xx) || defined(STM32F217xx) 330 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 331 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 332 #endif /* STM32F207xx || STM32F217xx */ 333 334 #if defined(STM32F215xx) || defined(STM32F217xx) 335 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 336 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 337 338 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 339 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 340 #endif /* STM32F215xx || STM32F217xx */ 341 /** 342 * @} 343 */ 344 345 /** 346 * @} 347 */ 348 349 /* Exported functions --------------------------------------------------------*/ 350 /** @addtogroup RCCEx_Exported_Functions 351 * @{ 352 */ 353 354 /** @addtogroup RCCEx_Exported_Functions_Group1 355 * @{ 356 */ 357 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 358 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 359 360 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 361 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 362 /** 363 * @} 364 */ 365 366 /** 367 * @} 368 */ 369 /* Private types -------------------------------------------------------------*/ 370 /* Private variables ---------------------------------------------------------*/ 371 /* Private constants ---------------------------------------------------------*/ 372 /** @defgroup RCCEx_Private_Constants RCC Private Constants 373 * @{ 374 */ 375 376 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 377 * @brief RCC registers bit address in the alias region 378 * @{ 379 */ 380 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ 381 /** 382 * @} 383 */ 384 385 /** 386 * @} 387 */ 388 389 /* Private macros ------------------------------------------------------------*/ 390 /** @defgroup RCCEx_Private_Macros RCC Private Macros 391 * @{ 392 */ 393 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 394 * @{ 395 */ 396 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F)) 397 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) 398 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 399 /** 400 * @} 401 */ 402 403 /** 404 * @} 405 */ 406 407 /** 408 * @} 409 */ 410 411 /** 412 * @} 413 */ 414 #ifdef __cplusplus 415 } 416 #endif 417 418 #endif /* __STM32F2xx_HAL_RCC_EX_H */ 419 420
