1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F2xx_HAL_ETH_H 21 #define __STM32F2xx_HAL_ETH_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 #if defined (ETH) 31 32 /** @addtogroup STM32F2xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup ETH 37 * @{ 38 */ 39 40 /** @defgroup ETH_Private_Macros ETH Private Macros 41 * @{ 42 */ 43 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 44 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 45 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 46 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 47 ((SPEED) == ETH_SPEED_100M)) 48 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 49 ((MODE) == ETH_MODE_HALFDUPLEX)) 50 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 51 ((MODE) == ETH_RXINTERRUPT_MODE)) 52 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 53 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 54 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 55 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 56 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 57 ((CMD) == ETH_WATCHDOG_DISABLE)) 58 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 59 ((CMD) == ETH_JABBER_DISABLE)) 60 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 61 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 62 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 63 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 64 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 65 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 66 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 67 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 68 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 69 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 70 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 71 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 72 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 73 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 74 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 75 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 76 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 77 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 78 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 79 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 80 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 81 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 82 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 83 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 84 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 85 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 86 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 87 ((CMD) == ETH_RECEIVEAll_DISABLE)) 88 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 89 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 90 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 91 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 92 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 93 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 94 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 95 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 96 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 97 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 98 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 99 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 100 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 101 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 104 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 105 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 106 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 107 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 108 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 109 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 110 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 111 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 114 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 115 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 116 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 117 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 118 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 119 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 120 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 121 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 122 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 123 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 124 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 125 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 126 ((ADDRESS) == ETH_MAC_ADDRESS3)) 127 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 128 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 129 ((ADDRESS) == ETH_MAC_ADDRESS3)) 130 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 131 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 132 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 133 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 138 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 139 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 140 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 141 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 142 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 143 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 144 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 145 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 146 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 154 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 155 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 156 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 157 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 158 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 159 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 162 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 163 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 164 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 165 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 166 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 167 ((CMD) == ETH_FIXEDBURST_DISABLE)) 168 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 169 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 170 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 171 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 172 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 173 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 174 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 180 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 181 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 182 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 183 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 184 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 185 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 186 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 192 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) 193 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 194 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 197 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 198 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 199 ((FLAG) == ETH_DMATXDESC_IC) || \ 200 ((FLAG) == ETH_DMATXDESC_LS) || \ 201 ((FLAG) == ETH_DMATXDESC_FS) || \ 202 ((FLAG) == ETH_DMATXDESC_DC) || \ 203 ((FLAG) == ETH_DMATXDESC_DP) || \ 204 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 205 ((FLAG) == ETH_DMATXDESC_TER) || \ 206 ((FLAG) == ETH_DMATXDESC_TCH) || \ 207 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 208 ((FLAG) == ETH_DMATXDESC_IHE) || \ 209 ((FLAG) == ETH_DMATXDESC_ES) || \ 210 ((FLAG) == ETH_DMATXDESC_JT) || \ 211 ((FLAG) == ETH_DMATXDESC_FF) || \ 212 ((FLAG) == ETH_DMATXDESC_PCE) || \ 213 ((FLAG) == ETH_DMATXDESC_LCA) || \ 214 ((FLAG) == ETH_DMATXDESC_NC) || \ 215 ((FLAG) == ETH_DMATXDESC_LCO) || \ 216 ((FLAG) == ETH_DMATXDESC_EC) || \ 217 ((FLAG) == ETH_DMATXDESC_VF) || \ 218 ((FLAG) == ETH_DMATXDESC_CC) || \ 219 ((FLAG) == ETH_DMATXDESC_ED) || \ 220 ((FLAG) == ETH_DMATXDESC_UF) || \ 221 ((FLAG) == ETH_DMATXDESC_DB)) 222 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 223 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 224 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 225 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 228 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 229 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 230 ((FLAG) == ETH_DMARXDESC_AFM) || \ 231 ((FLAG) == ETH_DMARXDESC_ES) || \ 232 ((FLAG) == ETH_DMARXDESC_DE) || \ 233 ((FLAG) == ETH_DMARXDESC_SAF) || \ 234 ((FLAG) == ETH_DMARXDESC_LE) || \ 235 ((FLAG) == ETH_DMARXDESC_OE) || \ 236 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 237 ((FLAG) == ETH_DMARXDESC_FS) || \ 238 ((FLAG) == ETH_DMARXDESC_LS) || \ 239 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 240 ((FLAG) == ETH_DMARXDESC_LC) || \ 241 ((FLAG) == ETH_DMARXDESC_FT) || \ 242 ((FLAG) == ETH_DMARXDESC_RWT) || \ 243 ((FLAG) == ETH_DMARXDESC_RE) || \ 244 ((FLAG) == ETH_DMARXDESC_DBE) || \ 245 ((FLAG) == ETH_DMARXDESC_CE) || \ 246 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 247 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 248 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 249 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 250 ((FLAG) == ETH_PMT_FLAG_MPR)) 251 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 252 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 253 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 254 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 255 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 256 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 257 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 258 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 259 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 260 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 261 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 262 ((FLAG) == ETH_DMA_FLAG_T)) 263 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFD87U) == 0x00U) && ((IT) != 0x00U)) 264 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 265 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 266 ((IT) == ETH_MAC_IT_PMT)) 267 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 268 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 269 ((FLAG) == ETH_MAC_FLAG_PMT)) 270 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 271 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 272 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 273 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 274 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 275 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 276 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 277 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 278 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 279 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 280 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 281 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 282 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFF) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 283 ((IT) != 0x00U)) 284 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 285 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 286 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 287 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 288 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 289 290 291 /** 292 * @} 293 */ 294 295 /** @defgroup ETH_Private_Defines ETH Private Defines 296 * @{ 297 */ 298 /* Delay to wait when writing to some Ethernet registers */ 299 #define ETH_REG_WRITE_DELAY 0x00000001U 300 301 /* ETHERNET Errors */ 302 #define ETH_SUCCESS 0U 303 #define ETH_ERROR 1U 304 305 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 306 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 307 308 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 309 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 310 311 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 312 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 313 314 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 315 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 316 317 /* ETHERNET DMA Rx descriptors Frame length Shift */ 318 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 319 320 /* ETHERNET MAC address offsets */ 321 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 322 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 323 324 /* ETHERNET MACMIIAR register Mask */ 325 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 326 327 /* ETHERNET MACCR register Mask */ 328 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 329 330 /* ETHERNET MACFCR register Mask */ 331 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 332 333 /* ETHERNET DMAOMR register Mask */ 334 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 335 336 /* ETHERNET Remote Wake-up frame register length */ 337 #define ETH_WAKEUP_REGISTER_LENGTH 8U 338 339 /* ETHERNET Missed frames counter Shift */ 340 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 341 /** 342 * @} 343 */ 344 345 /* Exported types ------------------------------------------------------------*/ 346 /** @defgroup ETH_Exported_Types ETH Exported Types 347 * @{ 348 */ 349 350 /** 351 * @brief HAL State structures definition 352 */ 353 typedef enum 354 { 355 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 356 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 357 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 358 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 359 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 360 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 361 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 362 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 363 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 364 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 365 } HAL_ETH_StateTypeDef; 366 367 /** 368 * @brief ETH Init Structure definition 369 */ 370 371 typedef struct 372 { 373 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 374 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 375 and the mode (half/full-duplex). 376 This parameter can be a value of @ref ETH_AutoNegotiation */ 377 378 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 379 This parameter can be a value of @ref ETH_Speed */ 380 381 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 382 This parameter can be a value of @ref ETH_Duplex_Mode */ 383 384 uint16_t PhyAddress; /*!< Ethernet PHY address. 385 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 386 387 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 388 389 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 390 This parameter can be a value of @ref ETH_Rx_Mode */ 391 392 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 393 This parameter can be a value of @ref ETH_Checksum_Mode */ 394 395 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. 396 This parameter can be a value of @ref ETH_Media_Interface */ 397 398 } ETH_InitTypeDef; 399 400 401 /** 402 * @brief ETH MAC Configuration Structure definition 403 */ 404 405 typedef struct 406 { 407 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 408 When enabled, the MAC allows no more then 2048 bytes to be received. 409 When disabled, the MAC can receive up to 16384 bytes. 410 This parameter can be a value of @ref ETH_Watchdog */ 411 412 uint32_t Jabber; /*!< Selects or not Jabber timer 413 When enabled, the MAC allows no more then 2048 bytes to be sent. 414 When disabled, the MAC can send up to 16384 bytes. 415 This parameter can be a value of @ref ETH_Jabber */ 416 417 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 418 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 419 420 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 421 This parameter can be a value of @ref ETH_Carrier_Sense */ 422 423 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 424 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 425 in Half-Duplex mode. 426 This parameter can be a value of @ref ETH_Receive_Own */ 427 428 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 429 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 430 431 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 432 This parameter can be a value of @ref ETH_Checksum_Offload */ 433 434 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 435 when a collision occurs (Half-Duplex mode). 436 This parameter can be a value of @ref ETH_Retry_Transmission */ 437 438 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 439 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 440 441 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 442 This parameter can be a value of @ref ETH_Back_Off_Limit */ 443 444 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 445 This parameter can be a value of @ref ETH_Deferral_Check */ 446 447 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 448 This parameter can be a value of @ref ETH_Receive_All */ 449 450 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 451 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 452 453 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 454 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 455 456 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 457 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 458 459 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 460 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 461 462 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 463 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 464 465 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 466 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 467 468 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 469 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 470 471 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 473 474 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ 476 477 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 478 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 479 480 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 481 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 482 483 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 484 automatic retransmission of PAUSE Frame. 485 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 486 487 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 488 unicast address and unique multicast address). 489 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 490 491 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 492 disable its transmitter for a specified time (Pause Time) 493 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 494 495 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 496 or the MAC back-pressure operation (Half-Duplex mode) 497 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 498 499 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 500 comparison and filtering. 501 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 502 503 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 504 505 } ETH_MACInitTypeDef; 506 507 508 /** 509 * @brief ETH DMA Configuration Structure definition 510 */ 511 512 typedef struct 513 { 514 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 515 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 516 517 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 518 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 519 520 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 521 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 522 523 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 524 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 525 526 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 527 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 528 529 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 530 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 531 532 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 533 and length less than 64 bytes) including pad-bytes and CRC) 534 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 535 536 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 537 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 538 539 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 540 frame of Transmit data even before obtaining the status for the first frame. 541 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 542 543 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 544 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 545 546 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 547 This parameter can be a value of @ref ETH_Fixed_Burst */ 548 549 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 550 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 551 552 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 553 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 554 555 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 556 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 557 558 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 559 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 560 561 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 562 This parameter can be a value of @ref ETH_DMA_Arbitration */ 563 } ETH_DMAInitTypeDef; 564 565 566 /** 567 * @brief ETH DMA Descriptors data structure definition 568 */ 569 570 typedef struct 571 { 572 __IO uint32_t Status; /*!< Status */ 573 574 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 575 576 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 577 578 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 579 580 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 581 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 582 583 uint32_t Reserved1; /*!< Reserved */ 584 585 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 586 587 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 588 589 } ETH_DMADescTypeDef; 590 591 592 /** 593 * @brief Received Frame Information structure definition 594 */ 595 typedef struct 596 { 597 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 598 599 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 600 601 uint32_t SegCount; /*!< Segment count */ 602 603 uint32_t length; /*!< Frame length */ 604 605 uint32_t buffer; /*!< Frame buffer */ 606 607 } ETH_DMARxFrameInfos; 608 609 610 /** 611 * @brief ETH Handle Structure definition 612 */ 613 614 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 615 typedef struct __ETH_HandleTypeDef 616 #else 617 typedef struct 618 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 619 { 620 ETH_TypeDef *Instance; /*!< Register base address */ 621 622 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 623 624 uint32_t LinkStatus; /*!< Ethernet link status */ 625 626 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 627 628 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 629 630 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 631 632 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 633 634 HAL_LockTypeDef Lock; /*!< ETH Lock */ 635 636 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 637 638 void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ 639 void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ 640 void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */ 641 void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ 642 void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ 643 644 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 645 646 } ETH_HandleTypeDef; 647 648 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 649 /** 650 * @brief HAL ETH Callback ID enumeration definition 651 */ 652 typedef enum 653 { 654 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 655 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 656 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 657 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 658 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 659 660 } HAL_ETH_CallbackIDTypeDef; 661 662 /** 663 * @brief HAL ETH Callback pointer definition 664 */ 665 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ 666 667 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 668 669 /** 670 * @} 671 */ 672 673 /* Exported constants --------------------------------------------------------*/ 674 /** @defgroup ETH_Exported_Constants ETH Exported Constants 675 * @{ 676 */ 677 678 /** @defgroup ETH_Buffers_setting ETH Buffers setting 679 * @{ 680 */ 681 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 682 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 683 #define ETH_CRC 4U /*!< Ethernet CRC */ 684 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 685 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 686 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 687 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 688 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 689 690 /* Ethernet driver receive buffers are organized in a chained linked-list, when 691 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 692 to the driver receive buffers memory. 693 694 Depending on the size of the received ethernet packet and the size of 695 each ethernet driver receive buffer, the received packet can take one or more 696 ethernet driver receive buffer. 697 698 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 699 and the total count of the driver receive buffers ETH_RXBUFNB. 700 701 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 702 example, they can be reconfigured in the application layer to fit the application 703 needs */ 704 705 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 706 packet */ 707 #ifndef ETH_RX_BUF_SIZE 708 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 709 #endif 710 711 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 712 #ifndef ETH_RXBUFNB 713 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 714 #endif 715 716 717 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 718 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 719 driver transmit buffers memory to the TxFIFO. 720 721 Depending on the size of the Ethernet packet to be transmitted and the size of 722 each ethernet driver transmit buffer, the packet to be transmitted can take 723 one or more ethernet driver transmit buffer. 724 725 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 726 and the total count of the driver transmit buffers ETH_TXBUFNB. 727 728 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 729 example, they can be reconfigured in the application layer to fit the application 730 needs */ 731 732 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 733 packet */ 734 #ifndef ETH_TX_BUF_SIZE 735 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 736 #endif 737 738 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 739 #ifndef ETH_TXBUFNB 740 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 741 #endif 742 743 /** 744 * @} 745 */ 746 747 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 748 * @{ 749 */ 750 751 /* 752 DMA Tx Descriptor 753 ----------------------------------------------------------------------------------------------- 754 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 755 ----------------------------------------------------------------------------------------------- 756 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 757 ----------------------------------------------------------------------------------------------- 758 TDES2 | Buffer1 Address [31:0] | 759 ----------------------------------------------------------------------------------------------- 760 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 761 ----------------------------------------------------------------------------------------------- 762 */ 763 764 /** 765 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 766 */ 767 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 768 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 769 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 770 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 771 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 772 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 773 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 774 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 775 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 776 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 777 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 778 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 779 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 780 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 781 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 782 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 783 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 784 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 785 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 786 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 787 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 788 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 789 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 790 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 791 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 792 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 793 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 794 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 795 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 796 797 /** 798 * @brief Bit definition of TDES1 register 799 */ 800 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 801 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 802 803 /** 804 * @brief Bit definition of TDES2 register 805 */ 806 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 807 808 /** 809 * @brief Bit definition of TDES3 register 810 */ 811 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 812 813 /*--------------------------------------------------------------------------------------------- 814 TDES6 | Transmit Time Stamp Low [31:0] | 815 ----------------------------------------------------------------------------------------------- 816 TDES7 | Transmit Time Stamp High [31:0] | 817 ----------------------------------------------------------------------------------------------*/ 818 819 /* Bit definition of TDES6 register */ 820 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 821 822 /* Bit definition of TDES7 register */ 823 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 824 825 /** 826 * @} 827 */ 828 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 829 * @{ 830 */ 831 832 /* 833 DMA Rx Descriptor 834 -------------------------------------------------------------------------------------------------------------------- 835 RDES0 | OWN(31) | Status [30:0] | 836 --------------------------------------------------------------------------------------------------------------------- 837 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 838 --------------------------------------------------------------------------------------------------------------------- 839 RDES2 | Buffer1 Address [31:0] | 840 --------------------------------------------------------------------------------------------------------------------- 841 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 842 --------------------------------------------------------------------------------------------------------------------- 843 */ 844 845 /** 846 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 847 */ 848 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 849 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 850 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 851 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 852 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 853 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 854 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 855 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 856 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 857 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 858 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 859 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 860 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 861 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 862 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 863 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 864 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 865 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 866 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 867 868 /** 869 * @brief Bit definition of RDES1 register 870 */ 871 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 872 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 873 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 874 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 875 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 876 877 /** 878 * @brief Bit definition of RDES2 register 879 */ 880 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 881 882 /** 883 * @brief Bit definition of RDES3 register 884 */ 885 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 886 887 /*--------------------------------------------------------------------------------------------------------------------- 888 RDES4 | Reserved[31:15] | Extended Status [14:0] | 889 --------------------------------------------------------------------------------------------------------------------- 890 RDES5 | Reserved[31:0] | 891 --------------------------------------------------------------------------------------------------------------------- 892 RDES6 | Receive Time Stamp Low [31:0] | 893 --------------------------------------------------------------------------------------------------------------------- 894 RDES7 | Receive Time Stamp High [31:0] | 895 --------------------------------------------------------------------------------------------------------------------*/ 896 897 /* Bit definition of RDES4 register */ 898 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 899 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 900 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 901 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ 902 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ 903 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ 904 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ 905 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 906 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 907 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 908 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 909 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 910 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 911 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 912 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 913 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 914 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ 915 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ 916 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ 917 918 /* Bit definition of RDES6 register */ 919 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 920 921 /* Bit definition of RDES7 register */ 922 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 923 /** 924 * @} 925 */ 926 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 927 * @{ 928 */ 929 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 930 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 931 932 /** 933 * @} 934 */ 935 /** @defgroup ETH_Speed ETH Speed 936 * @{ 937 */ 938 #define ETH_SPEED_10M 0x00000000U 939 #define ETH_SPEED_100M 0x00004000U 940 941 /** 942 * @} 943 */ 944 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 945 * @{ 946 */ 947 #define ETH_MODE_FULLDUPLEX 0x00000800U 948 #define ETH_MODE_HALFDUPLEX 0x00000000U 949 /** 950 * @} 951 */ 952 /** @defgroup ETH_Rx_Mode ETH Rx Mode 953 * @{ 954 */ 955 #define ETH_RXPOLLING_MODE 0x00000000U 956 #define ETH_RXINTERRUPT_MODE 0x00000001U 957 /** 958 * @} 959 */ 960 961 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 962 * @{ 963 */ 964 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 965 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 966 /** 967 * @} 968 */ 969 970 /** @defgroup ETH_Media_Interface ETH Media Interface 971 * @{ 972 */ 973 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 974 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 975 /** 976 * @} 977 */ 978 979 /** @defgroup ETH_Watchdog ETH Watchdog 980 * @{ 981 */ 982 #define ETH_WATCHDOG_ENABLE 0x00000000U 983 #define ETH_WATCHDOG_DISABLE 0x00800000U 984 /** 985 * @} 986 */ 987 988 /** @defgroup ETH_Jabber ETH Jabber 989 * @{ 990 */ 991 #define ETH_JABBER_ENABLE 0x00000000U 992 #define ETH_JABBER_DISABLE 0x00400000U 993 /** 994 * @} 995 */ 996 997 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 998 * @{ 999 */ 1000 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 1001 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 1002 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 1003 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 1004 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 1005 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 1006 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 1007 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 1008 /** 1009 * @} 1010 */ 1011 1012 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 1013 * @{ 1014 */ 1015 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 1016 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 1017 /** 1018 * @} 1019 */ 1020 1021 /** @defgroup ETH_Receive_Own ETH Receive Own 1022 * @{ 1023 */ 1024 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 1025 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 1031 * @{ 1032 */ 1033 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 1034 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 1035 /** 1036 * @} 1037 */ 1038 1039 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 1040 * @{ 1041 */ 1042 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 1043 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 1044 /** 1045 * @} 1046 */ 1047 1048 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 1049 * @{ 1050 */ 1051 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 1052 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 1053 /** 1054 * @} 1055 */ 1056 1057 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 1058 * @{ 1059 */ 1060 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 1061 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 1062 /** 1063 * @} 1064 */ 1065 1066 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1067 * @{ 1068 */ 1069 #define ETH_BACKOFFLIMIT_10 0x00000000U 1070 #define ETH_BACKOFFLIMIT_8 0x00000020U 1071 #define ETH_BACKOFFLIMIT_4 0x00000040U 1072 #define ETH_BACKOFFLIMIT_1 0x00000060U 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup ETH_Deferral_Check ETH Deferral Check 1078 * @{ 1079 */ 1080 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 1081 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 1082 /** 1083 * @} 1084 */ 1085 1086 /** @defgroup ETH_Receive_All ETH Receive All 1087 * @{ 1088 */ 1089 #define ETH_RECEIVEALL_ENABLE 0x80000000U 1090 #define ETH_RECEIVEAll_DISABLE 0x00000000U 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 1096 * @{ 1097 */ 1098 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 1099 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 1100 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 1101 /** 1102 * @} 1103 */ 1104 1105 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 1106 * @{ 1107 */ 1108 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 1109 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 1110 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 1111 /** 1112 * @} 1113 */ 1114 1115 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 1116 * @{ 1117 */ 1118 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 1119 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 1125 * @{ 1126 */ 1127 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 1128 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 1129 /** 1130 * @} 1131 */ 1132 1133 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 1134 * @{ 1135 */ 1136 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 1137 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 1138 /** 1139 * @} 1140 */ 1141 1142 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 1143 * @{ 1144 */ 1145 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 1146 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 1147 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 1148 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 1154 * @{ 1155 */ 1156 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 1157 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 1158 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 1159 /** 1160 * @} 1161 */ 1162 1163 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 1164 * @{ 1165 */ 1166 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 1167 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 1168 /** 1169 * @} 1170 */ 1171 1172 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1173 * @{ 1174 */ 1175 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 1176 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 1177 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 1178 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 1179 /** 1180 * @} 1181 */ 1182 1183 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 1184 * @{ 1185 */ 1186 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 1187 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 1188 /** 1189 * @} 1190 */ 1191 1192 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 1193 * @{ 1194 */ 1195 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 1196 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 1197 /** 1198 * @} 1199 */ 1200 1201 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 1202 * @{ 1203 */ 1204 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 1205 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 1206 /** 1207 * @} 1208 */ 1209 1210 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1211 * @{ 1212 */ 1213 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 1214 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 1215 /** 1216 * @} 1217 */ 1218 1219 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1220 * @{ 1221 */ 1222 #define ETH_MAC_ADDRESS0 0x00000000U 1223 #define ETH_MAC_ADDRESS1 0x00000008U 1224 #define ETH_MAC_ADDRESS2 0x00000010U 1225 #define ETH_MAC_ADDRESS3 0x00000018U 1226 /** 1227 * @} 1228 */ 1229 1230 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 1231 * @{ 1232 */ 1233 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 1234 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 1235 /** 1236 * @} 1237 */ 1238 1239 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 1240 * @{ 1241 */ 1242 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 1243 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 1244 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 1245 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 1246 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 1247 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 1248 /** 1249 * @} 1250 */ 1251 1252 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 1253 * @{ 1254 */ 1255 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 1256 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 1257 /** 1258 * @} 1259 */ 1260 1261 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 1262 * @{ 1263 */ 1264 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 1265 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 1266 /** 1267 * @} 1268 */ 1269 1270 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 1271 * @{ 1272 */ 1273 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 1274 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 1275 /** 1276 * @} 1277 */ 1278 1279 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 1280 * @{ 1281 */ 1282 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 1283 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 1284 /** 1285 * @} 1286 */ 1287 1288 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 1289 * @{ 1290 */ 1291 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1292 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1293 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1294 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1295 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1296 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1297 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1298 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1299 /** 1300 * @} 1301 */ 1302 1303 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 1304 * @{ 1305 */ 1306 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 1307 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 1308 /** 1309 * @} 1310 */ 1311 1312 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 1313 * @{ 1314 */ 1315 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 1316 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 1317 /** 1318 * @} 1319 */ 1320 1321 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 1322 * @{ 1323 */ 1324 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1325 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1326 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1327 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1328 /** 1329 * @} 1330 */ 1331 1332 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 1333 * @{ 1334 */ 1335 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 1336 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 1337 /** 1338 * @} 1339 */ 1340 1341 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 1342 * @{ 1343 */ 1344 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 1345 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 1346 /** 1347 * @} 1348 */ 1349 1350 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 1351 * @{ 1352 */ 1353 #define ETH_FIXEDBURST_ENABLE 0x00010000U 1354 #define ETH_FIXEDBURST_DISABLE 0x00000000U 1355 /** 1356 * @} 1357 */ 1358 1359 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1360 * @{ 1361 */ 1362 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1363 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1364 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1365 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1366 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1367 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1368 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1369 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1370 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1371 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1372 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1373 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1374 /** 1375 * @} 1376 */ 1377 1378 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1379 * @{ 1380 */ 1381 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1382 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1383 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1384 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1385 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1386 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1387 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1388 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1389 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1390 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1391 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1392 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1393 /** 1394 * @} 1395 */ 1396 1397 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 1398 * @{ 1399 */ 1400 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U 1401 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U 1402 /** 1403 * @} 1404 */ 1405 1406 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1407 * @{ 1408 */ 1409 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 1410 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 1411 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 1412 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 1413 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 1414 /** 1415 * @} 1416 */ 1417 1418 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 1419 * @{ 1420 */ 1421 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 1422 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 1423 /** 1424 * @} 1425 */ 1426 1427 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 1428 * @{ 1429 */ 1430 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 1431 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 1432 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1433 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1434 /** 1435 * @} 1436 */ 1437 1438 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 1439 * @{ 1440 */ 1441 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 1442 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 1443 /** 1444 * @} 1445 */ 1446 1447 /** @defgroup ETH_PMT_Flags ETH PMT Flags 1448 * @{ 1449 */ 1450 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 1451 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 1452 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 1453 /** 1454 * @} 1455 */ 1456 1457 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 1458 * @{ 1459 */ 1460 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 1461 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 1462 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 1463 /** 1464 * @} 1465 */ 1466 1467 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 1468 * @{ 1469 */ 1470 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 1471 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 1472 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 1473 /** 1474 * @} 1475 */ 1476 1477 /** @defgroup ETH_MAC_Flags ETH MAC Flags 1478 * @{ 1479 */ 1480 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 1481 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 1482 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 1483 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 1484 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 1485 /** 1486 * @} 1487 */ 1488 1489 /** @defgroup ETH_DMA_Flags ETH DMA Flags 1490 * @{ 1491 */ 1492 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1493 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1494 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1495 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1496 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 1497 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 1498 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 1499 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 1500 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 1501 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 1502 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 1503 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 1504 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 1505 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 1506 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 1507 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 1508 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 1509 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 1510 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 1511 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 1512 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 1513 /** 1514 * @} 1515 */ 1516 1517 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1518 * @{ 1519 */ 1520 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 1521 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 1522 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 1523 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 1524 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 1525 /** 1526 * @} 1527 */ 1528 1529 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1530 * @{ 1531 */ 1532 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 1533 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 1534 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 1535 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 1536 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 1537 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 1538 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 1539 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 1540 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 1541 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 1542 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 1543 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 1544 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 1545 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 1546 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 1547 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 1548 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 1549 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 1550 /** 1551 * @} 1552 */ 1553 1554 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 1555 * @{ 1556 */ 1557 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 1558 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 1559 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 1560 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 1561 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 1562 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 1563 1564 /** 1565 * @} 1566 */ 1567 1568 1569 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 1570 * @{ 1571 */ 1572 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 1573 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 1574 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 1575 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 1576 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 1577 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 1578 1579 /** 1580 * @} 1581 */ 1582 1583 /** @defgroup ETH_DMA_overflow ETH DMA overflow 1584 * @{ 1585 */ 1586 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 1587 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 1588 /** 1589 * @} 1590 */ 1591 1592 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 1593 * @{ 1594 */ 1595 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 1596 1597 /** 1598 * @} 1599 */ 1600 1601 /** 1602 * @} 1603 */ 1604 1605 /* Exported macro ------------------------------------------------------------*/ 1606 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1607 * @brief macros to handle interrupts and specific clock configurations 1608 * @{ 1609 */ 1610 1611 /** @brief Reset ETH handle state 1612 * @param __HANDLE__ specifies the ETH handle. 1613 * @retval None 1614 */ 1615 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1616 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1617 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 1618 (__HANDLE__)->MspInitCallback = NULL; \ 1619 (__HANDLE__)->MspDeInitCallback = NULL; \ 1620 } while(0) 1621 #else 1622 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 1623 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1624 1625 /** 1626 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 1627 * @param __HANDLE__ ETH Handle 1628 * @param __FLAG__ specifies the flag of TDES0 to check. 1629 * @retval the ETH_DMATxDescFlag (SET or RESET). 1630 */ 1631 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 1632 1633 /** 1634 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 1635 * @param __HANDLE__ ETH Handle 1636 * @param __FLAG__ specifies the flag of RDES0 to check. 1637 * @retval the ETH_DMATxDescFlag (SET or RESET). 1638 */ 1639 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 1640 1641 /** 1642 * @brief Enables the specified DMA Rx Desc receive interrupt. 1643 * @param __HANDLE__ ETH Handle 1644 * @retval None 1645 */ 1646 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 1647 1648 /** 1649 * @brief Disables the specified DMA Rx Desc receive interrupt. 1650 * @param __HANDLE__ ETH Handle 1651 * @retval None 1652 */ 1653 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 1654 1655 /** 1656 * @brief Set the specified DMA Rx Desc Own bit. 1657 * @param __HANDLE__ ETH Handle 1658 * @retval None 1659 */ 1660 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 1661 1662 /** 1663 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 1664 * @param __HANDLE__ ETH Handle 1665 * @retval The Transmit descriptor collision counter value. 1666 */ 1667 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 1668 1669 /** 1670 * @brief Set the specified DMA Tx Desc Own bit. 1671 * @param __HANDLE__ ETH Handle 1672 * @retval None 1673 */ 1674 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 1675 1676 /** 1677 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 1678 * @param __HANDLE__ ETH Handle 1679 * @retval None 1680 */ 1681 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 1682 1683 /** 1684 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 1685 * @param __HANDLE__ ETH Handle 1686 * @retval None 1687 */ 1688 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 1689 1690 /** 1691 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 1692 * @param __HANDLE__ ETH Handle 1693 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 1694 * This parameter can be one of the following values: 1695 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 1696 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 1697 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 1698 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 1699 * @retval None 1700 */ 1701 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 1702 1703 /** 1704 * @brief Enables the DMA Tx Desc CRC. 1705 * @param __HANDLE__ ETH Handle 1706 * @retval None 1707 */ 1708 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 1709 1710 /** 1711 * @brief Disables the DMA Tx Desc CRC. 1712 * @param __HANDLE__ ETH Handle 1713 * @retval None 1714 */ 1715 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 1716 1717 /** 1718 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 1719 * @param __HANDLE__ ETH Handle 1720 * @retval None 1721 */ 1722 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 1723 1724 /** 1725 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 1726 * @param __HANDLE__ ETH Handle 1727 * @retval None 1728 */ 1729 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 1730 1731 /** 1732 * @brief Enables the specified ETHERNET MAC interrupts. 1733 * @param __HANDLE__ ETH Handle 1734 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1735 * enabled or disabled. 1736 * This parameter can be any combination of the following values: 1737 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1738 * @arg ETH_MAC_IT_PMT : PMT interrupt 1739 * @retval None 1740 */ 1741 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 1742 1743 /** 1744 * @brief Disables the specified ETHERNET MAC interrupts. 1745 * @param __HANDLE__ ETH Handle 1746 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 1747 * enabled or disabled. 1748 * This parameter can be any combination of the following values: 1749 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 1750 * @arg ETH_MAC_IT_PMT : PMT interrupt 1751 * @retval None 1752 */ 1753 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 1754 1755 /** 1756 * @brief Initiate a Pause Control Frame (Full-duplex only). 1757 * @param __HANDLE__ ETH Handle 1758 * @retval None 1759 */ 1760 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1761 1762 /** 1763 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 1764 * @param __HANDLE__ ETH Handle 1765 * @retval The new state of flow control busy status bit (SET or RESET). 1766 */ 1767 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 1768 1769 /** 1770 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 1771 * @param __HANDLE__ ETH Handle 1772 * @retval None 1773 */ 1774 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 1775 1776 /** 1777 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 1778 * @param __HANDLE__ ETH Handle 1779 * @retval None 1780 */ 1781 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 1782 1783 /** 1784 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1785 * @param __HANDLE__ ETH Handle 1786 * @param __FLAG__ specifies the flag to check. 1787 * This parameter can be one of the following values: 1788 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 1789 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 1790 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 1791 * @arg ETH_MAC_FLAG_MMC : MMC flag 1792 * @arg ETH_MAC_FLAG_PMT : PMT flag 1793 * @retval The state of ETHERNET MAC flag. 1794 */ 1795 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 1796 1797 /** 1798 * @brief Enables the specified ETHERNET DMA interrupts. 1799 * @param __HANDLE__ ETH Handle 1800 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1801 * enabled @ref ETH_DMA_Interrupts 1802 * @retval None 1803 */ 1804 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 1805 1806 /** 1807 * @brief Disables the specified ETHERNET DMA interrupts. 1808 * @param __HANDLE__ ETH Handle 1809 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 1810 * disabled. @ref ETH_DMA_Interrupts 1811 * @retval None 1812 */ 1813 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 1814 1815 /** 1816 * @brief Clears the ETHERNET DMA IT pending bit. 1817 * @param __HANDLE__ ETH Handle 1818 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1819 * @retval None 1820 */ 1821 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 1822 1823 /** 1824 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1825 * @param __HANDLE__ ETH Handle 1826 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 1827 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1828 */ 1829 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 1830 1831 /** 1832 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1833 * @param __HANDLE__ ETH Handle 1834 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 1835 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 1836 */ 1837 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 1838 1839 /** 1840 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 1841 * @param __HANDLE__ ETH Handle 1842 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 1843 * This parameter can be one of the following values: 1844 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 1845 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 1846 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 1847 */ 1848 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 1849 1850 /** 1851 * @brief Set the DMA Receive status watchdog timer register value 1852 * @param __HANDLE__ ETH Handle 1853 * @param __VALUE__ DMA Receive status watchdog timer register value 1854 * @retval None 1855 */ 1856 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 1857 1858 /** 1859 * @brief Enables any unicast packet filtered by the MAC address 1860 * recognition to be a wake-up frame. 1861 * @param __HANDLE__ ETH Handle. 1862 * @retval None 1863 */ 1864 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 1865 1866 /** 1867 * @brief Disables any unicast packet filtered by the MAC address 1868 * recognition to be a wake-up frame. 1869 * @param __HANDLE__ ETH Handle. 1870 * @retval None 1871 */ 1872 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 1873 1874 /** 1875 * @brief Enables the MAC Wake-Up Frame Detection. 1876 * @param __HANDLE__ ETH Handle. 1877 * @retval None 1878 */ 1879 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 1880 1881 /** 1882 * @brief Disables the MAC Wake-Up Frame Detection. 1883 * @param __HANDLE__ ETH Handle. 1884 * @retval None 1885 */ 1886 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1887 1888 /** 1889 * @brief Enables the MAC Magic Packet Detection. 1890 * @param __HANDLE__ ETH Handle. 1891 * @retval None 1892 */ 1893 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 1894 1895 /** 1896 * @brief Disables the MAC Magic Packet Detection. 1897 * @param __HANDLE__ ETH Handle. 1898 * @retval None 1899 */ 1900 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 1901 1902 /** 1903 * @brief Enables the MAC Power Down. 1904 * @param __HANDLE__ ETH Handle 1905 * @retval None 1906 */ 1907 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 1908 1909 /** 1910 * @brief Disables the MAC Power Down. 1911 * @param __HANDLE__ ETH Handle 1912 * @retval None 1913 */ 1914 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 1915 1916 /** 1917 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 1918 * @param __HANDLE__ ETH Handle. 1919 * @param __FLAG__ specifies the flag to check. 1920 * This parameter can be one of the following values: 1921 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 1922 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 1923 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 1924 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 1925 */ 1926 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 1927 1928 /** 1929 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 1930 * @param __HANDLE__ ETH Handle. 1931 * @retval None 1932 */ 1933 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 1934 1935 /** 1936 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 1937 * @param __HANDLE__ ETH Handle. 1938 * @retval None 1939 */ 1940 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 1941 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 1942 1943 /** 1944 * @brief Enables the MMC Counter Freeze. 1945 * @param __HANDLE__ ETH Handle. 1946 * @retval None 1947 */ 1948 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 1949 1950 /** 1951 * @brief Disables the MMC Counter Freeze. 1952 * @param __HANDLE__ ETH Handle. 1953 * @retval None 1954 */ 1955 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 1956 1957 /** 1958 * @brief Enables the MMC Reset On Read. 1959 * @param __HANDLE__ ETH Handle. 1960 * @retval None 1961 */ 1962 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 1963 1964 /** 1965 * @brief Disables the MMC Reset On Read. 1966 * @param __HANDLE__ ETH Handle. 1967 * @retval None 1968 */ 1969 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 1970 1971 /** 1972 * @brief Enables the MMC Counter Stop Rollover. 1973 * @param __HANDLE__ ETH Handle. 1974 * @retval None 1975 */ 1976 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 1977 1978 /** 1979 * @brief Disables the MMC Counter Stop Rollover. 1980 * @param __HANDLE__ ETH Handle. 1981 * @retval None 1982 */ 1983 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 1984 1985 /** 1986 * @brief Resets the MMC Counters. 1987 * @param __HANDLE__ ETH Handle. 1988 * @retval None 1989 */ 1990 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 1991 1992 /** 1993 * @brief Enables the specified ETHERNET MMC Rx interrupts. 1994 * @param __HANDLE__ ETH Handle. 1995 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 1996 * This parameter can be one of the following values: 1997 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 1998 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 1999 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2000 * @retval None 2001 */ 2002 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) 2003 /** 2004 * @brief Disables the specified ETHERNET MMC Rx interrupts. 2005 * @param __HANDLE__ ETH Handle. 2006 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2007 * This parameter can be one of the following values: 2008 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 2009 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 2010 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 2011 * @retval None 2012 */ 2013 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) 2014 /** 2015 * @brief Enables the specified ETHERNET MMC Tx interrupts. 2016 * @param __HANDLE__ ETH Handle. 2017 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2018 * This parameter can be one of the following values: 2019 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2020 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2021 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2022 * @retval None 2023 */ 2024 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 2025 2026 /** 2027 * @brief Disables the specified ETHERNET MMC Tx interrupts. 2028 * @param __HANDLE__ ETH Handle. 2029 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 2030 * This parameter can be one of the following values: 2031 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 2032 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 2033 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 2034 * @retval None 2035 */ 2036 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 2037 2038 /** 2039 * @brief Enables the ETH External interrupt line. 2040 * @retval None 2041 */ 2042 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 2043 2044 /** 2045 * @brief Disables the ETH External interrupt line. 2046 * @retval None 2047 */ 2048 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 2049 2050 /** 2051 * @brief Enable event on ETH External event line. 2052 * @retval None. 2053 */ 2054 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 2055 2056 /** 2057 * @brief Disable event on ETH External event line 2058 * @retval None. 2059 */ 2060 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 2061 2062 /** 2063 * @brief Get flag of the ETH External interrupt line. 2064 * @retval None 2065 */ 2066 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 2067 2068 /** 2069 * @brief Clear flag of the ETH External interrupt line. 2070 * @retval None 2071 */ 2072 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 2073 2074 /** 2075 * @brief Enables rising edge trigger to the ETH External interrupt line. 2076 * @retval None 2077 */ 2078 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 2079 2080 /** 2081 * @brief Disables the rising edge trigger to the ETH External interrupt line. 2082 * @retval None 2083 */ 2084 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2085 2086 /** 2087 * @brief Enables falling edge trigger to the ETH External interrupt line. 2088 * @retval None 2089 */ 2090 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 2091 2092 /** 2093 * @brief Disables falling edge trigger to the ETH External interrupt line. 2094 * @retval None 2095 */ 2096 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 2097 2098 /** 2099 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 2100 * @retval None 2101 */ 2102 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 2103 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 2104 }while(0) 2105 2106 /** 2107 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 2108 * @retval None 2109 */ 2110 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2111 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 2112 }while(0) 2113 2114 /** 2115 * @brief Generate a Software interrupt on selected EXTI line. 2116 * @retval None. 2117 */ 2118 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 2119 2120 /** 2121 * @} 2122 */ 2123 /* Exported functions --------------------------------------------------------*/ 2124 2125 /** @addtogroup ETH_Exported_Functions 2126 * @{ 2127 */ 2128 2129 /* Initialization and de-initialization functions ****************************/ 2130 2131 /** @addtogroup ETH_Exported_Functions_Group1 2132 * @{ 2133 */ 2134 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 2135 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 2136 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 2137 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 2138 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); 2139 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 2140 /* Callbacks Register/UnRegister functions ***********************************/ 2141 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 2142 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 2143 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 2144 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 2145 2146 /** 2147 * @} 2148 */ 2149 /* IO operation functions ****************************************************/ 2150 2151 /** @addtogroup ETH_Exported_Functions_Group2 2152 * @{ 2153 */ 2154 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 2155 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 2156 /* Communication with PHY functions*/ 2157 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 2158 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 2159 /* Non-Blocking mode: Interrupt */ 2160 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 2161 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 2162 /* Callback in non blocking modes (Interrupt) */ 2163 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 2164 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 2165 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 2166 /** 2167 * @} 2168 */ 2169 2170 /* Peripheral Control functions **********************************************/ 2171 2172 /** @addtogroup ETH_Exported_Functions_Group3 2173 * @{ 2174 */ 2175 2176 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 2177 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 2178 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 2179 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 2180 /** 2181 * @} 2182 */ 2183 2184 /* Peripheral State functions ************************************************/ 2185 2186 /** @addtogroup ETH_Exported_Functions_Group4 2187 * @{ 2188 */ 2189 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 2190 /** 2191 * @} 2192 */ 2193 2194 /** 2195 * @} 2196 */ 2197 2198 /** 2199 * @} 2200 */ 2201 2202 /** 2203 * @} 2204 */ 2205 2206 #endif /* ETH */ 2207 2208 #ifdef __cplusplus 2209 } 2210 #endif 2211 2212 #endif /* __STM32F2xx_HAL_ETH_H */ 2213
