1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F2xx_HAL_CORTEX_H 21 #define __STM32F2xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 /** @addtogroup STM32F2xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup CORTEX 35 * @{ 36 */ 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 39 * @{ 40 */ 41 42 #if (__MPU_PRESENT == 1U) 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @brief MPU Region initialization structure 45 * @{ 46 */ 47 typedef struct 48 { 49 uint8_t Enable; /*!< Specifies the status of the region. 50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 51 uint8_t Number; /*!< Specifies the number of the region to protect. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 54 uint8_t Size; /*!< Specifies the size of the region to protect. 55 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 56 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 57 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 58 uint8_t TypeExtField; /*!< Specifies the TEX field level. 59 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 60 uint8_t AccessPermission; /*!< Specifies the region access permission type. 61 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 62 uint8_t DisableExec; /*!< Specifies the instruction access status. 63 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 64 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 65 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 66 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 68 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 70 }MPU_Region_InitTypeDef; 71 /** 72 * @} 73 */ 74 #endif /* __MPU_PRESENT */ 75 76 /** 77 * @} 78 */ 79 80 /* Exported constants --------------------------------------------------------*/ 81 82 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 83 * @{ 84 */ 85 86 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 87 * @{ 88 */ 89 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 90 4 bits for subpriority */ 91 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 92 3 bits for subpriority */ 93 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 94 2 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 96 1 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority 98 0 bits for subpriority */ 99 /** 100 * @} 101 */ 102 103 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 104 * @{ 105 */ 106 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 107 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 108 109 /** 110 * @} 111 */ 112 113 #if (__MPU_PRESENT == 1) 114 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 115 * @{ 116 */ 117 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 118 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk 119 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk 120 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 121 122 /** 123 * @} 124 */ 125 126 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 127 * @{ 128 */ 129 #define MPU_REGION_ENABLE ((uint8_t)0x01) 130 #define MPU_REGION_DISABLE ((uint8_t)0x00) 131 /** 132 * @} 133 */ 134 135 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 136 * @{ 137 */ 138 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 139 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 140 /** 141 * @} 142 */ 143 144 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 145 * @{ 146 */ 147 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 148 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 149 /** 150 * @} 151 */ 152 153 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 154 * @{ 155 */ 156 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 157 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 158 /** 159 * @} 160 */ 161 162 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 163 * @{ 164 */ 165 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 166 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 167 /** 168 * @} 169 */ 170 171 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 172 * @{ 173 */ 174 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 175 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 176 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 177 /** 178 * @} 179 */ 180 181 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 182 * @{ 183 */ 184 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 185 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 186 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 187 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 188 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 189 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 190 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 191 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 192 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 193 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 194 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 195 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 196 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 197 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 198 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 199 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 200 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 201 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 202 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 203 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 204 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 205 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 206 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 207 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 208 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 209 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 210 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 211 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 212 /** 213 * @} 214 */ 215 216 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 217 * @{ 218 */ 219 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 220 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 221 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 222 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 223 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 224 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 225 /** 226 * @} 227 */ 228 229 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 230 * @{ 231 */ 232 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 233 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 234 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 235 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 236 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 237 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 238 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 239 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 240 /** 241 * @} 242 */ 243 #endif /* __MPU_PRESENT */ 244 245 /** 246 * @} 247 */ 248 249 250 /* Exported Macros -----------------------------------------------------------*/ 251 252 /* Exported functions --------------------------------------------------------*/ 253 /** @addtogroup CORTEX_Exported_Functions 254 * @{ 255 */ 256 257 /** @addtogroup CORTEX_Exported_Functions_Group1 258 * @{ 259 */ 260 /* Initialization and de-initialization functions *****************************/ 261 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 262 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 263 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 264 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 265 void HAL_NVIC_SystemReset(void); 266 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 267 /** 268 * @} 269 */ 270 271 /** @addtogroup CORTEX_Exported_Functions_Group2 272 * @{ 273 */ 274 /* Peripheral Control functions ***********************************************/ 275 uint32_t HAL_NVIC_GetPriorityGrouping(void); 276 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 277 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 278 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 279 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 280 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 281 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 282 void HAL_SYSTICK_IRQHandler(void); 283 void HAL_SYSTICK_Callback(void); 284 285 #if (__MPU_PRESENT == 1U) 286 void HAL_MPU_Enable(uint32_t MPU_Control); 287 void HAL_MPU_Disable(void); 288 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 289 #endif /* __MPU_PRESENT */ 290 /** 291 * @} 292 */ 293 294 /** 295 * @} 296 */ 297 298 /* Private types -------------------------------------------------------------*/ 299 /* Private variables ---------------------------------------------------------*/ 300 /* Private constants ---------------------------------------------------------*/ 301 /* Private macros ------------------------------------------------------------*/ 302 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 303 * @{ 304 */ 305 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 306 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 307 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 308 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 309 ((GROUP) == NVIC_PRIORITYGROUP_4)) 310 311 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 312 313 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 314 315 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) 316 317 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 318 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 319 320 #if (__MPU_PRESENT == 1U) 321 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 322 ((STATE) == MPU_REGION_DISABLE)) 323 324 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 325 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 326 327 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 329 330 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 331 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 332 333 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 334 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 335 336 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 337 ((TYPE) == MPU_TEX_LEVEL1) || \ 338 ((TYPE) == MPU_TEX_LEVEL2)) 339 340 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 341 ((TYPE) == MPU_REGION_PRIV_RW) || \ 342 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 343 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 344 ((TYPE) == MPU_REGION_PRIV_RO) || \ 345 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 346 347 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 348 ((NUMBER) == MPU_REGION_NUMBER1) || \ 349 ((NUMBER) == MPU_REGION_NUMBER2) || \ 350 ((NUMBER) == MPU_REGION_NUMBER3) || \ 351 ((NUMBER) == MPU_REGION_NUMBER4) || \ 352 ((NUMBER) == MPU_REGION_NUMBER5) || \ 353 ((NUMBER) == MPU_REGION_NUMBER6) || \ 354 ((NUMBER) == MPU_REGION_NUMBER7)) 355 356 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 357 ((SIZE) == MPU_REGION_SIZE_64B) || \ 358 ((SIZE) == MPU_REGION_SIZE_128B) || \ 359 ((SIZE) == MPU_REGION_SIZE_256B) || \ 360 ((SIZE) == MPU_REGION_SIZE_512B) || \ 361 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 362 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 363 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 364 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 365 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 366 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 367 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 368 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 369 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 370 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 371 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 372 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 373 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 374 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 375 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 376 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 377 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 378 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 379 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 380 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 381 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 382 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 383 ((SIZE) == MPU_REGION_SIZE_4GB)) 384 385 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 386 #endif /* __MPU_PRESENT */ 387 388 /** 389 * @} 390 */ 391 392 /* Private functions ---------------------------------------------------------*/ 393 394 /** 395 * @} 396 */ 397 398 /** 399 * @} 400 */ 401 402 #ifdef __cplusplus 403 } 404 #endif 405 406 #endif /* __STM32F2xx_HAL_CORTEX_H */ 407 408 409
