1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F2xx_ADC_H 21 #define __STM32F2xx_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 /** @addtogroup STM32F2xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADC_Exported_Types ADC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief Structure definition of ADC and regular group initialization 45 * @note Parameters of this structure are shared within 2 scopes: 46 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 47 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 48 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 49 * ADC state can be either: 50 * - For all parameters: ADC disabled 51 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 52 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 53 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 54 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 55 */ 56 typedef struct 57 { 58 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for 59 all the ADCs. 60 This parameter can be a value of @ref ADC_ClockPrescaler */ 61 uint32_t Resolution; /*!< Configures the ADC resolution. 62 This parameter can be a value of @ref ADC_Resolution */ 63 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 64 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 65 This parameter can be a value of @ref ADC_Data_align */ 66 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 67 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 68 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 69 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 70 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 71 Scan direction is upward: from rank1 to rank 'n'. 72 This parameter can be set to ENABLE or DISABLE */ 73 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 74 This parameter can be a value of @ref ADC_EOCSelection. 75 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 76 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 77 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 78 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 79 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 80 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 81 after the selected trigger occurred (software start or external trigger). 82 This parameter can be set to ENABLE or DISABLE. */ 83 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 84 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 85 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 86 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 87 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 88 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 89 This parameter can be set to ENABLE or DISABLE. */ 90 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 91 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 92 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 93 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 94 If set to ADC_SOFTWARE_START, external triggers are disabled. 95 If set to external trigger source, triggering is on event rising edge by default. 96 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ 97 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 98 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 99 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 100 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 101 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 102 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 103 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 104 This parameter can be set to ENABLE or DISABLE. */ 105 }ADC_InitTypeDef; 106 107 108 109 /** 110 * @brief Structure definition of ADC channel for regular group 111 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 112 * ADC can be either disabled or enabled without conversion on going on regular group. 113 */ 114 typedef struct 115 { 116 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 117 This parameter can be a value of @ref ADC_channels */ 118 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 119 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 120 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 121 Unit: ADC clock cycles 122 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 123 This parameter can be a value of @ref ADC_sampling_times 124 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 125 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 126 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 127 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 128 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 129 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ 130 }ADC_ChannelConfTypeDef; 131 132 /** 133 * @brief ADC Configuration multi-mode structure definition 134 */ 135 typedef struct 136 { 137 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. 138 This parameter can be a value of @ref ADC_analog_watchdog_selection */ 139 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 140 This parameter must be a 12-bit value. */ 141 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 142 This parameter must be a 12-bit value. */ 143 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. 144 This parameter has an effect only if watchdog mode is configured on single channel 145 This parameter can be a value of @ref ADC_channels */ 146 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured 147 is interrupt mode or in polling mode. 148 This parameter can be set to ENABLE or DISABLE */ 149 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 150 }ADC_AnalogWDGConfTypeDef; 151 152 /** 153 * @brief HAL ADC state machine: ADC states definition (bitfields) 154 */ 155 /* States of ADC global scope */ 156 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 157 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 158 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 159 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 160 161 /* States of ADC errors */ 162 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 163 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 164 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 165 166 /* States of ADC group regular */ 167 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 168 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 169 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 170 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ 171 172 /* States of ADC group injected */ 173 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 174 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 175 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 176 177 /* States of ADC analog watchdogs */ 178 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 179 180 /** 181 * @brief ADC handle Structure definition 182 */ 183 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 184 typedef struct __ADC_HandleTypeDef 185 #else 186 typedef struct 187 #endif 188 { 189 ADC_TypeDef *Instance; /*!< Register base address */ 190 191 ADC_InitTypeDef Init; /*!< ADC required parameters */ 192 193 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ 194 195 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 196 197 HAL_LockTypeDef Lock; /*!< ADC locking object */ 198 199 __IO uint32_t State; /*!< ADC communication state */ 200 201 __IO uint32_t ErrorCode; /*!< ADC Error code */ 202 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 203 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 204 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 205 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 206 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 207 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 208 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 209 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 210 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 211 }ADC_HandleTypeDef; 212 213 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 214 /** 215 * @brief HAL ADC Callback ID enumeration definition 216 */ 217 typedef enum 218 { 219 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 220 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 221 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 222 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 223 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 224 HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ 225 HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ 226 } HAL_ADC_CallbackIDTypeDef; 227 228 /** 229 * @brief HAL ADC Callback pointer definition 230 */ 231 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 232 233 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 234 235 /** 236 * @} 237 */ 238 239 /* Exported constants --------------------------------------------------------*/ 240 /** @defgroup ADC_Exported_Constants ADC Exported Constants 241 * @{ 242 */ 243 244 /** @defgroup ADC_Error_Code ADC Error Code 245 * @{ 246 */ 247 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 248 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 249 enable/disable, erroneous state */ 250 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 251 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 252 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 253 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 254 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 255 /** 256 * @} 257 */ 258 259 260 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 261 * @{ 262 */ 263 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U 264 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) 265 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) 266 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) 267 /** 268 * @} 269 */ 270 271 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases 272 * @{ 273 */ 274 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U 275 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) 276 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) 277 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 278 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) 279 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 280 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 281 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 282 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) 283 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) 284 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) 285 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 286 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) 287 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 288 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 289 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) 290 /** 291 * @} 292 */ 293 294 /** @defgroup ADC_Resolution ADC Resolution 295 * @{ 296 */ 297 #define ADC_RESOLUTION_12B 0x00000000U 298 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) 299 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) 300 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) 301 /** 302 * @} 303 */ 304 305 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular 306 * @{ 307 */ 308 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 309 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 310 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 311 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 312 /** 313 * @} 314 */ 315 316 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular 317 * @{ 318 */ 319 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ 320 /* compatibility with other STM32 devices. */ 321 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U 322 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) 323 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) 324 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 325 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) 326 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 327 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 328 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 329 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) 330 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 331 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) 332 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 333 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) 334 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 335 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 336 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) 337 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) 338 /** 339 * @} 340 */ 341 342 /** @defgroup ADC_Data_align ADC Data Align 343 * @{ 344 */ 345 #define ADC_DATAALIGN_RIGHT 0x00000000U 346 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 347 /** 348 * @} 349 */ 350 351 /** @defgroup ADC_channels ADC Common Channels 352 * @{ 353 */ 354 #define ADC_CHANNEL_0 0x00000000U 355 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) 356 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) 357 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 358 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) 359 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 360 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 361 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 362 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) 363 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) 364 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) 365 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 366 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) 367 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 368 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 369 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 370 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) 371 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) 372 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) 373 374 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) 375 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) 376 /** 377 * @} 378 */ 379 380 /** @defgroup ADC_sampling_times ADC Sampling Times 381 * @{ 382 */ 383 #define ADC_SAMPLETIME_3CYCLES 0x00000000U 384 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) 385 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) 386 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) 387 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) 388 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) 389 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) 390 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) 391 /** 392 * @} 393 */ 394 395 /** @defgroup ADC_EOCSelection ADC EOC Selection 396 * @{ 397 */ 398 #define ADC_EOC_SEQ_CONV 0x00000000U 399 #define ADC_EOC_SINGLE_CONV 0x00000001U 400 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup ADC_Event_type ADC Event Type 406 * @{ 407 */ 408 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 409 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 410 /** 411 * @} 412 */ 413 414 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection 415 * @{ 416 */ 417 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 418 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 419 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 420 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 421 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 422 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 423 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 424 /** 425 * @} 426 */ 427 428 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 429 * @{ 430 */ 431 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) 432 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) 433 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) 434 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) 435 /** 436 * @} 437 */ 438 439 /** @defgroup ADC_flags_definition ADC Flags Definition 440 * @{ 441 */ 442 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) 443 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) 444 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) 445 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) 446 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) 447 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) 448 /** 449 * @} 450 */ 451 452 /** @defgroup ADC_channels_type ADC Channels Type 453 * @{ 454 */ 455 #define ADC_ALL_CHANNELS 0x00000001U 456 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ 457 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ 458 /** 459 * @} 460 */ 461 462 /** 463 * @} 464 */ 465 466 /* Exported macro ------------------------------------------------------------*/ 467 /** @defgroup ADC_Exported_Macros ADC Exported Macros 468 * @{ 469 */ 470 471 /** @brief Reset ADC handle state 472 * @param __HANDLE__ ADC handle 473 * @retval None 474 */ 475 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 476 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 477 do{ \ 478 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 479 (__HANDLE__)->MspInitCallback = NULL; \ 480 (__HANDLE__)->MspDeInitCallback = NULL; \ 481 } while(0) 482 #else 483 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 484 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 485 #endif 486 487 /** 488 * @brief Enable the ADC peripheral. 489 * @param __HANDLE__ ADC handle 490 * @retval None 491 */ 492 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) 493 494 /** 495 * @brief Disable the ADC peripheral. 496 * @param __HANDLE__ ADC handle 497 * @retval None 498 */ 499 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) 500 501 /** 502 * @brief Enable the ADC end of conversion interrupt. 503 * @param __HANDLE__ specifies the ADC Handle. 504 * @param __INTERRUPT__ ADC Interrupt. 505 * @retval None 506 */ 507 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) 508 509 /** 510 * @brief Disable the ADC end of conversion interrupt. 511 * @param __HANDLE__ specifies the ADC Handle. 512 * @param __INTERRUPT__ ADC interrupt. 513 * @retval None 514 */ 515 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) 516 517 /** @brief Check if the specified ADC interrupt source is enabled or disabled. 518 * @param __HANDLE__ specifies the ADC Handle. 519 * @param __INTERRUPT__ specifies the ADC interrupt source to check. 520 * @retval The new state of __IT__ (TRUE or FALSE). 521 */ 522 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 523 524 /** 525 * @brief Clear the ADC's pending flags. 526 * @param __HANDLE__ specifies the ADC Handle. 527 * @param __FLAG__ ADC flag. 528 * @retval None 529 */ 530 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 531 532 /** 533 * @brief Get the selected ADC's flag status. 534 * @param __HANDLE__ specifies the ADC Handle. 535 * @param __FLAG__ ADC flag. 536 * @retval None 537 */ 538 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 539 540 /** 541 * @} 542 */ 543 544 /* Include ADC HAL Extension module */ 545 #include "stm32f2xx_hal_adc_ex.h" 546 547 /* Exported functions --------------------------------------------------------*/ 548 /** @addtogroup ADC_Exported_Functions 549 * @{ 550 */ 551 552 /** @addtogroup ADC_Exported_Functions_Group1 553 * @{ 554 */ 555 /* Initialization/de-initialization functions ***********************************/ 556 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 557 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 558 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 559 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 560 561 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 562 /* Callbacks Register/UnRegister functions ***********************************/ 563 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 564 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 565 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 566 /** 567 * @} 568 */ 569 570 /** @addtogroup ADC_Exported_Functions_Group2 571 * @{ 572 */ 573 /* I/O operation functions ******************************************************/ 574 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 575 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 576 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 577 578 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 579 580 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 581 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 582 583 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 584 585 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 586 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 587 588 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 589 590 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 591 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 592 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 593 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 594 /** 595 * @} 596 */ 597 598 /** @addtogroup ADC_Exported_Functions_Group3 599 * @{ 600 */ 601 /* Peripheral Control functions *************************************************/ 602 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 603 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 604 /** 605 * @} 606 */ 607 608 /** @addtogroup ADC_Exported_Functions_Group4 609 * @{ 610 */ 611 /* Peripheral State functions ***************************************************/ 612 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 613 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 614 /** 615 * @} 616 */ 617 618 /** 619 * @} 620 */ 621 /* Private types -------------------------------------------------------------*/ 622 /* Private variables ---------------------------------------------------------*/ 623 /* Private constants ---------------------------------------------------------*/ 624 /** @defgroup ADC_Private_Constants ADC Private Constants 625 * @{ 626 */ 627 /* Delay for ADC stabilization time. */ 628 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ 629 /* Unit: us */ 630 #define ADC_STAB_DELAY_US 3U 631 /* Delay for temperature sensor stabilization time. */ 632 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ 633 /* Unit: us */ 634 #define ADC_TEMPSENSOR_DELAY_US 10U 635 /** 636 * @} 637 */ 638 639 /* Private macro ------------------------------------------------------------*/ 640 641 /** @defgroup ADC_Private_Macros ADC Private Macros 642 * @{ 643 */ 644 /* Macro reserved for internal HAL driver usage, not intended to be used in 645 code of final user */ 646 647 /** 648 * @brief Verification of ADC state: enabled or disabled 649 * @param __HANDLE__ ADC handle 650 * @retval SET (ADC enabled) or RESET (ADC disabled) 651 */ 652 #define ADC_IS_ENABLE(__HANDLE__) \ 653 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 654 ) ? SET : RESET) 655 656 /** 657 * @brief Test if conversion trigger of regular group is software start 658 * or external trigger. 659 * @param __HANDLE__ ADC handle 660 * @retval SET (software start) or RESET (external trigger) 661 */ 662 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 663 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 664 665 /** 666 * @brief Test if conversion trigger of injected group is software start 667 * or external trigger. 668 * @param __HANDLE__ ADC handle 669 * @retval SET (software start) or RESET (external trigger) 670 */ 671 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 672 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 673 674 /** 675 * @brief Simultaneously clears and sets specific bits of the handle State 676 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 677 * the first parameter is the ADC handle State, the second parameter is the 678 * bit field to clear, the third and last parameter is the bit field to set. 679 * @retval None 680 */ 681 #define ADC_STATE_CLR_SET MODIFY_REG 682 683 /** 684 * @brief Clear ADC error code (set it to error code: "no error") 685 * @param __HANDLE__ ADC handle 686 * @retval None 687 */ 688 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 689 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 690 691 692 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 693 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 694 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ 695 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) 696 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 697 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 698 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 699 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 700 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 701 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 702 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 703 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 704 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ 705 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ 706 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ 707 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ 708 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ 709 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ 710 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ 711 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) 712 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 713 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 714 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 715 ((RESOLUTION) == ADC_RESOLUTION_6B)) 716 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 717 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 718 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 719 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 720 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 721 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 722 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 723 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 724 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 725 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ 726 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 727 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 728 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 729 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 730 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ 731 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ 732 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ 733 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 734 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 735 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ 736 ((REGTRIG) == ADC_SOFTWARE_START)) 737 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 738 ((ALIGN) == ADC_DATAALIGN_LEFT)) 739 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ 740 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ 741 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ 742 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ 743 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ 744 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ 745 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ 746 ((TIME) == ADC_SAMPLETIME_480CYCLES)) 747 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ 748 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ 749 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) 750 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 751 ((EVENT) == ADC_OVR_EVENT)) 752 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 753 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 754 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 755 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 756 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 757 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ 758 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) 759 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ 760 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ 761 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) 762 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) 763 764 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 765 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) 766 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 767 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 768 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ 769 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ 770 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ 771 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) 772 773 /** 774 * @brief Set ADC Regular channel sequence length. 775 * @param _NbrOfConversion_ Regular channel sequence length. 776 * @retval None 777 */ 778 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U) 779 780 /** 781 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 782 * @param _SAMPLETIME_ Sample time parameter. 783 * @param _CHANNELNB_ Channel number. 784 * @retval None 785 */ 786 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) 787 788 /** 789 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 790 * @param _SAMPLETIME_ Sample time parameter. 791 * @param _CHANNELNB_ Channel number. 792 * @retval None 793 */ 794 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) 795 796 /** 797 * @brief Set the selected regular channel rank for rank between 1 and 6. 798 * @param _CHANNELNB_ Channel number. 799 * @param _RANKNB_ Rank number. 800 * @retval None 801 */ 802 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) 803 804 /** 805 * @brief Set the selected regular channel rank for rank between 7 and 12. 806 * @param _CHANNELNB_ Channel number. 807 * @param _RANKNB_ Rank number. 808 * @retval None 809 */ 810 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) 811 812 /** 813 * @brief Set the selected regular channel rank for rank between 13 and 16. 814 * @param _CHANNELNB_ Channel number. 815 * @param _RANKNB_ Rank number. 816 * @retval None 817 */ 818 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) 819 820 /** 821 * @brief Enable ADC continuous conversion mode. 822 * @param _CONTINUOUS_MODE_ Continuous mode. 823 * @retval None 824 */ 825 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) 826 827 /** 828 * @brief Configures the number of discontinuous conversions for the regular group channels. 829 * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. 830 * @retval None 831 */ 832 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM)) 833 834 /** 835 * @brief Enable ADC scan mode. 836 * @param _SCANCONV_MODE_ Scan conversion mode. 837 * @retval None 838 */ 839 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) 840 841 /** 842 * @brief Enable the ADC end of conversion selection. 843 * @param _EOCSelection_MODE_ End of conversion selection mode. 844 * @retval None 845 */ 846 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) 847 848 /** 849 * @brief Enable the ADC DMA continuous request. 850 * @param _DMAContReq_MODE_ DMA continuous request mode. 851 * @retval None 852 */ 853 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) 854 855 /** 856 * @brief Return resolution bits in CR1 register. 857 * @param __HANDLE__ ADC handle 858 * @retval None 859 */ 860 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) 861 862 /** 863 * @} 864 */ 865 866 /* Private functions ---------------------------------------------------------*/ 867 /** @defgroup ADC_Private_Functions ADC Private Functions 868 * @{ 869 */ 870 871 /** 872 * @} 873 */ 874 875 /** 876 * @} 877 */ 878 879 /** 880 * @} 881 */ 882 883 #ifdef __cplusplus 884 } 885 #endif 886 887 #endif /*__STM32F2xx_ADC_H */ 888 889 890
