1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_usart.c
4 * @author MCD Application Team
5 * @brief USART LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #if defined(USE_FULL_LL_DRIVER)
21
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32f1xx_ll_usart.h"
24 #include "stm32f1xx_ll_rcc.h"
25 #include "stm32f1xx_ll_bus.h"
26 #ifdef USE_FULL_ASSERT
27 #include "stm32_assert.h"
28 #else
29 #define assert_param(expr) ((void)0U)
30 #endif
31
32 /** @addtogroup STM32F1xx_LL_Driver
33 * @{
34 */
35
36 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
37
38 /** @addtogroup USART_LL
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /* Private constants ---------------------------------------------------------*/
45 /** @addtogroup USART_LL_Private_Constants
46 * @{
47 */
48
49 /**
50 * @}
51 */
52
53
54 /* Private macros ------------------------------------------------------------*/
55 /** @addtogroup USART_LL_Private_Macros
56 * @{
57 */
58
59 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
60 * divided by the smallest oversampling used on the USART (i.e. 8) */
61 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4500000U)
62
63 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
64 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
65
66 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
67 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
68 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
69 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
70
71 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
72 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
73 || ((__VALUE__) == LL_USART_PARITY_ODD))
74
75 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
76 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
77
78 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
79 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
80
81 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
82 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
83
84 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
85 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
86
87 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
88 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
89
90 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
91 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
92
93 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
94 || ((__VALUE__) == LL_USART_STOPBITS_1) \
95 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
96 || ((__VALUE__) == LL_USART_STOPBITS_2))
97
98 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
99 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
100 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
101 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
102
103 /**
104 * @}
105 */
106
107 /* Private function prototypes -----------------------------------------------*/
108
109 /* Exported functions --------------------------------------------------------*/
110 /** @addtogroup USART_LL_Exported_Functions
111 * @{
112 */
113
114 /** @addtogroup USART_LL_EF_Init
115 * @{
116 */
117
118 /**
119 * @brief De-initialize USART registers (Registers restored to their default values).
120 * @param USARTx USART Instance
121 * @retval An ErrorStatus enumeration value:
122 * - SUCCESS: USART registers are de-initialized
123 * - ERROR: USART registers are not de-initialized
124 */
LL_USART_DeInit(USART_TypeDef * USARTx)125 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
126 {
127 ErrorStatus status = SUCCESS;
128
129 /* Check the parameters */
130 assert_param(IS_UART_INSTANCE(USARTx));
131
132 if (USARTx == USART1)
133 {
134 /* Force reset of USART clock */
135 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
136
137 /* Release reset of USART clock */
138 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
139 }
140 else if (USARTx == USART2)
141 {
142 /* Force reset of USART clock */
143 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
144
145 /* Release reset of USART clock */
146 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
147 }
148 #if defined(USART3)
149 else if (USARTx == USART3)
150 {
151 /* Force reset of USART clock */
152 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
153
154 /* Release reset of USART clock */
155 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
156 }
157 #endif /* USART3 */
158 #if defined(UART4)
159 else if (USARTx == UART4)
160 {
161 /* Force reset of UART clock */
162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
163
164 /* Release reset of UART clock */
165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
166 }
167 #endif /* UART4 */
168 #if defined(UART5)
169 else if (USARTx == UART5)
170 {
171 /* Force reset of UART clock */
172 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
173
174 /* Release reset of UART clock */
175 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
176 }
177 #endif /* UART5 */
178 else
179 {
180 status = ERROR;
181 }
182
183 return (status);
184 }
185
186 /**
187 * @brief Initialize USART registers according to the specified
188 * parameters in USART_InitStruct.
189 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
190 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
191 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
192 * @param USARTx USART Instance
193 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
194 * that contains the configuration information for the specified USART peripheral.
195 * @retval An ErrorStatus enumeration value:
196 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
197 * - ERROR: Problem occurred during USART Registers initialization
198 */
LL_USART_Init(USART_TypeDef * USARTx,LL_USART_InitTypeDef * USART_InitStruct)199 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
200 {
201 ErrorStatus status = ERROR;
202 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
203 LL_RCC_ClocksTypeDef rcc_clocks;
204
205 /* Check the parameters */
206 assert_param(IS_UART_INSTANCE(USARTx));
207 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
208 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
209 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
210 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
211 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
212 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
213 #if defined(USART_CR1_OVER8)
214 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
215 #endif /* USART_OverSampling_Feature */
216
217 /* USART needs to be in disabled state, in order to be able to configure some bits in
218 CRx registers */
219 if (LL_USART_IsEnabled(USARTx) == 0U)
220 {
221 /*---------------------------- USART CR1 Configuration -----------------------
222 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
223 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
224 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
225 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
226 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
227 */
228 #if defined(USART_CR1_OVER8)
229 MODIFY_REG(USARTx->CR1,
230 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
231 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
232 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
233 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
234 #else
235 MODIFY_REG(USARTx->CR1,
236 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
237 USART_CR1_TE | USART_CR1_RE),
238 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
239 USART_InitStruct->TransferDirection));
240 #endif /* USART_OverSampling_Feature */
241
242 /*---------------------------- USART CR2 Configuration -----------------------
243 * Configure USARTx CR2 (Stop bits) with parameters:
244 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
245 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
246 */
247 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
248
249 /*---------------------------- USART CR3 Configuration -----------------------
250 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
251 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
252 */
253 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
254
255 /*---------------------------- USART BRR Configuration -----------------------
256 * Retrieve Clock frequency used for USART Peripheral
257 */
258 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
259 if (USARTx == USART1)
260 {
261 periphclk = rcc_clocks.PCLK2_Frequency;
262 }
263 else if (USARTx == USART2)
264 {
265 periphclk = rcc_clocks.PCLK1_Frequency;
266 }
267 #if defined(USART3)
268 else if (USARTx == USART3)
269 {
270 periphclk = rcc_clocks.PCLK1_Frequency;
271 }
272 #endif /* USART3 */
273 #if defined(UART4)
274 else if (USARTx == UART4)
275 {
276 periphclk = rcc_clocks.PCLK1_Frequency;
277 }
278 #endif /* UART4 */
279 #if defined(UART5)
280 else if (USARTx == UART5)
281 {
282 periphclk = rcc_clocks.PCLK1_Frequency;
283 }
284 #endif /* UART5 */
285 else
286 {
287 /* Nothing to do, as error code is already assigned to ERROR value */
288 }
289
290 /* Configure the USART Baud Rate :
291 - valid baud rate value (different from 0) is required
292 - Peripheral clock as returned by RCC service, should be valid (different from 0).
293 */
294 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
295 && (USART_InitStruct->BaudRate != 0U))
296 {
297 status = SUCCESS;
298 #if defined(USART_CR1_OVER8)
299 LL_USART_SetBaudRate(USARTx,
300 periphclk,
301 USART_InitStruct->OverSampling,
302 USART_InitStruct->BaudRate);
303 #else
304 LL_USART_SetBaudRate(USARTx,
305 periphclk,
306 USART_InitStruct->BaudRate);
307 #endif /* USART_OverSampling_Feature */
308
309 /* Check BRR is greater than or equal to 16d */
310 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
311 }
312 }
313 /* Endif (=> USART not in Disabled state => return ERROR) */
314
315 return (status);
316 }
317
318 /**
319 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
320 * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
321 * whose fields will be set to default values.
322 * @retval None
323 */
324
LL_USART_StructInit(LL_USART_InitTypeDef * USART_InitStruct)325 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
326 {
327 /* Set USART_InitStruct fields to default values */
328 USART_InitStruct->BaudRate = 9600U;
329 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
330 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
331 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
332 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
333 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
334 #if defined(USART_CR1_OVER8)
335 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
336 #endif /* USART_OverSampling_Feature */
337 }
338
339 /**
340 * @brief Initialize USART Clock related settings according to the
341 * specified parameters in the USART_ClockInitStruct.
342 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
343 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
344 * @param USARTx USART Instance
345 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
346 * that contains the Clock configuration information for the specified USART peripheral.
347 * @retval An ErrorStatus enumeration value:
348 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
349 * - ERROR: Problem occurred during USART Registers initialization
350 */
LL_USART_ClockInit(USART_TypeDef * USARTx,LL_USART_ClockInitTypeDef * USART_ClockInitStruct)351 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
352 {
353 ErrorStatus status = SUCCESS;
354
355 /* Check USART Instance and Clock signal output parameters */
356 assert_param(IS_UART_INSTANCE(USARTx));
357 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
358
359 /* USART needs to be in disabled state, in order to be able to configure some bits in
360 CRx registers */
361 if (LL_USART_IsEnabled(USARTx) == 0U)
362 {
363 /*---------------------------- USART CR2 Configuration -----------------------*/
364 /* If Clock signal has to be output */
365 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
366 {
367 /* Deactivate Clock signal delivery :
368 * - Disable Clock Output: USART_CR2_CLKEN cleared
369 */
370 LL_USART_DisableSCLKOutput(USARTx);
371 }
372 else
373 {
374 /* Ensure USART instance is USART capable */
375 assert_param(IS_USART_INSTANCE(USARTx));
376
377 /* Check clock related parameters */
378 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
379 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
380 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
381
382 /*---------------------------- USART CR2 Configuration -----------------------
383 * Configure USARTx CR2 (Clock signal related bits) with parameters:
384 * - Enable Clock Output: USART_CR2_CLKEN set
385 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
386 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
387 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
388 */
389 MODIFY_REG(USARTx->CR2,
390 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
391 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
392 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
393 }
394 }
395 /* Else (USART not in Disabled state => return ERROR */
396 else
397 {
398 status = ERROR;
399 }
400
401 return (status);
402 }
403
404 /**
405 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
406 * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
407 * whose fields will be set to default values.
408 * @retval None
409 */
LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef * USART_ClockInitStruct)410 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
411 {
412 /* Set LL_USART_ClockInitStruct fields with default values */
413 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
414 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
415 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
416 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
417 }
418
419 /**
420 * @}
421 */
422
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
432
433 /**
434 * @}
435 */
436
437 #endif /* USE_FULL_LL_DRIVER */
438
439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
440
441
