1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f1xx_ll_spi.h"
23 #include "stm32f1xx_ll_bus.h"
24 #include "stm32f1xx_ll_rcc.h"
25
26 #ifdef USE_FULL_ASSERT
27 #include "stm32_assert.h"
28 #else
29 #define assert_param(expr) ((void)0U)
30 #endif
31
32 /** @addtogroup STM32F1xx_LL_Driver
33 * @{
34 */
35
36 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
37
38 /** @addtogroup SPI_LL
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44
45 /* Private constants ---------------------------------------------------------*/
46 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
47 * @{
48 */
49 /* SPI registers Masks */
50 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
51 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
52 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
53 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
54 SPI_CR1_BIDIMODE)
55 /**
56 * @}
57 */
58
59 /* Private macros ------------------------------------------------------------*/
60 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
61 * @{
62 */
63 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
64 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
66 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
67
68 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
69 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
70
71 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
73
74 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
75 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
76
77 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
78 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
79
80 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
81 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
82 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
83
84 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
85 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
86 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
87 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
88 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
89 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
90 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
91 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
92
93 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
94 || ((__VALUE__) == LL_SPI_MSB_FIRST))
95
96 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
97 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
98
99 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
100
101 /**
102 * @}
103 */
104
105 /* Private function prototypes -----------------------------------------------*/
106
107 /* Exported functions --------------------------------------------------------*/
108 /** @addtogroup SPI_LL_Exported_Functions
109 * @{
110 */
111
112 /** @addtogroup SPI_LL_EF_Init
113 * @{
114 */
115
116 /**
117 * @brief De-initialize the SPI registers to their default reset values.
118 * @param SPIx SPI Instance
119 * @retval An ErrorStatus enumeration value:
120 * - SUCCESS: SPI registers are de-initialized
121 * - ERROR: SPI registers are not de-initialized
122 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)123 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
124 {
125 ErrorStatus status = ERROR;
126
127 /* Check the parameters */
128 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
129
130 #if defined(SPI1)
131 if (SPIx == SPI1)
132 {
133 /* Force reset of SPI clock */
134 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
135
136 /* Release reset of SPI clock */
137 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
138
139 status = SUCCESS;
140 }
141 #endif /* SPI1 */
142 #if defined(SPI2)
143 if (SPIx == SPI2)
144 {
145 /* Force reset of SPI clock */
146 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
147
148 /* Release reset of SPI clock */
149 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
150
151 status = SUCCESS;
152 }
153 #endif /* SPI2 */
154 #if defined(SPI3)
155 if (SPIx == SPI3)
156 {
157 /* Force reset of SPI clock */
158 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
159
160 /* Release reset of SPI clock */
161 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
162
163 status = SUCCESS;
164 }
165 #endif /* SPI3 */
166
167 return status;
168 }
169
170 /**
171 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
172 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
173 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
174 * @param SPIx SPI Instance
175 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
176 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
177 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)178 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
179 {
180 ErrorStatus status = ERROR;
181
182 /* Check the SPI Instance SPIx*/
183 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
184
185 /* Check the SPI parameters from SPI_InitStruct*/
186 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
187 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
188 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
189 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
190 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
191 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
192 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
193 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
194 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
195
196 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
197 {
198 /*---------------------------- SPIx CR1 Configuration ------------------------
199 * Configure SPIx CR1 with parameters:
200 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
201 * - Master/Slave Mode: SPI_CR1_MSTR bit
202 * - DataWidth: SPI_CR1_DFF bit
203 * - ClockPolarity: SPI_CR1_CPOL bit
204 * - ClockPhase: SPI_CR1_CPHA bit
205 * - NSS management: SPI_CR1_SSM bit
206 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
207 * - BitOrder: SPI_CR1_LSBFIRST bit
208 * - CRCCalculation: SPI_CR1_CRCEN bit
209 */
210 MODIFY_REG(SPIx->CR1,
211 SPI_CR1_CLEAR_MASK,
212 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
213 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
214 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
215 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
216
217 /*---------------------------- SPIx CR2 Configuration ------------------------
218 * Configure SPIx CR2 with parameters:
219 * - NSS management: SSOE bit
220 */
221 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
222
223 /*---------------------------- SPIx CRCPR Configuration ----------------------
224 * Configure SPIx CRCPR with parameters:
225 * - CRCPoly: CRCPOLY[15:0] bits
226 */
227 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
228 {
229 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
230 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
231 }
232 status = SUCCESS;
233 }
234
235 #if defined (SPI_I2S_SUPPORT)
236 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
237 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
238 #endif /* SPI_I2S_SUPPORT */
239 return status;
240 }
241
242 /**
243 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
244 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
245 * whose fields will be set to default values.
246 * @retval None
247 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)248 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
249 {
250 /* Set SPI_InitStruct fields to default values */
251 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
252 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
253 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
254 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
255 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
256 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
257 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
258 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
259 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
260 SPI_InitStruct->CRCPoly = 7U;
261 }
262
263 /**
264 * @}
265 */
266
267 /**
268 * @}
269 */
270
271 /**
272 * @}
273 */
274
275 #if defined(SPI_I2S_SUPPORT)
276 /** @addtogroup I2S_LL
277 * @{
278 */
279
280 /* Private types -------------------------------------------------------------*/
281 /* Private variables ---------------------------------------------------------*/
282 /* Private constants ---------------------------------------------------------*/
283 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
284 * @{
285 */
286 /* I2S registers Masks */
287 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
288 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
289 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
290
291 #define I2S_I2SPR_CLEAR_MASK 0x0002U
292 /**
293 * @}
294 */
295 /* Private macros ------------------------------------------------------------*/
296 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
297 * @{
298 */
299
300 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
301 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
302 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
303 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
304
305 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
306 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
307
308 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
309 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
310 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
311 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
312 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
313
314 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
315 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
316 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
317 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
318
319 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
320 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
321
322 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
323 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
324 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
325
326 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
327
328 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
329 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
330 /**
331 * @}
332 */
333
334 /* Private function prototypes -----------------------------------------------*/
335
336 /* Exported functions --------------------------------------------------------*/
337 /** @addtogroup I2S_LL_Exported_Functions
338 * @{
339 */
340
341 /** @addtogroup I2S_LL_EF_Init
342 * @{
343 */
344
345 /**
346 * @brief De-initialize the SPI/I2S registers to their default reset values.
347 * @param SPIx SPI Instance
348 * @retval An ErrorStatus enumeration value:
349 * - SUCCESS: SPI registers are de-initialized
350 * - ERROR: SPI registers are not de-initialized
351 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)352 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
353 {
354 return LL_SPI_DeInit(SPIx);
355 }
356
357 /**
358 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
359 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
360 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
361 * @param SPIx SPI Instance
362 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
363 * @retval An ErrorStatus enumeration value:
364 * - SUCCESS: SPI registers are Initialized
365 * - ERROR: SPI registers are not Initialized
366 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)367 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
368 {
369 uint32_t i2sdiv = 2U;
370 uint32_t i2sodd = 0U;
371 uint32_t packetlength = 1U;
372 uint32_t tmp;
373 LL_RCC_ClocksTypeDef rcc_clocks;
374 uint32_t sourceclock;
375 ErrorStatus status = ERROR;
376
377 /* Check the I2S parameters */
378 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
379 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
380 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
381 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
382 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
383 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
384 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
385
386 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
387 {
388 /*---------------------------- SPIx I2SCFGR Configuration --------------------
389 * Configure SPIx I2SCFGR with parameters:
390 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
391 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
392 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
393 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
394 */
395
396 /* Write to SPIx I2SCFGR */
397 MODIFY_REG(SPIx->I2SCFGR,
398 I2S_I2SCFGR_CLEAR_MASK,
399 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
400 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
401 SPI_I2SCFGR_I2SMOD);
402
403 /*---------------------------- SPIx I2SPR Configuration ----------------------
404 * Configure SPIx I2SPR with parameters:
405 * - MCLKOutput: SPI_I2SPR_MCKOE bit
406 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
407 */
408
409 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
410 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
411 */
412 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
413 {
414 /* Check the frame length (For the Prescaler computing)
415 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
416 */
417 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
418 {
419 /* Packet length is 32 bits */
420 packetlength = 2U;
421 }
422
423 /* I2S Clock source is System clock: Get System Clock frequency */
424 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
425
426 /* Get the source clock value: based on System Clock value */
427 sourceclock = rcc_clocks.SYSCLK_Frequency;
428
429 /* Compute the Real divider depending on the MCLK output state with a floating point */
430 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
431 {
432 /* MCLK output is enabled */
433 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
434 }
435 else
436 {
437 /* MCLK output is disabled */
438 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
439 }
440
441 /* Remove the floating point */
442 tmp = tmp / 10U;
443
444 /* Check the parity of the divider */
445 i2sodd = (tmp & (uint16_t)0x0001U);
446
447 /* Compute the i2sdiv prescaler */
448 i2sdiv = ((tmp - i2sodd) / 2U);
449
450 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
451 i2sodd = (i2sodd << 8U);
452 }
453
454 /* Test if the divider is 1 or 0 or greater than 0xFF */
455 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
456 {
457 /* Set the default values */
458 i2sdiv = 2U;
459 i2sodd = 0U;
460 }
461
462 /* Write to SPIx I2SPR register the computed value */
463 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
464
465 status = SUCCESS;
466 }
467 return status;
468 }
469
470 /**
471 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
472 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
473 * whose fields will be set to default values.
474 * @retval None
475 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)476 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
477 {
478 /*--------------- Reset I2S init structure parameters values -----------------*/
479 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
480 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
481 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
482 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
483 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
484 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
485 }
486
487 /**
488 * @brief Set linear and parity prescaler.
489 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
490 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
491 * @param SPIx SPI Instance
492 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
493 * @param PrescalerParity This parameter can be one of the following values:
494 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
495 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
496 * @retval None
497 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)498 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
499 {
500 /* Check the I2S parameters */
501 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
502 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
503 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
504
505 /* Write to SPIx I2SPR */
506 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
507 }
508
509 /**
510 * @}
511 */
512
513 /**
514 * @}
515 */
516
517 /**
518 * @}
519 */
520 #endif /* SPI_I2S_SUPPORT */
521
522 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
523
524 /**
525 * @}
526 */
527
528 #endif /* USE_FULL_LL_DRIVER */
529
530 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
531
