1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145
146 [..]
147 By default, after the Init and when the state is HAL_TIM_STATE_RESET
148 all interrupt callbacks are set to the corresponding weak functions:
149 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
150
151 [..]
152 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
153 functionalities in the Init / DeInit only when these callbacks are null
154 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
155 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
156
157 [..]
158 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
159 Exception done MspInit / MspDeInit that can be registered / unregistered
160 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
161 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
162 In that case first register the MspInit/MspDeInit user callbacks
163 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
164
165 [..]
166 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
167 not defined, the callback registration feature is not available and all callbacks
168 are set to the corresponding weak functions.
169
170 @endverbatim
171 ******************************************************************************
172 * @attention
173 *
174 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
175 * All rights reserved.</center></h2>
176 *
177 * This software component is licensed by ST under BSD 3-Clause license,
178 * the "License"; You may not use this file except in compliance with the
179 * License. You may obtain a copy of the License at:
180 * opensource.org/licenses/BSD-3-Clause
181 *
182 ******************************************************************************
183 */
184
185 /* Includes ------------------------------------------------------------------*/
186 #include "stm32f1xx_hal.h"
187
188 /** @addtogroup STM32F1xx_HAL_Driver
189 * @{
190 */
191
192 /** @defgroup TIM TIM
193 * @brief TIM HAL module driver
194 * @{
195 */
196
197 #ifdef HAL_TIM_MODULE_ENABLED
198
199 /* Private typedef -----------------------------------------------------------*/
200 /* Private define ------------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
202 /* Private variables ---------------------------------------------------------*/
203 /* Private function prototypes -----------------------------------------------*/
204 /** @addtogroup TIM_Private_Functions
205 * @{
206 */
207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
211 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
212 uint32_t TIM_ICFilter);
213 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
219 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
220 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
221 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
224 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
225 TIM_SlaveConfigTypeDef *sSlaveConfig);
226 /**
227 * @}
228 */
229 /* Exported functions --------------------------------------------------------*/
230
231 /** @defgroup TIM_Exported_Functions TIM Exported Functions
232 * @{
233 */
234
235 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
236 * @brief Time Base functions
237 *
238 @verbatim
239 ==============================================================================
240 ##### Time Base functions #####
241 ==============================================================================
242 [..]
243 This section provides functions allowing to:
244 (+) Initialize and configure the TIM base.
245 (+) De-initialize the TIM base.
246 (+) Start the Time Base.
247 (+) Stop the Time Base.
248 (+) Start the Time Base and enable interrupt.
249 (+) Stop the Time Base and disable interrupt.
250 (+) Start the Time Base and enable DMA transfer.
251 (+) Stop the Time Base and disable DMA transfer.
252
253 @endverbatim
254 * @{
255 */
256 /**
257 * @brief Initializes the TIM Time base Unit according to the specified
258 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
259 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
260 * requires a timer reset to avoid unexpected direction
261 * due to DIR bit readonly in center aligned mode.
262 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
263 * @param htim TIM Base handle
264 * @retval HAL status
265 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)266 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
267 {
268 /* Check the TIM handle allocation */
269 if (htim == NULL)
270 {
271 return HAL_ERROR;
272 }
273
274 /* Check the parameters */
275 assert_param(IS_TIM_INSTANCE(htim->Instance));
276 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
277 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
278 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
279
280 if (htim->State == HAL_TIM_STATE_RESET)
281 {
282 /* Allocate lock resource and initialize it */
283 htim->Lock = HAL_UNLOCKED;
284
285 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
286 /* Reset interrupt callbacks to legacy weak callbacks */
287 TIM_ResetCallback(htim);
288
289 if (htim->Base_MspInitCallback == NULL)
290 {
291 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
292 }
293 /* Init the low level hardware : GPIO, CLOCK, NVIC */
294 htim->Base_MspInitCallback(htim);
295 #else
296 /* Init the low level hardware : GPIO, CLOCK, NVIC */
297 HAL_TIM_Base_MspInit(htim);
298 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
299 }
300
301 /* Set the TIM state */
302 htim->State = HAL_TIM_STATE_BUSY;
303
304 /* Set the Time Base configuration */
305 TIM_Base_SetConfig(htim->Instance, &htim->Init);
306
307 /* Initialize the DMA burst operation state */
308 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
309
310 /* Initialize the TIM channels state */
311 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
312 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
313
314 /* Initialize the TIM state*/
315 htim->State = HAL_TIM_STATE_READY;
316
317 return HAL_OK;
318 }
319
320 /**
321 * @brief DeInitializes the TIM Base peripheral
322 * @param htim TIM Base handle
323 * @retval HAL status
324 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)325 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
326 {
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(htim->Instance));
329
330 htim->State = HAL_TIM_STATE_BUSY;
331
332 /* Disable the TIM Peripheral Clock */
333 __HAL_TIM_DISABLE(htim);
334
335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
336 if (htim->Base_MspDeInitCallback == NULL)
337 {
338 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
339 }
340 /* DeInit the low level hardware */
341 htim->Base_MspDeInitCallback(htim);
342 #else
343 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
344 HAL_TIM_Base_MspDeInit(htim);
345 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
346
347 /* Change the DMA burst operation state */
348 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
349
350 /* Change the TIM channels state */
351 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
352 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
353
354 /* Change TIM state */
355 htim->State = HAL_TIM_STATE_RESET;
356
357 /* Release Lock */
358 __HAL_UNLOCK(htim);
359
360 return HAL_OK;
361 }
362
363 /**
364 * @brief Initializes the TIM Base MSP.
365 * @param htim TIM Base handle
366 * @retval None
367 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)368 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
369 {
370 /* Prevent unused argument(s) compilation warning */
371 UNUSED(htim);
372
373 /* NOTE : This function should not be modified, when the callback is needed,
374 the HAL_TIM_Base_MspInit could be implemented in the user file
375 */
376 }
377
378 /**
379 * @brief DeInitializes TIM Base MSP.
380 * @param htim TIM Base handle
381 * @retval None
382 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)383 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
384 {
385 /* Prevent unused argument(s) compilation warning */
386 UNUSED(htim);
387
388 /* NOTE : This function should not be modified, when the callback is needed,
389 the HAL_TIM_Base_MspDeInit could be implemented in the user file
390 */
391 }
392
393
394 /**
395 * @brief Starts the TIM Base generation.
396 * @param htim TIM Base handle
397 * @retval HAL status
398 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)399 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
400 {
401 uint32_t tmpsmcr;
402
403 /* Check the parameters */
404 assert_param(IS_TIM_INSTANCE(htim->Instance));
405
406 /* Check the TIM state */
407 if (htim->State != HAL_TIM_STATE_READY)
408 {
409 return HAL_ERROR;
410 }
411
412 /* Set the TIM state */
413 htim->State = HAL_TIM_STATE_BUSY;
414
415 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
416 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
417 {
418 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
419 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
420 {
421 __HAL_TIM_ENABLE(htim);
422 }
423 }
424 else
425 {
426 __HAL_TIM_ENABLE(htim);
427 }
428
429 /* Return function status */
430 return HAL_OK;
431 }
432
433 /**
434 * @brief Stops the TIM Base generation.
435 * @param htim TIM Base handle
436 * @retval HAL status
437 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)438 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
439 {
440 /* Check the parameters */
441 assert_param(IS_TIM_INSTANCE(htim->Instance));
442
443 /* Disable the Peripheral */
444 __HAL_TIM_DISABLE(htim);
445
446 /* Set the TIM state */
447 htim->State = HAL_TIM_STATE_READY;
448
449 /* Return function status */
450 return HAL_OK;
451 }
452
453 /**
454 * @brief Starts the TIM Base generation in interrupt mode.
455 * @param htim TIM Base handle
456 * @retval HAL status
457 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)458 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
459 {
460 uint32_t tmpsmcr;
461
462 /* Check the parameters */
463 assert_param(IS_TIM_INSTANCE(htim->Instance));
464
465 /* Check the TIM state */
466 if (htim->State != HAL_TIM_STATE_READY)
467 {
468 return HAL_ERROR;
469 }
470
471 /* Set the TIM state */
472 htim->State = HAL_TIM_STATE_BUSY;
473
474 /* Enable the TIM Update interrupt */
475 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
476
477 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
478 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
479 {
480 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
481 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
482 {
483 __HAL_TIM_ENABLE(htim);
484 }
485 }
486 else
487 {
488 __HAL_TIM_ENABLE(htim);
489 }
490
491 /* Return function status */
492 return HAL_OK;
493 }
494
495 /**
496 * @brief Stops the TIM Base generation in interrupt mode.
497 * @param htim TIM Base handle
498 * @retval HAL status
499 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)500 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
501 {
502 /* Check the parameters */
503 assert_param(IS_TIM_INSTANCE(htim->Instance));
504
505 /* Disable the TIM Update interrupt */
506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
507
508 /* Disable the Peripheral */
509 __HAL_TIM_DISABLE(htim);
510
511 /* Set the TIM state */
512 htim->State = HAL_TIM_STATE_READY;
513
514 /* Return function status */
515 return HAL_OK;
516 }
517
518 /**
519 * @brief Starts the TIM Base generation in DMA mode.
520 * @param htim TIM Base handle
521 * @param pData The source Buffer address.
522 * @param Length The length of data to be transferred from memory to peripheral.
523 * @retval HAL status
524 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)525 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
526 {
527 uint32_t tmpsmcr;
528
529 /* Check the parameters */
530 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
531
532 /* Set the TIM state */
533 if (htim->State == HAL_TIM_STATE_BUSY)
534 {
535 return HAL_BUSY;
536 }
537 else if (htim->State == HAL_TIM_STATE_READY)
538 {
539 if ((pData == NULL) && (Length > 0U))
540 {
541 return HAL_ERROR;
542 }
543 else
544 {
545 htim->State = HAL_TIM_STATE_BUSY;
546 }
547 }
548 else
549 {
550 return HAL_ERROR;
551 }
552
553 /* Set the DMA Period elapsed callbacks */
554 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
555 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
556
557 /* Set the DMA error callback */
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
559
560 /* Enable the DMA channel */
561 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
562 Length) != HAL_OK)
563 {
564 /* Return error status */
565 return HAL_ERROR;
566 }
567
568 /* Enable the TIM Update DMA request */
569 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
570
571 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
572 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
573 {
574 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
575 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
576 {
577 __HAL_TIM_ENABLE(htim);
578 }
579 }
580 else
581 {
582 __HAL_TIM_ENABLE(htim);
583 }
584
585 /* Return function status */
586 return HAL_OK;
587 }
588
589 /**
590 * @brief Stops the TIM Base generation in DMA mode.
591 * @param htim TIM Base handle
592 * @retval HAL status
593 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)594 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
595 {
596 /* Check the parameters */
597 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
598
599 /* Disable the TIM Update DMA request */
600 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
601
602 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
603
604 /* Disable the Peripheral */
605 __HAL_TIM_DISABLE(htim);
606
607 /* Set the TIM state */
608 htim->State = HAL_TIM_STATE_READY;
609
610 /* Return function status */
611 return HAL_OK;
612 }
613
614 /**
615 * @}
616 */
617
618 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
619 * @brief TIM Output Compare functions
620 *
621 @verbatim
622 ==============================================================================
623 ##### TIM Output Compare functions #####
624 ==============================================================================
625 [..]
626 This section provides functions allowing to:
627 (+) Initialize and configure the TIM Output Compare.
628 (+) De-initialize the TIM Output Compare.
629 (+) Start the TIM Output Compare.
630 (+) Stop the TIM Output Compare.
631 (+) Start the TIM Output Compare and enable interrupt.
632 (+) Stop the TIM Output Compare and disable interrupt.
633 (+) Start the TIM Output Compare and enable DMA transfer.
634 (+) Stop the TIM Output Compare and disable DMA transfer.
635
636 @endverbatim
637 * @{
638 */
639 /**
640 * @brief Initializes the TIM Output Compare according to the specified
641 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
642 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
643 * requires a timer reset to avoid unexpected direction
644 * due to DIR bit readonly in center aligned mode.
645 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
646 * @param htim TIM Output Compare handle
647 * @retval HAL status
648 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)649 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
650 {
651 /* Check the TIM handle allocation */
652 if (htim == NULL)
653 {
654 return HAL_ERROR;
655 }
656
657 /* Check the parameters */
658 assert_param(IS_TIM_INSTANCE(htim->Instance));
659 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
660 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
661 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
662
663 if (htim->State == HAL_TIM_STATE_RESET)
664 {
665 /* Allocate lock resource and initialize it */
666 htim->Lock = HAL_UNLOCKED;
667
668 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
669 /* Reset interrupt callbacks to legacy weak callbacks */
670 TIM_ResetCallback(htim);
671
672 if (htim->OC_MspInitCallback == NULL)
673 {
674 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
675 }
676 /* Init the low level hardware : GPIO, CLOCK, NVIC */
677 htim->OC_MspInitCallback(htim);
678 #else
679 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
680 HAL_TIM_OC_MspInit(htim);
681 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
682 }
683
684 /* Set the TIM state */
685 htim->State = HAL_TIM_STATE_BUSY;
686
687 /* Init the base time for the Output Compare */
688 TIM_Base_SetConfig(htim->Instance, &htim->Init);
689
690 /* Initialize the DMA burst operation state */
691 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
692
693 /* Initialize the TIM channels state */
694 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
695 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
696
697 /* Initialize the TIM state*/
698 htim->State = HAL_TIM_STATE_READY;
699
700 return HAL_OK;
701 }
702
703 /**
704 * @brief DeInitializes the TIM peripheral
705 * @param htim TIM Output Compare handle
706 * @retval HAL status
707 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)708 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
709 {
710 /* Check the parameters */
711 assert_param(IS_TIM_INSTANCE(htim->Instance));
712
713 htim->State = HAL_TIM_STATE_BUSY;
714
715 /* Disable the TIM Peripheral Clock */
716 __HAL_TIM_DISABLE(htim);
717
718 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
719 if (htim->OC_MspDeInitCallback == NULL)
720 {
721 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
722 }
723 /* DeInit the low level hardware */
724 htim->OC_MspDeInitCallback(htim);
725 #else
726 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
727 HAL_TIM_OC_MspDeInit(htim);
728 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
729
730 /* Change the DMA burst operation state */
731 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
732
733 /* Change the TIM channels state */
734 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
735 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
736
737 /* Change TIM state */
738 htim->State = HAL_TIM_STATE_RESET;
739
740 /* Release Lock */
741 __HAL_UNLOCK(htim);
742
743 return HAL_OK;
744 }
745
746 /**
747 * @brief Initializes the TIM Output Compare MSP.
748 * @param htim TIM Output Compare handle
749 * @retval None
750 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)751 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
752 {
753 /* Prevent unused argument(s) compilation warning */
754 UNUSED(htim);
755
756 /* NOTE : This function should not be modified, when the callback is needed,
757 the HAL_TIM_OC_MspInit could be implemented in the user file
758 */
759 }
760
761 /**
762 * @brief DeInitializes TIM Output Compare MSP.
763 * @param htim TIM Output Compare handle
764 * @retval None
765 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)766 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
767 {
768 /* Prevent unused argument(s) compilation warning */
769 UNUSED(htim);
770
771 /* NOTE : This function should not be modified, when the callback is needed,
772 the HAL_TIM_OC_MspDeInit could be implemented in the user file
773 */
774 }
775
776 /**
777 * @brief Starts the TIM Output Compare signal generation.
778 * @param htim TIM Output Compare handle
779 * @param Channel TIM Channel to be enabled
780 * This parameter can be one of the following values:
781 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
782 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
783 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
784 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
785 * @retval HAL status
786 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)787 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
788 {
789 uint32_t tmpsmcr;
790
791 /* Check the parameters */
792 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
793
794 /* Check the TIM channel state */
795 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
796 {
797 return HAL_ERROR;
798 }
799
800 /* Set the TIM channel state */
801 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
802
803 /* Enable the Output compare channel */
804 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
805
806 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
807 {
808 /* Enable the main output */
809 __HAL_TIM_MOE_ENABLE(htim);
810 }
811
812 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
813 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
814 {
815 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
816 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
817 {
818 __HAL_TIM_ENABLE(htim);
819 }
820 }
821 else
822 {
823 __HAL_TIM_ENABLE(htim);
824 }
825
826 /* Return function status */
827 return HAL_OK;
828 }
829
830 /**
831 * @brief Stops the TIM Output Compare signal generation.
832 * @param htim TIM Output Compare handle
833 * @param Channel TIM Channel to be disabled
834 * This parameter can be one of the following values:
835 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
836 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
837 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
838 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
839 * @retval HAL status
840 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)841 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
842 {
843 /* Check the parameters */
844 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
845
846 /* Disable the Output compare channel */
847 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
848
849 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
850 {
851 /* Disable the Main Output */
852 __HAL_TIM_MOE_DISABLE(htim);
853 }
854
855 /* Disable the Peripheral */
856 __HAL_TIM_DISABLE(htim);
857
858 /* Set the TIM channel state */
859 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
860
861 /* Return function status */
862 return HAL_OK;
863 }
864
865 /**
866 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
867 * @param htim TIM Output Compare handle
868 * @param Channel TIM Channel to be enabled
869 * This parameter can be one of the following values:
870 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
871 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
872 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
873 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
874 * @retval HAL status
875 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)876 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
877 {
878 uint32_t tmpsmcr;
879
880 /* Check the parameters */
881 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
882
883 /* Check the TIM channel state */
884 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
885 {
886 return HAL_ERROR;
887 }
888
889 /* Set the TIM channel state */
890 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
891
892 switch (Channel)
893 {
894 case TIM_CHANNEL_1:
895 {
896 /* Enable the TIM Capture/Compare 1 interrupt */
897 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
898 break;
899 }
900
901 case TIM_CHANNEL_2:
902 {
903 /* Enable the TIM Capture/Compare 2 interrupt */
904 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
905 break;
906 }
907
908 case TIM_CHANNEL_3:
909 {
910 /* Enable the TIM Capture/Compare 3 interrupt */
911 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
912 break;
913 }
914
915 case TIM_CHANNEL_4:
916 {
917 /* Enable the TIM Capture/Compare 4 interrupt */
918 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
919 break;
920 }
921
922 default:
923 break;
924 }
925
926 /* Enable the Output compare channel */
927 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
928
929 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
930 {
931 /* Enable the main output */
932 __HAL_TIM_MOE_ENABLE(htim);
933 }
934
935 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
936 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
937 {
938 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
939 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
940 {
941 __HAL_TIM_ENABLE(htim);
942 }
943 }
944 else
945 {
946 __HAL_TIM_ENABLE(htim);
947 }
948
949 /* Return function status */
950 return HAL_OK;
951 }
952
953 /**
954 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
955 * @param htim TIM Output Compare handle
956 * @param Channel TIM Channel to be disabled
957 * This parameter can be one of the following values:
958 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
959 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
960 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
961 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
962 * @retval HAL status
963 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)964 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
965 {
966 /* Check the parameters */
967 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
968
969 switch (Channel)
970 {
971 case TIM_CHANNEL_1:
972 {
973 /* Disable the TIM Capture/Compare 1 interrupt */
974 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
975 break;
976 }
977
978 case TIM_CHANNEL_2:
979 {
980 /* Disable the TIM Capture/Compare 2 interrupt */
981 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
982 break;
983 }
984
985 case TIM_CHANNEL_3:
986 {
987 /* Disable the TIM Capture/Compare 3 interrupt */
988 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
989 break;
990 }
991
992 case TIM_CHANNEL_4:
993 {
994 /* Disable the TIM Capture/Compare 4 interrupt */
995 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
996 break;
997 }
998
999 default:
1000 break;
1001 }
1002
1003 /* Disable the Output compare channel */
1004 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1005
1006 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1007 {
1008 /* Disable the Main Output */
1009 __HAL_TIM_MOE_DISABLE(htim);
1010 }
1011
1012 /* Disable the Peripheral */
1013 __HAL_TIM_DISABLE(htim);
1014
1015 /* Set the TIM channel state */
1016 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1017
1018 /* Return function status */
1019 return HAL_OK;
1020 }
1021
1022 /**
1023 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1024 * @param htim TIM Output Compare handle
1025 * @param Channel TIM Channel to be enabled
1026 * This parameter can be one of the following values:
1027 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1028 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1029 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1030 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1031 * @param pData The source Buffer address.
1032 * @param Length The length of data to be transferred from memory to TIM peripheral
1033 * @retval HAL status
1034 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1035 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1036 {
1037 uint32_t tmpsmcr;
1038
1039 /* Check the parameters */
1040 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1041
1042 /* Set the TIM channel state */
1043 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1044 {
1045 return HAL_BUSY;
1046 }
1047 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1048 {
1049 if ((pData == NULL) && (Length > 0U))
1050 {
1051 return HAL_ERROR;
1052 }
1053 else
1054 {
1055 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1056 }
1057 }
1058 else
1059 {
1060 return HAL_ERROR;
1061 }
1062
1063 switch (Channel)
1064 {
1065 case TIM_CHANNEL_1:
1066 {
1067 /* Set the DMA compare callbacks */
1068 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1069 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1070
1071 /* Set the DMA error callback */
1072 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1073
1074 /* Enable the DMA channel */
1075 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1076 Length) != HAL_OK)
1077 {
1078 /* Return error status */
1079 return HAL_ERROR;
1080 }
1081
1082 /* Enable the TIM Capture/Compare 1 DMA request */
1083 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1084 break;
1085 }
1086
1087 case TIM_CHANNEL_2:
1088 {
1089 /* Set the DMA compare callbacks */
1090 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1091 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1092
1093 /* Set the DMA error callback */
1094 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1095
1096 /* Enable the DMA channel */
1097 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1098 Length) != HAL_OK)
1099 {
1100 /* Return error status */
1101 return HAL_ERROR;
1102 }
1103
1104 /* Enable the TIM Capture/Compare 2 DMA request */
1105 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1106 break;
1107 }
1108
1109 case TIM_CHANNEL_3:
1110 {
1111 /* Set the DMA compare callbacks */
1112 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1113 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1114
1115 /* Set the DMA error callback */
1116 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1117
1118 /* Enable the DMA channel */
1119 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1120 Length) != HAL_OK)
1121 {
1122 /* Return error status */
1123 return HAL_ERROR;
1124 }
1125 /* Enable the TIM Capture/Compare 3 DMA request */
1126 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1127 break;
1128 }
1129
1130 case TIM_CHANNEL_4:
1131 {
1132 /* Set the DMA compare callbacks */
1133 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1134 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1135
1136 /* Set the DMA error callback */
1137 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1138
1139 /* Enable the DMA channel */
1140 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1141 Length) != HAL_OK)
1142 {
1143 /* Return error status */
1144 return HAL_ERROR;
1145 }
1146 /* Enable the TIM Capture/Compare 4 DMA request */
1147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1148 break;
1149 }
1150
1151 default:
1152 break;
1153 }
1154
1155 /* Enable the Output compare channel */
1156 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1157
1158 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1159 {
1160 /* Enable the main output */
1161 __HAL_TIM_MOE_ENABLE(htim);
1162 }
1163
1164 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1165 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1166 {
1167 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1168 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1169 {
1170 __HAL_TIM_ENABLE(htim);
1171 }
1172 }
1173 else
1174 {
1175 __HAL_TIM_ENABLE(htim);
1176 }
1177
1178 /* Return function status */
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1184 * @param htim TIM Output Compare handle
1185 * @param Channel TIM Channel to be disabled
1186 * This parameter can be one of the following values:
1187 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1188 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1189 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1190 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1191 * @retval HAL status
1192 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1193 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1194 {
1195 /* Check the parameters */
1196 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1197
1198 switch (Channel)
1199 {
1200 case TIM_CHANNEL_1:
1201 {
1202 /* Disable the TIM Capture/Compare 1 DMA request */
1203 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1204 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1205 break;
1206 }
1207
1208 case TIM_CHANNEL_2:
1209 {
1210 /* Disable the TIM Capture/Compare 2 DMA request */
1211 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1212 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1213 break;
1214 }
1215
1216 case TIM_CHANNEL_3:
1217 {
1218 /* Disable the TIM Capture/Compare 3 DMA request */
1219 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1220 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1221 break;
1222 }
1223
1224 case TIM_CHANNEL_4:
1225 {
1226 /* Disable the TIM Capture/Compare 4 interrupt */
1227 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1228 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1229 break;
1230 }
1231
1232 default:
1233 break;
1234 }
1235
1236 /* Disable the Output compare channel */
1237 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1238
1239 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1240 {
1241 /* Disable the Main Output */
1242 __HAL_TIM_MOE_DISABLE(htim);
1243 }
1244
1245 /* Disable the Peripheral */
1246 __HAL_TIM_DISABLE(htim);
1247
1248 /* Set the TIM channel state */
1249 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1250
1251 /* Return function status */
1252 return HAL_OK;
1253 }
1254
1255 /**
1256 * @}
1257 */
1258
1259 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1260 * @brief TIM PWM functions
1261 *
1262 @verbatim
1263 ==============================================================================
1264 ##### TIM PWM functions #####
1265 ==============================================================================
1266 [..]
1267 This section provides functions allowing to:
1268 (+) Initialize and configure the TIM PWM.
1269 (+) De-initialize the TIM PWM.
1270 (+) Start the TIM PWM.
1271 (+) Stop the TIM PWM.
1272 (+) Start the TIM PWM and enable interrupt.
1273 (+) Stop the TIM PWM and disable interrupt.
1274 (+) Start the TIM PWM and enable DMA transfer.
1275 (+) Stop the TIM PWM and disable DMA transfer.
1276
1277 @endverbatim
1278 * @{
1279 */
1280 /**
1281 * @brief Initializes the TIM PWM Time Base according to the specified
1282 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1283 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1284 * requires a timer reset to avoid unexpected direction
1285 * due to DIR bit readonly in center aligned mode.
1286 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1287 * @param htim TIM PWM handle
1288 * @retval HAL status
1289 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1290 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1291 {
1292 /* Check the TIM handle allocation */
1293 if (htim == NULL)
1294 {
1295 return HAL_ERROR;
1296 }
1297
1298 /* Check the parameters */
1299 assert_param(IS_TIM_INSTANCE(htim->Instance));
1300 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1301 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1302 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1303
1304 if (htim->State == HAL_TIM_STATE_RESET)
1305 {
1306 /* Allocate lock resource and initialize it */
1307 htim->Lock = HAL_UNLOCKED;
1308
1309 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1310 /* Reset interrupt callbacks to legacy weak callbacks */
1311 TIM_ResetCallback(htim);
1312
1313 if (htim->PWM_MspInitCallback == NULL)
1314 {
1315 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1316 }
1317 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1318 htim->PWM_MspInitCallback(htim);
1319 #else
1320 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1321 HAL_TIM_PWM_MspInit(htim);
1322 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1323 }
1324
1325 /* Set the TIM state */
1326 htim->State = HAL_TIM_STATE_BUSY;
1327
1328 /* Init the base time for the PWM */
1329 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1330
1331 /* Initialize the DMA burst operation state */
1332 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1333
1334 /* Initialize the TIM channels state */
1335 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1336 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1337
1338 /* Initialize the TIM state*/
1339 htim->State = HAL_TIM_STATE_READY;
1340
1341 return HAL_OK;
1342 }
1343
1344 /**
1345 * @brief DeInitializes the TIM peripheral
1346 * @param htim TIM PWM handle
1347 * @retval HAL status
1348 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1349 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1350 {
1351 /* Check the parameters */
1352 assert_param(IS_TIM_INSTANCE(htim->Instance));
1353
1354 htim->State = HAL_TIM_STATE_BUSY;
1355
1356 /* Disable the TIM Peripheral Clock */
1357 __HAL_TIM_DISABLE(htim);
1358
1359 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1360 if (htim->PWM_MspDeInitCallback == NULL)
1361 {
1362 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1363 }
1364 /* DeInit the low level hardware */
1365 htim->PWM_MspDeInitCallback(htim);
1366 #else
1367 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1368 HAL_TIM_PWM_MspDeInit(htim);
1369 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1370
1371 /* Change the DMA burst operation state */
1372 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1373
1374 /* Change the TIM channels state */
1375 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1376 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1377
1378 /* Change TIM state */
1379 htim->State = HAL_TIM_STATE_RESET;
1380
1381 /* Release Lock */
1382 __HAL_UNLOCK(htim);
1383
1384 return HAL_OK;
1385 }
1386
1387 /**
1388 * @brief Initializes the TIM PWM MSP.
1389 * @param htim TIM PWM handle
1390 * @retval None
1391 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1392 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1393 {
1394 /* Prevent unused argument(s) compilation warning */
1395 UNUSED(htim);
1396
1397 /* NOTE : This function should not be modified, when the callback is needed,
1398 the HAL_TIM_PWM_MspInit could be implemented in the user file
1399 */
1400 }
1401
1402 /**
1403 * @brief DeInitializes TIM PWM MSP.
1404 * @param htim TIM PWM handle
1405 * @retval None
1406 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1407 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1408 {
1409 /* Prevent unused argument(s) compilation warning */
1410 UNUSED(htim);
1411
1412 /* NOTE : This function should not be modified, when the callback is needed,
1413 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1414 */
1415 }
1416
1417 /**
1418 * @brief Starts the PWM signal generation.
1419 * @param htim TIM handle
1420 * @param Channel TIM Channels to be enabled
1421 * This parameter can be one of the following values:
1422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1424 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1425 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1426 * @retval HAL status
1427 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1428 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1429 {
1430 uint32_t tmpsmcr;
1431
1432 /* Check the parameters */
1433 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1434
1435 /* Check the TIM channel state */
1436 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1437 {
1438 return HAL_ERROR;
1439 }
1440
1441 /* Set the TIM channel state */
1442 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1443
1444 /* Enable the Capture compare channel */
1445 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1446
1447 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1448 {
1449 /* Enable the main output */
1450 __HAL_TIM_MOE_ENABLE(htim);
1451 }
1452
1453 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1454 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1455 {
1456 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1457 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1458 {
1459 __HAL_TIM_ENABLE(htim);
1460 }
1461 }
1462 else
1463 {
1464 __HAL_TIM_ENABLE(htim);
1465 }
1466
1467 /* Return function status */
1468 return HAL_OK;
1469 }
1470
1471 /**
1472 * @brief Stops the PWM signal generation.
1473 * @param htim TIM PWM handle
1474 * @param Channel TIM Channels to be disabled
1475 * This parameter can be one of the following values:
1476 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1477 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1478 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1479 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1480 * @retval HAL status
1481 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1482 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1483 {
1484 /* Check the parameters */
1485 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1486
1487 /* Disable the Capture compare channel */
1488 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1489
1490 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1491 {
1492 /* Disable the Main Output */
1493 __HAL_TIM_MOE_DISABLE(htim);
1494 }
1495
1496 /* Disable the Peripheral */
1497 __HAL_TIM_DISABLE(htim);
1498
1499 /* Set the TIM channel state */
1500 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1501
1502 /* Return function status */
1503 return HAL_OK;
1504 }
1505
1506 /**
1507 * @brief Starts the PWM signal generation in interrupt mode.
1508 * @param htim TIM PWM handle
1509 * @param Channel TIM Channel to be enabled
1510 * This parameter can be one of the following values:
1511 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1512 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1513 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1514 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1515 * @retval HAL status
1516 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1517 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1518 {
1519 uint32_t tmpsmcr;
1520 /* Check the parameters */
1521 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1522
1523 /* Check the TIM channel state */
1524 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1525 {
1526 return HAL_ERROR;
1527 }
1528
1529 /* Set the TIM channel state */
1530 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1531
1532 switch (Channel)
1533 {
1534 case TIM_CHANNEL_1:
1535 {
1536 /* Enable the TIM Capture/Compare 1 interrupt */
1537 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1538 break;
1539 }
1540
1541 case TIM_CHANNEL_2:
1542 {
1543 /* Enable the TIM Capture/Compare 2 interrupt */
1544 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1545 break;
1546 }
1547
1548 case TIM_CHANNEL_3:
1549 {
1550 /* Enable the TIM Capture/Compare 3 interrupt */
1551 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1552 break;
1553 }
1554
1555 case TIM_CHANNEL_4:
1556 {
1557 /* Enable the TIM Capture/Compare 4 interrupt */
1558 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1559 break;
1560 }
1561
1562 default:
1563 break;
1564 }
1565
1566 /* Enable the Capture compare channel */
1567 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1568
1569 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1570 {
1571 /* Enable the main output */
1572 __HAL_TIM_MOE_ENABLE(htim);
1573 }
1574
1575 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1576 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1577 {
1578 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1579 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1580 {
1581 __HAL_TIM_ENABLE(htim);
1582 }
1583 }
1584 else
1585 {
1586 __HAL_TIM_ENABLE(htim);
1587 }
1588
1589 /* Return function status */
1590 return HAL_OK;
1591 }
1592
1593 /**
1594 * @brief Stops the PWM signal generation in interrupt mode.
1595 * @param htim TIM PWM handle
1596 * @param Channel TIM Channels to be disabled
1597 * This parameter can be one of the following values:
1598 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1599 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1600 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1601 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1602 * @retval HAL status
1603 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1604 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1605 {
1606 /* Check the parameters */
1607 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1608
1609 switch (Channel)
1610 {
1611 case TIM_CHANNEL_1:
1612 {
1613 /* Disable the TIM Capture/Compare 1 interrupt */
1614 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1615 break;
1616 }
1617
1618 case TIM_CHANNEL_2:
1619 {
1620 /* Disable the TIM Capture/Compare 2 interrupt */
1621 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1622 break;
1623 }
1624
1625 case TIM_CHANNEL_3:
1626 {
1627 /* Disable the TIM Capture/Compare 3 interrupt */
1628 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1629 break;
1630 }
1631
1632 case TIM_CHANNEL_4:
1633 {
1634 /* Disable the TIM Capture/Compare 4 interrupt */
1635 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1636 break;
1637 }
1638
1639 default:
1640 break;
1641 }
1642
1643 /* Disable the Capture compare channel */
1644 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1645
1646 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1647 {
1648 /* Disable the Main Output */
1649 __HAL_TIM_MOE_DISABLE(htim);
1650 }
1651
1652 /* Disable the Peripheral */
1653 __HAL_TIM_DISABLE(htim);
1654
1655 /* Set the TIM channel state */
1656 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1657
1658 /* Return function status */
1659 return HAL_OK;
1660 }
1661
1662 /**
1663 * @brief Starts the TIM PWM signal generation in DMA mode.
1664 * @param htim TIM PWM handle
1665 * @param Channel TIM Channels to be enabled
1666 * This parameter can be one of the following values:
1667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1669 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1670 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1671 * @param pData The source Buffer address.
1672 * @param Length The length of data to be transferred from memory to TIM peripheral
1673 * @retval HAL status
1674 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1675 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1676 {
1677 uint32_t tmpsmcr;
1678
1679 /* Check the parameters */
1680 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1681
1682 /* Set the TIM channel state */
1683 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1684 {
1685 return HAL_BUSY;
1686 }
1687 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1688 {
1689 if ((pData == NULL) && (Length > 0U))
1690 {
1691 return HAL_ERROR;
1692 }
1693 else
1694 {
1695 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1696 }
1697 }
1698 else
1699 {
1700 return HAL_ERROR;
1701 }
1702
1703 switch (Channel)
1704 {
1705 case TIM_CHANNEL_1:
1706 {
1707 /* Set the DMA compare callbacks */
1708 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1709 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1710
1711 /* Set the DMA error callback */
1712 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1713
1714 /* Enable the DMA channel */
1715 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1716 Length) != HAL_OK)
1717 {
1718 /* Return error status */
1719 return HAL_ERROR;
1720 }
1721
1722 /* Enable the TIM Capture/Compare 1 DMA request */
1723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1724 break;
1725 }
1726
1727 case TIM_CHANNEL_2:
1728 {
1729 /* Set the DMA compare callbacks */
1730 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1731 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1732
1733 /* Set the DMA error callback */
1734 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1735
1736 /* Enable the DMA channel */
1737 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1738 Length) != HAL_OK)
1739 {
1740 /* Return error status */
1741 return HAL_ERROR;
1742 }
1743 /* Enable the TIM Capture/Compare 2 DMA request */
1744 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1745 break;
1746 }
1747
1748 case TIM_CHANNEL_3:
1749 {
1750 /* Set the DMA compare callbacks */
1751 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1752 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1753
1754 /* Set the DMA error callback */
1755 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1756
1757 /* Enable the DMA channel */
1758 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1759 Length) != HAL_OK)
1760 {
1761 /* Return error status */
1762 return HAL_ERROR;
1763 }
1764 /* Enable the TIM Output Capture/Compare 3 request */
1765 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1766 break;
1767 }
1768
1769 case TIM_CHANNEL_4:
1770 {
1771 /* Set the DMA compare callbacks */
1772 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1773 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1774
1775 /* Set the DMA error callback */
1776 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1777
1778 /* Enable the DMA channel */
1779 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1780 Length) != HAL_OK)
1781 {
1782 /* Return error status */
1783 return HAL_ERROR;
1784 }
1785 /* Enable the TIM Capture/Compare 4 DMA request */
1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1787 break;
1788 }
1789
1790 default:
1791 break;
1792 }
1793
1794 /* Enable the Capture compare channel */
1795 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1796
1797 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1798 {
1799 /* Enable the main output */
1800 __HAL_TIM_MOE_ENABLE(htim);
1801 }
1802
1803 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1804 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1805 {
1806 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1807 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1808 {
1809 __HAL_TIM_ENABLE(htim);
1810 }
1811 }
1812 else
1813 {
1814 __HAL_TIM_ENABLE(htim);
1815 }
1816
1817 /* Return function status */
1818 return HAL_OK;
1819 }
1820
1821 /**
1822 * @brief Stops the TIM PWM signal generation in DMA mode.
1823 * @param htim TIM PWM handle
1824 * @param Channel TIM Channels to be disabled
1825 * This parameter can be one of the following values:
1826 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1827 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1828 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1829 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1830 * @retval HAL status
1831 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1832 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1833 {
1834 /* Check the parameters */
1835 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1836
1837 switch (Channel)
1838 {
1839 case TIM_CHANNEL_1:
1840 {
1841 /* Disable the TIM Capture/Compare 1 DMA request */
1842 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1843 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1844 break;
1845 }
1846
1847 case TIM_CHANNEL_2:
1848 {
1849 /* Disable the TIM Capture/Compare 2 DMA request */
1850 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1851 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1852 break;
1853 }
1854
1855 case TIM_CHANNEL_3:
1856 {
1857 /* Disable the TIM Capture/Compare 3 DMA request */
1858 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1859 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1860 break;
1861 }
1862
1863 case TIM_CHANNEL_4:
1864 {
1865 /* Disable the TIM Capture/Compare 4 interrupt */
1866 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1867 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1868 break;
1869 }
1870
1871 default:
1872 break;
1873 }
1874
1875 /* Disable the Capture compare channel */
1876 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1877
1878 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1879 {
1880 /* Disable the Main Output */
1881 __HAL_TIM_MOE_DISABLE(htim);
1882 }
1883
1884 /* Disable the Peripheral */
1885 __HAL_TIM_DISABLE(htim);
1886
1887 /* Set the TIM channel state */
1888 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1889
1890 /* Return function status */
1891 return HAL_OK;
1892 }
1893
1894 /**
1895 * @}
1896 */
1897
1898 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1899 * @brief TIM Input Capture functions
1900 *
1901 @verbatim
1902 ==============================================================================
1903 ##### TIM Input Capture functions #####
1904 ==============================================================================
1905 [..]
1906 This section provides functions allowing to:
1907 (+) Initialize and configure the TIM Input Capture.
1908 (+) De-initialize the TIM Input Capture.
1909 (+) Start the TIM Input Capture.
1910 (+) Stop the TIM Input Capture.
1911 (+) Start the TIM Input Capture and enable interrupt.
1912 (+) Stop the TIM Input Capture and disable interrupt.
1913 (+) Start the TIM Input Capture and enable DMA transfer.
1914 (+) Stop the TIM Input Capture and disable DMA transfer.
1915
1916 @endverbatim
1917 * @{
1918 */
1919 /**
1920 * @brief Initializes the TIM Input Capture Time base according to the specified
1921 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1922 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1923 * requires a timer reset to avoid unexpected direction
1924 * due to DIR bit readonly in center aligned mode.
1925 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1926 * @param htim TIM Input Capture handle
1927 * @retval HAL status
1928 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1929 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1930 {
1931 /* Check the TIM handle allocation */
1932 if (htim == NULL)
1933 {
1934 return HAL_ERROR;
1935 }
1936
1937 /* Check the parameters */
1938 assert_param(IS_TIM_INSTANCE(htim->Instance));
1939 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1940 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1941 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1942
1943 if (htim->State == HAL_TIM_STATE_RESET)
1944 {
1945 /* Allocate lock resource and initialize it */
1946 htim->Lock = HAL_UNLOCKED;
1947
1948 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1949 /* Reset interrupt callbacks to legacy weak callbacks */
1950 TIM_ResetCallback(htim);
1951
1952 if (htim->IC_MspInitCallback == NULL)
1953 {
1954 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1955 }
1956 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1957 htim->IC_MspInitCallback(htim);
1958 #else
1959 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1960 HAL_TIM_IC_MspInit(htim);
1961 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1962 }
1963
1964 /* Set the TIM state */
1965 htim->State = HAL_TIM_STATE_BUSY;
1966
1967 /* Init the base time for the input capture */
1968 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1969
1970 /* Initialize the DMA burst operation state */
1971 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1972
1973 /* Initialize the TIM channels state */
1974 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1975 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1976
1977 /* Initialize the TIM state*/
1978 htim->State = HAL_TIM_STATE_READY;
1979
1980 return HAL_OK;
1981 }
1982
1983 /**
1984 * @brief DeInitializes the TIM peripheral
1985 * @param htim TIM Input Capture handle
1986 * @retval HAL status
1987 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1988 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1989 {
1990 /* Check the parameters */
1991 assert_param(IS_TIM_INSTANCE(htim->Instance));
1992
1993 htim->State = HAL_TIM_STATE_BUSY;
1994
1995 /* Disable the TIM Peripheral Clock */
1996 __HAL_TIM_DISABLE(htim);
1997
1998 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1999 if (htim->IC_MspDeInitCallback == NULL)
2000 {
2001 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2002 }
2003 /* DeInit the low level hardware */
2004 htim->IC_MspDeInitCallback(htim);
2005 #else
2006 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2007 HAL_TIM_IC_MspDeInit(htim);
2008 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2009
2010 /* Change the DMA burst operation state */
2011 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2012
2013 /* Change the TIM channels state */
2014 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2015 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2016
2017 /* Change TIM state */
2018 htim->State = HAL_TIM_STATE_RESET;
2019
2020 /* Release Lock */
2021 __HAL_UNLOCK(htim);
2022
2023 return HAL_OK;
2024 }
2025
2026 /**
2027 * @brief Initializes the TIM Input Capture MSP.
2028 * @param htim TIM Input Capture handle
2029 * @retval None
2030 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2031 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2032 {
2033 /* Prevent unused argument(s) compilation warning */
2034 UNUSED(htim);
2035
2036 /* NOTE : This function should not be modified, when the callback is needed,
2037 the HAL_TIM_IC_MspInit could be implemented in the user file
2038 */
2039 }
2040
2041 /**
2042 * @brief DeInitializes TIM Input Capture MSP.
2043 * @param htim TIM handle
2044 * @retval None
2045 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2046 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2047 {
2048 /* Prevent unused argument(s) compilation warning */
2049 UNUSED(htim);
2050
2051 /* NOTE : This function should not be modified, when the callback is needed,
2052 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2053 */
2054 }
2055
2056 /**
2057 * @brief Starts the TIM Input Capture measurement.
2058 * @param htim TIM Input Capture handle
2059 * @param Channel TIM Channels to be enabled
2060 * This parameter can be one of the following values:
2061 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2062 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2063 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2064 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2065 * @retval HAL status
2066 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2067 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2068 {
2069 uint32_t tmpsmcr;
2070 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2071 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2072
2073 /* Check the parameters */
2074 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2075
2076 /* Check the TIM channel state */
2077 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2078 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2079 {
2080 return HAL_ERROR;
2081 }
2082
2083 /* Set the TIM channel state */
2084 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2085 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2086
2087 /* Enable the Input Capture channel */
2088 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2089
2090 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2091 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2092 {
2093 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2094 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2095 {
2096 __HAL_TIM_ENABLE(htim);
2097 }
2098 }
2099 else
2100 {
2101 __HAL_TIM_ENABLE(htim);
2102 }
2103
2104 /* Return function status */
2105 return HAL_OK;
2106 }
2107
2108 /**
2109 * @brief Stops the TIM Input Capture measurement.
2110 * @param htim TIM Input Capture handle
2111 * @param Channel TIM Channels to be disabled
2112 * This parameter can be one of the following values:
2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2115 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2116 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2117 * @retval HAL status
2118 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2119 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2120 {
2121 /* Check the parameters */
2122 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2123
2124 /* Disable the Input Capture channel */
2125 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2126
2127 /* Disable the Peripheral */
2128 __HAL_TIM_DISABLE(htim);
2129
2130 /* Set the TIM channel state */
2131 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2132 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2133
2134 /* Return function status */
2135 return HAL_OK;
2136 }
2137
2138 /**
2139 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2140 * @param htim TIM Input Capture handle
2141 * @param Channel TIM Channels to be enabled
2142 * This parameter can be one of the following values:
2143 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2144 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2145 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2146 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2147 * @retval HAL status
2148 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2149 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2150 {
2151 uint32_t tmpsmcr;
2152 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2153 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2154
2155 /* Check the parameters */
2156 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2157
2158 /* Check the TIM channel state */
2159 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2160 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2161 {
2162 return HAL_ERROR;
2163 }
2164
2165 /* Set the TIM channel state */
2166 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2167 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2168
2169 switch (Channel)
2170 {
2171 case TIM_CHANNEL_1:
2172 {
2173 /* Enable the TIM Capture/Compare 1 interrupt */
2174 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2175 break;
2176 }
2177
2178 case TIM_CHANNEL_2:
2179 {
2180 /* Enable the TIM Capture/Compare 2 interrupt */
2181 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2182 break;
2183 }
2184
2185 case TIM_CHANNEL_3:
2186 {
2187 /* Enable the TIM Capture/Compare 3 interrupt */
2188 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2189 break;
2190 }
2191
2192 case TIM_CHANNEL_4:
2193 {
2194 /* Enable the TIM Capture/Compare 4 interrupt */
2195 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2196 break;
2197 }
2198
2199 default:
2200 break;
2201 }
2202 /* Enable the Input Capture channel */
2203 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2204
2205 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2206 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2207 {
2208 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2209 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2210 {
2211 __HAL_TIM_ENABLE(htim);
2212 }
2213 }
2214 else
2215 {
2216 __HAL_TIM_ENABLE(htim);
2217 }
2218
2219 /* Return function status */
2220 return HAL_OK;
2221 }
2222
2223 /**
2224 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2225 * @param htim TIM Input Capture handle
2226 * @param Channel TIM Channels to be disabled
2227 * This parameter can be one of the following values:
2228 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2229 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2230 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2231 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2232 * @retval HAL status
2233 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2234 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2235 {
2236 /* Check the parameters */
2237 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2238
2239 switch (Channel)
2240 {
2241 case TIM_CHANNEL_1:
2242 {
2243 /* Disable the TIM Capture/Compare 1 interrupt */
2244 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2245 break;
2246 }
2247
2248 case TIM_CHANNEL_2:
2249 {
2250 /* Disable the TIM Capture/Compare 2 interrupt */
2251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2252 break;
2253 }
2254
2255 case TIM_CHANNEL_3:
2256 {
2257 /* Disable the TIM Capture/Compare 3 interrupt */
2258 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2259 break;
2260 }
2261
2262 case TIM_CHANNEL_4:
2263 {
2264 /* Disable the TIM Capture/Compare 4 interrupt */
2265 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2266 break;
2267 }
2268
2269 default:
2270 break;
2271 }
2272
2273 /* Disable the Input Capture channel */
2274 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2275
2276 /* Disable the Peripheral */
2277 __HAL_TIM_DISABLE(htim);
2278
2279 /* Set the TIM channel state */
2280 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2281 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2282
2283 /* Return function status */
2284 return HAL_OK;
2285 }
2286
2287 /**
2288 * @brief Starts the TIM Input Capture measurement in DMA mode.
2289 * @param htim TIM Input Capture handle
2290 * @param Channel TIM Channels to be enabled
2291 * This parameter can be one of the following values:
2292 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2293 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2294 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2295 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2296 * @param pData The destination Buffer address.
2297 * @param Length The length of data to be transferred from TIM peripheral to memory.
2298 * @retval HAL status
2299 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2300 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2301 {
2302 uint32_t tmpsmcr;
2303 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2304 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2305
2306 /* Check the parameters */
2307 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2308 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2309
2310 /* Set the TIM channel state */
2311 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2312 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2313 {
2314 return HAL_BUSY;
2315 }
2316 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2317 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2318 {
2319 if ((pData == NULL) && (Length > 0U))
2320 {
2321 return HAL_ERROR;
2322 }
2323 else
2324 {
2325 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2326 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2327 }
2328 }
2329 else
2330 {
2331 return HAL_ERROR;
2332 }
2333
2334 /* Enable the Input Capture channel */
2335 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2336
2337 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2338 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2339 {
2340 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2341 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2342 {
2343 __HAL_TIM_ENABLE(htim);
2344 }
2345 }
2346 else
2347 {
2348 __HAL_TIM_ENABLE(htim);
2349 }
2350
2351 switch (Channel)
2352 {
2353 case TIM_CHANNEL_1:
2354 {
2355 /* Set the DMA capture callbacks */
2356 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2357 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2358
2359 /* Set the DMA error callback */
2360 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2361
2362 /* Enable the DMA channel */
2363 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2364 Length) != HAL_OK)
2365 {
2366 /* Return error status */
2367 return HAL_ERROR;
2368 }
2369 /* Enable the TIM Capture/Compare 1 DMA request */
2370 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2371 break;
2372 }
2373
2374 case TIM_CHANNEL_2:
2375 {
2376 /* Set the DMA capture callbacks */
2377 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2378 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2379
2380 /* Set the DMA error callback */
2381 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2382
2383 /* Enable the DMA channel */
2384 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2385 Length) != HAL_OK)
2386 {
2387 /* Return error status */
2388 return HAL_ERROR;
2389 }
2390 /* Enable the TIM Capture/Compare 2 DMA request */
2391 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2392 break;
2393 }
2394
2395 case TIM_CHANNEL_3:
2396 {
2397 /* Set the DMA capture callbacks */
2398 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2399 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2400
2401 /* Set the DMA error callback */
2402 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2403
2404 /* Enable the DMA channel */
2405 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2406 Length) != HAL_OK)
2407 {
2408 /* Return error status */
2409 return HAL_ERROR;
2410 }
2411 /* Enable the TIM Capture/Compare 3 DMA request */
2412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2413 break;
2414 }
2415
2416 case TIM_CHANNEL_4:
2417 {
2418 /* Set the DMA capture callbacks */
2419 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2420 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2421
2422 /* Set the DMA error callback */
2423 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2424
2425 /* Enable the DMA channel */
2426 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2427 Length) != HAL_OK)
2428 {
2429 /* Return error status */
2430 return HAL_ERROR;
2431 }
2432 /* Enable the TIM Capture/Compare 4 DMA request */
2433 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2434 break;
2435 }
2436
2437 default:
2438 break;
2439 }
2440
2441 /* Return function status */
2442 return HAL_OK;
2443 }
2444
2445 /**
2446 * @brief Stops the TIM Input Capture measurement in DMA mode.
2447 * @param htim TIM Input Capture handle
2448 * @param Channel TIM Channels to be disabled
2449 * This parameter can be one of the following values:
2450 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2451 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2452 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2453 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2454 * @retval HAL status
2455 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2456 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2457 {
2458 /* Check the parameters */
2459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2460 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2461
2462 /* Disable the Input Capture channel */
2463 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2464
2465 switch (Channel)
2466 {
2467 case TIM_CHANNEL_1:
2468 {
2469 /* Disable the TIM Capture/Compare 1 DMA request */
2470 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2471 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2472 break;
2473 }
2474
2475 case TIM_CHANNEL_2:
2476 {
2477 /* Disable the TIM Capture/Compare 2 DMA request */
2478 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2479 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2480 break;
2481 }
2482
2483 case TIM_CHANNEL_3:
2484 {
2485 /* Disable the TIM Capture/Compare 3 DMA request */
2486 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2487 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2488 break;
2489 }
2490
2491 case TIM_CHANNEL_4:
2492 {
2493 /* Disable the TIM Capture/Compare 4 DMA request */
2494 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2495 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2496 break;
2497 }
2498
2499 default:
2500 break;
2501 }
2502
2503 /* Disable the Peripheral */
2504 __HAL_TIM_DISABLE(htim);
2505
2506 /* Set the TIM channel state */
2507 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2508 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2509
2510 /* Return function status */
2511 return HAL_OK;
2512 }
2513 /**
2514 * @}
2515 */
2516
2517 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2518 * @brief TIM One Pulse functions
2519 *
2520 @verbatim
2521 ==============================================================================
2522 ##### TIM One Pulse functions #####
2523 ==============================================================================
2524 [..]
2525 This section provides functions allowing to:
2526 (+) Initialize and configure the TIM One Pulse.
2527 (+) De-initialize the TIM One Pulse.
2528 (+) Start the TIM One Pulse.
2529 (+) Stop the TIM One Pulse.
2530 (+) Start the TIM One Pulse and enable interrupt.
2531 (+) Stop the TIM One Pulse and disable interrupt.
2532 (+) Start the TIM One Pulse and enable DMA transfer.
2533 (+) Stop the TIM One Pulse and disable DMA transfer.
2534
2535 @endverbatim
2536 * @{
2537 */
2538 /**
2539 * @brief Initializes the TIM One Pulse Time Base according to the specified
2540 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2541 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2542 * requires a timer reset to avoid unexpected direction
2543 * due to DIR bit readonly in center aligned mode.
2544 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2545 * @note When the timer instance is initialized in One Pulse mode, timer
2546 * channels 1 and channel 2 are reserved and cannot be used for other
2547 * purpose.
2548 * @param htim TIM One Pulse handle
2549 * @param OnePulseMode Select the One pulse mode.
2550 * This parameter can be one of the following values:
2551 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2552 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2553 * @retval HAL status
2554 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2555 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2556 {
2557 /* Check the TIM handle allocation */
2558 if (htim == NULL)
2559 {
2560 return HAL_ERROR;
2561 }
2562
2563 /* Check the parameters */
2564 assert_param(IS_TIM_INSTANCE(htim->Instance));
2565 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2566 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2567 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2568 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2569
2570 if (htim->State == HAL_TIM_STATE_RESET)
2571 {
2572 /* Allocate lock resource and initialize it */
2573 htim->Lock = HAL_UNLOCKED;
2574
2575 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2576 /* Reset interrupt callbacks to legacy weak callbacks */
2577 TIM_ResetCallback(htim);
2578
2579 if (htim->OnePulse_MspInitCallback == NULL)
2580 {
2581 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2582 }
2583 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2584 htim->OnePulse_MspInitCallback(htim);
2585 #else
2586 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2587 HAL_TIM_OnePulse_MspInit(htim);
2588 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2589 }
2590
2591 /* Set the TIM state */
2592 htim->State = HAL_TIM_STATE_BUSY;
2593
2594 /* Configure the Time base in the One Pulse Mode */
2595 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2596
2597 /* Reset the OPM Bit */
2598 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2599
2600 /* Configure the OPM Mode */
2601 htim->Instance->CR1 |= OnePulseMode;
2602
2603 /* Initialize the DMA burst operation state */
2604 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2605
2606 /* Initialize the TIM channels state */
2607 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2608 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2609 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2611
2612 /* Initialize the TIM state*/
2613 htim->State = HAL_TIM_STATE_READY;
2614
2615 return HAL_OK;
2616 }
2617
2618 /**
2619 * @brief DeInitializes the TIM One Pulse
2620 * @param htim TIM One Pulse handle
2621 * @retval HAL status
2622 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2623 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2624 {
2625 /* Check the parameters */
2626 assert_param(IS_TIM_INSTANCE(htim->Instance));
2627
2628 htim->State = HAL_TIM_STATE_BUSY;
2629
2630 /* Disable the TIM Peripheral Clock */
2631 __HAL_TIM_DISABLE(htim);
2632
2633 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2634 if (htim->OnePulse_MspDeInitCallback == NULL)
2635 {
2636 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2637 }
2638 /* DeInit the low level hardware */
2639 htim->OnePulse_MspDeInitCallback(htim);
2640 #else
2641 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2642 HAL_TIM_OnePulse_MspDeInit(htim);
2643 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2644
2645 /* Change the DMA burst operation state */
2646 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2647
2648 /* Set the TIM channel state */
2649 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2650 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2651 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2652 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2653
2654 /* Change TIM state */
2655 htim->State = HAL_TIM_STATE_RESET;
2656
2657 /* Release Lock */
2658 __HAL_UNLOCK(htim);
2659
2660 return HAL_OK;
2661 }
2662
2663 /**
2664 * @brief Initializes the TIM One Pulse MSP.
2665 * @param htim TIM One Pulse handle
2666 * @retval None
2667 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2668 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2669 {
2670 /* Prevent unused argument(s) compilation warning */
2671 UNUSED(htim);
2672
2673 /* NOTE : This function should not be modified, when the callback is needed,
2674 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2675 */
2676 }
2677
2678 /**
2679 * @brief DeInitializes TIM One Pulse MSP.
2680 * @param htim TIM One Pulse handle
2681 * @retval None
2682 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2683 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2684 {
2685 /* Prevent unused argument(s) compilation warning */
2686 UNUSED(htim);
2687
2688 /* NOTE : This function should not be modified, when the callback is needed,
2689 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2690 */
2691 }
2692
2693 /**
2694 * @brief Starts the TIM One Pulse signal generation.
2695 * @note Though OutputChannel parameter is deprecated and ignored by the function
2696 * it has been kept to avoid HAL_TIM API compatibility break.
2697 * @note The pulse output channel is determined when calling
2698 * @ref HAL_TIM_OnePulse_ConfigChannel().
2699 * @param htim TIM One Pulse handle
2700 * @param OutputChannel See note above
2701 * @retval HAL status
2702 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2703 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2704 {
2705 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2706 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2707 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2708 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2709
2710 /* Prevent unused argument(s) compilation warning */
2711 UNUSED(OutputChannel);
2712
2713 /* Check the TIM channels state */
2714 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2715 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2716 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2717 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2718 {
2719 return HAL_ERROR;
2720 }
2721
2722 /* Set the TIM channels state */
2723 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2724 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2725 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2726 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2727
2728 /* Enable the Capture compare and the Input Capture channels
2729 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2730 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2731 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2732 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2733
2734 No need to enable the counter, it's enabled automatically by hardware
2735 (the counter starts in response to a stimulus and generate a pulse */
2736
2737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2738 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2739
2740 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2741 {
2742 /* Enable the main output */
2743 __HAL_TIM_MOE_ENABLE(htim);
2744 }
2745
2746 /* Return function status */
2747 return HAL_OK;
2748 }
2749
2750 /**
2751 * @brief Stops the TIM One Pulse signal generation.
2752 * @note Though OutputChannel parameter is deprecated and ignored by the function
2753 * it has been kept to avoid HAL_TIM API compatibility break.
2754 * @note The pulse output channel is determined when calling
2755 * @ref HAL_TIM_OnePulse_ConfigChannel().
2756 * @param htim TIM One Pulse handle
2757 * @param OutputChannel See note above
2758 * @retval HAL status
2759 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2760 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2761 {
2762 /* Prevent unused argument(s) compilation warning */
2763 UNUSED(OutputChannel);
2764
2765 /* Disable the Capture compare and the Input Capture channels
2766 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2767 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2768 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2769 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2770
2771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2772 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2773
2774 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2775 {
2776 /* Disable the Main Output */
2777 __HAL_TIM_MOE_DISABLE(htim);
2778 }
2779
2780 /* Disable the Peripheral */
2781 __HAL_TIM_DISABLE(htim);
2782
2783 /* Set the TIM channels state */
2784 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2785 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2786 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2787 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2788
2789 /* Return function status */
2790 return HAL_OK;
2791 }
2792
2793 /**
2794 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2795 * @note Though OutputChannel parameter is deprecated and ignored by the function
2796 * it has been kept to avoid HAL_TIM API compatibility break.
2797 * @note The pulse output channel is determined when calling
2798 * @ref HAL_TIM_OnePulse_ConfigChannel().
2799 * @param htim TIM One Pulse handle
2800 * @param OutputChannel See note above
2801 * @retval HAL status
2802 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2803 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2804 {
2805 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2806 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2807 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2808 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2809
2810 /* Prevent unused argument(s) compilation warning */
2811 UNUSED(OutputChannel);
2812
2813 /* Check the TIM channels state */
2814 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2815 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2816 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2817 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2818 {
2819 return HAL_ERROR;
2820 }
2821
2822 /* Set the TIM channels state */
2823 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2824 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2825 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2826 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2827
2828 /* Enable the Capture compare and the Input Capture channels
2829 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2830 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2831 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2832 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2833
2834 No need to enable the counter, it's enabled automatically by hardware
2835 (the counter starts in response to a stimulus and generate a pulse */
2836
2837 /* Enable the TIM Capture/Compare 1 interrupt */
2838 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2839
2840 /* Enable the TIM Capture/Compare 2 interrupt */
2841 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2842
2843 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2844 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2845
2846 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2847 {
2848 /* Enable the main output */
2849 __HAL_TIM_MOE_ENABLE(htim);
2850 }
2851
2852 /* Return function status */
2853 return HAL_OK;
2854 }
2855
2856 /**
2857 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2858 * @note Though OutputChannel parameter is deprecated and ignored by the function
2859 * it has been kept to avoid HAL_TIM API compatibility break.
2860 * @note The pulse output channel is determined when calling
2861 * @ref HAL_TIM_OnePulse_ConfigChannel().
2862 * @param htim TIM One Pulse handle
2863 * @param OutputChannel See note above
2864 * @retval HAL status
2865 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2866 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2867 {
2868 /* Prevent unused argument(s) compilation warning */
2869 UNUSED(OutputChannel);
2870
2871 /* Disable the TIM Capture/Compare 1 interrupt */
2872 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2873
2874 /* Disable the TIM Capture/Compare 2 interrupt */
2875 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2876
2877 /* Disable the Capture compare and the Input Capture channels
2878 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2879 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2880 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2881 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2882 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2883 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2884
2885 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2886 {
2887 /* Disable the Main Output */
2888 __HAL_TIM_MOE_DISABLE(htim);
2889 }
2890
2891 /* Disable the Peripheral */
2892 __HAL_TIM_DISABLE(htim);
2893
2894 /* Set the TIM channels state */
2895 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2896 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2897 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2898 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2899
2900 /* Return function status */
2901 return HAL_OK;
2902 }
2903
2904 /**
2905 * @}
2906 */
2907
2908 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2909 * @brief TIM Encoder functions
2910 *
2911 @verbatim
2912 ==============================================================================
2913 ##### TIM Encoder functions #####
2914 ==============================================================================
2915 [..]
2916 This section provides functions allowing to:
2917 (+) Initialize and configure the TIM Encoder.
2918 (+) De-initialize the TIM Encoder.
2919 (+) Start the TIM Encoder.
2920 (+) Stop the TIM Encoder.
2921 (+) Start the TIM Encoder and enable interrupt.
2922 (+) Stop the TIM Encoder and disable interrupt.
2923 (+) Start the TIM Encoder and enable DMA transfer.
2924 (+) Stop the TIM Encoder and disable DMA transfer.
2925
2926 @endverbatim
2927 * @{
2928 */
2929 /**
2930 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2931 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2932 * requires a timer reset to avoid unexpected direction
2933 * due to DIR bit readonly in center aligned mode.
2934 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2935 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2936 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2937 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2938 * @note When the timer instance is initialized in Encoder mode, timer
2939 * channels 1 and channel 2 are reserved and cannot be used for other
2940 * purpose.
2941 * @param htim TIM Encoder Interface handle
2942 * @param sConfig TIM Encoder Interface configuration structure
2943 * @retval HAL status
2944 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2945 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2946 {
2947 uint32_t tmpsmcr;
2948 uint32_t tmpccmr1;
2949 uint32_t tmpccer;
2950
2951 /* Check the TIM handle allocation */
2952 if (htim == NULL)
2953 {
2954 return HAL_ERROR;
2955 }
2956
2957 /* Check the parameters */
2958 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2959 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2960 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2961 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2962 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2963 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2964 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2965 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2966 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2967 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2968 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2969 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2970 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2971
2972 if (htim->State == HAL_TIM_STATE_RESET)
2973 {
2974 /* Allocate lock resource and initialize it */
2975 htim->Lock = HAL_UNLOCKED;
2976
2977 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2978 /* Reset interrupt callbacks to legacy weak callbacks */
2979 TIM_ResetCallback(htim);
2980
2981 if (htim->Encoder_MspInitCallback == NULL)
2982 {
2983 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2984 }
2985 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2986 htim->Encoder_MspInitCallback(htim);
2987 #else
2988 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2989 HAL_TIM_Encoder_MspInit(htim);
2990 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2991 }
2992
2993 /* Set the TIM state */
2994 htim->State = HAL_TIM_STATE_BUSY;
2995
2996 /* Reset the SMS and ECE bits */
2997 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2998
2999 /* Configure the Time base in the Encoder Mode */
3000 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3001
3002 /* Get the TIMx SMCR register value */
3003 tmpsmcr = htim->Instance->SMCR;
3004
3005 /* Get the TIMx CCMR1 register value */
3006 tmpccmr1 = htim->Instance->CCMR1;
3007
3008 /* Get the TIMx CCER register value */
3009 tmpccer = htim->Instance->CCER;
3010
3011 /* Set the encoder Mode */
3012 tmpsmcr |= sConfig->EncoderMode;
3013
3014 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3015 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3016 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3017
3018 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3019 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3020 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3021 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3022 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3023
3024 /* Set the TI1 and the TI2 Polarities */
3025 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3026 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3027
3028 /* Write to TIMx SMCR */
3029 htim->Instance->SMCR = tmpsmcr;
3030
3031 /* Write to TIMx CCMR1 */
3032 htim->Instance->CCMR1 = tmpccmr1;
3033
3034 /* Write to TIMx CCER */
3035 htim->Instance->CCER = tmpccer;
3036
3037 /* Initialize the DMA burst operation state */
3038 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3039
3040 /* Set the TIM channels state */
3041 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3042 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3043 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3044 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3045
3046 /* Initialize the TIM state*/
3047 htim->State = HAL_TIM_STATE_READY;
3048
3049 return HAL_OK;
3050 }
3051
3052
3053 /**
3054 * @brief DeInitializes the TIM Encoder interface
3055 * @param htim TIM Encoder Interface handle
3056 * @retval HAL status
3057 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3058 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3059 {
3060 /* Check the parameters */
3061 assert_param(IS_TIM_INSTANCE(htim->Instance));
3062
3063 htim->State = HAL_TIM_STATE_BUSY;
3064
3065 /* Disable the TIM Peripheral Clock */
3066 __HAL_TIM_DISABLE(htim);
3067
3068 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3069 if (htim->Encoder_MspDeInitCallback == NULL)
3070 {
3071 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3072 }
3073 /* DeInit the low level hardware */
3074 htim->Encoder_MspDeInitCallback(htim);
3075 #else
3076 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3077 HAL_TIM_Encoder_MspDeInit(htim);
3078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3079
3080 /* Change the DMA burst operation state */
3081 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3082
3083 /* Set the TIM channels state */
3084 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3085 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3086 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3087 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3088
3089 /* Change TIM state */
3090 htim->State = HAL_TIM_STATE_RESET;
3091
3092 /* Release Lock */
3093 __HAL_UNLOCK(htim);
3094
3095 return HAL_OK;
3096 }
3097
3098 /**
3099 * @brief Initializes the TIM Encoder Interface MSP.
3100 * @param htim TIM Encoder Interface handle
3101 * @retval None
3102 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3103 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3104 {
3105 /* Prevent unused argument(s) compilation warning */
3106 UNUSED(htim);
3107
3108 /* NOTE : This function should not be modified, when the callback is needed,
3109 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3110 */
3111 }
3112
3113 /**
3114 * @brief DeInitializes TIM Encoder Interface MSP.
3115 * @param htim TIM Encoder Interface handle
3116 * @retval None
3117 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3118 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3119 {
3120 /* Prevent unused argument(s) compilation warning */
3121 UNUSED(htim);
3122
3123 /* NOTE : This function should not be modified, when the callback is needed,
3124 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3125 */
3126 }
3127
3128 /**
3129 * @brief Starts the TIM Encoder Interface.
3130 * @param htim TIM Encoder Interface handle
3131 * @param Channel TIM Channels to be enabled
3132 * This parameter can be one of the following values:
3133 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3134 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3135 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3136 * @retval HAL status
3137 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3138 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3139 {
3140 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3141 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3142 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3143 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3144
3145 /* Check the parameters */
3146 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3147
3148 /* Set the TIM channel(s) state */
3149 if (Channel == TIM_CHANNEL_1)
3150 {
3151 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3152 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3153 {
3154 return HAL_ERROR;
3155 }
3156 else
3157 {
3158 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3159 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3160 }
3161 }
3162 else if (Channel == TIM_CHANNEL_2)
3163 {
3164 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3165 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3166 {
3167 return HAL_ERROR;
3168 }
3169 else
3170 {
3171 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3172 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3173 }
3174 }
3175 else
3176 {
3177 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3178 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3179 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3180 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3181 {
3182 return HAL_ERROR;
3183 }
3184 else
3185 {
3186 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3187 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3188 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3189 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3190 }
3191 }
3192
3193 /* Enable the encoder interface channels */
3194 switch (Channel)
3195 {
3196 case TIM_CHANNEL_1:
3197 {
3198 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3199 break;
3200 }
3201
3202 case TIM_CHANNEL_2:
3203 {
3204 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3205 break;
3206 }
3207
3208 default :
3209 {
3210 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3211 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3212 break;
3213 }
3214 }
3215 /* Enable the Peripheral */
3216 __HAL_TIM_ENABLE(htim);
3217
3218 /* Return function status */
3219 return HAL_OK;
3220 }
3221
3222 /**
3223 * @brief Stops the TIM Encoder Interface.
3224 * @param htim TIM Encoder Interface handle
3225 * @param Channel TIM Channels to be disabled
3226 * This parameter can be one of the following values:
3227 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3228 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3229 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3230 * @retval HAL status
3231 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3232 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3233 {
3234 /* Check the parameters */
3235 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3236
3237 /* Disable the Input Capture channels 1 and 2
3238 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3239 switch (Channel)
3240 {
3241 case TIM_CHANNEL_1:
3242 {
3243 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3244 break;
3245 }
3246
3247 case TIM_CHANNEL_2:
3248 {
3249 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3250 break;
3251 }
3252
3253 default :
3254 {
3255 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3256 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3257 break;
3258 }
3259 }
3260
3261 /* Disable the Peripheral */
3262 __HAL_TIM_DISABLE(htim);
3263
3264 /* Set the TIM channel(s) state */
3265 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3266 {
3267 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3268 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3269 }
3270 else
3271 {
3272 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3273 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3274 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3275 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3276 }
3277
3278 /* Return function status */
3279 return HAL_OK;
3280 }
3281
3282 /**
3283 * @brief Starts the TIM Encoder Interface in interrupt mode.
3284 * @param htim TIM Encoder Interface handle
3285 * @param Channel TIM Channels to be enabled
3286 * This parameter can be one of the following values:
3287 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3288 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3289 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3290 * @retval HAL status
3291 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3292 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3293 {
3294 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3295 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3296 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3297 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3298
3299 /* Check the parameters */
3300 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3301
3302 /* Set the TIM channel(s) state */
3303 if (Channel == TIM_CHANNEL_1)
3304 {
3305 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3306 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3307 {
3308 return HAL_ERROR;
3309 }
3310 else
3311 {
3312 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3313 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3314 }
3315 }
3316 else if (Channel == TIM_CHANNEL_2)
3317 {
3318 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3319 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3320 {
3321 return HAL_ERROR;
3322 }
3323 else
3324 {
3325 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3326 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3327 }
3328 }
3329 else
3330 {
3331 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3332 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3333 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3334 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3335 {
3336 return HAL_ERROR;
3337 }
3338 else
3339 {
3340 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3341 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3342 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3343 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3344 }
3345 }
3346
3347 /* Enable the encoder interface channels */
3348 /* Enable the capture compare Interrupts 1 and/or 2 */
3349 switch (Channel)
3350 {
3351 case TIM_CHANNEL_1:
3352 {
3353 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3354 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3355 break;
3356 }
3357
3358 case TIM_CHANNEL_2:
3359 {
3360 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3361 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3362 break;
3363 }
3364
3365 default :
3366 {
3367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3368 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3369 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3370 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3371 break;
3372 }
3373 }
3374
3375 /* Enable the Peripheral */
3376 __HAL_TIM_ENABLE(htim);
3377
3378 /* Return function status */
3379 return HAL_OK;
3380 }
3381
3382 /**
3383 * @brief Stops the TIM Encoder Interface in interrupt mode.
3384 * @param htim TIM Encoder Interface handle
3385 * @param Channel TIM Channels to be disabled
3386 * This parameter can be one of the following values:
3387 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3388 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3389 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3390 * @retval HAL status
3391 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3392 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3393 {
3394 /* Check the parameters */
3395 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3396
3397 /* Disable the Input Capture channels 1 and 2
3398 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3399 if (Channel == TIM_CHANNEL_1)
3400 {
3401 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3402
3403 /* Disable the capture compare Interrupts 1 */
3404 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3405 }
3406 else if (Channel == TIM_CHANNEL_2)
3407 {
3408 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3409
3410 /* Disable the capture compare Interrupts 2 */
3411 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3412 }
3413 else
3414 {
3415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3416 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3417
3418 /* Disable the capture compare Interrupts 1 and 2 */
3419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3420 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3421 }
3422
3423 /* Disable the Peripheral */
3424 __HAL_TIM_DISABLE(htim);
3425
3426 /* Set the TIM channel(s) state */
3427 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3428 {
3429 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3430 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3431 }
3432 else
3433 {
3434 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3435 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3436 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3437 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3438 }
3439
3440 /* Return function status */
3441 return HAL_OK;
3442 }
3443
3444 /**
3445 * @brief Starts the TIM Encoder Interface in DMA mode.
3446 * @param htim TIM Encoder Interface handle
3447 * @param Channel TIM Channels to be enabled
3448 * This parameter can be one of the following values:
3449 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3450 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3451 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3452 * @param pData1 The destination Buffer address for IC1.
3453 * @param pData2 The destination Buffer address for IC2.
3454 * @param Length The length of data to be transferred from TIM peripheral to memory.
3455 * @retval HAL status
3456 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3457 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3458 uint32_t *pData2, uint16_t Length)
3459 {
3460 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3461 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3462 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3463 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3464
3465 /* Check the parameters */
3466 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3467
3468 /* Set the TIM channel(s) state */
3469 if (Channel == TIM_CHANNEL_1)
3470 {
3471 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3472 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3473 {
3474 return HAL_BUSY;
3475 }
3476 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3477 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3478 {
3479 if ((pData1 == NULL) && (Length > 0U))
3480 {
3481 return HAL_ERROR;
3482 }
3483 else
3484 {
3485 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3486 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3487 }
3488 }
3489 else
3490 {
3491 return HAL_ERROR;
3492 }
3493 }
3494 else if (Channel == TIM_CHANNEL_2)
3495 {
3496 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3497 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3498 {
3499 return HAL_BUSY;
3500 }
3501 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3502 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3503 {
3504 if ((pData2 == NULL) && (Length > 0U))
3505 {
3506 return HAL_ERROR;
3507 }
3508 else
3509 {
3510 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3511 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3512 }
3513 }
3514 else
3515 {
3516 return HAL_ERROR;
3517 }
3518 }
3519 else
3520 {
3521 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3522 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3523 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3524 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3525 {
3526 return HAL_BUSY;
3527 }
3528 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3529 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3530 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3531 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3532 {
3533 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
3534 {
3535 return HAL_ERROR;
3536 }
3537 else
3538 {
3539 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3540 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3541 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3542 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3543 }
3544 }
3545 else
3546 {
3547 return HAL_ERROR;
3548 }
3549 }
3550
3551 switch (Channel)
3552 {
3553 case TIM_CHANNEL_1:
3554 {
3555 /* Set the DMA capture callbacks */
3556 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3557 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3558
3559 /* Set the DMA error callback */
3560 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3561
3562 /* Enable the DMA channel */
3563 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3564 Length) != HAL_OK)
3565 {
3566 /* Return error status */
3567 return HAL_ERROR;
3568 }
3569 /* Enable the TIM Input Capture DMA request */
3570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3571
3572 /* Enable the Peripheral */
3573 __HAL_TIM_ENABLE(htim);
3574
3575 /* Enable the Capture compare channel */
3576 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3577 break;
3578 }
3579
3580 case TIM_CHANNEL_2:
3581 {
3582 /* Set the DMA capture callbacks */
3583 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3584 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3585
3586 /* Set the DMA error callback */
3587 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3588 /* Enable the DMA channel */
3589 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3590 Length) != HAL_OK)
3591 {
3592 /* Return error status */
3593 return HAL_ERROR;
3594 }
3595 /* Enable the TIM Input Capture DMA request */
3596 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3597
3598 /* Enable the Peripheral */
3599 __HAL_TIM_ENABLE(htim);
3600
3601 /* Enable the Capture compare channel */
3602 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3603 break;
3604 }
3605
3606 case TIM_CHANNEL_ALL:
3607 {
3608 /* Set the DMA capture callbacks */
3609 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3610 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3611
3612 /* Set the DMA error callback */
3613 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3614
3615 /* Enable the DMA channel */
3616 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3617 Length) != HAL_OK)
3618 {
3619 /* Return error status */
3620 return HAL_ERROR;
3621 }
3622
3623 /* Set the DMA capture callbacks */
3624 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3625 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3626
3627 /* Set the DMA error callback */
3628 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3629
3630 /* Enable the DMA channel */
3631 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3632 Length) != HAL_OK)
3633 {
3634 /* Return error status */
3635 return HAL_ERROR;
3636 }
3637 /* Enable the Peripheral */
3638 __HAL_TIM_ENABLE(htim);
3639
3640 /* Enable the Capture compare channel */
3641 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3642 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3643
3644 /* Enable the TIM Input Capture DMA request */
3645 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3646 /* Enable the TIM Input Capture DMA request */
3647 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3648 break;
3649 }
3650
3651 default:
3652 break;
3653 }
3654
3655 /* Return function status */
3656 return HAL_OK;
3657 }
3658
3659 /**
3660 * @brief Stops the TIM Encoder Interface in DMA mode.
3661 * @param htim TIM Encoder Interface handle
3662 * @param Channel TIM Channels to be enabled
3663 * This parameter can be one of the following values:
3664 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3665 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3666 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3667 * @retval HAL status
3668 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3669 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3670 {
3671 /* Check the parameters */
3672 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3673
3674 /* Disable the Input Capture channels 1 and 2
3675 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3676 if (Channel == TIM_CHANNEL_1)
3677 {
3678 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3679
3680 /* Disable the capture compare DMA Request 1 */
3681 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3682 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3683 }
3684 else if (Channel == TIM_CHANNEL_2)
3685 {
3686 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3687
3688 /* Disable the capture compare DMA Request 2 */
3689 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3690 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3691 }
3692 else
3693 {
3694 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3695 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3696
3697 /* Disable the capture compare DMA Request 1 and 2 */
3698 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3699 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3700 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3701 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3702 }
3703
3704 /* Disable the Peripheral */
3705 __HAL_TIM_DISABLE(htim);
3706
3707 /* Set the TIM channel(s) state */
3708 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3709 {
3710 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3711 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3712 }
3713 else
3714 {
3715 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3716 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3717 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3718 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3719 }
3720
3721 /* Return function status */
3722 return HAL_OK;
3723 }
3724
3725 /**
3726 * @}
3727 */
3728 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3729 * @brief TIM IRQ handler management
3730 *
3731 @verbatim
3732 ==============================================================================
3733 ##### IRQ handler management #####
3734 ==============================================================================
3735 [..]
3736 This section provides Timer IRQ handler function.
3737
3738 @endverbatim
3739 * @{
3740 */
3741 /**
3742 * @brief This function handles TIM interrupts requests.
3743 * @param htim TIM handle
3744 * @retval None
3745 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3746 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3747 {
3748 /* Capture compare 1 event */
3749 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3750 {
3751 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3752 {
3753 {
3754 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3755 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3756
3757 /* Input capture event */
3758 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3759 {
3760 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3761 htim->IC_CaptureCallback(htim);
3762 #else
3763 HAL_TIM_IC_CaptureCallback(htim);
3764 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3765 }
3766 /* Output compare event */
3767 else
3768 {
3769 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3770 htim->OC_DelayElapsedCallback(htim);
3771 htim->PWM_PulseFinishedCallback(htim);
3772 #else
3773 HAL_TIM_OC_DelayElapsedCallback(htim);
3774 HAL_TIM_PWM_PulseFinishedCallback(htim);
3775 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3776 }
3777 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3778 }
3779 }
3780 }
3781 /* Capture compare 2 event */
3782 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3783 {
3784 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3785 {
3786 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3787 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3788 /* Input capture event */
3789 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3790 {
3791 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3792 htim->IC_CaptureCallback(htim);
3793 #else
3794 HAL_TIM_IC_CaptureCallback(htim);
3795 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3796 }
3797 /* Output compare event */
3798 else
3799 {
3800 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3801 htim->OC_DelayElapsedCallback(htim);
3802 htim->PWM_PulseFinishedCallback(htim);
3803 #else
3804 HAL_TIM_OC_DelayElapsedCallback(htim);
3805 HAL_TIM_PWM_PulseFinishedCallback(htim);
3806 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3807 }
3808 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3809 }
3810 }
3811 /* Capture compare 3 event */
3812 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3813 {
3814 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3815 {
3816 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3817 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3818 /* Input capture event */
3819 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3820 {
3821 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3822 htim->IC_CaptureCallback(htim);
3823 #else
3824 HAL_TIM_IC_CaptureCallback(htim);
3825 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3826 }
3827 /* Output compare event */
3828 else
3829 {
3830 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3831 htim->OC_DelayElapsedCallback(htim);
3832 htim->PWM_PulseFinishedCallback(htim);
3833 #else
3834 HAL_TIM_OC_DelayElapsedCallback(htim);
3835 HAL_TIM_PWM_PulseFinishedCallback(htim);
3836 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3837 }
3838 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3839 }
3840 }
3841 /* Capture compare 4 event */
3842 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3843 {
3844 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3845 {
3846 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3847 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3848 /* Input capture event */
3849 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3850 {
3851 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3852 htim->IC_CaptureCallback(htim);
3853 #else
3854 HAL_TIM_IC_CaptureCallback(htim);
3855 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3856 }
3857 /* Output compare event */
3858 else
3859 {
3860 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3861 htim->OC_DelayElapsedCallback(htim);
3862 htim->PWM_PulseFinishedCallback(htim);
3863 #else
3864 HAL_TIM_OC_DelayElapsedCallback(htim);
3865 HAL_TIM_PWM_PulseFinishedCallback(htim);
3866 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3867 }
3868 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3869 }
3870 }
3871 /* TIM Update event */
3872 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3873 {
3874 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3875 {
3876 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3877 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3878 htim->PeriodElapsedCallback(htim);
3879 #else
3880 HAL_TIM_PeriodElapsedCallback(htim);
3881 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3882 }
3883 }
3884 /* TIM Break input event */
3885 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3886 {
3887 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3888 {
3889 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3890 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3891 htim->BreakCallback(htim);
3892 #else
3893 HAL_TIMEx_BreakCallback(htim);
3894 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3895 }
3896 }
3897 /* TIM Trigger detection event */
3898 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3899 {
3900 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3901 {
3902 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3904 htim->TriggerCallback(htim);
3905 #else
3906 HAL_TIM_TriggerCallback(htim);
3907 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3908 }
3909 }
3910 /* TIM commutation event */
3911 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3912 {
3913 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3914 {
3915 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3916 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3917 htim->CommutationCallback(htim);
3918 #else
3919 HAL_TIMEx_CommutCallback(htim);
3920 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3921 }
3922 }
3923 }
3924
3925 /**
3926 * @}
3927 */
3928
3929 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3930 * @brief TIM Peripheral Control functions
3931 *
3932 @verbatim
3933 ==============================================================================
3934 ##### Peripheral Control functions #####
3935 ==============================================================================
3936 [..]
3937 This section provides functions allowing to:
3938 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3939 (+) Configure External Clock source.
3940 (+) Configure Complementary channels, break features and dead time.
3941 (+) Configure Master and the Slave synchronization.
3942 (+) Configure the DMA Burst Mode.
3943
3944 @endverbatim
3945 * @{
3946 */
3947
3948 /**
3949 * @brief Initializes the TIM Output Compare Channels according to the specified
3950 * parameters in the TIM_OC_InitTypeDef.
3951 * @param htim TIM Output Compare handle
3952 * @param sConfig TIM Output Compare configuration structure
3953 * @param Channel TIM Channels to configure
3954 * This parameter can be one of the following values:
3955 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3956 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3957 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3958 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3959 * @retval HAL status
3960 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3961 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3962 TIM_OC_InitTypeDef *sConfig,
3963 uint32_t Channel)
3964 {
3965 /* Check the parameters */
3966 assert_param(IS_TIM_CHANNELS(Channel));
3967 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3968 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3969
3970 /* Process Locked */
3971 __HAL_LOCK(htim);
3972
3973 switch (Channel)
3974 {
3975 case TIM_CHANNEL_1:
3976 {
3977 /* Check the parameters */
3978 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3979
3980 /* Configure the TIM Channel 1 in Output Compare */
3981 TIM_OC1_SetConfig(htim->Instance, sConfig);
3982 break;
3983 }
3984
3985 case TIM_CHANNEL_2:
3986 {
3987 /* Check the parameters */
3988 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3989
3990 /* Configure the TIM Channel 2 in Output Compare */
3991 TIM_OC2_SetConfig(htim->Instance, sConfig);
3992 break;
3993 }
3994
3995 case TIM_CHANNEL_3:
3996 {
3997 /* Check the parameters */
3998 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3999
4000 /* Configure the TIM Channel 3 in Output Compare */
4001 TIM_OC3_SetConfig(htim->Instance, sConfig);
4002 break;
4003 }
4004
4005 case TIM_CHANNEL_4:
4006 {
4007 /* Check the parameters */
4008 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4009
4010 /* Configure the TIM Channel 4 in Output Compare */
4011 TIM_OC4_SetConfig(htim->Instance, sConfig);
4012 break;
4013 }
4014
4015 default:
4016 break;
4017 }
4018
4019 __HAL_UNLOCK(htim);
4020
4021 return HAL_OK;
4022 }
4023
4024 /**
4025 * @brief Initializes the TIM Input Capture Channels according to the specified
4026 * parameters in the TIM_IC_InitTypeDef.
4027 * @param htim TIM IC handle
4028 * @param sConfig TIM Input Capture configuration structure
4029 * @param Channel TIM Channel to configure
4030 * This parameter can be one of the following values:
4031 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4032 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4033 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4034 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4035 * @retval HAL status
4036 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4037 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4038 {
4039 /* Check the parameters */
4040 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4041 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4042 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4043 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4044 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4045
4046 /* Process Locked */
4047 __HAL_LOCK(htim);
4048
4049 if (Channel == TIM_CHANNEL_1)
4050 {
4051 /* TI1 Configuration */
4052 TIM_TI1_SetConfig(htim->Instance,
4053 sConfig->ICPolarity,
4054 sConfig->ICSelection,
4055 sConfig->ICFilter);
4056
4057 /* Reset the IC1PSC Bits */
4058 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4059
4060 /* Set the IC1PSC value */
4061 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4062 }
4063 else if (Channel == TIM_CHANNEL_2)
4064 {
4065 /* TI2 Configuration */
4066 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4067
4068 TIM_TI2_SetConfig(htim->Instance,
4069 sConfig->ICPolarity,
4070 sConfig->ICSelection,
4071 sConfig->ICFilter);
4072
4073 /* Reset the IC2PSC Bits */
4074 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4075
4076 /* Set the IC2PSC value */
4077 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4078 }
4079 else if (Channel == TIM_CHANNEL_3)
4080 {
4081 /* TI3 Configuration */
4082 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4083
4084 TIM_TI3_SetConfig(htim->Instance,
4085 sConfig->ICPolarity,
4086 sConfig->ICSelection,
4087 sConfig->ICFilter);
4088
4089 /* Reset the IC3PSC Bits */
4090 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4091
4092 /* Set the IC3PSC value */
4093 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4094 }
4095 else
4096 {
4097 /* TI4 Configuration */
4098 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4099
4100 TIM_TI4_SetConfig(htim->Instance,
4101 sConfig->ICPolarity,
4102 sConfig->ICSelection,
4103 sConfig->ICFilter);
4104
4105 /* Reset the IC4PSC Bits */
4106 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4107
4108 /* Set the IC4PSC value */
4109 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4110 }
4111
4112 __HAL_UNLOCK(htim);
4113
4114 return HAL_OK;
4115 }
4116
4117 /**
4118 * @brief Initializes the TIM PWM channels according to the specified
4119 * parameters in the TIM_OC_InitTypeDef.
4120 * @param htim TIM PWM handle
4121 * @param sConfig TIM PWM configuration structure
4122 * @param Channel TIM Channels to be configured
4123 * This parameter can be one of the following values:
4124 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4125 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4126 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4127 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4128 * @retval HAL status
4129 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4130 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4131 TIM_OC_InitTypeDef *sConfig,
4132 uint32_t Channel)
4133 {
4134 /* Check the parameters */
4135 assert_param(IS_TIM_CHANNELS(Channel));
4136 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4137 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4138 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4139
4140 /* Process Locked */
4141 __HAL_LOCK(htim);
4142
4143 switch (Channel)
4144 {
4145 case TIM_CHANNEL_1:
4146 {
4147 /* Check the parameters */
4148 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4149
4150 /* Configure the Channel 1 in PWM mode */
4151 TIM_OC1_SetConfig(htim->Instance, sConfig);
4152
4153 /* Set the Preload enable bit for channel1 */
4154 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4155
4156 /* Configure the Output Fast mode */
4157 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4158 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4159 break;
4160 }
4161
4162 case TIM_CHANNEL_2:
4163 {
4164 /* Check the parameters */
4165 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4166
4167 /* Configure the Channel 2 in PWM mode */
4168 TIM_OC2_SetConfig(htim->Instance, sConfig);
4169
4170 /* Set the Preload enable bit for channel2 */
4171 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4172
4173 /* Configure the Output Fast mode */
4174 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4175 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4176 break;
4177 }
4178
4179 case TIM_CHANNEL_3:
4180 {
4181 /* Check the parameters */
4182 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4183
4184 /* Configure the Channel 3 in PWM mode */
4185 TIM_OC3_SetConfig(htim->Instance, sConfig);
4186
4187 /* Set the Preload enable bit for channel3 */
4188 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4189
4190 /* Configure the Output Fast mode */
4191 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4192 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4193 break;
4194 }
4195
4196 case TIM_CHANNEL_4:
4197 {
4198 /* Check the parameters */
4199 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4200
4201 /* Configure the Channel 4 in PWM mode */
4202 TIM_OC4_SetConfig(htim->Instance, sConfig);
4203
4204 /* Set the Preload enable bit for channel4 */
4205 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4206
4207 /* Configure the Output Fast mode */
4208 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4209 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4210 break;
4211 }
4212
4213 default:
4214 break;
4215 }
4216
4217 __HAL_UNLOCK(htim);
4218
4219 return HAL_OK;
4220 }
4221
4222 /**
4223 * @brief Initializes the TIM One Pulse Channels according to the specified
4224 * parameters in the TIM_OnePulse_InitTypeDef.
4225 * @param htim TIM One Pulse handle
4226 * @param sConfig TIM One Pulse configuration structure
4227 * @param OutputChannel TIM output channel to configure
4228 * This parameter can be one of the following values:
4229 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4230 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4231 * @param InputChannel TIM input Channel to configure
4232 * This parameter can be one of the following values:
4233 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4234 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4235 * @note To output a waveform with a minimum delay user can enable the fast
4236 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4237 * output is forced in response to the edge detection on TIx input,
4238 * without taking in account the comparison.
4239 * @retval HAL status
4240 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4241 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4242 uint32_t OutputChannel, uint32_t InputChannel)
4243 {
4244 TIM_OC_InitTypeDef temp1;
4245
4246 /* Check the parameters */
4247 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4248 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4249
4250 if (OutputChannel != InputChannel)
4251 {
4252 /* Process Locked */
4253 __HAL_LOCK(htim);
4254
4255 htim->State = HAL_TIM_STATE_BUSY;
4256
4257 /* Extract the Output compare configuration from sConfig structure */
4258 temp1.OCMode = sConfig->OCMode;
4259 temp1.Pulse = sConfig->Pulse;
4260 temp1.OCPolarity = sConfig->OCPolarity;
4261 temp1.OCNPolarity = sConfig->OCNPolarity;
4262 temp1.OCIdleState = sConfig->OCIdleState;
4263 temp1.OCNIdleState = sConfig->OCNIdleState;
4264
4265 switch (OutputChannel)
4266 {
4267 case TIM_CHANNEL_1:
4268 {
4269 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4270
4271 TIM_OC1_SetConfig(htim->Instance, &temp1);
4272 break;
4273 }
4274 case TIM_CHANNEL_2:
4275 {
4276 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4277
4278 TIM_OC2_SetConfig(htim->Instance, &temp1);
4279 break;
4280 }
4281 default:
4282 break;
4283 }
4284
4285 switch (InputChannel)
4286 {
4287 case TIM_CHANNEL_1:
4288 {
4289 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4290
4291 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4292 sConfig->ICSelection, sConfig->ICFilter);
4293
4294 /* Reset the IC1PSC Bits */
4295 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4296
4297 /* Select the Trigger source */
4298 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4299 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4300
4301 /* Select the Slave Mode */
4302 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4303 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4304 break;
4305 }
4306 case TIM_CHANNEL_2:
4307 {
4308 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4309
4310 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4311 sConfig->ICSelection, sConfig->ICFilter);
4312
4313 /* Reset the IC2PSC Bits */
4314 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4315
4316 /* Select the Trigger source */
4317 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4318 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4319
4320 /* Select the Slave Mode */
4321 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4322 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4323 break;
4324 }
4325
4326 default:
4327 break;
4328 }
4329
4330 htim->State = HAL_TIM_STATE_READY;
4331
4332 __HAL_UNLOCK(htim);
4333
4334 return HAL_OK;
4335 }
4336 else
4337 {
4338 return HAL_ERROR;
4339 }
4340 }
4341
4342 /**
4343 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4344 * @param htim TIM handle
4345 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4346 * This parameter can be one of the following values:
4347 * @arg TIM_DMABASE_CR1
4348 * @arg TIM_DMABASE_CR2
4349 * @arg TIM_DMABASE_SMCR
4350 * @arg TIM_DMABASE_DIER
4351 * @arg TIM_DMABASE_SR
4352 * @arg TIM_DMABASE_EGR
4353 * @arg TIM_DMABASE_CCMR1
4354 * @arg TIM_DMABASE_CCMR2
4355 * @arg TIM_DMABASE_CCER
4356 * @arg TIM_DMABASE_CNT
4357 * @arg TIM_DMABASE_PSC
4358 * @arg TIM_DMABASE_ARR
4359 * @arg TIM_DMABASE_RCR
4360 * @arg TIM_DMABASE_CCR1
4361 * @arg TIM_DMABASE_CCR2
4362 * @arg TIM_DMABASE_CCR3
4363 * @arg TIM_DMABASE_CCR4
4364 * @arg TIM_DMABASE_BDTR
4365 * @param BurstRequestSrc TIM DMA Request sources
4366 * This parameter can be one of the following values:
4367 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4368 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4369 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4370 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4371 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4372 * @arg TIM_DMA_COM: TIM Commutation DMA source
4373 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4374 * @param BurstBuffer The Buffer address.
4375 * @param BurstLength DMA Burst length. This parameter can be one value
4376 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4377 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4378 * @retval HAL status
4379 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4380 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4381 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4382 {
4383 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4384 ((BurstLength) >> 8U) + 1U);
4385 }
4386
4387 /**
4388 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4389 * @param htim TIM handle
4390 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4391 * This parameter can be one of the following values:
4392 * @arg TIM_DMABASE_CR1
4393 * @arg TIM_DMABASE_CR2
4394 * @arg TIM_DMABASE_SMCR
4395 * @arg TIM_DMABASE_DIER
4396 * @arg TIM_DMABASE_SR
4397 * @arg TIM_DMABASE_EGR
4398 * @arg TIM_DMABASE_CCMR1
4399 * @arg TIM_DMABASE_CCMR2
4400 * @arg TIM_DMABASE_CCER
4401 * @arg TIM_DMABASE_CNT
4402 * @arg TIM_DMABASE_PSC
4403 * @arg TIM_DMABASE_ARR
4404 * @arg TIM_DMABASE_RCR
4405 * @arg TIM_DMABASE_CCR1
4406 * @arg TIM_DMABASE_CCR2
4407 * @arg TIM_DMABASE_CCR3
4408 * @arg TIM_DMABASE_CCR4
4409 * @arg TIM_DMABASE_BDTR
4410 * @param BurstRequestSrc TIM DMA Request sources
4411 * This parameter can be one of the following values:
4412 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4413 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4414 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4415 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4416 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4417 * @arg TIM_DMA_COM: TIM Commutation DMA source
4418 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4419 * @param BurstBuffer The Buffer address.
4420 * @param BurstLength DMA Burst length. This parameter can be one value
4421 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4422 * @param DataLength Data length. This parameter can be one value
4423 * between 1 and 0xFFFF.
4424 * @retval HAL status
4425 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4426 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4427 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4428 uint32_t BurstLength, uint32_t DataLength)
4429 {
4430 /* Check the parameters */
4431 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4432 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4433 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4434 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4435 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4436
4437 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4438 {
4439 return HAL_BUSY;
4440 }
4441 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4442 {
4443 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4444 {
4445 return HAL_ERROR;
4446 }
4447 else
4448 {
4449 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4450 }
4451 }
4452 else
4453 {
4454 /* nothing to do */
4455 }
4456 switch (BurstRequestSrc)
4457 {
4458 case TIM_DMA_UPDATE:
4459 {
4460 /* Set the DMA Period elapsed callbacks */
4461 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4462 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4463
4464 /* Set the DMA error callback */
4465 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4466
4467 /* Enable the DMA channel */
4468 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4469 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4470 {
4471 /* Return error status */
4472 return HAL_ERROR;
4473 }
4474 break;
4475 }
4476 case TIM_DMA_CC1:
4477 {
4478 /* Set the DMA compare callbacks */
4479 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4480 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4481
4482 /* Set the DMA error callback */
4483 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4484
4485 /* Enable the DMA channel */
4486 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4487 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4488 {
4489 /* Return error status */
4490 return HAL_ERROR;
4491 }
4492 break;
4493 }
4494 case TIM_DMA_CC2:
4495 {
4496 /* Set the DMA compare callbacks */
4497 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4498 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4499
4500 /* Set the DMA error callback */
4501 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4502
4503 /* Enable the DMA channel */
4504 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4505 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4506 {
4507 /* Return error status */
4508 return HAL_ERROR;
4509 }
4510 break;
4511 }
4512 case TIM_DMA_CC3:
4513 {
4514 /* Set the DMA compare callbacks */
4515 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4516 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4517
4518 /* Set the DMA error callback */
4519 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4520
4521 /* Enable the DMA channel */
4522 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4523 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4524 {
4525 /* Return error status */
4526 return HAL_ERROR;
4527 }
4528 break;
4529 }
4530 case TIM_DMA_CC4:
4531 {
4532 /* Set the DMA compare callbacks */
4533 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4534 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4535
4536 /* Set the DMA error callback */
4537 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4538
4539 /* Enable the DMA channel */
4540 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4541 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4542 {
4543 /* Return error status */
4544 return HAL_ERROR;
4545 }
4546 break;
4547 }
4548 case TIM_DMA_COM:
4549 {
4550 /* Set the DMA commutation callbacks */
4551 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4552 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4553
4554 /* Set the DMA error callback */
4555 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4556
4557 /* Enable the DMA channel */
4558 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4559 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4560 {
4561 /* Return error status */
4562 return HAL_ERROR;
4563 }
4564 break;
4565 }
4566 case TIM_DMA_TRIGGER:
4567 {
4568 /* Set the DMA trigger callbacks */
4569 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4570 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4571
4572 /* Set the DMA error callback */
4573 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4574
4575 /* Enable the DMA channel */
4576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4577 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4578 {
4579 /* Return error status */
4580 return HAL_ERROR;
4581 }
4582 break;
4583 }
4584 default:
4585 break;
4586 }
4587
4588 /* Configure the DMA Burst Mode */
4589 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4590 /* Enable the TIM DMA Request */
4591 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4592
4593 /* Return function status */
4594 return HAL_OK;
4595 }
4596
4597 /**
4598 * @brief Stops the TIM DMA Burst mode
4599 * @param htim TIM handle
4600 * @param BurstRequestSrc TIM DMA Request sources to disable
4601 * @retval HAL status
4602 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4603 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4604 {
4605 /* Check the parameters */
4606 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4607
4608 /* Abort the DMA transfer (at least disable the DMA channel) */
4609 switch (BurstRequestSrc)
4610 {
4611 case TIM_DMA_UPDATE:
4612 {
4613 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4614 break;
4615 }
4616 case TIM_DMA_CC1:
4617 {
4618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4619 break;
4620 }
4621 case TIM_DMA_CC2:
4622 {
4623 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4624 break;
4625 }
4626 case TIM_DMA_CC3:
4627 {
4628 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4629 break;
4630 }
4631 case TIM_DMA_CC4:
4632 {
4633 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4634 break;
4635 }
4636 case TIM_DMA_COM:
4637 {
4638 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4639 break;
4640 }
4641 case TIM_DMA_TRIGGER:
4642 {
4643 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4644 break;
4645 }
4646 default:
4647 break;
4648 }
4649
4650 /* Disable the TIM Update DMA request */
4651 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4652
4653 /* Change the DMA burst operation state */
4654 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4655
4656 /* Return function status */
4657 return HAL_OK;
4658 }
4659
4660 /**
4661 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4662 * @param htim TIM handle
4663 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4664 * This parameter can be one of the following values:
4665 * @arg TIM_DMABASE_CR1
4666 * @arg TIM_DMABASE_CR2
4667 * @arg TIM_DMABASE_SMCR
4668 * @arg TIM_DMABASE_DIER
4669 * @arg TIM_DMABASE_SR
4670 * @arg TIM_DMABASE_EGR
4671 * @arg TIM_DMABASE_CCMR1
4672 * @arg TIM_DMABASE_CCMR2
4673 * @arg TIM_DMABASE_CCER
4674 * @arg TIM_DMABASE_CNT
4675 * @arg TIM_DMABASE_PSC
4676 * @arg TIM_DMABASE_ARR
4677 * @arg TIM_DMABASE_RCR
4678 * @arg TIM_DMABASE_CCR1
4679 * @arg TIM_DMABASE_CCR2
4680 * @arg TIM_DMABASE_CCR3
4681 * @arg TIM_DMABASE_CCR4
4682 * @arg TIM_DMABASE_BDTR
4683 * @param BurstRequestSrc TIM DMA Request sources
4684 * This parameter can be one of the following values:
4685 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4686 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4687 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4688 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4689 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4690 * @arg TIM_DMA_COM: TIM Commutation DMA source
4691 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4692 * @param BurstBuffer The Buffer address.
4693 * @param BurstLength DMA Burst length. This parameter can be one value
4694 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4695 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4696 * @retval HAL status
4697 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4698 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4699 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4700 {
4701 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4702 ((BurstLength) >> 8U) + 1U);
4703 }
4704
4705 /**
4706 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4707 * @param htim TIM handle
4708 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4709 * This parameter can be one of the following values:
4710 * @arg TIM_DMABASE_CR1
4711 * @arg TIM_DMABASE_CR2
4712 * @arg TIM_DMABASE_SMCR
4713 * @arg TIM_DMABASE_DIER
4714 * @arg TIM_DMABASE_SR
4715 * @arg TIM_DMABASE_EGR
4716 * @arg TIM_DMABASE_CCMR1
4717 * @arg TIM_DMABASE_CCMR2
4718 * @arg TIM_DMABASE_CCER
4719 * @arg TIM_DMABASE_CNT
4720 * @arg TIM_DMABASE_PSC
4721 * @arg TIM_DMABASE_ARR
4722 * @arg TIM_DMABASE_RCR
4723 * @arg TIM_DMABASE_CCR1
4724 * @arg TIM_DMABASE_CCR2
4725 * @arg TIM_DMABASE_CCR3
4726 * @arg TIM_DMABASE_CCR4
4727 * @arg TIM_DMABASE_BDTR
4728 * @param BurstRequestSrc TIM DMA Request sources
4729 * This parameter can be one of the following values:
4730 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4731 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4732 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4733 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4734 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4735 * @arg TIM_DMA_COM: TIM Commutation DMA source
4736 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4737 * @param BurstBuffer The Buffer address.
4738 * @param BurstLength DMA Burst length. This parameter can be one value
4739 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4740 * @param DataLength Data length. This parameter can be one value
4741 * between 1 and 0xFFFF.
4742 * @retval HAL status
4743 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4744 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4745 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4746 uint32_t BurstLength, uint32_t DataLength)
4747 {
4748 /* Check the parameters */
4749 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4750 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4751 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4752 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4753 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4754
4755 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4756 {
4757 return HAL_BUSY;
4758 }
4759 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4760 {
4761 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4762 {
4763 return HAL_ERROR;
4764 }
4765 else
4766 {
4767 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4768 }
4769 }
4770 else
4771 {
4772 /* nothing to do */
4773 }
4774 switch (BurstRequestSrc)
4775 {
4776 case TIM_DMA_UPDATE:
4777 {
4778 /* Set the DMA Period elapsed callbacks */
4779 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4780 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4781
4782 /* Set the DMA error callback */
4783 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4784
4785 /* Enable the DMA channel */
4786 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4787 DataLength) != HAL_OK)
4788 {
4789 /* Return error status */
4790 return HAL_ERROR;
4791 }
4792 break;
4793 }
4794 case TIM_DMA_CC1:
4795 {
4796 /* Set the DMA capture callbacks */
4797 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4798 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4799
4800 /* Set the DMA error callback */
4801 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4802
4803 /* Enable the DMA channel */
4804 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4805 DataLength) != HAL_OK)
4806 {
4807 /* Return error status */
4808 return HAL_ERROR;
4809 }
4810 break;
4811 }
4812 case TIM_DMA_CC2:
4813 {
4814 /* Set the DMA capture callbacks */
4815 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4816 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4817
4818 /* Set the DMA error callback */
4819 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4820
4821 /* Enable the DMA channel */
4822 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4823 DataLength) != HAL_OK)
4824 {
4825 /* Return error status */
4826 return HAL_ERROR;
4827 }
4828 break;
4829 }
4830 case TIM_DMA_CC3:
4831 {
4832 /* Set the DMA capture callbacks */
4833 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4834 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4835
4836 /* Set the DMA error callback */
4837 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4838
4839 /* Enable the DMA channel */
4840 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4841 DataLength) != HAL_OK)
4842 {
4843 /* Return error status */
4844 return HAL_ERROR;
4845 }
4846 break;
4847 }
4848 case TIM_DMA_CC4:
4849 {
4850 /* Set the DMA capture callbacks */
4851 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4852 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4853
4854 /* Set the DMA error callback */
4855 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4856
4857 /* Enable the DMA channel */
4858 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4859 DataLength) != HAL_OK)
4860 {
4861 /* Return error status */
4862 return HAL_ERROR;
4863 }
4864 break;
4865 }
4866 case TIM_DMA_COM:
4867 {
4868 /* Set the DMA commutation callbacks */
4869 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4870 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4871
4872 /* Set the DMA error callback */
4873 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4874
4875 /* Enable the DMA channel */
4876 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4877 DataLength) != HAL_OK)
4878 {
4879 /* Return error status */
4880 return HAL_ERROR;
4881 }
4882 break;
4883 }
4884 case TIM_DMA_TRIGGER:
4885 {
4886 /* Set the DMA trigger callbacks */
4887 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4888 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4889
4890 /* Set the DMA error callback */
4891 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4892
4893 /* Enable the DMA channel */
4894 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4895 DataLength) != HAL_OK)
4896 {
4897 /* Return error status */
4898 return HAL_ERROR;
4899 }
4900 break;
4901 }
4902 default:
4903 break;
4904 }
4905
4906 /* Configure the DMA Burst Mode */
4907 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4908
4909 /* Enable the TIM DMA Request */
4910 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4911
4912 /* Return function status */
4913 return HAL_OK;
4914 }
4915
4916 /**
4917 * @brief Stop the DMA burst reading
4918 * @param htim TIM handle
4919 * @param BurstRequestSrc TIM DMA Request sources to disable.
4920 * @retval HAL status
4921 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4922 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4923 {
4924 /* Check the parameters */
4925 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4926
4927 /* Abort the DMA transfer (at least disable the DMA channel) */
4928 switch (BurstRequestSrc)
4929 {
4930 case TIM_DMA_UPDATE:
4931 {
4932 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4933 break;
4934 }
4935 case TIM_DMA_CC1:
4936 {
4937 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4938 break;
4939 }
4940 case TIM_DMA_CC2:
4941 {
4942 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4943 break;
4944 }
4945 case TIM_DMA_CC3:
4946 {
4947 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4948 break;
4949 }
4950 case TIM_DMA_CC4:
4951 {
4952 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4953 break;
4954 }
4955 case TIM_DMA_COM:
4956 {
4957 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4958 break;
4959 }
4960 case TIM_DMA_TRIGGER:
4961 {
4962 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4963 break;
4964 }
4965 default:
4966 break;
4967 }
4968
4969 /* Disable the TIM Update DMA request */
4970 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4971
4972 /* Change the DMA burst operation state */
4973 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4974
4975 /* Return function status */
4976 return HAL_OK;
4977 }
4978
4979 /**
4980 * @brief Generate a software event
4981 * @param htim TIM handle
4982 * @param EventSource specifies the event source.
4983 * This parameter can be one of the following values:
4984 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4985 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4986 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4987 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4988 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4989 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4990 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4991 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4992 * @note Basic timers can only generate an update event.
4993 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4994 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
4995 * supporting a break input.
4996 * @retval HAL status
4997 */
4998
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4999 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5000 {
5001 /* Check the parameters */
5002 assert_param(IS_TIM_INSTANCE(htim->Instance));
5003 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5004
5005 /* Process Locked */
5006 __HAL_LOCK(htim);
5007
5008 /* Change the TIM state */
5009 htim->State = HAL_TIM_STATE_BUSY;
5010
5011 /* Set the event sources */
5012 htim->Instance->EGR = EventSource;
5013
5014 /* Change the TIM state */
5015 htim->State = HAL_TIM_STATE_READY;
5016
5017 __HAL_UNLOCK(htim);
5018
5019 /* Return function status */
5020 return HAL_OK;
5021 }
5022
5023 /**
5024 * @brief Configures the OCRef clear feature
5025 * @param htim TIM handle
5026 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5027 * contains the OCREF clear feature and parameters for the TIM peripheral.
5028 * @param Channel specifies the TIM Channel
5029 * This parameter can be one of the following values:
5030 * @arg TIM_CHANNEL_1: TIM Channel 1
5031 * @arg TIM_CHANNEL_2: TIM Channel 2
5032 * @arg TIM_CHANNEL_3: TIM Channel 3
5033 * @arg TIM_CHANNEL_4: TIM Channel 4
5034 * @retval HAL status
5035 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5036 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5037 TIM_ClearInputConfigTypeDef *sClearInputConfig,
5038 uint32_t Channel)
5039 {
5040 /* Check the parameters */
5041 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5042 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5043
5044 /* Process Locked */
5045 __HAL_LOCK(htim);
5046
5047 htim->State = HAL_TIM_STATE_BUSY;
5048
5049 switch (sClearInputConfig->ClearInputSource)
5050 {
5051 case TIM_CLEARINPUTSOURCE_NONE:
5052 {
5053 /* Clear the OCREF clear selection bit and the the ETR Bits */
5054 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5055 break;
5056 }
5057
5058 case TIM_CLEARINPUTSOURCE_ETR:
5059 {
5060 /* Check the parameters */
5061 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5062 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5063 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5064
5065 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5066 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5067 {
5068 htim->State = HAL_TIM_STATE_READY;
5069 __HAL_UNLOCK(htim);
5070 return HAL_ERROR;
5071 }
5072
5073 TIM_ETR_SetConfig(htim->Instance,
5074 sClearInputConfig->ClearInputPrescaler,
5075 sClearInputConfig->ClearInputPolarity,
5076 sClearInputConfig->ClearInputFilter);
5077 break;
5078 }
5079
5080 default:
5081 break;
5082 }
5083
5084 switch (Channel)
5085 {
5086 case TIM_CHANNEL_1:
5087 {
5088 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5089 {
5090 /* Enable the OCREF clear feature for Channel 1 */
5091 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5092 }
5093 else
5094 {
5095 /* Disable the OCREF clear feature for Channel 1 */
5096 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5097 }
5098 break;
5099 }
5100 case TIM_CHANNEL_2:
5101 {
5102 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5103 {
5104 /* Enable the OCREF clear feature for Channel 2 */
5105 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5106 }
5107 else
5108 {
5109 /* Disable the OCREF clear feature for Channel 2 */
5110 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5111 }
5112 break;
5113 }
5114 case TIM_CHANNEL_3:
5115 {
5116 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5117 {
5118 /* Enable the OCREF clear feature for Channel 3 */
5119 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5120 }
5121 else
5122 {
5123 /* Disable the OCREF clear feature for Channel 3 */
5124 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5125 }
5126 break;
5127 }
5128 case TIM_CHANNEL_4:
5129 {
5130 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5131 {
5132 /* Enable the OCREF clear feature for Channel 4 */
5133 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5134 }
5135 else
5136 {
5137 /* Disable the OCREF clear feature for Channel 4 */
5138 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5139 }
5140 break;
5141 }
5142 default:
5143 break;
5144 }
5145
5146 htim->State = HAL_TIM_STATE_READY;
5147
5148 __HAL_UNLOCK(htim);
5149
5150 return HAL_OK;
5151 }
5152
5153 /**
5154 * @brief Configures the clock source to be used
5155 * @param htim TIM handle
5156 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5157 * contains the clock source information for the TIM peripheral.
5158 * @retval HAL status
5159 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)5160 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
5161 {
5162 uint32_t tmpsmcr;
5163
5164 /* Process Locked */
5165 __HAL_LOCK(htim);
5166
5167 htim->State = HAL_TIM_STATE_BUSY;
5168
5169 /* Check the parameters */
5170 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5171
5172 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5173 tmpsmcr = htim->Instance->SMCR;
5174 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5175 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5176 htim->Instance->SMCR = tmpsmcr;
5177
5178 switch (sClockSourceConfig->ClockSource)
5179 {
5180 case TIM_CLOCKSOURCE_INTERNAL:
5181 {
5182 assert_param(IS_TIM_INSTANCE(htim->Instance));
5183 break;
5184 }
5185
5186 case TIM_CLOCKSOURCE_ETRMODE1:
5187 {
5188 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5189 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5190
5191 /* Check ETR input conditioning related parameters */
5192 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5193 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5194 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5195
5196 /* Configure the ETR Clock source */
5197 TIM_ETR_SetConfig(htim->Instance,
5198 sClockSourceConfig->ClockPrescaler,
5199 sClockSourceConfig->ClockPolarity,
5200 sClockSourceConfig->ClockFilter);
5201
5202 /* Select the External clock mode1 and the ETRF trigger */
5203 tmpsmcr = htim->Instance->SMCR;
5204 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5205 /* Write to TIMx SMCR */
5206 htim->Instance->SMCR = tmpsmcr;
5207 break;
5208 }
5209
5210 case TIM_CLOCKSOURCE_ETRMODE2:
5211 {
5212 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5213 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5214
5215 /* Check ETR input conditioning related parameters */
5216 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5217 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5218 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5219
5220 /* Configure the ETR Clock source */
5221 TIM_ETR_SetConfig(htim->Instance,
5222 sClockSourceConfig->ClockPrescaler,
5223 sClockSourceConfig->ClockPolarity,
5224 sClockSourceConfig->ClockFilter);
5225 /* Enable the External clock mode2 */
5226 htim->Instance->SMCR |= TIM_SMCR_ECE;
5227 break;
5228 }
5229
5230 case TIM_CLOCKSOURCE_TI1:
5231 {
5232 /* Check whether or not the timer instance supports external clock mode 1 */
5233 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5234
5235 /* Check TI1 input conditioning related parameters */
5236 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5237 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5238
5239 TIM_TI1_ConfigInputStage(htim->Instance,
5240 sClockSourceConfig->ClockPolarity,
5241 sClockSourceConfig->ClockFilter);
5242 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5243 break;
5244 }
5245
5246 case TIM_CLOCKSOURCE_TI2:
5247 {
5248 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5249 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5250
5251 /* Check TI2 input conditioning related parameters */
5252 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5253 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5254
5255 TIM_TI2_ConfigInputStage(htim->Instance,
5256 sClockSourceConfig->ClockPolarity,
5257 sClockSourceConfig->ClockFilter);
5258 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5259 break;
5260 }
5261
5262 case TIM_CLOCKSOURCE_TI1ED:
5263 {
5264 /* Check whether or not the timer instance supports external clock mode 1 */
5265 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5266
5267 /* Check TI1 input conditioning related parameters */
5268 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5269 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5270
5271 TIM_TI1_ConfigInputStage(htim->Instance,
5272 sClockSourceConfig->ClockPolarity,
5273 sClockSourceConfig->ClockFilter);
5274 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5275 break;
5276 }
5277
5278 case TIM_CLOCKSOURCE_ITR0:
5279 case TIM_CLOCKSOURCE_ITR1:
5280 case TIM_CLOCKSOURCE_ITR2:
5281 case TIM_CLOCKSOURCE_ITR3:
5282 {
5283 /* Check whether or not the timer instance supports internal trigger input */
5284 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5285
5286 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5287 break;
5288 }
5289
5290 default:
5291 break;
5292 }
5293 htim->State = HAL_TIM_STATE_READY;
5294
5295 __HAL_UNLOCK(htim);
5296
5297 return HAL_OK;
5298 }
5299
5300 /**
5301 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5302 * or a XOR combination between CH1_input, CH2_input & CH3_input
5303 * @param htim TIM handle.
5304 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5305 * output of a XOR gate.
5306 * This parameter can be one of the following values:
5307 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5308 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5309 * pins are connected to the TI1 input (XOR combination)
5310 * @retval HAL status
5311 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5312 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5313 {
5314 uint32_t tmpcr2;
5315
5316 /* Check the parameters */
5317 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5318 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5319
5320 /* Get the TIMx CR2 register value */
5321 tmpcr2 = htim->Instance->CR2;
5322
5323 /* Reset the TI1 selection */
5324 tmpcr2 &= ~TIM_CR2_TI1S;
5325
5326 /* Set the TI1 selection */
5327 tmpcr2 |= TI1_Selection;
5328
5329 /* Write to TIMxCR2 */
5330 htim->Instance->CR2 = tmpcr2;
5331
5332 return HAL_OK;
5333 }
5334
5335 /**
5336 * @brief Configures the TIM in Slave mode
5337 * @param htim TIM handle.
5338 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5339 * contains the selected trigger (internal trigger input, filtered
5340 * timer input or external trigger input) and the Slave mode
5341 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5342 * @retval HAL status
5343 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5344 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
5345 {
5346 /* Check the parameters */
5347 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5348 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5349 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5350
5351 __HAL_LOCK(htim);
5352
5353 htim->State = HAL_TIM_STATE_BUSY;
5354
5355 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5356 {
5357 htim->State = HAL_TIM_STATE_READY;
5358 __HAL_UNLOCK(htim);
5359 return HAL_ERROR;
5360 }
5361
5362 /* Disable Trigger Interrupt */
5363 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5364
5365 /* Disable Trigger DMA request */
5366 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5367
5368 htim->State = HAL_TIM_STATE_READY;
5369
5370 __HAL_UNLOCK(htim);
5371
5372 return HAL_OK;
5373 }
5374
5375 /**
5376 * @brief Configures the TIM in Slave mode in interrupt mode
5377 * @param htim TIM handle.
5378 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5379 * contains the selected trigger (internal trigger input, filtered
5380 * timer input or external trigger input) and the Slave mode
5381 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5382 * @retval HAL status
5383 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5384 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5385 TIM_SlaveConfigTypeDef *sSlaveConfig)
5386 {
5387 /* Check the parameters */
5388 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5389 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5390 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5391
5392 __HAL_LOCK(htim);
5393
5394 htim->State = HAL_TIM_STATE_BUSY;
5395
5396 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5397 {
5398 htim->State = HAL_TIM_STATE_READY;
5399 __HAL_UNLOCK(htim);
5400 return HAL_ERROR;
5401 }
5402
5403 /* Enable Trigger Interrupt */
5404 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5405
5406 /* Disable Trigger DMA request */
5407 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5408
5409 htim->State = HAL_TIM_STATE_READY;
5410
5411 __HAL_UNLOCK(htim);
5412
5413 return HAL_OK;
5414 }
5415
5416 /**
5417 * @brief Read the captured value from Capture Compare unit
5418 * @param htim TIM handle.
5419 * @param Channel TIM Channels to be enabled
5420 * This parameter can be one of the following values:
5421 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5422 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5423 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5424 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5425 * @retval Captured value
5426 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)5427 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
5428 {
5429 uint32_t tmpreg = 0U;
5430
5431 switch (Channel)
5432 {
5433 case TIM_CHANNEL_1:
5434 {
5435 /* Check the parameters */
5436 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5437
5438 /* Return the capture 1 value */
5439 tmpreg = htim->Instance->CCR1;
5440
5441 break;
5442 }
5443 case TIM_CHANNEL_2:
5444 {
5445 /* Check the parameters */
5446 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5447
5448 /* Return the capture 2 value */
5449 tmpreg = htim->Instance->CCR2;
5450
5451 break;
5452 }
5453
5454 case TIM_CHANNEL_3:
5455 {
5456 /* Check the parameters */
5457 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5458
5459 /* Return the capture 3 value */
5460 tmpreg = htim->Instance->CCR3;
5461
5462 break;
5463 }
5464
5465 case TIM_CHANNEL_4:
5466 {
5467 /* Check the parameters */
5468 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5469
5470 /* Return the capture 4 value */
5471 tmpreg = htim->Instance->CCR4;
5472
5473 break;
5474 }
5475
5476 default:
5477 break;
5478 }
5479
5480 return tmpreg;
5481 }
5482
5483 /**
5484 * @}
5485 */
5486
5487 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5488 * @brief TIM Callbacks functions
5489 *
5490 @verbatim
5491 ==============================================================================
5492 ##### TIM Callbacks functions #####
5493 ==============================================================================
5494 [..]
5495 This section provides TIM callback functions:
5496 (+) TIM Period elapsed callback
5497 (+) TIM Output Compare callback
5498 (+) TIM Input capture callback
5499 (+) TIM Trigger callback
5500 (+) TIM Error callback
5501
5502 @endverbatim
5503 * @{
5504 */
5505
5506 /**
5507 * @brief Period elapsed callback in non-blocking mode
5508 * @param htim TIM handle
5509 * @retval None
5510 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5511 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5512 {
5513 /* Prevent unused argument(s) compilation warning */
5514 UNUSED(htim);
5515
5516 /* NOTE : This function should not be modified, when the callback is needed,
5517 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5518 */
5519 }
5520
5521 /**
5522 * @brief Period elapsed half complete callback in non-blocking mode
5523 * @param htim TIM handle
5524 * @retval None
5525 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5526 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5527 {
5528 /* Prevent unused argument(s) compilation warning */
5529 UNUSED(htim);
5530
5531 /* NOTE : This function should not be modified, when the callback is needed,
5532 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5533 */
5534 }
5535
5536 /**
5537 * @brief Output Compare callback in non-blocking mode
5538 * @param htim TIM OC handle
5539 * @retval None
5540 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5541 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5542 {
5543 /* Prevent unused argument(s) compilation warning */
5544 UNUSED(htim);
5545
5546 /* NOTE : This function should not be modified, when the callback is needed,
5547 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5548 */
5549 }
5550
5551 /**
5552 * @brief Input Capture callback in non-blocking mode
5553 * @param htim TIM IC handle
5554 * @retval None
5555 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5556 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5557 {
5558 /* Prevent unused argument(s) compilation warning */
5559 UNUSED(htim);
5560
5561 /* NOTE : This function should not be modified, when the callback is needed,
5562 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5563 */
5564 }
5565
5566 /**
5567 * @brief Input Capture half complete callback in non-blocking mode
5568 * @param htim TIM IC handle
5569 * @retval None
5570 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5571 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5572 {
5573 /* Prevent unused argument(s) compilation warning */
5574 UNUSED(htim);
5575
5576 /* NOTE : This function should not be modified, when the callback is needed,
5577 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5578 */
5579 }
5580
5581 /**
5582 * @brief PWM Pulse finished callback in non-blocking mode
5583 * @param htim TIM handle
5584 * @retval None
5585 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5586 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5587 {
5588 /* Prevent unused argument(s) compilation warning */
5589 UNUSED(htim);
5590
5591 /* NOTE : This function should not be modified, when the callback is needed,
5592 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5593 */
5594 }
5595
5596 /**
5597 * @brief PWM Pulse finished half complete callback in non-blocking mode
5598 * @param htim TIM handle
5599 * @retval None
5600 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5601 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5602 {
5603 /* Prevent unused argument(s) compilation warning */
5604 UNUSED(htim);
5605
5606 /* NOTE : This function should not be modified, when the callback is needed,
5607 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5608 */
5609 }
5610
5611 /**
5612 * @brief Hall Trigger detection callback in non-blocking mode
5613 * @param htim TIM handle
5614 * @retval None
5615 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5616 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5617 {
5618 /* Prevent unused argument(s) compilation warning */
5619 UNUSED(htim);
5620
5621 /* NOTE : This function should not be modified, when the callback is needed,
5622 the HAL_TIM_TriggerCallback could be implemented in the user file
5623 */
5624 }
5625
5626 /**
5627 * @brief Hall Trigger detection half complete callback in non-blocking mode
5628 * @param htim TIM handle
5629 * @retval None
5630 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5631 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5632 {
5633 /* Prevent unused argument(s) compilation warning */
5634 UNUSED(htim);
5635
5636 /* NOTE : This function should not be modified, when the callback is needed,
5637 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5638 */
5639 }
5640
5641 /**
5642 * @brief Timer error callback in non-blocking mode
5643 * @param htim TIM handle
5644 * @retval None
5645 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5646 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5647 {
5648 /* Prevent unused argument(s) compilation warning */
5649 UNUSED(htim);
5650
5651 /* NOTE : This function should not be modified, when the callback is needed,
5652 the HAL_TIM_ErrorCallback could be implemented in the user file
5653 */
5654 }
5655
5656 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5657 /**
5658 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5659 * @param htim tim handle
5660 * @param CallbackID ID of the callback to be registered
5661 * This parameter can be one of the following values:
5662 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5663 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5664 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5665 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5666 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5667 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5668 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5669 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5670 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5671 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5672 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5673 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5674 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5675 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5676 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5677 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5678 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5679 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5680 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5681 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5682 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5683 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5684 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5685 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5686 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5687 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5688 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5689 * @param pCallback pointer to the callback function
5690 * @retval status
5691 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5692 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5693 pTIM_CallbackTypeDef pCallback)
5694 {
5695 HAL_StatusTypeDef status = HAL_OK;
5696
5697 if (pCallback == NULL)
5698 {
5699 return HAL_ERROR;
5700 }
5701 /* Process locked */
5702 __HAL_LOCK(htim);
5703
5704 if (htim->State == HAL_TIM_STATE_READY)
5705 {
5706 switch (CallbackID)
5707 {
5708 case HAL_TIM_BASE_MSPINIT_CB_ID :
5709 htim->Base_MspInitCallback = pCallback;
5710 break;
5711
5712 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5713 htim->Base_MspDeInitCallback = pCallback;
5714 break;
5715
5716 case HAL_TIM_IC_MSPINIT_CB_ID :
5717 htim->IC_MspInitCallback = pCallback;
5718 break;
5719
5720 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5721 htim->IC_MspDeInitCallback = pCallback;
5722 break;
5723
5724 case HAL_TIM_OC_MSPINIT_CB_ID :
5725 htim->OC_MspInitCallback = pCallback;
5726 break;
5727
5728 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5729 htim->OC_MspDeInitCallback = pCallback;
5730 break;
5731
5732 case HAL_TIM_PWM_MSPINIT_CB_ID :
5733 htim->PWM_MspInitCallback = pCallback;
5734 break;
5735
5736 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5737 htim->PWM_MspDeInitCallback = pCallback;
5738 break;
5739
5740 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5741 htim->OnePulse_MspInitCallback = pCallback;
5742 break;
5743
5744 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5745 htim->OnePulse_MspDeInitCallback = pCallback;
5746 break;
5747
5748 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5749 htim->Encoder_MspInitCallback = pCallback;
5750 break;
5751
5752 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5753 htim->Encoder_MspDeInitCallback = pCallback;
5754 break;
5755
5756 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5757 htim->HallSensor_MspInitCallback = pCallback;
5758 break;
5759
5760 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5761 htim->HallSensor_MspDeInitCallback = pCallback;
5762 break;
5763
5764 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5765 htim->PeriodElapsedCallback = pCallback;
5766 break;
5767
5768 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5769 htim->PeriodElapsedHalfCpltCallback = pCallback;
5770 break;
5771
5772 case HAL_TIM_TRIGGER_CB_ID :
5773 htim->TriggerCallback = pCallback;
5774 break;
5775
5776 case HAL_TIM_TRIGGER_HALF_CB_ID :
5777 htim->TriggerHalfCpltCallback = pCallback;
5778 break;
5779
5780 case HAL_TIM_IC_CAPTURE_CB_ID :
5781 htim->IC_CaptureCallback = pCallback;
5782 break;
5783
5784 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5785 htim->IC_CaptureHalfCpltCallback = pCallback;
5786 break;
5787
5788 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5789 htim->OC_DelayElapsedCallback = pCallback;
5790 break;
5791
5792 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5793 htim->PWM_PulseFinishedCallback = pCallback;
5794 break;
5795
5796 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5797 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5798 break;
5799
5800 case HAL_TIM_ERROR_CB_ID :
5801 htim->ErrorCallback = pCallback;
5802 break;
5803
5804 case HAL_TIM_COMMUTATION_CB_ID :
5805 htim->CommutationCallback = pCallback;
5806 break;
5807
5808 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5809 htim->CommutationHalfCpltCallback = pCallback;
5810 break;
5811
5812 case HAL_TIM_BREAK_CB_ID :
5813 htim->BreakCallback = pCallback;
5814 break;
5815
5816 default :
5817 /* Return error status */
5818 status = HAL_ERROR;
5819 break;
5820 }
5821 }
5822 else if (htim->State == HAL_TIM_STATE_RESET)
5823 {
5824 switch (CallbackID)
5825 {
5826 case HAL_TIM_BASE_MSPINIT_CB_ID :
5827 htim->Base_MspInitCallback = pCallback;
5828 break;
5829
5830 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5831 htim->Base_MspDeInitCallback = pCallback;
5832 break;
5833
5834 case HAL_TIM_IC_MSPINIT_CB_ID :
5835 htim->IC_MspInitCallback = pCallback;
5836 break;
5837
5838 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5839 htim->IC_MspDeInitCallback = pCallback;
5840 break;
5841
5842 case HAL_TIM_OC_MSPINIT_CB_ID :
5843 htim->OC_MspInitCallback = pCallback;
5844 break;
5845
5846 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5847 htim->OC_MspDeInitCallback = pCallback;
5848 break;
5849
5850 case HAL_TIM_PWM_MSPINIT_CB_ID :
5851 htim->PWM_MspInitCallback = pCallback;
5852 break;
5853
5854 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5855 htim->PWM_MspDeInitCallback = pCallback;
5856 break;
5857
5858 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5859 htim->OnePulse_MspInitCallback = pCallback;
5860 break;
5861
5862 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5863 htim->OnePulse_MspDeInitCallback = pCallback;
5864 break;
5865
5866 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5867 htim->Encoder_MspInitCallback = pCallback;
5868 break;
5869
5870 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5871 htim->Encoder_MspDeInitCallback = pCallback;
5872 break;
5873
5874 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5875 htim->HallSensor_MspInitCallback = pCallback;
5876 break;
5877
5878 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5879 htim->HallSensor_MspDeInitCallback = pCallback;
5880 break;
5881
5882 default :
5883 /* Return error status */
5884 status = HAL_ERROR;
5885 break;
5886 }
5887 }
5888 else
5889 {
5890 /* Return error status */
5891 status = HAL_ERROR;
5892 }
5893
5894 /* Release Lock */
5895 __HAL_UNLOCK(htim);
5896
5897 return status;
5898 }
5899
5900 /**
5901 * @brief Unregister a TIM callback
5902 * TIM callback is redirected to the weak predefined callback
5903 * @param htim tim handle
5904 * @param CallbackID ID of the callback to be unregistered
5905 * This parameter can be one of the following values:
5906 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5907 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5908 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5909 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5910 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5911 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5912 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5913 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5914 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5915 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5916 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5917 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5918 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5919 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5920 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5921 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5922 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5923 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5924 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5925 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5926 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5927 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5928 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5929 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5930 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5931 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5932 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5933 * @retval status
5934 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5935 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5936 {
5937 HAL_StatusTypeDef status = HAL_OK;
5938
5939 /* Process locked */
5940 __HAL_LOCK(htim);
5941
5942 if (htim->State == HAL_TIM_STATE_READY)
5943 {
5944 switch (CallbackID)
5945 {
5946 case HAL_TIM_BASE_MSPINIT_CB_ID :
5947 /* Legacy weak Base MspInit Callback */
5948 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
5949 break;
5950
5951 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5952 /* Legacy weak Base Msp DeInit Callback */
5953 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
5954 break;
5955
5956 case HAL_TIM_IC_MSPINIT_CB_ID :
5957 /* Legacy weak IC Msp Init Callback */
5958 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
5959 break;
5960
5961 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5962 /* Legacy weak IC Msp DeInit Callback */
5963 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
5964 break;
5965
5966 case HAL_TIM_OC_MSPINIT_CB_ID :
5967 /* Legacy weak OC Msp Init Callback */
5968 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
5969 break;
5970
5971 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5972 /* Legacy weak OC Msp DeInit Callback */
5973 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
5974 break;
5975
5976 case HAL_TIM_PWM_MSPINIT_CB_ID :
5977 /* Legacy weak PWM Msp Init Callback */
5978 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
5979 break;
5980
5981 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5982 /* Legacy weak PWM Msp DeInit Callback */
5983 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
5984 break;
5985
5986 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5987 /* Legacy weak One Pulse Msp Init Callback */
5988 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
5989 break;
5990
5991 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5992 /* Legacy weak One Pulse Msp DeInit Callback */
5993 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
5994 break;
5995
5996 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5997 /* Legacy weak Encoder Msp Init Callback */
5998 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
5999 break;
6000
6001 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6002 /* Legacy weak Encoder Msp DeInit Callback */
6003 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6004 break;
6005
6006 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6007 /* Legacy weak Hall Sensor Msp Init Callback */
6008 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6009 break;
6010
6011 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6012 /* Legacy weak Hall Sensor Msp DeInit Callback */
6013 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6014 break;
6015
6016 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6017 /* Legacy weak Period Elapsed Callback */
6018 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6019 break;
6020
6021 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6022 /* Legacy weak Period Elapsed half complete Callback */
6023 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6024 break;
6025
6026 case HAL_TIM_TRIGGER_CB_ID :
6027 /* Legacy weak Trigger Callback */
6028 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6029 break;
6030
6031 case HAL_TIM_TRIGGER_HALF_CB_ID :
6032 /* Legacy weak Trigger half complete Callback */
6033 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6034 break;
6035
6036 case HAL_TIM_IC_CAPTURE_CB_ID :
6037 /* Legacy weak IC Capture Callback */
6038 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6039 break;
6040
6041 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6042 /* Legacy weak IC Capture half complete Callback */
6043 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6044 break;
6045
6046 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6047 /* Legacy weak OC Delay Elapsed Callback */
6048 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6049 break;
6050
6051 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6052 /* Legacy weak PWM Pulse Finished Callback */
6053 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6054 break;
6055
6056 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6057 /* Legacy weak PWM Pulse Finished half complete Callback */
6058 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6059 break;
6060
6061 case HAL_TIM_ERROR_CB_ID :
6062 /* Legacy weak Error Callback */
6063 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6064 break;
6065
6066 case HAL_TIM_COMMUTATION_CB_ID :
6067 /* Legacy weak Commutation Callback */
6068 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6069 break;
6070
6071 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6072 /* Legacy weak Commutation half complete Callback */
6073 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6074 break;
6075
6076 case HAL_TIM_BREAK_CB_ID :
6077 /* Legacy weak Break Callback */
6078 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6079 break;
6080
6081 default :
6082 /* Return error status */
6083 status = HAL_ERROR;
6084 break;
6085 }
6086 }
6087 else if (htim->State == HAL_TIM_STATE_RESET)
6088 {
6089 switch (CallbackID)
6090 {
6091 case HAL_TIM_BASE_MSPINIT_CB_ID :
6092 /* Legacy weak Base MspInit Callback */
6093 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6094 break;
6095
6096 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6097 /* Legacy weak Base Msp DeInit Callback */
6098 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6099 break;
6100
6101 case HAL_TIM_IC_MSPINIT_CB_ID :
6102 /* Legacy weak IC Msp Init Callback */
6103 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6104 break;
6105
6106 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6107 /* Legacy weak IC Msp DeInit Callback */
6108 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6109 break;
6110
6111 case HAL_TIM_OC_MSPINIT_CB_ID :
6112 /* Legacy weak OC Msp Init Callback */
6113 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6114 break;
6115
6116 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6117 /* Legacy weak OC Msp DeInit Callback */
6118 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6119 break;
6120
6121 case HAL_TIM_PWM_MSPINIT_CB_ID :
6122 /* Legacy weak PWM Msp Init Callback */
6123 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6124 break;
6125
6126 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6127 /* Legacy weak PWM Msp DeInit Callback */
6128 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6129 break;
6130
6131 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6132 /* Legacy weak One Pulse Msp Init Callback */
6133 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6134 break;
6135
6136 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6137 /* Legacy weak One Pulse Msp DeInit Callback */
6138 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6139 break;
6140
6141 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6142 /* Legacy weak Encoder Msp Init Callback */
6143 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6144 break;
6145
6146 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6147 /* Legacy weak Encoder Msp DeInit Callback */
6148 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6149 break;
6150
6151 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6152 /* Legacy weak Hall Sensor Msp Init Callback */
6153 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6154 break;
6155
6156 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6157 /* Legacy weak Hall Sensor Msp DeInit Callback */
6158 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6159 break;
6160
6161 default :
6162 /* Return error status */
6163 status = HAL_ERROR;
6164 break;
6165 }
6166 }
6167 else
6168 {
6169 /* Return error status */
6170 status = HAL_ERROR;
6171 }
6172
6173 /* Release Lock */
6174 __HAL_UNLOCK(htim);
6175
6176 return status;
6177 }
6178 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6179
6180 /**
6181 * @}
6182 */
6183
6184 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6185 * @brief TIM Peripheral State functions
6186 *
6187 @verbatim
6188 ==============================================================================
6189 ##### Peripheral State functions #####
6190 ==============================================================================
6191 [..]
6192 This subsection permits to get in run-time the status of the peripheral
6193 and the data flow.
6194
6195 @endverbatim
6196 * @{
6197 */
6198
6199 /**
6200 * @brief Return the TIM Base handle state.
6201 * @param htim TIM Base handle
6202 * @retval HAL state
6203 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)6204 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
6205 {
6206 return htim->State;
6207 }
6208
6209 /**
6210 * @brief Return the TIM OC handle state.
6211 * @param htim TIM Output Compare handle
6212 * @retval HAL state
6213 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)6214 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
6215 {
6216 return htim->State;
6217 }
6218
6219 /**
6220 * @brief Return the TIM PWM handle state.
6221 * @param htim TIM handle
6222 * @retval HAL state
6223 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)6224 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
6225 {
6226 return htim->State;
6227 }
6228
6229 /**
6230 * @brief Return the TIM Input Capture handle state.
6231 * @param htim TIM IC handle
6232 * @retval HAL state
6233 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)6234 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
6235 {
6236 return htim->State;
6237 }
6238
6239 /**
6240 * @brief Return the TIM One Pulse Mode handle state.
6241 * @param htim TIM OPM handle
6242 * @retval HAL state
6243 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)6244 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
6245 {
6246 return htim->State;
6247 }
6248
6249 /**
6250 * @brief Return the TIM Encoder Mode handle state.
6251 * @param htim TIM Encoder Interface handle
6252 * @retval HAL state
6253 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)6254 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
6255 {
6256 return htim->State;
6257 }
6258
6259 /**
6260 * @brief Return the TIM Encoder Mode handle state.
6261 * @param htim TIM handle
6262 * @retval Active channel
6263 */
HAL_TIM_GetActiveChannel(TIM_HandleTypeDef * htim)6264 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
6265 {
6266 return htim->Channel;
6267 }
6268
6269 /**
6270 * @brief Return actual state of the TIM channel.
6271 * @param htim TIM handle
6272 * @param Channel TIM Channel
6273 * This parameter can be one of the following values:
6274 * @arg TIM_CHANNEL_1: TIM Channel 1
6275 * @arg TIM_CHANNEL_2: TIM Channel 2
6276 * @arg TIM_CHANNEL_3: TIM Channel 3
6277 * @arg TIM_CHANNEL_4: TIM Channel 4
6278 * @arg TIM_CHANNEL_5: TIM Channel 5
6279 * @arg TIM_CHANNEL_6: TIM Channel 6
6280 * @retval TIM Channel state
6281 */
HAL_TIM_GetChannelState(TIM_HandleTypeDef * htim,uint32_t Channel)6282 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
6283 {
6284 HAL_TIM_ChannelStateTypeDef channel_state;
6285
6286 /* Check the parameters */
6287 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6288
6289 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6290
6291 return channel_state;
6292 }
6293
6294 /**
6295 * @brief Return actual state of a DMA burst operation.
6296 * @param htim TIM handle
6297 * @retval DMA burst state
6298 */
HAL_TIM_DMABurstState(TIM_HandleTypeDef * htim)6299 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
6300 {
6301 /* Check the parameters */
6302 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6303
6304 return htim->DMABurstState;
6305 }
6306
6307 /**
6308 * @}
6309 */
6310
6311 /**
6312 * @}
6313 */
6314
6315 /** @defgroup TIM_Private_Functions TIM Private Functions
6316 * @{
6317 */
6318
6319 /**
6320 * @brief TIM DMA error callback
6321 * @param hdma pointer to DMA handle.
6322 * @retval None
6323 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6324 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6325 {
6326 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6327
6328 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6329 {
6330 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6331 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6332 }
6333 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6334 {
6335 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6336 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6337 }
6338 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6339 {
6340 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6341 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6342 }
6343 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6344 {
6345 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6346 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6347 }
6348 else
6349 {
6350 htim->State = HAL_TIM_STATE_READY;
6351 }
6352
6353 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6354 htim->ErrorCallback(htim);
6355 #else
6356 HAL_TIM_ErrorCallback(htim);
6357 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6358
6359 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6360 }
6361
6362 /**
6363 * @brief TIM DMA Delay Pulse complete callback.
6364 * @param hdma pointer to DMA handle.
6365 * @retval None
6366 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6367 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6368 {
6369 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6370
6371 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6372 {
6373 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6374
6375 if (hdma->Init.Mode == DMA_NORMAL)
6376 {
6377 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6378 }
6379 }
6380 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6381 {
6382 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6383
6384 if (hdma->Init.Mode == DMA_NORMAL)
6385 {
6386 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6387 }
6388 }
6389 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6390 {
6391 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6392
6393 if (hdma->Init.Mode == DMA_NORMAL)
6394 {
6395 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6396 }
6397 }
6398 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6399 {
6400 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6401
6402 if (hdma->Init.Mode == DMA_NORMAL)
6403 {
6404 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6405 }
6406 }
6407 else
6408 {
6409 /* nothing to do */
6410 }
6411
6412 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6413 htim->PWM_PulseFinishedCallback(htim);
6414 #else
6415 HAL_TIM_PWM_PulseFinishedCallback(htim);
6416 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6417
6418 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6419 }
6420
6421 /**
6422 * @brief TIM DMA Delay Pulse half complete callback.
6423 * @param hdma pointer to DMA handle.
6424 * @retval None
6425 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6426 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6427 {
6428 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6429
6430 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6431 {
6432 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6433 }
6434 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6435 {
6436 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6437 }
6438 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6439 {
6440 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6441 }
6442 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6443 {
6444 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6445 }
6446 else
6447 {
6448 /* nothing to do */
6449 }
6450
6451 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6452 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6453 #else
6454 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6455 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6456
6457 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6458 }
6459
6460 /**
6461 * @brief TIM DMA Capture complete callback.
6462 * @param hdma pointer to DMA handle.
6463 * @retval None
6464 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6465 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6466 {
6467 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6468
6469 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6470 {
6471 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6472
6473 if (hdma->Init.Mode == DMA_NORMAL)
6474 {
6475 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6476 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6477 }
6478 }
6479 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6480 {
6481 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6482
6483 if (hdma->Init.Mode == DMA_NORMAL)
6484 {
6485 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6486 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6487 }
6488 }
6489 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6490 {
6491 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6492
6493 if (hdma->Init.Mode == DMA_NORMAL)
6494 {
6495 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6496 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6497 }
6498 }
6499 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6500 {
6501 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6502
6503 if (hdma->Init.Mode == DMA_NORMAL)
6504 {
6505 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6506 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6507 }
6508 }
6509 else
6510 {
6511 /* nothing to do */
6512 }
6513
6514 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6515 htim->IC_CaptureCallback(htim);
6516 #else
6517 HAL_TIM_IC_CaptureCallback(htim);
6518 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6519
6520 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6521 }
6522
6523 /**
6524 * @brief TIM DMA Capture half complete callback.
6525 * @param hdma pointer to DMA handle.
6526 * @retval None
6527 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6528 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6529 {
6530 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6531
6532 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6533 {
6534 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6535 }
6536 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6537 {
6538 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6539 }
6540 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6541 {
6542 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6543 }
6544 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6545 {
6546 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6547 }
6548 else
6549 {
6550 /* nothing to do */
6551 }
6552
6553 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6554 htim->IC_CaptureHalfCpltCallback(htim);
6555 #else
6556 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6557 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6558
6559 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6560 }
6561
6562 /**
6563 * @brief TIM DMA Period Elapse complete callback.
6564 * @param hdma pointer to DMA handle.
6565 * @retval None
6566 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6567 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6568 {
6569 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6570
6571 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6572 {
6573 htim->State = HAL_TIM_STATE_READY;
6574 }
6575
6576 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6577 htim->PeriodElapsedCallback(htim);
6578 #else
6579 HAL_TIM_PeriodElapsedCallback(htim);
6580 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6581 }
6582
6583 /**
6584 * @brief TIM DMA Period Elapse half complete callback.
6585 * @param hdma pointer to DMA handle.
6586 * @retval None
6587 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6588 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6589 {
6590 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6591
6592 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6593 htim->PeriodElapsedHalfCpltCallback(htim);
6594 #else
6595 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6596 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6597 }
6598
6599 /**
6600 * @brief TIM DMA Trigger callback.
6601 * @param hdma pointer to DMA handle.
6602 * @retval None
6603 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6604 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6605 {
6606 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6607
6608 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6609 {
6610 htim->State = HAL_TIM_STATE_READY;
6611 }
6612
6613 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6614 htim->TriggerCallback(htim);
6615 #else
6616 HAL_TIM_TriggerCallback(htim);
6617 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6618 }
6619
6620 /**
6621 * @brief TIM DMA Trigger half complete callback.
6622 * @param hdma pointer to DMA handle.
6623 * @retval None
6624 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6625 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6626 {
6627 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6628
6629 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6630 htim->TriggerHalfCpltCallback(htim);
6631 #else
6632 HAL_TIM_TriggerHalfCpltCallback(htim);
6633 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6634 }
6635
6636 /**
6637 * @brief Time Base configuration
6638 * @param TIMx TIM peripheral
6639 * @param Structure TIM Base configuration structure
6640 * @retval None
6641 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)6642 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
6643 {
6644 uint32_t tmpcr1;
6645 tmpcr1 = TIMx->CR1;
6646
6647 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6648 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6649 {
6650 /* Select the Counter Mode */
6651 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6652 tmpcr1 |= Structure->CounterMode;
6653 }
6654
6655 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6656 {
6657 /* Set the clock division */
6658 tmpcr1 &= ~TIM_CR1_CKD;
6659 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6660 }
6661
6662 /* Set the auto-reload preload */
6663 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6664
6665 TIMx->CR1 = tmpcr1;
6666
6667 /* Set the Autoreload value */
6668 TIMx->ARR = (uint32_t)Structure->Period ;
6669
6670 /* Set the Prescaler value */
6671 TIMx->PSC = Structure->Prescaler;
6672
6673 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6674 {
6675 /* Set the Repetition Counter value */
6676 TIMx->RCR = Structure->RepetitionCounter;
6677 }
6678
6679 /* Generate an update event to reload the Prescaler
6680 and the repetition counter (only for advanced timer) value immediately */
6681 TIMx->EGR = TIM_EGR_UG;
6682 }
6683
6684 /**
6685 * @brief Timer Output Compare 1 configuration
6686 * @param TIMx to select the TIM peripheral
6687 * @param OC_Config The output configuration structure
6688 * @retval None
6689 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6690 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6691 {
6692 uint32_t tmpccmrx;
6693 uint32_t tmpccer;
6694 uint32_t tmpcr2;
6695
6696 /* Disable the Channel 1: Reset the CC1E Bit */
6697 TIMx->CCER &= ~TIM_CCER_CC1E;
6698
6699 /* Get the TIMx CCER register value */
6700 tmpccer = TIMx->CCER;
6701 /* Get the TIMx CR2 register value */
6702 tmpcr2 = TIMx->CR2;
6703
6704 /* Get the TIMx CCMR1 register value */
6705 tmpccmrx = TIMx->CCMR1;
6706
6707 /* Reset the Output Compare Mode Bits */
6708 tmpccmrx &= ~TIM_CCMR1_OC1M;
6709 tmpccmrx &= ~TIM_CCMR1_CC1S;
6710 /* Select the Output Compare Mode */
6711 tmpccmrx |= OC_Config->OCMode;
6712
6713 /* Reset the Output Polarity level */
6714 tmpccer &= ~TIM_CCER_CC1P;
6715 /* Set the Output Compare Polarity */
6716 tmpccer |= OC_Config->OCPolarity;
6717
6718 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6719 {
6720 /* Check parameters */
6721 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6722
6723 /* Reset the Output N Polarity level */
6724 tmpccer &= ~TIM_CCER_CC1NP;
6725 /* Set the Output N Polarity */
6726 tmpccer |= OC_Config->OCNPolarity;
6727 /* Reset the Output N State */
6728 tmpccer &= ~TIM_CCER_CC1NE;
6729 }
6730
6731 if (IS_TIM_BREAK_INSTANCE(TIMx))
6732 {
6733 /* Check parameters */
6734 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6735 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6736
6737 /* Reset the Output Compare and Output Compare N IDLE State */
6738 tmpcr2 &= ~TIM_CR2_OIS1;
6739 tmpcr2 &= ~TIM_CR2_OIS1N;
6740 /* Set the Output Idle state */
6741 tmpcr2 |= OC_Config->OCIdleState;
6742 /* Set the Output N Idle state */
6743 tmpcr2 |= OC_Config->OCNIdleState;
6744 }
6745
6746 /* Write to TIMx CR2 */
6747 TIMx->CR2 = tmpcr2;
6748
6749 /* Write to TIMx CCMR1 */
6750 TIMx->CCMR1 = tmpccmrx;
6751
6752 /* Set the Capture Compare Register value */
6753 TIMx->CCR1 = OC_Config->Pulse;
6754
6755 /* Write to TIMx CCER */
6756 TIMx->CCER = tmpccer;
6757 }
6758
6759 /**
6760 * @brief Timer Output Compare 2 configuration
6761 * @param TIMx to select the TIM peripheral
6762 * @param OC_Config The output configuration structure
6763 * @retval None
6764 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6765 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6766 {
6767 uint32_t tmpccmrx;
6768 uint32_t tmpccer;
6769 uint32_t tmpcr2;
6770
6771 /* Disable the Channel 2: Reset the CC2E Bit */
6772 TIMx->CCER &= ~TIM_CCER_CC2E;
6773
6774 /* Get the TIMx CCER register value */
6775 tmpccer = TIMx->CCER;
6776 /* Get the TIMx CR2 register value */
6777 tmpcr2 = TIMx->CR2;
6778
6779 /* Get the TIMx CCMR1 register value */
6780 tmpccmrx = TIMx->CCMR1;
6781
6782 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6783 tmpccmrx &= ~TIM_CCMR1_OC2M;
6784 tmpccmrx &= ~TIM_CCMR1_CC2S;
6785
6786 /* Select the Output Compare Mode */
6787 tmpccmrx |= (OC_Config->OCMode << 8U);
6788
6789 /* Reset the Output Polarity level */
6790 tmpccer &= ~TIM_CCER_CC2P;
6791 /* Set the Output Compare Polarity */
6792 tmpccer |= (OC_Config->OCPolarity << 4U);
6793
6794 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6795 {
6796 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6797
6798 /* Reset the Output N Polarity level */
6799 tmpccer &= ~TIM_CCER_CC2NP;
6800 /* Set the Output N Polarity */
6801 tmpccer |= (OC_Config->OCNPolarity << 4U);
6802 /* Reset the Output N State */
6803 tmpccer &= ~TIM_CCER_CC2NE;
6804
6805 }
6806
6807 if (IS_TIM_BREAK_INSTANCE(TIMx))
6808 {
6809 /* Check parameters */
6810 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6811 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6812
6813 /* Reset the Output Compare and Output Compare N IDLE State */
6814 tmpcr2 &= ~TIM_CR2_OIS2;
6815 tmpcr2 &= ~TIM_CR2_OIS2N;
6816 /* Set the Output Idle state */
6817 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6818 /* Set the Output N Idle state */
6819 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6820 }
6821
6822 /* Write to TIMx CR2 */
6823 TIMx->CR2 = tmpcr2;
6824
6825 /* Write to TIMx CCMR1 */
6826 TIMx->CCMR1 = tmpccmrx;
6827
6828 /* Set the Capture Compare Register value */
6829 TIMx->CCR2 = OC_Config->Pulse;
6830
6831 /* Write to TIMx CCER */
6832 TIMx->CCER = tmpccer;
6833 }
6834
6835 /**
6836 * @brief Timer Output Compare 3 configuration
6837 * @param TIMx to select the TIM peripheral
6838 * @param OC_Config The output configuration structure
6839 * @retval None
6840 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6841 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6842 {
6843 uint32_t tmpccmrx;
6844 uint32_t tmpccer;
6845 uint32_t tmpcr2;
6846
6847 /* Disable the Channel 3: Reset the CC2E Bit */
6848 TIMx->CCER &= ~TIM_CCER_CC3E;
6849
6850 /* Get the TIMx CCER register value */
6851 tmpccer = TIMx->CCER;
6852 /* Get the TIMx CR2 register value */
6853 tmpcr2 = TIMx->CR2;
6854
6855 /* Get the TIMx CCMR2 register value */
6856 tmpccmrx = TIMx->CCMR2;
6857
6858 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6859 tmpccmrx &= ~TIM_CCMR2_OC3M;
6860 tmpccmrx &= ~TIM_CCMR2_CC3S;
6861 /* Select the Output Compare Mode */
6862 tmpccmrx |= OC_Config->OCMode;
6863
6864 /* Reset the Output Polarity level */
6865 tmpccer &= ~TIM_CCER_CC3P;
6866 /* Set the Output Compare Polarity */
6867 tmpccer |= (OC_Config->OCPolarity << 8U);
6868
6869 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6870 {
6871 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6872
6873 /* Reset the Output N Polarity level */
6874 tmpccer &= ~TIM_CCER_CC3NP;
6875 /* Set the Output N Polarity */
6876 tmpccer |= (OC_Config->OCNPolarity << 8U);
6877 /* Reset the Output N State */
6878 tmpccer &= ~TIM_CCER_CC3NE;
6879 }
6880
6881 if (IS_TIM_BREAK_INSTANCE(TIMx))
6882 {
6883 /* Check parameters */
6884 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6885 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6886
6887 /* Reset the Output Compare and Output Compare N IDLE State */
6888 tmpcr2 &= ~TIM_CR2_OIS3;
6889 tmpcr2 &= ~TIM_CR2_OIS3N;
6890 /* Set the Output Idle state */
6891 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6892 /* Set the Output N Idle state */
6893 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6894 }
6895
6896 /* Write to TIMx CR2 */
6897 TIMx->CR2 = tmpcr2;
6898
6899 /* Write to TIMx CCMR2 */
6900 TIMx->CCMR2 = tmpccmrx;
6901
6902 /* Set the Capture Compare Register value */
6903 TIMx->CCR3 = OC_Config->Pulse;
6904
6905 /* Write to TIMx CCER */
6906 TIMx->CCER = tmpccer;
6907 }
6908
6909 /**
6910 * @brief Timer Output Compare 4 configuration
6911 * @param TIMx to select the TIM peripheral
6912 * @param OC_Config The output configuration structure
6913 * @retval None
6914 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6915 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6916 {
6917 uint32_t tmpccmrx;
6918 uint32_t tmpccer;
6919 uint32_t tmpcr2;
6920
6921 /* Disable the Channel 4: Reset the CC4E Bit */
6922 TIMx->CCER &= ~TIM_CCER_CC4E;
6923
6924 /* Get the TIMx CCER register value */
6925 tmpccer = TIMx->CCER;
6926 /* Get the TIMx CR2 register value */
6927 tmpcr2 = TIMx->CR2;
6928
6929 /* Get the TIMx CCMR2 register value */
6930 tmpccmrx = TIMx->CCMR2;
6931
6932 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6933 tmpccmrx &= ~TIM_CCMR2_OC4M;
6934 tmpccmrx &= ~TIM_CCMR2_CC4S;
6935
6936 /* Select the Output Compare Mode */
6937 tmpccmrx |= (OC_Config->OCMode << 8U);
6938
6939 /* Reset the Output Polarity level */
6940 tmpccer &= ~TIM_CCER_CC4P;
6941 /* Set the Output Compare Polarity */
6942 tmpccer |= (OC_Config->OCPolarity << 12U);
6943
6944 if (IS_TIM_BREAK_INSTANCE(TIMx))
6945 {
6946 /* Check parameters */
6947 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6948
6949 /* Reset the Output Compare IDLE State */
6950 tmpcr2 &= ~TIM_CR2_OIS4;
6951
6952 /* Set the Output Idle state */
6953 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6954 }
6955
6956 /* Write to TIMx CR2 */
6957 TIMx->CR2 = tmpcr2;
6958
6959 /* Write to TIMx CCMR2 */
6960 TIMx->CCMR2 = tmpccmrx;
6961
6962 /* Set the Capture Compare Register value */
6963 TIMx->CCR4 = OC_Config->Pulse;
6964
6965 /* Write to TIMx CCER */
6966 TIMx->CCER = tmpccer;
6967 }
6968
6969 /**
6970 * @brief Slave Timer configuration function
6971 * @param htim TIM handle
6972 * @param sSlaveConfig Slave timer configuration
6973 * @retval None
6974 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6975 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6976 TIM_SlaveConfigTypeDef *sSlaveConfig)
6977 {
6978 uint32_t tmpsmcr;
6979 uint32_t tmpccmr1;
6980 uint32_t tmpccer;
6981
6982 /* Get the TIMx SMCR register value */
6983 tmpsmcr = htim->Instance->SMCR;
6984
6985 /* Reset the Trigger Selection Bits */
6986 tmpsmcr &= ~TIM_SMCR_TS;
6987 /* Set the Input Trigger source */
6988 tmpsmcr |= sSlaveConfig->InputTrigger;
6989
6990 /* Reset the slave mode Bits */
6991 tmpsmcr &= ~TIM_SMCR_SMS;
6992 /* Set the slave mode */
6993 tmpsmcr |= sSlaveConfig->SlaveMode;
6994
6995 /* Write to TIMx SMCR */
6996 htim->Instance->SMCR = tmpsmcr;
6997
6998 /* Configure the trigger prescaler, filter, and polarity */
6999 switch (sSlaveConfig->InputTrigger)
7000 {
7001 case TIM_TS_ETRF:
7002 {
7003 /* Check the parameters */
7004 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7005 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7006 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7007 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7008 /* Configure the ETR Trigger source */
7009 TIM_ETR_SetConfig(htim->Instance,
7010 sSlaveConfig->TriggerPrescaler,
7011 sSlaveConfig->TriggerPolarity,
7012 sSlaveConfig->TriggerFilter);
7013 break;
7014 }
7015
7016 case TIM_TS_TI1F_ED:
7017 {
7018 /* Check the parameters */
7019 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7020 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7021
7022 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7023 {
7024 return HAL_ERROR;
7025 }
7026
7027 /* Disable the Channel 1: Reset the CC1E Bit */
7028 tmpccer = htim->Instance->CCER;
7029 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7030 tmpccmr1 = htim->Instance->CCMR1;
7031
7032 /* Set the filter */
7033 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7034 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7035
7036 /* Write to TIMx CCMR1 and CCER registers */
7037 htim->Instance->CCMR1 = tmpccmr1;
7038 htim->Instance->CCER = tmpccer;
7039 break;
7040 }
7041
7042 case TIM_TS_TI1FP1:
7043 {
7044 /* Check the parameters */
7045 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7046 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7047 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7048
7049 /* Configure TI1 Filter and Polarity */
7050 TIM_TI1_ConfigInputStage(htim->Instance,
7051 sSlaveConfig->TriggerPolarity,
7052 sSlaveConfig->TriggerFilter);
7053 break;
7054 }
7055
7056 case TIM_TS_TI2FP2:
7057 {
7058 /* Check the parameters */
7059 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7060 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7061 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7062
7063 /* Configure TI2 Filter and Polarity */
7064 TIM_TI2_ConfigInputStage(htim->Instance,
7065 sSlaveConfig->TriggerPolarity,
7066 sSlaveConfig->TriggerFilter);
7067 break;
7068 }
7069
7070 case TIM_TS_ITR0:
7071 case TIM_TS_ITR1:
7072 case TIM_TS_ITR2:
7073 case TIM_TS_ITR3:
7074 {
7075 /* Check the parameter */
7076 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7077 break;
7078 }
7079
7080 default:
7081 break;
7082 }
7083 return HAL_OK;
7084 }
7085
7086 /**
7087 * @brief Configure the TI1 as Input.
7088 * @param TIMx to select the TIM peripheral.
7089 * @param TIM_ICPolarity The Input Polarity.
7090 * This parameter can be one of the following values:
7091 * @arg TIM_ICPOLARITY_RISING
7092 * @arg TIM_ICPOLARITY_FALLING
7093 * @arg TIM_ICPOLARITY_BOTHEDGE
7094 * @param TIM_ICSelection specifies the input to be used.
7095 * This parameter can be one of the following values:
7096 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7097 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7098 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7099 * @param TIM_ICFilter Specifies the Input Capture Filter.
7100 * This parameter must be a value between 0x00 and 0x0F.
7101 * @retval None
7102 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7103 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7104 * protected against un-initialized filter and polarity values.
7105 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7106 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7107 uint32_t TIM_ICFilter)
7108 {
7109 uint32_t tmpccmr1;
7110 uint32_t tmpccer;
7111
7112 /* Disable the Channel 1: Reset the CC1E Bit */
7113 TIMx->CCER &= ~TIM_CCER_CC1E;
7114 tmpccmr1 = TIMx->CCMR1;
7115 tmpccer = TIMx->CCER;
7116
7117 /* Select the Input */
7118 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7119 {
7120 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7121 tmpccmr1 |= TIM_ICSelection;
7122 }
7123 else
7124 {
7125 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7126 }
7127
7128 /* Set the filter */
7129 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7130 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7131
7132 /* Select the Polarity and set the CC1E Bit */
7133 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7134 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7135
7136 /* Write to TIMx CCMR1 and CCER registers */
7137 TIMx->CCMR1 = tmpccmr1;
7138 TIMx->CCER = tmpccer;
7139 }
7140
7141 /**
7142 * @brief Configure the Polarity and Filter for TI1.
7143 * @param TIMx to select the TIM peripheral.
7144 * @param TIM_ICPolarity The Input Polarity.
7145 * This parameter can be one of the following values:
7146 * @arg TIM_ICPOLARITY_RISING
7147 * @arg TIM_ICPOLARITY_FALLING
7148 * @arg TIM_ICPOLARITY_BOTHEDGE
7149 * @param TIM_ICFilter Specifies the Input Capture Filter.
7150 * This parameter must be a value between 0x00 and 0x0F.
7151 * @retval None
7152 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7153 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7154 {
7155 uint32_t tmpccmr1;
7156 uint32_t tmpccer;
7157
7158 /* Disable the Channel 1: Reset the CC1E Bit */
7159 tmpccer = TIMx->CCER;
7160 TIMx->CCER &= ~TIM_CCER_CC1E;
7161 tmpccmr1 = TIMx->CCMR1;
7162
7163 /* Set the filter */
7164 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7165 tmpccmr1 |= (TIM_ICFilter << 4U);
7166
7167 /* Select the Polarity and set the CC1E Bit */
7168 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7169 tmpccer |= TIM_ICPolarity;
7170
7171 /* Write to TIMx CCMR1 and CCER registers */
7172 TIMx->CCMR1 = tmpccmr1;
7173 TIMx->CCER = tmpccer;
7174 }
7175
7176 /**
7177 * @brief Configure the TI2 as Input.
7178 * @param TIMx to select the TIM peripheral
7179 * @param TIM_ICPolarity The Input Polarity.
7180 * This parameter can be one of the following values:
7181 * @arg TIM_ICPOLARITY_RISING
7182 * @arg TIM_ICPOLARITY_FALLING
7183 * @arg TIM_ICPOLARITY_BOTHEDGE
7184 * @param TIM_ICSelection specifies the input to be used.
7185 * This parameter can be one of the following values:
7186 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7187 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7188 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7189 * @param TIM_ICFilter Specifies the Input Capture Filter.
7190 * This parameter must be a value between 0x00 and 0x0F.
7191 * @retval None
7192 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7193 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7194 * protected against un-initialized filter and polarity values.
7195 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7196 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7197 uint32_t TIM_ICFilter)
7198 {
7199 uint32_t tmpccmr1;
7200 uint32_t tmpccer;
7201
7202 /* Disable the Channel 2: Reset the CC2E Bit */
7203 TIMx->CCER &= ~TIM_CCER_CC2E;
7204 tmpccmr1 = TIMx->CCMR1;
7205 tmpccer = TIMx->CCER;
7206
7207 /* Select the Input */
7208 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7209 tmpccmr1 |= (TIM_ICSelection << 8U);
7210
7211 /* Set the filter */
7212 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7213 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7214
7215 /* Select the Polarity and set the CC2E Bit */
7216 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7217 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7218
7219 /* Write to TIMx CCMR1 and CCER registers */
7220 TIMx->CCMR1 = tmpccmr1 ;
7221 TIMx->CCER = tmpccer;
7222 }
7223
7224 /**
7225 * @brief Configure the Polarity and Filter for TI2.
7226 * @param TIMx to select the TIM peripheral.
7227 * @param TIM_ICPolarity The Input Polarity.
7228 * This parameter can be one of the following values:
7229 * @arg TIM_ICPOLARITY_RISING
7230 * @arg TIM_ICPOLARITY_FALLING
7231 * @arg TIM_ICPOLARITY_BOTHEDGE
7232 * @param TIM_ICFilter Specifies the Input Capture Filter.
7233 * This parameter must be a value between 0x00 and 0x0F.
7234 * @retval None
7235 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7236 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7237 {
7238 uint32_t tmpccmr1;
7239 uint32_t tmpccer;
7240
7241 /* Disable the Channel 2: Reset the CC2E Bit */
7242 TIMx->CCER &= ~TIM_CCER_CC2E;
7243 tmpccmr1 = TIMx->CCMR1;
7244 tmpccer = TIMx->CCER;
7245
7246 /* Set the filter */
7247 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7248 tmpccmr1 |= (TIM_ICFilter << 12U);
7249
7250 /* Select the Polarity and set the CC2E Bit */
7251 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7252 tmpccer |= (TIM_ICPolarity << 4U);
7253
7254 /* Write to TIMx CCMR1 and CCER registers */
7255 TIMx->CCMR1 = tmpccmr1 ;
7256 TIMx->CCER = tmpccer;
7257 }
7258
7259 /**
7260 * @brief Configure the TI3 as Input.
7261 * @param TIMx to select the TIM peripheral
7262 * @param TIM_ICPolarity The Input Polarity.
7263 * This parameter can be one of the following values:
7264 * @arg TIM_ICPOLARITY_RISING
7265 * @arg TIM_ICPOLARITY_FALLING
7266 * @param TIM_ICSelection specifies the input to be used.
7267 * This parameter can be one of the following values:
7268 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7269 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7270 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7271 * @param TIM_ICFilter Specifies the Input Capture Filter.
7272 * This parameter must be a value between 0x00 and 0x0F.
7273 * @retval None
7274 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7275 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7276 * protected against un-initialized filter and polarity values.
7277 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7278 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7279 uint32_t TIM_ICFilter)
7280 {
7281 uint32_t tmpccmr2;
7282 uint32_t tmpccer;
7283
7284 /* Disable the Channel 3: Reset the CC3E Bit */
7285 TIMx->CCER &= ~TIM_CCER_CC3E;
7286 tmpccmr2 = TIMx->CCMR2;
7287 tmpccer = TIMx->CCER;
7288
7289 /* Select the Input */
7290 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7291 tmpccmr2 |= TIM_ICSelection;
7292
7293 /* Set the filter */
7294 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7295 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7296
7297 /* Select the Polarity and set the CC3E Bit */
7298 tmpccer &= ~(TIM_CCER_CC3P);
7299 tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);
7300
7301 /* Write to TIMx CCMR2 and CCER registers */
7302 TIMx->CCMR2 = tmpccmr2;
7303 TIMx->CCER = tmpccer;
7304 }
7305
7306 /**
7307 * @brief Configure the TI4 as Input.
7308 * @param TIMx to select the TIM peripheral
7309 * @param TIM_ICPolarity The Input Polarity.
7310 * This parameter can be one of the following values:
7311 * @arg TIM_ICPOLARITY_RISING
7312 * @arg TIM_ICPOLARITY_FALLING
7313 * @param TIM_ICSelection specifies the input to be used.
7314 * This parameter can be one of the following values:
7315 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7316 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7317 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7318 * @param TIM_ICFilter Specifies the Input Capture Filter.
7319 * This parameter must be a value between 0x00 and 0x0F.
7320 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7321 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7322 * protected against un-initialized filter and polarity values.
7323 * @retval None
7324 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7325 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7326 uint32_t TIM_ICFilter)
7327 {
7328 uint32_t tmpccmr2;
7329 uint32_t tmpccer;
7330
7331 /* Disable the Channel 4: Reset the CC4E Bit */
7332 TIMx->CCER &= ~TIM_CCER_CC4E;
7333 tmpccmr2 = TIMx->CCMR2;
7334 tmpccer = TIMx->CCER;
7335
7336 /* Select the Input */
7337 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7338 tmpccmr2 |= (TIM_ICSelection << 8U);
7339
7340 /* Set the filter */
7341 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7342 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7343
7344 /* Select the Polarity and set the CC4E Bit */
7345 tmpccer &= ~(TIM_CCER_CC4P);
7346 tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
7347
7348 /* Write to TIMx CCMR2 and CCER registers */
7349 TIMx->CCMR2 = tmpccmr2;
7350 TIMx->CCER = tmpccer ;
7351 }
7352
7353 /**
7354 * @brief Selects the Input Trigger source
7355 * @param TIMx to select the TIM peripheral
7356 * @param InputTriggerSource The Input Trigger source.
7357 * This parameter can be one of the following values:
7358 * @arg TIM_TS_ITR0: Internal Trigger 0
7359 * @arg TIM_TS_ITR1: Internal Trigger 1
7360 * @arg TIM_TS_ITR2: Internal Trigger 2
7361 * @arg TIM_TS_ITR3: Internal Trigger 3
7362 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7363 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7364 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7365 * @arg TIM_TS_ETRF: External Trigger input
7366 * @retval None
7367 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7368 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7369 {
7370 uint32_t tmpsmcr;
7371
7372 /* Get the TIMx SMCR register value */
7373 tmpsmcr = TIMx->SMCR;
7374 /* Reset the TS Bits */
7375 tmpsmcr &= ~TIM_SMCR_TS;
7376 /* Set the Input Trigger source and the slave mode*/
7377 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7378 /* Write to TIMx SMCR */
7379 TIMx->SMCR = tmpsmcr;
7380 }
7381 /**
7382 * @brief Configures the TIMx External Trigger (ETR).
7383 * @param TIMx to select the TIM peripheral
7384 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7385 * This parameter can be one of the following values:
7386 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7387 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7388 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7389 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7390 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7391 * This parameter can be one of the following values:
7392 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7393 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7394 * @param ExtTRGFilter External Trigger Filter.
7395 * This parameter must be a value between 0x00 and 0x0F
7396 * @retval None
7397 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7398 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7399 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7400 {
7401 uint32_t tmpsmcr;
7402
7403 tmpsmcr = TIMx->SMCR;
7404
7405 /* Reset the ETR Bits */
7406 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7407
7408 /* Set the Prescaler, the Filter value and the Polarity */
7409 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7410
7411 /* Write to TIMx SMCR */
7412 TIMx->SMCR = tmpsmcr;
7413 }
7414
7415 /**
7416 * @brief Enables or disables the TIM Capture Compare Channel x.
7417 * @param TIMx to select the TIM peripheral
7418 * @param Channel specifies the TIM Channel
7419 * This parameter can be one of the following values:
7420 * @arg TIM_CHANNEL_1: TIM Channel 1
7421 * @arg TIM_CHANNEL_2: TIM Channel 2
7422 * @arg TIM_CHANNEL_3: TIM Channel 3
7423 * @arg TIM_CHANNEL_4: TIM Channel 4
7424 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7425 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7426 * @retval None
7427 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7428 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7429 {
7430 uint32_t tmp;
7431
7432 /* Check the parameters */
7433 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7434 assert_param(IS_TIM_CHANNELS(Channel));
7435
7436 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7437
7438 /* Reset the CCxE Bit */
7439 TIMx->CCER &= ~tmp;
7440
7441 /* Set or reset the CCxE Bit */
7442 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7443 }
7444
7445 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7446 /**
7447 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7448 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7449 * the configuration information for TIM module.
7450 * @retval None
7451 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7452 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7453 {
7454 /* Reset the TIM callback to the legacy weak callbacks */
7455 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7456 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7457 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7458 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7459 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7460 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7461 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7462 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7463 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7464 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7465 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7466 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7467 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7468 }
7469 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7470
7471 /**
7472 * @}
7473 */
7474
7475 #endif /* HAL_TIM_MODULE_ENABLED */
7476 /**
7477 * @}
7478 */
7479
7480 /**
7481 * @}
7482 */
7483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7484
