1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Power Controller (PWR) peripheral:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f1xx_hal.h"
28
29 /** @addtogroup STM32F1xx_HAL_Driver
30 * @{
31 */
32
33 /** @defgroup PWR PWR
34 * @brief PWR HAL module driver
35 * @{
36 */
37
38 #ifdef HAL_PWR_MODULE_ENABLED
39
40 /* Private typedef -----------------------------------------------------------*/
41 /* Private define ------------------------------------------------------------*/
42
43 /** @defgroup PWR_Private_Constants PWR Private Constants
44 * @{
45 */
46
47 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
48 * @{
49 */
50 #define PVD_MODE_IT 0x00010000U
51 #define PVD_MODE_EVT 0x00020000U
52 #define PVD_RISING_EDGE 0x00000001U
53 #define PVD_FALLING_EDGE 0x00000002U
54 /**
55 * @}
56 */
57
58
59 /** @defgroup PWR_register_alias_address PWR Register alias address
60 * @{
61 */
62 /* ------------- PWR registers bit address in the alias region ---------------*/
63 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
64 #define PWR_CR_OFFSET 0x00U
65 #define PWR_CSR_OFFSET 0x04U
66 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
67 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
68 /**
69 * @}
70 */
71
72 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
73 * @{
74 */
75 /* --- CR Register ---*/
76 /* Alias word address of LPSDSR bit */
77 #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
78 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
79
80 /* Alias word address of DBP bit */
81 #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
82 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
83
84 /* Alias word address of PVDE bit */
85 #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
86 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
87
88 /**
89 * @}
90 */
91
92 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
93 * @{
94 */
95
96 /* --- CSR Register ---*/
97 /* Alias word address of EWUP1 bit */
98 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
99 /**
100 * @}
101 */
102
103 /**
104 * @}
105 */
106
107 /* Private variables ---------------------------------------------------------*/
108 /* Private function prototypes -----------------------------------------------*/
109 /** @defgroup PWR_Private_Functions PWR Private Functions
110 * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
111 * @{
112 */
113 static void PWR_OverloadWfe(void);
114
115 /* Private functions ---------------------------------------------------------*/
116 __NOINLINE
PWR_OverloadWfe(void)117 static void PWR_OverloadWfe(void)
118 {
119 __asm volatile( "wfe" );
120 __asm volatile( "nop" );
121 }
122
123 /**
124 * @}
125 */
126
127
128 /** @defgroup PWR_Exported_Functions PWR Exported Functions
129 * @{
130 */
131
132 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
133 * @brief Initialization and de-initialization functions
134 *
135 @verbatim
136 ===============================================================================
137 ##### Initialization and de-initialization functions #####
138 ===============================================================================
139 [..]
140 After reset, the backup domain (RTC registers, RTC backup data
141 registers) is protected against possible unwanted
142 write accesses.
143 To enable access to the RTC Domain and RTC registers, proceed as follows:
144 (+) Enable the Power Controller (PWR) APB1 interface clock using the
145 __HAL_RCC_PWR_CLK_ENABLE() macro.
146 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
147
148 @endverbatim
149 * @{
150 */
151
152 /**
153 * @brief Deinitializes the PWR peripheral registers to their default reset values.
154 * @retval None
155 */
HAL_PWR_DeInit(void)156 void HAL_PWR_DeInit(void)
157 {
158 __HAL_RCC_PWR_FORCE_RESET();
159 __HAL_RCC_PWR_RELEASE_RESET();
160 }
161
162 /**
163 * @brief Enables access to the backup domain (RTC registers, RTC
164 * backup data registers ).
165 * @note If the HSE divided by 128 is used as the RTC clock, the
166 * Backup Domain Access should be kept enabled.
167 * @retval None
168 */
HAL_PWR_EnableBkUpAccess(void)169 void HAL_PWR_EnableBkUpAccess(void)
170 {
171 /* Enable access to RTC and backup registers */
172 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
173 }
174
175 /**
176 * @brief Disables access to the backup domain (RTC registers, RTC
177 * backup data registers).
178 * @note If the HSE divided by 128 is used as the RTC clock, the
179 * Backup Domain Access should be kept enabled.
180 * @retval None
181 */
HAL_PWR_DisableBkUpAccess(void)182 void HAL_PWR_DisableBkUpAccess(void)
183 {
184 /* Disable access to RTC and backup registers */
185 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
186 }
187
188 /**
189 * @}
190 */
191
192 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
193 * @brief Low Power modes configuration functions
194 *
195 @verbatim
196 ===============================================================================
197 ##### Peripheral Control functions #####
198 ===============================================================================
199
200 *** PVD configuration ***
201 =========================
202 [..]
203 (+) The PVD is used to monitor the VDD power supply by comparing it to a
204 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
205
206 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
207 than the PVD threshold. This event is internally connected to the EXTI
208 line16 and can generate an interrupt if enabled. This is done through
209 __HAL_PVD_EXTI_ENABLE_IT() macro.
210 (+) The PVD is stopped in Standby mode.
211
212 *** WakeUp pin configuration ***
213 ================================
214 [..]
215 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
216 forced in input pull-down configuration and is active on rising edges.
217 (+) There is one WakeUp pin:
218 WakeUp Pin 1 on PA.00.
219
220 [..]
221
222 *** Low Power modes configuration ***
223 =====================================
224 [..]
225 The device features 3 low-power modes:
226 (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
227 NVIC, SysTick, etc. are kept running
228 (+) Stop mode: All clocks are stopped
229 (+) Standby mode: 1.8V domain powered off
230
231
232 *** Sleep mode ***
233 ==================
234 [..]
235 (+) Entry:
236 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
237 functions with
238 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
239 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
240
241 (+) Exit:
242 (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
243 controller (NVIC) can wake up the device from Sleep mode.
244 (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
245 (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
246 (+++) Any EXTI Line (Internal or External) configured in Event mode
247
248 *** Stop mode ***
249 =================
250 [..]
251 The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
252 clock gating. The voltage regulator can be configured either in normal or low-power mode.
253 In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
254 oscillators are disabled. SRAM and register contents are preserved.
255 In Stop mode, all I/O pins keep the same state as in Run mode.
256
257 (+) Entry:
258 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
259 function with:
260 (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
261 (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
262 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
263 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
264 (+) Exit:
265 (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
266 (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
267
268 *** Standby mode ***
269 ====================
270 [..]
271 The Standby mode allows to achieve the lowest power consumption. It is based on the
272 Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
273 consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
274 switched off. SRAM and register contents are lost except for registers in the Backup domain
275 and Standby circuitry
276
277 (+) Entry:
278 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
279 (+) Exit:
280 (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
281 NRSTpin, IWDG Reset
282
283 *** Auto-wakeup (AWU) from low-power mode ***
284 =============================================
285 [..]
286
287 (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
288 without depending on an external interrupt (Auto-wakeup mode).
289
290 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
291
292 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
293 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
294
295 *** PWR Workarounds linked to Silicon Limitation ***
296 ====================================================
297 [..]
298 Below the list of all silicon limitations known on STM32F1xx prouct.
299
300 (#)Workarounds Implemented inside PWR HAL Driver
301 (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
309 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
310 * information for the PVD.
311 * @note Refer to the electrical characteristics of your device datasheet for
312 * more details about the voltage threshold corresponding to each
313 * detection level.
314 * @retval None
315 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)316 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
317 {
318 /* Check the parameters */
319 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
320 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
321
322 /* Set PLS[7:5] bits according to PVDLevel value */
323 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
324
325 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
326 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
327 __HAL_PWR_PVD_EXTI_DISABLE_IT();
328 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
329 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
330
331 /* Configure interrupt mode */
332 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
333 {
334 __HAL_PWR_PVD_EXTI_ENABLE_IT();
335 }
336
337 /* Configure event mode */
338 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
339 {
340 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
341 }
342
343 /* Configure the edge */
344 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
345 {
346 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
347 }
348
349 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
350 {
351 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
352 }
353 }
354
355 /**
356 * @brief Enables the Power Voltage Detector(PVD).
357 * @retval None
358 */
HAL_PWR_EnablePVD(void)359 void HAL_PWR_EnablePVD(void)
360 {
361 /* Enable the power voltage detector */
362 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
363 }
364
365 /**
366 * @brief Disables the Power Voltage Detector(PVD).
367 * @retval None
368 */
HAL_PWR_DisablePVD(void)369 void HAL_PWR_DisablePVD(void)
370 {
371 /* Disable the power voltage detector */
372 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
373 }
374
375 /**
376 * @brief Enables the WakeUp PINx functionality.
377 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
378 * This parameter can be one of the following values:
379 * @arg PWR_WAKEUP_PIN1
380 * @retval None
381 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)382 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
383 {
384 /* Check the parameter */
385 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
386 /* Enable the EWUPx pin */
387 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
388 }
389
390 /**
391 * @brief Disables the WakeUp PINx functionality.
392 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
393 * This parameter can be one of the following values:
394 * @arg PWR_WAKEUP_PIN1
395 * @retval None
396 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)397 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
398 {
399 /* Check the parameter */
400 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
401 /* Disable the EWUPx pin */
402 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
403 }
404
405 /**
406 * @brief Enters Sleep mode.
407 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
408 * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
409 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
410 * When WFI entry is used, tick interrupt have to be disabled if not desired as
411 * the interrupt wake up source.
412 * This parameter can be one of the following values:
413 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
414 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
415 * @retval None
416 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)417 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
418 {
419 /* Check the parameters */
420 /* No check on Regulator because parameter not used in SLEEP mode */
421 /* Prevent unused argument(s) compilation warning */
422 UNUSED(Regulator);
423
424 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
425
426 /* Clear SLEEPDEEP bit of Cortex System Control Register */
427 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
428
429 /* Select SLEEP mode entry -------------------------------------------------*/
430 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
431 {
432 /* Request Wait For Interrupt */
433 __WFI();
434 }
435 else
436 {
437 /* Request Wait For Event */
438 __SEV();
439 __WFE();
440 __WFE();
441 }
442 }
443
444 /**
445 * @brief Enters Stop mode.
446 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
447 * @note When exiting Stop mode by using an interrupt or a wakeup event,
448 * HSI RC oscillator is selected as system clock.
449 * @note When the voltage regulator operates in low power mode, an additional
450 * startup delay is incurred when waking up from Stop mode.
451 * By keeping the internal regulator ON during Stop mode, the consumption
452 * is higher although the startup time is reduced.
453 * @param Regulator: Specifies the regulator state in Stop mode.
454 * This parameter can be one of the following values:
455 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
456 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
457 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
458 * This parameter can be one of the following values:
459 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
460 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
461 * @retval None
462 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)463 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
464 {
465 /* Check the parameters */
466 assert_param(IS_PWR_REGULATOR(Regulator));
467 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
468
469 /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
470 CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
471
472 /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
473 MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
474
475 /* Set SLEEPDEEP bit of Cortex System Control Register */
476 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
477
478 /* Select Stop mode entry --------------------------------------------------*/
479 if(STOPEntry == PWR_STOPENTRY_WFI)
480 {
481 /* Request Wait For Interrupt */
482 __WFI();
483 }
484 else
485 {
486 /* Request Wait For Event */
487 __SEV();
488 PWR_OverloadWfe(); /* WFE redefine locally */
489 PWR_OverloadWfe(); /* WFE redefine locally */
490 }
491 /* Reset SLEEPDEEP bit of Cortex System Control Register */
492 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
493 }
494
495 /**
496 * @brief Enters Standby mode.
497 * @note In Standby mode, all I/O pins are high impedance except for:
498 * - Reset pad (still available)
499 * - TAMPER pin if configured for tamper or calibration out.
500 * - WKUP pin (PA0) if enabled.
501 * @retval None
502 */
HAL_PWR_EnterSTANDBYMode(void)503 void HAL_PWR_EnterSTANDBYMode(void)
504 {
505 /* Select Standby mode */
506 SET_BIT(PWR->CR, PWR_CR_PDDS);
507
508 /* Set SLEEPDEEP bit of Cortex System Control Register */
509 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
510
511 /* This option is used to ensure that store operations are completed */
512 #if defined ( __CC_ARM)
513 __force_stores();
514 #endif
515 /* Request Wait For Interrupt */
516 __WFI();
517 }
518
519
520 /**
521 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
522 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
523 * re-enters SLEEP mode when an interruption handling is over.
524 * Setting this bit is useful when the processor is expected to run only on
525 * interruptions handling.
526 * @retval None
527 */
HAL_PWR_EnableSleepOnExit(void)528 void HAL_PWR_EnableSleepOnExit(void)
529 {
530 /* Set SLEEPONEXIT bit of Cortex System Control Register */
531 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
532 }
533
534
535 /**
536 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
537 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
538 * re-enters SLEEP mode when an interruption handling is over.
539 * @retval None
540 */
HAL_PWR_DisableSleepOnExit(void)541 void HAL_PWR_DisableSleepOnExit(void)
542 {
543 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
544 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
545 }
546
547
548 /**
549 * @brief Enables CORTEX M3 SEVONPEND bit.
550 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
551 * WFE to wake up when an interrupt moves from inactive to pended.
552 * @retval None
553 */
HAL_PWR_EnableSEVOnPend(void)554 void HAL_PWR_EnableSEVOnPend(void)
555 {
556 /* Set SEVONPEND bit of Cortex System Control Register */
557 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
558 }
559
560
561 /**
562 * @brief Disables CORTEX M3 SEVONPEND bit.
563 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
564 * WFE to wake up when an interrupt moves from inactive to pended.
565 * @retval None
566 */
HAL_PWR_DisableSEVOnPend(void)567 void HAL_PWR_DisableSEVOnPend(void)
568 {
569 /* Clear SEVONPEND bit of Cortex System Control Register */
570 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
571 }
572
573
574
575 /**
576 * @brief This function handles the PWR PVD interrupt request.
577 * @note This API should be called under the PVD_IRQHandler().
578 * @retval None
579 */
HAL_PWR_PVD_IRQHandler(void)580 void HAL_PWR_PVD_IRQHandler(void)
581 {
582 /* Check PWR exti flag */
583 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
584 {
585 /* PWR PVD interrupt user callback */
586 HAL_PWR_PVDCallback();
587
588 /* Clear PWR Exti pending bit */
589 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
590 }
591 }
592
593 /**
594 * @brief PWR PVD interrupt callback
595 * @retval None
596 */
HAL_PWR_PVDCallback(void)597 __weak void HAL_PWR_PVDCallback(void)
598 {
599 /* NOTE : This function Should not be modified, when the callback is needed,
600 the HAL_PWR_PVDCallback could be implemented in the user file
601 */
602 }
603
604 /**
605 * @}
606 */
607
608 /**
609 * @}
610 */
611
612 #endif /* HAL_PWR_MODULE_ENABLED */
613 /**
614 * @}
615 */
616
617 /**
618 * @}
619 */
620
621 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
622
