1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_gpio.h
4 * @author MCD Application Team
5 * @brief Header file of GPIO LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F1xx_LL_GPIO_H
22 #define STM32F1xx_LL_GPIO_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx.h"
30
31 /** @addtogroup STM32F1xx_LL_Driver
32 * @{
33 */
34
35 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
36
37 /** @defgroup GPIO_LL GPIO
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44
45 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
46 * @{
47 */
48 /* Defines used for Pin Mask Initialization */
49 #define GPIO_PIN_MASK_POS 8U
50 #define GPIO_PIN_NB 16U
51 /**
52 * @}
53 */
54
55 /* Private macros ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
58 * @{
59 */
60
61 /**
62 * @}
63 */
64 #endif /*USE_FULL_LL_DRIVER*/
65
66 /* Exported types ------------------------------------------------------------*/
67 #if defined(USE_FULL_LL_DRIVER)
68 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
69 * @{
70 */
71
72 /**
73 * @brief LL GPIO Init Structure definition
74 */
75 typedef struct
76 {
77 uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
78 This parameter can be any value of @ref GPIO_LL_EC_PIN */
79
80 uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
81 This parameter can be a value of @ref GPIO_LL_EC_MODE.
82
83 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
84
85 uint32_t Speed; /*!< Specifies the speed for the selected pins.
86 This parameter can be a value of @ref GPIO_LL_EC_SPEED.
87
88 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
89
90 uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
91 This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
92
93 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
94
95 uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
96 This parameter can be a value of @ref GPIO_LL_EC_PULL.
97
98 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
99 } LL_GPIO_InitTypeDef;
100
101 /**
102 * @}
103 */
104 #endif /* USE_FULL_LL_DRIVER */
105
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
108 * @{
109 */
110
111 /** @defgroup GPIO_LL_EC_PIN PIN
112 * @{
113 */
114 #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */
115 #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */
116 #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */
117 #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */
118 #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */
119 #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */
120 #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */
121 #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */
122 #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */
123 #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */
124 #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */
125 #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */
126 #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */
127 #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */
128 #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */
129 #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */
130 #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
131 LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
132 LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
133 LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
134 LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
135 LL_GPIO_PIN_15) /*!< Select all pins */
136 /**
137 * @}
138 */
139
140 /** @defgroup GPIO_LL_EC_MODE Mode
141 * @{
142 */
143 #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
144 #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
145 #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
146 #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
147 #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
148 /**
149 * @}
150 */
151
152 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
153 * @{
154 */
155 #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
156 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
157 /**
158 * @}
159 */
160
161 /** @defgroup GPIO_LL_EC_SPEED Output Speed
162 * @{
163 */
164 #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
165 #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
166 #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
167 /**
168 * @}
169 */
170
171 #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
172 #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
173 #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
174
175 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
176 * @{
177 */
178 #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
179 #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
180
181 /**
182 * @}
183 */
184
185 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
186 * @{
187 */
188
189 #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
190 #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
191 #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
192 #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
193 #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
194 #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
195 #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
196 #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
197 #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
198 #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
199 #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
200 #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
201 #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
202 #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
203 #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
204 #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
205
206 /**
207 * @}
208 */
209
210 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
211 * @{
212 */
213
214 #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
215 #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
216 #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
217 #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
218 #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
219
220 /**
221 * @}
222 */
223
224 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
225 * @{
226 */
227 #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
228 #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
229 #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
230 #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
231 #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
232 #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
233 #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
234 /**
235 * @}
236 */
237
238 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
239 * @{
240 */
241 #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
242 #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
243 #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
244 #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
245 #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
246 #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
247 #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
248 #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
249 #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
250 #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
251 #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
252 #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
253 #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
254 #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
255 #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
256 #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
257 /**
258 * @}
259 */
260
261 /**
262 * @}
263 */
264
265 /* Exported macro ------------------------------------------------------------*/
266 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
267 * @{
268 */
269
270 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
271 * @{
272 */
273
274 /**
275 * @brief Write a value in GPIO register
276 * @param __INSTANCE__ GPIO Instance
277 * @param __REG__ Register to be written
278 * @param __VALUE__ Value to be written in the register
279 * @retval None
280 */
281 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
282
283 /**
284 * @brief Read a value in GPIO register
285 * @param __INSTANCE__ GPIO Instance
286 * @param __REG__ Register to be read
287 * @retval Register value
288 */
289 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
290 /**
291 * @}
292 */
293
294 /**
295 * @}
296 */
297
298 /* Exported functions --------------------------------------------------------*/
299 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
300 * @{
301 */
302
303 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
304 * @{
305 */
306
307 /**
308 * @brief Configure gpio mode for a dedicated pin on dedicated port.
309 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
310 * Alternate function Output.
311 * @note Warning: only one pin can be passed as parameter.
312 * @rmtoll CRL CNFy LL_GPIO_SetPinMode
313 * @rmtoll CRL MODEy LL_GPIO_SetPinMode
314 * @rmtoll CRH CNFy LL_GPIO_SetPinMode
315 * @rmtoll CRH MODEy LL_GPIO_SetPinMode
316 * @param GPIOx GPIO Port
317 * @param Pin This parameter can be one of the following values:
318 * @arg @ref LL_GPIO_PIN_0
319 * @arg @ref LL_GPIO_PIN_1
320 * @arg @ref LL_GPIO_PIN_2
321 * @arg @ref LL_GPIO_PIN_3
322 * @arg @ref LL_GPIO_PIN_4
323 * @arg @ref LL_GPIO_PIN_5
324 * @arg @ref LL_GPIO_PIN_6
325 * @arg @ref LL_GPIO_PIN_7
326 * @arg @ref LL_GPIO_PIN_8
327 * @arg @ref LL_GPIO_PIN_9
328 * @arg @ref LL_GPIO_PIN_10
329 * @arg @ref LL_GPIO_PIN_11
330 * @arg @ref LL_GPIO_PIN_12
331 * @arg @ref LL_GPIO_PIN_13
332 * @arg @ref LL_GPIO_PIN_14
333 * @arg @ref LL_GPIO_PIN_15
334 * @param Mode This parameter can be one of the following values:
335 * @arg @ref LL_GPIO_MODE_ANALOG
336 * @arg @ref LL_GPIO_MODE_FLOATING
337 * @arg @ref LL_GPIO_MODE_INPUT
338 * @arg @ref LL_GPIO_MODE_OUTPUT
339 * @arg @ref LL_GPIO_MODE_ALTERNATE
340 * @retval None
341 */
LL_GPIO_SetPinMode(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Mode)342 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
343 {
344 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
345 MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
346 }
347
348 /**
349 * @brief Return gpio mode for a dedicated pin on dedicated port.
350 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
351 * Alternate function Output.
352 * @note Warning: only one pin can be passed as parameter.
353 * @rmtoll CRL CNFy LL_GPIO_GetPinMode
354 * @rmtoll CRL MODEy LL_GPIO_GetPinMode
355 * @rmtoll CRH CNFy LL_GPIO_GetPinMode
356 * @rmtoll CRH MODEy LL_GPIO_GetPinMode
357 * @param GPIOx GPIO Port
358 * @param Pin This parameter can be one of the following values:
359 * @arg @ref LL_GPIO_PIN_0
360 * @arg @ref LL_GPIO_PIN_1
361 * @arg @ref LL_GPIO_PIN_2
362 * @arg @ref LL_GPIO_PIN_3
363 * @arg @ref LL_GPIO_PIN_4
364 * @arg @ref LL_GPIO_PIN_5
365 * @arg @ref LL_GPIO_PIN_6
366 * @arg @ref LL_GPIO_PIN_7
367 * @arg @ref LL_GPIO_PIN_8
368 * @arg @ref LL_GPIO_PIN_9
369 * @arg @ref LL_GPIO_PIN_10
370 * @arg @ref LL_GPIO_PIN_11
371 * @arg @ref LL_GPIO_PIN_12
372 * @arg @ref LL_GPIO_PIN_13
373 * @arg @ref LL_GPIO_PIN_14
374 * @arg @ref LL_GPIO_PIN_15
375 * @retval Returned value can be one of the following values:
376 * @arg @ref LL_GPIO_MODE_ANALOG
377 * @arg @ref LL_GPIO_MODE_FLOATING
378 * @arg @ref LL_GPIO_MODE_INPUT
379 * @arg @ref LL_GPIO_MODE_OUTPUT
380 * @arg @ref LL_GPIO_MODE_ALTERNATE
381 */
LL_GPIO_GetPinMode(GPIO_TypeDef * GPIOx,uint32_t Pin)382 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
383 {
384 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
385 return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
386 }
387
388 /**
389 * @brief Configure gpio speed for a dedicated pin on dedicated port.
390 * @note I/O speed can be Low, Medium or Fast speed.
391 * @note Warning: only one pin can be passed as parameter.
392 * @note Refer to datasheet for frequency specifications and the power
393 * supply and load conditions for each speed.
394 * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
395 * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
396 * @param GPIOx GPIO Port
397 * @param Pin This parameter can be one of the following values:
398 * @arg @ref LL_GPIO_PIN_0
399 * @arg @ref LL_GPIO_PIN_1
400 * @arg @ref LL_GPIO_PIN_2
401 * @arg @ref LL_GPIO_PIN_3
402 * @arg @ref LL_GPIO_PIN_4
403 * @arg @ref LL_GPIO_PIN_5
404 * @arg @ref LL_GPIO_PIN_6
405 * @arg @ref LL_GPIO_PIN_7
406 * @arg @ref LL_GPIO_PIN_8
407 * @arg @ref LL_GPIO_PIN_9
408 * @arg @ref LL_GPIO_PIN_10
409 * @arg @ref LL_GPIO_PIN_11
410 * @arg @ref LL_GPIO_PIN_12
411 * @arg @ref LL_GPIO_PIN_13
412 * @arg @ref LL_GPIO_PIN_14
413 * @arg @ref LL_GPIO_PIN_15
414 * @param Speed This parameter can be one of the following values:
415 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
416 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
417 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
418 * @retval None
419 */
LL_GPIO_SetPinSpeed(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Speed)420 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
421 {
422 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
423 MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
424 (Speed << (POSITION_VAL(Pin) * 4U)));
425 }
426
427 /**
428 * @brief Return gpio speed for a dedicated pin on dedicated port.
429 * @note I/O speed can be Low, Medium, Fast or High speed.
430 * @note Warning: only one pin can be passed as parameter.
431 * @note Refer to datasheet for frequency specifications and the power
432 * supply and load conditions for each speed.
433 * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
434 * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
435 * @param GPIOx GPIO Port
436 * @param Pin This parameter can be one of the following values:
437 * @arg @ref LL_GPIO_PIN_0
438 * @arg @ref LL_GPIO_PIN_1
439 * @arg @ref LL_GPIO_PIN_2
440 * @arg @ref LL_GPIO_PIN_3
441 * @arg @ref LL_GPIO_PIN_4
442 * @arg @ref LL_GPIO_PIN_5
443 * @arg @ref LL_GPIO_PIN_6
444 * @arg @ref LL_GPIO_PIN_7
445 * @arg @ref LL_GPIO_PIN_8
446 * @arg @ref LL_GPIO_PIN_9
447 * @arg @ref LL_GPIO_PIN_10
448 * @arg @ref LL_GPIO_PIN_11
449 * @arg @ref LL_GPIO_PIN_12
450 * @arg @ref LL_GPIO_PIN_13
451 * @arg @ref LL_GPIO_PIN_14
452 * @arg @ref LL_GPIO_PIN_15
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_GPIO_SPEED_FREQ_LOW
455 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
456 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
457 */
LL_GPIO_GetPinSpeed(GPIO_TypeDef * GPIOx,uint32_t Pin)458 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
459 {
460 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
461 return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
462 }
463
464 /**
465 * @brief Configure gpio output type for several pins on dedicated port.
466 * @note Output type as to be set when gpio pin is in output or
467 * alternate modes. Possible type are Push-pull or Open-drain.
468 * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
469 * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
470 * @param GPIOx GPIO Port
471 * @param Pin This parameter can be a combination of the following values:
472 * @arg @ref LL_GPIO_PIN_0
473 * @arg @ref LL_GPIO_PIN_1
474 * @arg @ref LL_GPIO_PIN_2
475 * @arg @ref LL_GPIO_PIN_3
476 * @arg @ref LL_GPIO_PIN_4
477 * @arg @ref LL_GPIO_PIN_5
478 * @arg @ref LL_GPIO_PIN_6
479 * @arg @ref LL_GPIO_PIN_7
480 * @arg @ref LL_GPIO_PIN_8
481 * @arg @ref LL_GPIO_PIN_9
482 * @arg @ref LL_GPIO_PIN_10
483 * @arg @ref LL_GPIO_PIN_11
484 * @arg @ref LL_GPIO_PIN_12
485 * @arg @ref LL_GPIO_PIN_13
486 * @arg @ref LL_GPIO_PIN_14
487 * @arg @ref LL_GPIO_PIN_15
488 * @arg @ref LL_GPIO_PIN_ALL
489 * @param OutputType This parameter can be one of the following values:
490 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
491 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
492 * @retval None
493 */
LL_GPIO_SetPinOutputType(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t OutputType)494 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
495 {
496 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
497 MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
498 (OutputType << (POSITION_VAL(Pin) * 4U)));
499 }
500
501 /**
502 * @brief Return gpio output type for several pins on dedicated port.
503 * @note Output type as to be set when gpio pin is in output or
504 * alternate modes. Possible type are Push-pull or Open-drain.
505 * @note Warning: only one pin can be passed as parameter.
506 * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
507 * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
508 * @param GPIOx GPIO Port
509 * @param Pin This parameter can be one of the following values:
510 * @arg @ref LL_GPIO_PIN_0
511 * @arg @ref LL_GPIO_PIN_1
512 * @arg @ref LL_GPIO_PIN_2
513 * @arg @ref LL_GPIO_PIN_3
514 * @arg @ref LL_GPIO_PIN_4
515 * @arg @ref LL_GPIO_PIN_5
516 * @arg @ref LL_GPIO_PIN_6
517 * @arg @ref LL_GPIO_PIN_7
518 * @arg @ref LL_GPIO_PIN_8
519 * @arg @ref LL_GPIO_PIN_9
520 * @arg @ref LL_GPIO_PIN_10
521 * @arg @ref LL_GPIO_PIN_11
522 * @arg @ref LL_GPIO_PIN_12
523 * @arg @ref LL_GPIO_PIN_13
524 * @arg @ref LL_GPIO_PIN_14
525 * @arg @ref LL_GPIO_PIN_15
526 * @arg @ref LL_GPIO_PIN_ALL
527 * @retval Returned value can be one of the following values:
528 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
529 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
530 */
LL_GPIO_GetPinOutputType(GPIO_TypeDef * GPIOx,uint32_t Pin)531 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
532 {
533 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
534 return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
535
536 }
537
538 /**
539 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
540 * @note Warning: only one pin can be passed as parameter.
541 * @rmtoll ODR ODR LL_GPIO_SetPinPull
542 * @param GPIOx GPIO Port
543 * @param Pin This parameter can be one of the following values:
544 * @arg @ref LL_GPIO_PIN_0
545 * @arg @ref LL_GPIO_PIN_1
546 * @arg @ref LL_GPIO_PIN_2
547 * @arg @ref LL_GPIO_PIN_3
548 * @arg @ref LL_GPIO_PIN_4
549 * @arg @ref LL_GPIO_PIN_5
550 * @arg @ref LL_GPIO_PIN_6
551 * @arg @ref LL_GPIO_PIN_7
552 * @arg @ref LL_GPIO_PIN_8
553 * @arg @ref LL_GPIO_PIN_9
554 * @arg @ref LL_GPIO_PIN_10
555 * @arg @ref LL_GPIO_PIN_11
556 * @arg @ref LL_GPIO_PIN_12
557 * @arg @ref LL_GPIO_PIN_13
558 * @arg @ref LL_GPIO_PIN_14
559 * @arg @ref LL_GPIO_PIN_15
560 * @param Pull This parameter can be one of the following values:
561 * @arg @ref LL_GPIO_PULL_DOWN
562 * @arg @ref LL_GPIO_PULL_UP
563 * @retval None
564 */
LL_GPIO_SetPinPull(GPIO_TypeDef * GPIOx,uint32_t Pin,uint32_t Pull)565 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
566 {
567 MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
568 }
569
570 /**
571 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
572 * @note Warning: only one pin can be passed as parameter.
573 * @rmtoll ODR ODR LL_GPIO_GetPinPull
574 * @param GPIOx GPIO Port
575 * @param Pin This parameter can be one of the following values:
576 * @arg @ref LL_GPIO_PIN_0
577 * @arg @ref LL_GPIO_PIN_1
578 * @arg @ref LL_GPIO_PIN_2
579 * @arg @ref LL_GPIO_PIN_3
580 * @arg @ref LL_GPIO_PIN_4
581 * @arg @ref LL_GPIO_PIN_5
582 * @arg @ref LL_GPIO_PIN_6
583 * @arg @ref LL_GPIO_PIN_7
584 * @arg @ref LL_GPIO_PIN_8
585 * @arg @ref LL_GPIO_PIN_9
586 * @arg @ref LL_GPIO_PIN_10
587 * @arg @ref LL_GPIO_PIN_11
588 * @arg @ref LL_GPIO_PIN_12
589 * @arg @ref LL_GPIO_PIN_13
590 * @arg @ref LL_GPIO_PIN_14
591 * @arg @ref LL_GPIO_PIN_15
592 * @retval Returned value can be one of the following values:
593 * @arg @ref LL_GPIO_PULL_DOWN
594 * @arg @ref LL_GPIO_PULL_UP
595 */
LL_GPIO_GetPinPull(GPIO_TypeDef * GPIOx,uint32_t Pin)596 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
597 {
598 return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
599 }
600
601 /**
602 * @brief Lock configuration of several pins for a dedicated port.
603 * @note When the lock sequence has been applied on a port bit, the
604 * value of this port bit can no longer be modified until the
605 * next reset.
606 * @note Each lock bit freezes a specific configuration register
607 * (control and alternate function registers).
608 * @rmtoll LCKR LCKK LL_GPIO_LockPin
609 * @param GPIOx GPIO Port
610 * @param PinMask This parameter can be a combination of the following values:
611 * @arg @ref LL_GPIO_PIN_0
612 * @arg @ref LL_GPIO_PIN_1
613 * @arg @ref LL_GPIO_PIN_2
614 * @arg @ref LL_GPIO_PIN_3
615 * @arg @ref LL_GPIO_PIN_4
616 * @arg @ref LL_GPIO_PIN_5
617 * @arg @ref LL_GPIO_PIN_6
618 * @arg @ref LL_GPIO_PIN_7
619 * @arg @ref LL_GPIO_PIN_8
620 * @arg @ref LL_GPIO_PIN_9
621 * @arg @ref LL_GPIO_PIN_10
622 * @arg @ref LL_GPIO_PIN_11
623 * @arg @ref LL_GPIO_PIN_12
624 * @arg @ref LL_GPIO_PIN_13
625 * @arg @ref LL_GPIO_PIN_14
626 * @arg @ref LL_GPIO_PIN_15
627 * @arg @ref LL_GPIO_PIN_ALL
628 * @retval None
629 */
LL_GPIO_LockPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)630 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
631 {
632 __IO uint32_t temp;
633 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
634 WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
635 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
636 temp = READ_REG(GPIOx->LCKR);
637 (void) temp;
638 }
639
640 /**
641 * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
642 * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
643 * @param GPIOx GPIO Port
644 * @param PinMask This parameter can be a combination of the following values:
645 * @arg @ref LL_GPIO_PIN_0
646 * @arg @ref LL_GPIO_PIN_1
647 * @arg @ref LL_GPIO_PIN_2
648 * @arg @ref LL_GPIO_PIN_3
649 * @arg @ref LL_GPIO_PIN_4
650 * @arg @ref LL_GPIO_PIN_5
651 * @arg @ref LL_GPIO_PIN_6
652 * @arg @ref LL_GPIO_PIN_7
653 * @arg @ref LL_GPIO_PIN_8
654 * @arg @ref LL_GPIO_PIN_9
655 * @arg @ref LL_GPIO_PIN_10
656 * @arg @ref LL_GPIO_PIN_11
657 * @arg @ref LL_GPIO_PIN_12
658 * @arg @ref LL_GPIO_PIN_13
659 * @arg @ref LL_GPIO_PIN_14
660 * @arg @ref LL_GPIO_PIN_15
661 * @arg @ref LL_GPIO_PIN_ALL
662 * @retval State of bit (1 or 0).
663 */
LL_GPIO_IsPinLocked(GPIO_TypeDef * GPIOx,uint32_t PinMask)664 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
665 {
666 return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
667 }
668
669 /**
670 * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
671 * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
672 * @param GPIOx GPIO Port
673 * @retval State of bit (1 or 0).
674 */
LL_GPIO_IsAnyPinLocked(GPIO_TypeDef * GPIOx)675 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
676 {
677 return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
678 }
679
680 /**
681 * @}
682 */
683
684 /** @defgroup GPIO_LL_EF_Data_Access Data Access
685 * @{
686 */
687
688 /**
689 * @brief Return full input data register value for a dedicated port.
690 * @rmtoll IDR IDy LL_GPIO_ReadInputPort
691 * @param GPIOx GPIO Port
692 * @retval Input data register value of port
693 */
LL_GPIO_ReadInputPort(GPIO_TypeDef * GPIOx)694 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
695 {
696 return (READ_REG(GPIOx->IDR));
697 }
698
699 /**
700 * @brief Return if input data level for several pins of dedicated port is high or low.
701 * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
702 * @param GPIOx GPIO Port
703 * @param PinMask This parameter can be a combination of the following values:
704 * @arg @ref LL_GPIO_PIN_0
705 * @arg @ref LL_GPIO_PIN_1
706 * @arg @ref LL_GPIO_PIN_2
707 * @arg @ref LL_GPIO_PIN_3
708 * @arg @ref LL_GPIO_PIN_4
709 * @arg @ref LL_GPIO_PIN_5
710 * @arg @ref LL_GPIO_PIN_6
711 * @arg @ref LL_GPIO_PIN_7
712 * @arg @ref LL_GPIO_PIN_8
713 * @arg @ref LL_GPIO_PIN_9
714 * @arg @ref LL_GPIO_PIN_10
715 * @arg @ref LL_GPIO_PIN_11
716 * @arg @ref LL_GPIO_PIN_12
717 * @arg @ref LL_GPIO_PIN_13
718 * @arg @ref LL_GPIO_PIN_14
719 * @arg @ref LL_GPIO_PIN_15
720 * @arg @ref LL_GPIO_PIN_ALL
721 * @retval State of bit (1 or 0).
722 */
LL_GPIO_IsInputPinSet(GPIO_TypeDef * GPIOx,uint32_t PinMask)723 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
724 {
725 return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
726 }
727
728 /**
729 * @brief Write output data register for the port.
730 * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
731 * @param GPIOx GPIO Port
732 * @param PortValue Level value for each pin of the port
733 * @retval None
734 */
LL_GPIO_WriteOutputPort(GPIO_TypeDef * GPIOx,uint32_t PortValue)735 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
736 {
737 WRITE_REG(GPIOx->ODR, PortValue);
738 }
739
740 /**
741 * @brief Return full output data register value for a dedicated port.
742 * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
743 * @param GPIOx GPIO Port
744 * @retval Output data register value of port
745 */
LL_GPIO_ReadOutputPort(GPIO_TypeDef * GPIOx)746 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
747 {
748 return (uint32_t)(READ_REG(GPIOx->ODR));
749 }
750
751 /**
752 * @brief Return if input data level for several pins of dedicated port is high or low.
753 * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
754 * @param GPIOx GPIO Port
755 * @param PinMask This parameter can be a combination of the following values:
756 * @arg @ref LL_GPIO_PIN_0
757 * @arg @ref LL_GPIO_PIN_1
758 * @arg @ref LL_GPIO_PIN_2
759 * @arg @ref LL_GPIO_PIN_3
760 * @arg @ref LL_GPIO_PIN_4
761 * @arg @ref LL_GPIO_PIN_5
762 * @arg @ref LL_GPIO_PIN_6
763 * @arg @ref LL_GPIO_PIN_7
764 * @arg @ref LL_GPIO_PIN_8
765 * @arg @ref LL_GPIO_PIN_9
766 * @arg @ref LL_GPIO_PIN_10
767 * @arg @ref LL_GPIO_PIN_11
768 * @arg @ref LL_GPIO_PIN_12
769 * @arg @ref LL_GPIO_PIN_13
770 * @arg @ref LL_GPIO_PIN_14
771 * @arg @ref LL_GPIO_PIN_15
772 * @arg @ref LL_GPIO_PIN_ALL
773 * @retval State of bit (1 or 0).
774 */
LL_GPIO_IsOutputPinSet(GPIO_TypeDef * GPIOx,uint32_t PinMask)775 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
776 {
777 return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
778 }
779
780 /**
781 * @brief Set several pins to high level on dedicated gpio port.
782 * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
783 * @param GPIOx GPIO Port
784 * @param PinMask This parameter can be a combination of the following values:
785 * @arg @ref LL_GPIO_PIN_0
786 * @arg @ref LL_GPIO_PIN_1
787 * @arg @ref LL_GPIO_PIN_2
788 * @arg @ref LL_GPIO_PIN_3
789 * @arg @ref LL_GPIO_PIN_4
790 * @arg @ref LL_GPIO_PIN_5
791 * @arg @ref LL_GPIO_PIN_6
792 * @arg @ref LL_GPIO_PIN_7
793 * @arg @ref LL_GPIO_PIN_8
794 * @arg @ref LL_GPIO_PIN_9
795 * @arg @ref LL_GPIO_PIN_10
796 * @arg @ref LL_GPIO_PIN_11
797 * @arg @ref LL_GPIO_PIN_12
798 * @arg @ref LL_GPIO_PIN_13
799 * @arg @ref LL_GPIO_PIN_14
800 * @arg @ref LL_GPIO_PIN_15
801 * @arg @ref LL_GPIO_PIN_ALL
802 * @retval None
803 */
LL_GPIO_SetOutputPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)804 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
805 {
806 WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
807 }
808
809 /**
810 * @brief Set several pins to low level on dedicated gpio port.
811 * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
812 * @param GPIOx GPIO Port
813 * @param PinMask This parameter can be a combination of the following values:
814 * @arg @ref LL_GPIO_PIN_0
815 * @arg @ref LL_GPIO_PIN_1
816 * @arg @ref LL_GPIO_PIN_2
817 * @arg @ref LL_GPIO_PIN_3
818 * @arg @ref LL_GPIO_PIN_4
819 * @arg @ref LL_GPIO_PIN_5
820 * @arg @ref LL_GPIO_PIN_6
821 * @arg @ref LL_GPIO_PIN_7
822 * @arg @ref LL_GPIO_PIN_8
823 * @arg @ref LL_GPIO_PIN_9
824 * @arg @ref LL_GPIO_PIN_10
825 * @arg @ref LL_GPIO_PIN_11
826 * @arg @ref LL_GPIO_PIN_12
827 * @arg @ref LL_GPIO_PIN_13
828 * @arg @ref LL_GPIO_PIN_14
829 * @arg @ref LL_GPIO_PIN_15
830 * @arg @ref LL_GPIO_PIN_ALL
831 * @retval None
832 */
LL_GPIO_ResetOutputPin(GPIO_TypeDef * GPIOx,uint32_t PinMask)833 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
834 {
835 WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
836 }
837
838 /**
839 * @brief Toggle data value for several pin of dedicated port.
840 * @rmtoll ODR ODy LL_GPIO_TogglePin
841 * @param GPIOx GPIO Port
842 * @param PinMask This parameter can be a combination of the following values:
843 * @arg @ref LL_GPIO_PIN_0
844 * @arg @ref LL_GPIO_PIN_1
845 * @arg @ref LL_GPIO_PIN_2
846 * @arg @ref LL_GPIO_PIN_3
847 * @arg @ref LL_GPIO_PIN_4
848 * @arg @ref LL_GPIO_PIN_5
849 * @arg @ref LL_GPIO_PIN_6
850 * @arg @ref LL_GPIO_PIN_7
851 * @arg @ref LL_GPIO_PIN_8
852 * @arg @ref LL_GPIO_PIN_9
853 * @arg @ref LL_GPIO_PIN_10
854 * @arg @ref LL_GPIO_PIN_11
855 * @arg @ref LL_GPIO_PIN_12
856 * @arg @ref LL_GPIO_PIN_13
857 * @arg @ref LL_GPIO_PIN_14
858 * @arg @ref LL_GPIO_PIN_15
859 * @arg @ref LL_GPIO_PIN_ALL
860 * @retval None
861 */
LL_GPIO_TogglePin(GPIO_TypeDef * GPIOx,uint32_t PinMask)862 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
863 {
864 uint32_t odr = READ_REG(GPIOx->ODR);
865 uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
866 WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask));
867 }
868
869 /**
870 * @}
871 */
872
873 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
874 * @brief This section propose definition to remap the alternate function to some other port/pins.
875 * @{
876 */
877
878 /**
879 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
880 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
881 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
882 * @retval None
883 */
LL_GPIO_AF_EnableRemap_SPI1(void)884 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
885 {
886 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG);
887 }
888
889 /**
890 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
891 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
892 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
893 * @retval None
894 */
LL_GPIO_AF_DisableRemap_SPI1(void)895 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
896 {
897 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
898 }
899
900 /**
901 * @brief Check if SPI1 has been remaped or not
902 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
903 * @retval State of bit (1 or 0).
904 */
LL_GPIO_AF_IsEnabledRemap_SPI1(void)905 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
906 {
907 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
908 }
909
910 /**
911 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
912 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
913 * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
914 * @retval None
915 */
LL_GPIO_AF_EnableRemap_I2C1(void)916 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
917 {
918 SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG);
919 }
920
921 /**
922 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
923 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
924 * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
925 * @retval None
926 */
LL_GPIO_AF_DisableRemap_I2C1(void)927 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
928 {
929 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
930 }
931
932 /**
933 * @brief Check if I2C1 has been remaped or not
934 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
935 * @retval State of bit (1 or 0).
936 */
LL_GPIO_AF_IsEnabledRemap_I2C1(void)937 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
938 {
939 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
940 }
941
942 /**
943 * @brief Enable the remapping of USART1 alternate function TX and RX.
944 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
945 * @note ENABLE: Remap (TX/PB6, RX/PB7)
946 * @retval None
947 */
LL_GPIO_AF_EnableRemap_USART1(void)948 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
949 {
950 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG);
951 }
952
953 /**
954 * @brief Disable the remapping of USART1 alternate function TX and RX.
955 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
956 * @note DISABLE: No remap (TX/PA9, RX/PA10)
957 * @retval None
958 */
LL_GPIO_AF_DisableRemap_USART1(void)959 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
960 {
961 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
962 }
963
964 /**
965 * @brief Check if USART1 has been remaped or not
966 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
967 * @retval State of bit (1 or 0).
968 */
LL_GPIO_AF_IsEnabledRemap_USART1(void)969 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
970 {
971 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
972 }
973
974 /**
975 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
976 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
977 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
978 * @retval None
979 */
LL_GPIO_AF_EnableRemap_USART2(void)980 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
981 {
982 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG);
983 }
984
985 /**
986 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
987 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
988 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
989 * @retval None
990 */
LL_GPIO_AF_DisableRemap_USART2(void)991 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
992 {
993 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
994 }
995
996 /**
997 * @brief Check if USART2 has been remaped or not
998 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
999 * @retval State of bit (1 or 0).
1000 */
LL_GPIO_AF_IsEnabledRemap_USART2(void)1001 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
1002 {
1003 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
1004 }
1005
1006 #if defined (AFIO_MAPR_USART3_REMAP)
1007 /**
1008 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1009 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
1010 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
1011 * @retval None
1012 */
LL_GPIO_AF_EnableRemap_USART3(void)1013 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
1014 {
1015 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1016 }
1017
1018 /**
1019 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1020 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
1021 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
1022 * @retval None
1023 */
LL_GPIO_AF_RemapPartial_USART3(void)1024 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
1025 {
1026 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1027 }
1028
1029 /**
1030 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1031 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
1032 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
1033 * @retval None
1034 */
LL_GPIO_AF_DisableRemap_USART3(void)1035 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
1036 {
1037 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1038 }
1039 #endif
1040
1041 /**
1042 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1043 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
1044 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
1045 * @retval None
1046 */
LL_GPIO_AF_EnableRemap_TIM1(void)1047 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
1048 {
1049 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1050 }
1051
1052 /**
1053 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1054 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
1055 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
1056 * @retval None
1057 */
LL_GPIO_AF_RemapPartial_TIM1(void)1058 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
1059 {
1060 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1061 }
1062
1063 /**
1064 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1065 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
1066 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
1067 * @retval None
1068 */
LL_GPIO_AF_DisableRemap_TIM1(void)1069 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
1070 {
1071 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1072 }
1073
1074 /**
1075 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1076 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
1077 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
1078 * @retval None
1079 */
LL_GPIO_AF_EnableRemap_TIM2(void)1080 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
1081 {
1082 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1083 }
1084
1085 /**
1086 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1087 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
1088 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
1089 * @retval None
1090 */
LL_GPIO_AF_RemapPartial2_TIM2(void)1091 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
1092 {
1093 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG));
1094 }
1095
1096 /**
1097 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1098 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
1099 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
1100 * @retval None
1101 */
LL_GPIO_AF_RemapPartial1_TIM2(void)1102 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
1103 {
1104 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG));
1105 }
1106
1107 /**
1108 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1109 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
1110 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
1111 * @retval None
1112 */
LL_GPIO_AF_DisableRemap_TIM2(void)1113 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
1114 {
1115 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1116 }
1117
1118 /**
1119 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1120 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
1121 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
1122 * @note TIM3_ETR on PE0 is not re-mapped.
1123 * @retval None
1124 */
LL_GPIO_AF_EnableRemap_TIM3(void)1125 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
1126 {
1127 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1128 }
1129
1130 /**
1131 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1132 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
1133 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
1134 * @note TIM3_ETR on PE0 is not re-mapped.
1135 * @retval None
1136 */
LL_GPIO_AF_RemapPartial_TIM3(void)1137 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
1138 {
1139 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1140 }
1141
1142 /**
1143 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
1144 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
1145 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
1146 * @note TIM3_ETR on PE0 is not re-mapped.
1147 * @retval None
1148 */
LL_GPIO_AF_DisableRemap_TIM3(void)1149 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
1150 {
1151 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1152 }
1153
1154 #if defined(AFIO_MAPR_TIM4_REMAP)
1155 /**
1156 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
1157 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
1158 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
1159 * @note TIM4_ETR on PE0 is not re-mapped.
1160 * @retval None
1161 */
LL_GPIO_AF_EnableRemap_TIM4(void)1162 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
1163 {
1164 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG);
1165 }
1166 /**
1167 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
1168 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
1169 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1170 * @note TIM4_ETR on PE0 is not re-mapped.
1171 * @retval None
1172 */
LL_GPIO_AF_DisableRemap_TIM4(void)1173 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
1174 {
1175 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1176 }
1177
1178 /**
1179 * @brief Check if TIM4 has been remaped or not
1180 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
1181 * @retval State of bit (1 or 0).
1182 */
LL_GPIO_AF_IsEnabledRemap_TIM4(void)1183 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
1184 {
1185 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
1186 }
1187 #endif
1188
1189 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
1190
1191 /**
1192 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1193 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
1194 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
1195 * @retval None
1196 */
LL_GPIO_AF_RemapPartial1_CAN1(void)1197 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
1198 {
1199 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG));
1200 }
1201
1202 /**
1203 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1204 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
1205 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
1206 * @retval None
1207 */
LL_GPIO_AF_RemapPartial2_CAN1(void)1208 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
1209 {
1210 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG));
1211 }
1212
1213 /**
1214 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1215 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
1216 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
1217 * @retval None
1218 */
LL_GPIO_AF_RemapPartial3_CAN1(void)1219 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
1220 {
1221 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG));
1222 }
1223 #endif
1224
1225 /**
1226 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
1227 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1228 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1229 * on 100-pin and 144-pin packages, no need for remapping).
1230 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
1231 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
1232 * @retval None
1233 */
LL_GPIO_AF_EnableRemap_PD01(void)1234 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
1235 {
1236 SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG);
1237 }
1238
1239 /**
1240 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
1241 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
1242 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
1243 * on 100-pin and 144-pin packages, no need for remapping).
1244 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
1245 * @note DISABLE: No remapping of PD0 and PD1
1246 * @retval None
1247 */
LL_GPIO_AF_DisableRemap_PD01(void)1248 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
1249 {
1250 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1251 }
1252
1253 /**
1254 * @brief Check if PD01 has been remaped or not
1255 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
1256 * @retval State of bit (1 or 0).
1257 */
LL_GPIO_AF_IsEnabledRemap_PD01(void)1258 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
1259 {
1260 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
1261 }
1262
1263 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
1264 /**
1265 * @brief Enable the remapping of TIM5CH4.
1266 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
1267 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
1268 * @note This function is available only in high density value line devices.
1269 * @retval None
1270 */
LL_GPIO_AF_EnableRemap_TIM5CH4(void)1271 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
1272 {
1273 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG);
1274 }
1275
1276 /**
1277 * @brief Disable the remapping of TIM5CH4.
1278 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
1279 * @note DISABLE: TIM5_CH4 is connected to PA3
1280 * @note This function is available only in high density value line devices.
1281 * @retval None
1282 */
LL_GPIO_AF_DisableRemap_TIM5CH4(void)1283 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
1284 {
1285 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1286 }
1287
1288 /**
1289 * @brief Check if TIM5CH4 has been remaped or not
1290 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
1291 * @retval State of bit (1 or 0).
1292 */
LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)1293 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
1294 {
1295 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
1296 }
1297 #endif
1298
1299 #if defined(AFIO_MAPR_ETH_REMAP)
1300 /**
1301 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
1302 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
1303 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
1304 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1305 * @retval None
1306 */
LL_GPIO_AF_EnableRemap_ETH(void)1307 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
1308 {
1309 SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG);
1310 }
1311
1312 /**
1313 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
1314 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
1315 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
1316 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1317 * @retval None
1318 */
LL_GPIO_AF_DisableRemap_ETH(void)1319 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
1320 {
1321 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1322 }
1323
1324 /**
1325 * @brief Check if ETH has been remaped or not
1326 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
1327 * @retval State of bit (1 or 0).
1328 */
LL_GPIO_AF_IsEnabledRemap_ETH(void)1329 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
1330 {
1331 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
1332 }
1333 #endif
1334
1335 #if defined(AFIO_MAPR_CAN2_REMAP)
1336
1337 /**
1338 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1339 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
1340 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
1341 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1342 * @retval None
1343 */
LL_GPIO_AF_EnableRemap_CAN2(void)1344 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
1345 {
1346 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG);
1347 }
1348 /**
1349 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1350 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
1351 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1352 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1353 * @retval None
1354 */
LL_GPIO_AF_DisableRemap_CAN2(void)1355 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
1356 {
1357 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1358 }
1359
1360 /**
1361 * @brief Check if CAN2 has been remaped or not
1362 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
1363 * @retval State of bit (1 or 0).
1364 */
LL_GPIO_AF_IsEnabledRemap_CAN2(void)1365 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
1366 {
1367 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
1368 }
1369 #endif
1370
1371 #if defined(AFIO_MAPR_MII_RMII_SEL)
1372 /**
1373 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1374 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
1375 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
1376 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1377 * @retval None
1378 */
LL_GPIO_AF_Select_ETH_RMII(void)1379 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
1380 {
1381 SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG);
1382 }
1383
1384 /**
1385 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1386 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
1387 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
1388 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1389 * @retval None
1390 */
LL_GPIO_AF_Select_ETH_MII(void)1391 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
1392 {
1393 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1394 }
1395 #endif
1396
1397 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
1398 /**
1399 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1400 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
1401 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
1402 * @retval None
1403 */
LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)1404 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
1405 {
1406 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1407 }
1408
1409 /**
1410 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1411 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
1412 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
1413 * @retval None
1414 */
LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)1415 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
1416 {
1417 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1418 }
1419
1420 /**
1421 * @brief Check if ADC1_ETRGINJ has been remaped or not
1422 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
1423 * @retval State of bit (1 or 0).
1424 */
LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)1425 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
1426 {
1427 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
1428 }
1429 #endif
1430
1431 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
1432 /**
1433 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1434 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
1435 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
1436 * @retval None
1437 */
LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)1438 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
1439 {
1440 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1441 }
1442
1443 /**
1444 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1445 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
1446 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
1447 * @retval None
1448 */
LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)1449 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
1450 {
1451 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1452 }
1453
1454 /**
1455 * @brief Check if ADC1_ETRGREG has been remaped or not
1456 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
1457 * @retval State of bit (1 or 0).
1458 */
LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)1459 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
1460 {
1461 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
1462 }
1463 #endif
1464
1465 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
1466
1467 /**
1468 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1469 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
1470 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
1471 * @retval None
1472 */
LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)1473 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
1474 {
1475 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1476 }
1477
1478 /**
1479 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1480 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
1481 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
1482 * @retval None
1483 */
LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)1484 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
1485 {
1486 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1487 }
1488
1489 /**
1490 * @brief Check if ADC2_ETRGINJ has been remaped or not
1491 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
1492 * @retval State of bit (1 or 0).
1493 */
LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)1494 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
1495 {
1496 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
1497 }
1498 #endif
1499
1500 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
1501
1502 /**
1503 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1504 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
1505 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
1506 * @retval None
1507 */
LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)1508 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
1509 {
1510 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1511 }
1512
1513 /**
1514 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1515 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
1516 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
1517 * @retval None
1518 */
LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)1519 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
1520 {
1521 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1522 }
1523
1524 /**
1525 * @brief Check if ADC2_ETRGREG has been remaped or not
1526 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
1527 * @retval State of bit (1 or 0).
1528 */
LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)1529 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
1530 {
1531 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
1532 }
1533 #endif
1534
1535 /**
1536 * @brief Enable the Serial wire JTAG configuration
1537 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
1538 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
1539 * @retval None
1540 */
LL_GPIO_AF_EnableRemap_SWJ(void)1541 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
1542 {
1543 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1544 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
1545 }
1546
1547 /**
1548 * @brief Enable the Serial wire JTAG configuration
1549 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
1550 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
1551 * @retval None
1552 */
LL_GPIO_AF_Remap_SWJ_NONJTRST(void)1553 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
1554 {
1555 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1556 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
1557 }
1558
1559 /**
1560 * @brief Enable the Serial wire JTAG configuration
1561 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
1562 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
1563 * @retval None
1564 */
LL_GPIO_AF_Remap_SWJ_NOJTAG(void)1565 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
1566 {
1567 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1568 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
1569 }
1570
1571 /**
1572 * @brief Disable the Serial wire JTAG configuration
1573 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
1574 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
1575 * @retval None
1576 */
LL_GPIO_AF_DisableRemap_SWJ(void)1577 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
1578 {
1579 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
1580 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
1581 }
1582
1583 #if defined(AFIO_MAPR_SPI3_REMAP)
1584
1585 /**
1586 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1587 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
1588 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
1589 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1590 * @retval None
1591 */
LL_GPIO_AF_EnableRemap_SPI3(void)1592 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
1593 {
1594 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG);
1595 }
1596
1597 /**
1598 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1599 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
1600 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
1601 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1602 * @retval None
1603 */
LL_GPIO_AF_DisableRemap_SPI3(void)1604 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
1605 {
1606 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1607 }
1608
1609 /**
1610 * @brief Check if SPI3 has been remaped or not
1611 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
1612 * @retval State of bit (1 or 0).
1613 */
LL_GPIO_AF_IsEnabledRemap_SPI3(void)1614 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
1615 {
1616 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
1617 }
1618 #endif
1619
1620 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
1621
1622 /**
1623 * @brief Control of TIM2_ITR1 internal mapping.
1624 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
1625 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
1626 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1627 * @retval None
1628 */
LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)1629 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
1630 {
1631 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG);
1632 }
1633
1634 /**
1635 * @brief Control of TIM2_ITR1 internal mapping.
1636 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
1637 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1638 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1639 * @retval None
1640 */
LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)1641 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
1642 {
1643 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1644 }
1645 #endif
1646
1647 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
1648
1649 /**
1650 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1651 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
1652 * @note ENABLE: PTP_PPS is output on PB5 pin.
1653 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1654 * @retval None
1655 */
LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)1656 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
1657 {
1658 SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG);
1659 }
1660
1661 /**
1662 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1663 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
1664 * @note DISABLE: PTP_PPS not output on PB5 pin.
1665 * @note This bit is available only in connectivity line devices and is reserved otherwise.
1666 * @retval None
1667 */
LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)1668 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
1669 {
1670 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1671 }
1672 #endif
1673
1674 #if defined(AFIO_MAPR2_TIM9_REMAP)
1675
1676 /**
1677 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
1678 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
1679 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
1680 * @retval None
1681 */
LL_GPIO_AF_EnableRemap_TIM9(void)1682 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
1683 {
1684 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1685 }
1686
1687 /**
1688 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
1689 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
1690 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
1691 * @retval None
1692 */
LL_GPIO_AF_DisableRemap_TIM9(void)1693 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
1694 {
1695 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
1696 }
1697
1698 /**
1699 * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
1700 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
1701 * @retval State of bit (1 or 0).
1702 */
LL_GPIO_AF_IsEnabledRemap_TIM9(void)1703 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
1704 {
1705 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
1706 }
1707 #endif
1708
1709 #if defined(AFIO_MAPR2_TIM10_REMAP)
1710
1711 /**
1712 * @brief Enable the remapping of TIM10_CH1.
1713 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
1714 * @note ENABLE: Remap (TIM10_CH1 on PF6).
1715 * @retval None
1716 */
LL_GPIO_AF_EnableRemap_TIM10(void)1717 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
1718 {
1719 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1720 }
1721
1722 /**
1723 * @brief Disable the remapping of TIM10_CH1.
1724 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
1725 * @note DISABLE: No remap (TIM10_CH1 on PB8).
1726 * @retval None
1727 */
LL_GPIO_AF_DisableRemap_TIM10(void)1728 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
1729 {
1730 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
1731 }
1732
1733 /**
1734 * @brief Check if TIM10_CH1 has been remaped or not
1735 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
1736 * @retval State of bit (1 or 0).
1737 */
LL_GPIO_AF_IsEnabledRemap_TIM10(void)1738 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
1739 {
1740 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
1741 }
1742 #endif
1743
1744 #if defined(AFIO_MAPR2_TIM11_REMAP)
1745 /**
1746 * @brief Enable the remapping of TIM11_CH1.
1747 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
1748 * @note ENABLE: Remap (TIM11_CH1 on PF7).
1749 * @retval None
1750 */
LL_GPIO_AF_EnableRemap_TIM11(void)1751 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
1752 {
1753 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1754 }
1755
1756 /**
1757 * @brief Disable the remapping of TIM11_CH1.
1758 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
1759 * @note DISABLE: No remap (TIM11_CH1 on PB9).
1760 * @retval None
1761 */
LL_GPIO_AF_DisableRemap_TIM11(void)1762 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
1763 {
1764 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
1765 }
1766
1767 /**
1768 * @brief Check if TIM11_CH1 has been remaped or not
1769 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
1770 * @retval State of bit (1 or 0).
1771 */
LL_GPIO_AF_IsEnabledRemap_TIM11(void)1772 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
1773 {
1774 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
1775 }
1776 #endif
1777
1778 #if defined(AFIO_MAPR2_TIM13_REMAP)
1779
1780 /**
1781 * @brief Enable the remapping of TIM13_CH1.
1782 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
1783 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
1784 * @retval None
1785 */
LL_GPIO_AF_EnableRemap_TIM13(void)1786 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
1787 {
1788 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1789 }
1790
1791 /**
1792 * @brief Disable the remapping of TIM13_CH1.
1793 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
1794 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
1795 * @retval None
1796 */
LL_GPIO_AF_DisableRemap_TIM13(void)1797 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
1798 {
1799 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
1800 }
1801
1802 /**
1803 * @brief Check if TIM13_CH1 has been remaped or not
1804 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
1805 * @retval State of bit (1 or 0).
1806 */
LL_GPIO_AF_IsEnabledRemap_TIM13(void)1807 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
1808 {
1809 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
1810 }
1811 #endif
1812
1813 #if defined(AFIO_MAPR2_TIM14_REMAP)
1814
1815 /**
1816 * @brief Enable the remapping of TIM14_CH1.
1817 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
1818 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
1819 * @retval None
1820 */
LL_GPIO_AF_EnableRemap_TIM14(void)1821 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
1822 {
1823 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1824 }
1825
1826 /**
1827 * @brief Disable the remapping of TIM14_CH1.
1828 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
1829 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
1830 * @retval None
1831 */
LL_GPIO_AF_DisableRemap_TIM14(void)1832 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
1833 {
1834 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
1835 }
1836
1837 /**
1838 * @brief Check if TIM14_CH1 has been remaped or not
1839 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
1840 * @retval State of bit (1 or 0).
1841 */
LL_GPIO_AF_IsEnabledRemap_TIM14(void)1842 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
1843 {
1844 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
1845 }
1846 #endif
1847
1848 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
1849
1850 /**
1851 * @brief Controls the use of the optional FSMC_NADV signal.
1852 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
1853 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
1854 * @retval None
1855 */
LL_GPIO_AF_Disconnect_FSMCNADV(void)1856 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
1857 {
1858 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1859 }
1860
1861 /**
1862 * @brief Controls the use of the optional FSMC_NADV signal.
1863 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
1864 * @note CONNECTED: The NADV signal is connected to the output (default).
1865 * @retval None
1866 */
LL_GPIO_AF_Connect_FSMCNADV(void)1867 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
1868 {
1869 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
1870 }
1871 #endif
1872
1873 #if defined(AFIO_MAPR2_TIM15_REMAP)
1874
1875 /**
1876 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
1877 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
1878 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
1879 * @retval None
1880 */
LL_GPIO_AF_EnableRemap_TIM15(void)1881 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
1882 {
1883 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1884 }
1885 /**
1886 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
1887 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
1888 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
1889 * @retval None
1890 */
LL_GPIO_AF_DisableRemap_TIM15(void)1891 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
1892 {
1893 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
1894 }
1895
1896 /**
1897 * @brief Check if TIM15_CH1 has been remaped or not
1898 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
1899 * @retval State of bit (1 or 0).
1900 */
LL_GPIO_AF_IsEnabledRemap_TIM15(void)1901 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
1902 {
1903 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
1904 }
1905 #endif
1906
1907 #if defined(AFIO_MAPR2_TIM16_REMAP)
1908
1909 /**
1910 * @brief Enable the remapping of TIM16_CH1.
1911 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
1912 * @note ENABLE: Remap (TIM16_CH1 on PA6).
1913 * @retval None
1914 */
LL_GPIO_AF_EnableRemap_TIM16(void)1915 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
1916 {
1917 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1918 }
1919
1920 /**
1921 * @brief Disable the remapping of TIM16_CH1.
1922 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
1923 * @note DISABLE: No remap (TIM16_CH1 on PB8).
1924 * @retval None
1925 */
LL_GPIO_AF_DisableRemap_TIM16(void)1926 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
1927 {
1928 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
1929 }
1930
1931 /**
1932 * @brief Check if TIM16_CH1 has been remaped or not
1933 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
1934 * @retval State of bit (1 or 0).
1935 */
LL_GPIO_AF_IsEnabledRemap_TIM16(void)1936 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
1937 {
1938 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
1939 }
1940 #endif
1941
1942 #if defined(AFIO_MAPR2_TIM17_REMAP)
1943
1944 /**
1945 * @brief Enable the remapping of TIM17_CH1.
1946 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
1947 * @note ENABLE: Remap (TIM17_CH1 on PA7).
1948 * @retval None
1949 */
LL_GPIO_AF_EnableRemap_TIM17(void)1950 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
1951 {
1952 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1953 }
1954
1955 /**
1956 * @brief Disable the remapping of TIM17_CH1.
1957 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
1958 * @note DISABLE: No remap (TIM17_CH1 on PB9).
1959 * @retval None
1960 */
LL_GPIO_AF_DisableRemap_TIM17(void)1961 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
1962 {
1963 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
1964 }
1965
1966 /**
1967 * @brief Check if TIM17_CH1 has been remaped or not
1968 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
1969 * @retval State of bit (1 or 0).
1970 */
LL_GPIO_AF_IsEnabledRemap_TIM17(void)1971 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
1972 {
1973 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
1974 }
1975 #endif
1976
1977 #if defined(AFIO_MAPR2_CEC_REMAP)
1978
1979 /**
1980 * @brief Enable the remapping of CEC.
1981 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
1982 * @note ENABLE: Remap (CEC on PB10).
1983 * @retval None
1984 */
LL_GPIO_AF_EnableRemap_CEC(void)1985 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
1986 {
1987 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
1988 }
1989
1990 /**
1991 * @brief Disable the remapping of CEC.
1992 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
1993 * @note DISABLE: No remap (CEC on PB8).
1994 * @retval None
1995 */
LL_GPIO_AF_DisableRemap_CEC(void)1996 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
1997 {
1998 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
1999 }
2000
2001 /**
2002 * @brief Check if CEC has been remaped or not
2003 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
2004 * @retval State of bit (1 or 0).
2005 */
LL_GPIO_AF_IsEnabledRemap_CEC(void)2006 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
2007 {
2008 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
2009 }
2010 #endif
2011
2012 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
2013
2014 /**
2015 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2016 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
2017 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
2018 * @retval None
2019 */
LL_GPIO_AF_EnableRemap_TIM1DMA(void)2020 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
2021 {
2022 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2023 }
2024
2025 /**
2026 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
2027 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
2028 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
2029 * @retval None
2030 */
LL_GPIO_AF_DisableRemap_TIM1DMA(void)2031 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
2032 {
2033 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
2034 }
2035
2036 /**
2037 * @brief Check if TIM1DMA has been remaped or not
2038 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
2039 * @retval State of bit (1 or 0).
2040 */
LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)2041 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
2042 {
2043 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
2044 }
2045 #endif
2046
2047 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
2048
2049 /**
2050 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2051 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
2052 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
2053 * @retval None
2054 */
LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)2055 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
2056 {
2057 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2058 }
2059
2060 /**
2061 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
2062 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
2063 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
2064 * @retval None
2065 */
LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)2066 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
2067 {
2068 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
2069 }
2070
2071 /**
2072 * @brief Check if TIM67DACDMA has been remaped or not
2073 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
2074 * @retval State of bit (1 or 0).
2075 */
LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)2076 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
2077 {
2078 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
2079 }
2080 #endif
2081
2082 #if defined(AFIO_MAPR2_TIM12_REMAP)
2083
2084 /**
2085 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
2086 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
2087 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
2088 * @note This bit is available only in high density value line devices.
2089 * @retval None
2090 */
LL_GPIO_AF_EnableRemap_TIM12(void)2091 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
2092 {
2093 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2094 }
2095
2096 /**
2097 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
2098 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
2099 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
2100 * @note This bit is available only in high density value line devices.
2101 * @retval None
2102 */
LL_GPIO_AF_DisableRemap_TIM12(void)2103 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
2104 {
2105 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
2106 }
2107
2108 /**
2109 * @brief Check if TIM12_CH1 has been remaped or not
2110 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
2111 * @retval State of bit (1 or 0).
2112 */
LL_GPIO_AF_IsEnabledRemap_TIM12(void)2113 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
2114 {
2115 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
2116 }
2117 #endif
2118
2119 #if defined(AFIO_MAPR2_MISC_REMAP)
2120
2121 /**
2122 * @brief Miscellaneous features remapping.
2123 * This bit is set and cleared by software. It controls miscellaneous features.
2124 * The DMA2 channel 5 interrupt position in the vector table.
2125 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2126 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
2127 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
2128 * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
2129 * @note This bit is available only in high density value line devices.
2130 * @retval None
2131 */
LL_GPIO_AF_EnableRemap_MISC(void)2132 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
2133 {
2134 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2135 }
2136
2137 /**
2138 * @brief Miscellaneous features remapping.
2139 * This bit is set and cleared by software. It controls miscellaneous features.
2140 * The DMA2 channel 5 interrupt position in the vector table.
2141 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
2142 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
2143 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
2144 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
2145 * @note This bit is available only in high density value line devices.
2146 * @retval None
2147 */
LL_GPIO_AF_DisableRemap_MISC(void)2148 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
2149 {
2150 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
2151 }
2152
2153 /**
2154 * @brief Check if MISC has been remaped or not
2155 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
2156 * @retval State of bit (1 or 0).
2157 */
LL_GPIO_AF_IsEnabledRemap_MISC(void)2158 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
2159 {
2160 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
2161 }
2162 #endif
2163
2164 /**
2165 * @}
2166 */
2167
2168 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
2169 * @brief This section propose definition to Configure EVENTOUT Cortex feature .
2170 * @{
2171 */
2172
2173 /**
2174 * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
2175 * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
2176 * EVCR PIN LL_GPIO_AF_ConfigEventout
2177 * @param LL_GPIO_PortSource This parameter can be one of the following values:
2178 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
2179 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
2180 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
2181 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
2182 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
2183 * @param LL_GPIO_PinSource This parameter can be one of the following values:
2184 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
2185 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
2186 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
2187 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
2188 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
2189 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
2190 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
2191 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
2192 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
2193 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
2194 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
2195 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
2196 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
2197 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
2198 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
2199 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
2200 * @retval None
2201 */
LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource,uint32_t LL_GPIO_PinSource)2202 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
2203 {
2204 MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
2205 }
2206
2207 /**
2208 * @brief Enables the Event Output.
2209 * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
2210 * @retval None
2211 */
LL_GPIO_AF_EnableEventout(void)2212 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
2213 {
2214 SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2215 }
2216
2217 /**
2218 * @brief Disables the Event Output.
2219 * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
2220 * @retval None
2221 */
LL_GPIO_AF_DisableEventout(void)2222 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
2223 {
2224 CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
2225 }
2226
2227 /**
2228 * @}
2229 */
2230 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
2231 * @brief This section Configure source input for the EXTI external interrupt .
2232 * @{
2233 */
2234
2235 /**
2236 * @brief Configure source input for the EXTI external interrupt.
2237 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
2238 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
2239 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
2240 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
2241 * @param Port This parameter can be one of the following values:
2242 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2243 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2244 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2245 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2246 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2247 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2248 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2249 * @param Line This parameter can be one of the following values:
2250 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2251 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2252 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2253 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2254 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2255 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2256 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2257 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2258 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2259 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2260 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2261 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2262 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2263 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2264 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2265 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2266 * @retval None
2267 */
LL_GPIO_AF_SetEXTISource(uint32_t Port,uint32_t Line)2268 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
2269 {
2270 MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
2271 }
2272
2273 /**
2274 * @brief Get the configured defined for specific EXTI Line
2275 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
2276 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
2277 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
2278 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
2279 * @param Line This parameter can be one of the following values:
2280 * @arg @ref LL_GPIO_AF_EXTI_LINE0
2281 * @arg @ref LL_GPIO_AF_EXTI_LINE1
2282 * @arg @ref LL_GPIO_AF_EXTI_LINE2
2283 * @arg @ref LL_GPIO_AF_EXTI_LINE3
2284 * @arg @ref LL_GPIO_AF_EXTI_LINE4
2285 * @arg @ref LL_GPIO_AF_EXTI_LINE5
2286 * @arg @ref LL_GPIO_AF_EXTI_LINE6
2287 * @arg @ref LL_GPIO_AF_EXTI_LINE7
2288 * @arg @ref LL_GPIO_AF_EXTI_LINE8
2289 * @arg @ref LL_GPIO_AF_EXTI_LINE9
2290 * @arg @ref LL_GPIO_AF_EXTI_LINE10
2291 * @arg @ref LL_GPIO_AF_EXTI_LINE11
2292 * @arg @ref LL_GPIO_AF_EXTI_LINE12
2293 * @arg @ref LL_GPIO_AF_EXTI_LINE13
2294 * @arg @ref LL_GPIO_AF_EXTI_LINE14
2295 * @arg @ref LL_GPIO_AF_EXTI_LINE15
2296 * @retval Returned value can be one of the following values:
2297 * @arg @ref LL_GPIO_AF_EXTI_PORTA
2298 * @arg @ref LL_GPIO_AF_EXTI_PORTB
2299 * @arg @ref LL_GPIO_AF_EXTI_PORTC
2300 * @arg @ref LL_GPIO_AF_EXTI_PORTD
2301 * @arg @ref LL_GPIO_AF_EXTI_PORTE
2302 * @arg @ref LL_GPIO_AF_EXTI_PORTF
2303 * @arg @ref LL_GPIO_AF_EXTI_PORTG
2304 */
LL_GPIO_AF_GetEXTISource(uint32_t Line)2305 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
2306 {
2307 return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
2308 }
2309
2310 /**
2311 * @}
2312 */
2313
2314 #if defined(USE_FULL_LL_DRIVER)
2315 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
2316 * @{
2317 */
2318
2319 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
2320 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
2321 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
2322
2323 /**
2324 * @}
2325 */
2326 #endif /* USE_FULL_LL_DRIVER */
2327
2328 /**
2329 * @}
2330 */
2331
2332 /**
2333 * @}
2334 */
2335
2336 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
2337 /**
2338 * @}
2339 */
2340
2341 #ifdef __cplusplus
2342 }
2343 #endif
2344
2345 #endif /* STM32F1xx_LL_GPIO_H */
2346
2347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2348
