1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F1xx_LL_DMA_H
22 #define __STM32F1xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx.h"
30
31 /** @addtogroup STM32F1xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
56 };
57 /**
58 * @}
59 */
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
64 * @{
65 */
66 /**
67 * @}
68 */
69 #endif /*USE_FULL_LL_DRIVER*/
70
71 /* Exported types ------------------------------------------------------------*/
72 #if defined(USE_FULL_LL_DRIVER)
73 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
74 * @{
75 */
76 typedef struct
77 {
78 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
79 or as Source base address in case of memory to memory transfer direction.
80
81 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
82
83 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
84 or as Destination base address in case of memory to memory transfer direction.
85
86 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
87
88 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
89 from memory to memory or from peripheral to memory.
90 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
91
92 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
93
94 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
95 This parameter can be a value of @ref DMA_LL_EC_MODE
96 @note: The circular buffer mode cannot be used if the memory to memory
97 data transfer direction is configured on the selected Channel
98
99 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
100
101 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
102 is incremented or not.
103 This parameter can be a value of @ref DMA_LL_EC_PERIPH
104
105 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
106
107 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
108 is incremented or not.
109 This parameter can be a value of @ref DMA_LL_EC_MEMORY
110
111 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
112
113 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
114 in case of memory to memory transfer direction.
115 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
116
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
118
119 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
120 in case of memory to memory transfer direction.
121 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
122
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
124
125 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
126 The data unit is equal to the source buffer configuration set in PeripheralSize
127 or MemorySize parameters depending in the transfer direction.
128 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
129
130 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
131
132 uint32_t Priority; /*!< Specifies the channel priority level.
133 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
136
137 } LL_DMA_InitTypeDef;
138 /**
139 * @}
140 */
141 #endif /*USE_FULL_LL_DRIVER*/
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
145 * @{
146 */
147 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
148 * @brief Flags defines which can be used with LL_DMA_WriteReg function
149 * @{
150 */
151 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
152 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
153 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
154 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
155 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
156 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
157 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
158 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
159 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
160 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
161 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
162 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
163 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
164 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
165 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
166 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
167 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
168 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
169 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
170 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
171 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
172 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
173 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
174 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
175 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
176 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
177 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
178 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
179 /**
180 * @}
181 */
182
183 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
184 * @brief Flags defines which can be used with LL_DMA_ReadReg function
185 * @{
186 */
187 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
188 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
189 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
190 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
191 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
192 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
193 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
194 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
195 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
196 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
197 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
198 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
199 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
200 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
201 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
202 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
203 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
204 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
205 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
206 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
207 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
208 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
209 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
210 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
211 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
212 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
213 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
214 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
215 /**
216 * @}
217 */
218
219 /** @defgroup DMA_LL_EC_IT IT Defines
220 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
221 * @{
222 */
223 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
224 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
225 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
226 /**
227 * @}
228 */
229
230 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
231 * @{
232 */
233 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
234 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
235 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
236 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
237 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
238 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
239 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
240 #if defined(USE_FULL_LL_DRIVER)
241 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
242 #endif /*USE_FULL_LL_DRIVER*/
243 /**
244 * @}
245 */
246
247 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
248 * @{
249 */
250 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
251 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
252 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
253 /**
254 * @}
255 */
256
257 /** @defgroup DMA_LL_EC_MODE Transfer mode
258 * @{
259 */
260 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
261 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
262 /**
263 * @}
264 */
265
266 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
267 * @{
268 */
269 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
270 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
271 /**
272 * @}
273 */
274
275 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
276 * @{
277 */
278 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
279 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
280 /**
281 * @}
282 */
283
284 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
285 * @{
286 */
287 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
288 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
289 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
290 /**
291 * @}
292 */
293
294 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
295 * @{
296 */
297 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
298 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
299 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
300 /**
301 * @}
302 */
303
304 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
305 * @{
306 */
307 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
308 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
309 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
310 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
311 /**
312 * @}
313 */
314
315 /**
316 * @}
317 */
318
319 /* Exported macro ------------------------------------------------------------*/
320 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
321 * @{
322 */
323
324 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
325 * @{
326 */
327 /**
328 * @brief Write a value in DMA register
329 * @param __INSTANCE__ DMA Instance
330 * @param __REG__ Register to be written
331 * @param __VALUE__ Value to be written in the register
332 * @retval None
333 */
334 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
335
336 /**
337 * @brief Read a value in DMA register
338 * @param __INSTANCE__ DMA Instance
339 * @param __REG__ Register to be read
340 * @retval Register value
341 */
342 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
343 /**
344 * @}
345 */
346
347 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
348 * @{
349 */
350
351 /**
352 * @brief Convert DMAx_Channely into DMAx
353 * @param __CHANNEL_INSTANCE__ DMAx_Channely
354 * @retval DMAx
355 */
356 #if defined(DMA2)
357 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
358 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
359 #else
360 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
361 #endif
362
363 /**
364 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
365 * @param __CHANNEL_INSTANCE__ DMAx_Channely
366 * @retval LL_DMA_CHANNEL_y
367 */
368 #if defined (DMA2)
369 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
370 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
371 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
381 LL_DMA_CHANNEL_7)
382 #else
383 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
384 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
385 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
386 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
390 LL_DMA_CHANNEL_7)
391 #endif
392
393 /**
394 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
395 * @param __DMA_INSTANCE__ DMAx
396 * @param __CHANNEL__ LL_DMA_CHANNEL_y
397 * @retval DMAx_Channely
398 */
399 #if defined (DMA2)
400 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
401 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
402 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
403 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
404 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
405 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
406 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
407 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
408 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
409 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
410 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
411 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
412 DMA1_Channel7)
413 #else
414 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
415 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
416 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
417 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
418 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
419 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
421 DMA1_Channel7)
422 #endif
423
424 /**
425 * @}
426 */
427
428 /**
429 * @}
430 */
431
432 /* Exported functions --------------------------------------------------------*/
433 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
434 * @{
435 */
436
437 /** @defgroup DMA_LL_EF_Configuration Configuration
438 * @{
439 */
440 /**
441 * @brief Enable DMA channel.
442 * @rmtoll CCR EN LL_DMA_EnableChannel
443 * @param DMAx DMAx Instance
444 * @param Channel This parameter can be one of the following values:
445 * @arg @ref LL_DMA_CHANNEL_1
446 * @arg @ref LL_DMA_CHANNEL_2
447 * @arg @ref LL_DMA_CHANNEL_3
448 * @arg @ref LL_DMA_CHANNEL_4
449 * @arg @ref LL_DMA_CHANNEL_5
450 * @arg @ref LL_DMA_CHANNEL_6
451 * @arg @ref LL_DMA_CHANNEL_7
452 * @retval None
453 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)454 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
455 {
456 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
457 }
458
459 /**
460 * @brief Disable DMA channel.
461 * @rmtoll CCR EN LL_DMA_DisableChannel
462 * @param DMAx DMAx Instance
463 * @param Channel This parameter can be one of the following values:
464 * @arg @ref LL_DMA_CHANNEL_1
465 * @arg @ref LL_DMA_CHANNEL_2
466 * @arg @ref LL_DMA_CHANNEL_3
467 * @arg @ref LL_DMA_CHANNEL_4
468 * @arg @ref LL_DMA_CHANNEL_5
469 * @arg @ref LL_DMA_CHANNEL_6
470 * @arg @ref LL_DMA_CHANNEL_7
471 * @retval None
472 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)473 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
474 {
475 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
476 }
477
478 /**
479 * @brief Check if DMA channel is enabled or disabled.
480 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
481 * @param DMAx DMAx Instance
482 * @param Channel This parameter can be one of the following values:
483 * @arg @ref LL_DMA_CHANNEL_1
484 * @arg @ref LL_DMA_CHANNEL_2
485 * @arg @ref LL_DMA_CHANNEL_3
486 * @arg @ref LL_DMA_CHANNEL_4
487 * @arg @ref LL_DMA_CHANNEL_5
488 * @arg @ref LL_DMA_CHANNEL_6
489 * @arg @ref LL_DMA_CHANNEL_7
490 * @retval State of bit (1 or 0).
491 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)492 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
493 {
494 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
495 DMA_CCR_EN) == (DMA_CCR_EN));
496 }
497
498 /**
499 * @brief Configure all parameters link to DMA transfer.
500 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
501 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
502 * CCR CIRC LL_DMA_ConfigTransfer\n
503 * CCR PINC LL_DMA_ConfigTransfer\n
504 * CCR MINC LL_DMA_ConfigTransfer\n
505 * CCR PSIZE LL_DMA_ConfigTransfer\n
506 * CCR MSIZE LL_DMA_ConfigTransfer\n
507 * CCR PL LL_DMA_ConfigTransfer
508 * @param DMAx DMAx Instance
509 * @param Channel This parameter can be one of the following values:
510 * @arg @ref LL_DMA_CHANNEL_1
511 * @arg @ref LL_DMA_CHANNEL_2
512 * @arg @ref LL_DMA_CHANNEL_3
513 * @arg @ref LL_DMA_CHANNEL_4
514 * @arg @ref LL_DMA_CHANNEL_5
515 * @arg @ref LL_DMA_CHANNEL_6
516 * @arg @ref LL_DMA_CHANNEL_7
517 * @param Configuration This parameter must be a combination of all the following values:
518 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
519 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
520 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
521 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
522 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
523 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
524 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
525 * @retval None
526 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)527 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
528 {
529 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
530 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
531 Configuration);
532 }
533
534 /**
535 * @brief Set Data transfer direction (read from peripheral or from memory).
536 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
537 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
538 * @param DMAx DMAx Instance
539 * @param Channel This parameter can be one of the following values:
540 * @arg @ref LL_DMA_CHANNEL_1
541 * @arg @ref LL_DMA_CHANNEL_2
542 * @arg @ref LL_DMA_CHANNEL_3
543 * @arg @ref LL_DMA_CHANNEL_4
544 * @arg @ref LL_DMA_CHANNEL_5
545 * @arg @ref LL_DMA_CHANNEL_6
546 * @arg @ref LL_DMA_CHANNEL_7
547 * @param Direction This parameter can be one of the following values:
548 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
549 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
550 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
551 * @retval None
552 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)553 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
554 {
555 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
556 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
557 }
558
559 /**
560 * @brief Get Data transfer direction (read from peripheral or from memory).
561 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
562 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
563 * @param DMAx DMAx Instance
564 * @param Channel This parameter can be one of the following values:
565 * @arg @ref LL_DMA_CHANNEL_1
566 * @arg @ref LL_DMA_CHANNEL_2
567 * @arg @ref LL_DMA_CHANNEL_3
568 * @arg @ref LL_DMA_CHANNEL_4
569 * @arg @ref LL_DMA_CHANNEL_5
570 * @arg @ref LL_DMA_CHANNEL_6
571 * @arg @ref LL_DMA_CHANNEL_7
572 * @retval Returned value can be one of the following values:
573 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
574 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
575 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
576 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)577 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
578 {
579 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
580 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
581 }
582
583 /**
584 * @brief Set DMA mode circular or normal.
585 * @note The circular buffer mode cannot be used if the memory-to-memory
586 * data transfer is configured on the selected Channel.
587 * @rmtoll CCR CIRC LL_DMA_SetMode
588 * @param DMAx DMAx Instance
589 * @param Channel This parameter can be one of the following values:
590 * @arg @ref LL_DMA_CHANNEL_1
591 * @arg @ref LL_DMA_CHANNEL_2
592 * @arg @ref LL_DMA_CHANNEL_3
593 * @arg @ref LL_DMA_CHANNEL_4
594 * @arg @ref LL_DMA_CHANNEL_5
595 * @arg @ref LL_DMA_CHANNEL_6
596 * @arg @ref LL_DMA_CHANNEL_7
597 * @param Mode This parameter can be one of the following values:
598 * @arg @ref LL_DMA_MODE_NORMAL
599 * @arg @ref LL_DMA_MODE_CIRCULAR
600 * @retval None
601 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)602 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
603 {
604 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
605 Mode);
606 }
607
608 /**
609 * @brief Get DMA mode circular or normal.
610 * @rmtoll CCR CIRC LL_DMA_GetMode
611 * @param DMAx DMAx Instance
612 * @param Channel This parameter can be one of the following values:
613 * @arg @ref LL_DMA_CHANNEL_1
614 * @arg @ref LL_DMA_CHANNEL_2
615 * @arg @ref LL_DMA_CHANNEL_3
616 * @arg @ref LL_DMA_CHANNEL_4
617 * @arg @ref LL_DMA_CHANNEL_5
618 * @arg @ref LL_DMA_CHANNEL_6
619 * @arg @ref LL_DMA_CHANNEL_7
620 * @retval Returned value can be one of the following values:
621 * @arg @ref LL_DMA_MODE_NORMAL
622 * @arg @ref LL_DMA_MODE_CIRCULAR
623 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)624 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
625 {
626 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
627 DMA_CCR_CIRC));
628 }
629
630 /**
631 * @brief Set Peripheral increment mode.
632 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
633 * @param DMAx DMAx Instance
634 * @param Channel This parameter can be one of the following values:
635 * @arg @ref LL_DMA_CHANNEL_1
636 * @arg @ref LL_DMA_CHANNEL_2
637 * @arg @ref LL_DMA_CHANNEL_3
638 * @arg @ref LL_DMA_CHANNEL_4
639 * @arg @ref LL_DMA_CHANNEL_5
640 * @arg @ref LL_DMA_CHANNEL_6
641 * @arg @ref LL_DMA_CHANNEL_7
642 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
643 * @arg @ref LL_DMA_PERIPH_INCREMENT
644 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
645 * @retval None
646 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)647 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
648 {
649 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
650 PeriphOrM2MSrcIncMode);
651 }
652
653 /**
654 * @brief Get Peripheral increment mode.
655 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
656 * @param DMAx DMAx Instance
657 * @param Channel This parameter can be one of the following values:
658 * @arg @ref LL_DMA_CHANNEL_1
659 * @arg @ref LL_DMA_CHANNEL_2
660 * @arg @ref LL_DMA_CHANNEL_3
661 * @arg @ref LL_DMA_CHANNEL_4
662 * @arg @ref LL_DMA_CHANNEL_5
663 * @arg @ref LL_DMA_CHANNEL_6
664 * @arg @ref LL_DMA_CHANNEL_7
665 * @retval Returned value can be one of the following values:
666 * @arg @ref LL_DMA_PERIPH_INCREMENT
667 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
668 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)669 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
670 {
671 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
672 DMA_CCR_PINC));
673 }
674
675 /**
676 * @brief Set Memory increment mode.
677 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
678 * @param DMAx DMAx Instance
679 * @param Channel This parameter can be one of the following values:
680 * @arg @ref LL_DMA_CHANNEL_1
681 * @arg @ref LL_DMA_CHANNEL_2
682 * @arg @ref LL_DMA_CHANNEL_3
683 * @arg @ref LL_DMA_CHANNEL_4
684 * @arg @ref LL_DMA_CHANNEL_5
685 * @arg @ref LL_DMA_CHANNEL_6
686 * @arg @ref LL_DMA_CHANNEL_7
687 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
688 * @arg @ref LL_DMA_MEMORY_INCREMENT
689 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
690 * @retval None
691 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)692 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
693 {
694 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
695 MemoryOrM2MDstIncMode);
696 }
697
698 /**
699 * @brief Get Memory increment mode.
700 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
701 * @param DMAx DMAx Instance
702 * @param Channel This parameter can be one of the following values:
703 * @arg @ref LL_DMA_CHANNEL_1
704 * @arg @ref LL_DMA_CHANNEL_2
705 * @arg @ref LL_DMA_CHANNEL_3
706 * @arg @ref LL_DMA_CHANNEL_4
707 * @arg @ref LL_DMA_CHANNEL_5
708 * @arg @ref LL_DMA_CHANNEL_6
709 * @arg @ref LL_DMA_CHANNEL_7
710 * @retval Returned value can be one of the following values:
711 * @arg @ref LL_DMA_MEMORY_INCREMENT
712 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
713 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)714 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
715 {
716 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
717 DMA_CCR_MINC));
718 }
719
720 /**
721 * @brief Set Peripheral size.
722 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
723 * @param DMAx DMAx Instance
724 * @param Channel This parameter can be one of the following values:
725 * @arg @ref LL_DMA_CHANNEL_1
726 * @arg @ref LL_DMA_CHANNEL_2
727 * @arg @ref LL_DMA_CHANNEL_3
728 * @arg @ref LL_DMA_CHANNEL_4
729 * @arg @ref LL_DMA_CHANNEL_5
730 * @arg @ref LL_DMA_CHANNEL_6
731 * @arg @ref LL_DMA_CHANNEL_7
732 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
733 * @arg @ref LL_DMA_PDATAALIGN_BYTE
734 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
735 * @arg @ref LL_DMA_PDATAALIGN_WORD
736 * @retval None
737 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)738 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
739 {
740 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
741 PeriphOrM2MSrcDataSize);
742 }
743
744 /**
745 * @brief Get Peripheral size.
746 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
747 * @param DMAx DMAx Instance
748 * @param Channel This parameter can be one of the following values:
749 * @arg @ref LL_DMA_CHANNEL_1
750 * @arg @ref LL_DMA_CHANNEL_2
751 * @arg @ref LL_DMA_CHANNEL_3
752 * @arg @ref LL_DMA_CHANNEL_4
753 * @arg @ref LL_DMA_CHANNEL_5
754 * @arg @ref LL_DMA_CHANNEL_6
755 * @arg @ref LL_DMA_CHANNEL_7
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_DMA_PDATAALIGN_BYTE
758 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
759 * @arg @ref LL_DMA_PDATAALIGN_WORD
760 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)761 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
762 {
763 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
764 DMA_CCR_PSIZE));
765 }
766
767 /**
768 * @brief Set Memory size.
769 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
770 * @param DMAx DMAx Instance
771 * @param Channel This parameter can be one of the following values:
772 * @arg @ref LL_DMA_CHANNEL_1
773 * @arg @ref LL_DMA_CHANNEL_2
774 * @arg @ref LL_DMA_CHANNEL_3
775 * @arg @ref LL_DMA_CHANNEL_4
776 * @arg @ref LL_DMA_CHANNEL_5
777 * @arg @ref LL_DMA_CHANNEL_6
778 * @arg @ref LL_DMA_CHANNEL_7
779 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
780 * @arg @ref LL_DMA_MDATAALIGN_BYTE
781 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
782 * @arg @ref LL_DMA_MDATAALIGN_WORD
783 * @retval None
784 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)785 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
786 {
787 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
788 MemoryOrM2MDstDataSize);
789 }
790
791 /**
792 * @brief Get Memory size.
793 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
794 * @param DMAx DMAx Instance
795 * @param Channel This parameter can be one of the following values:
796 * @arg @ref LL_DMA_CHANNEL_1
797 * @arg @ref LL_DMA_CHANNEL_2
798 * @arg @ref LL_DMA_CHANNEL_3
799 * @arg @ref LL_DMA_CHANNEL_4
800 * @arg @ref LL_DMA_CHANNEL_5
801 * @arg @ref LL_DMA_CHANNEL_6
802 * @arg @ref LL_DMA_CHANNEL_7
803 * @retval Returned value can be one of the following values:
804 * @arg @ref LL_DMA_MDATAALIGN_BYTE
805 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
806 * @arg @ref LL_DMA_MDATAALIGN_WORD
807 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)808 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
809 {
810 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
811 DMA_CCR_MSIZE));
812 }
813
814 /**
815 * @brief Set Channel priority level.
816 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
817 * @param DMAx DMAx Instance
818 * @param Channel This parameter can be one of the following values:
819 * @arg @ref LL_DMA_CHANNEL_1
820 * @arg @ref LL_DMA_CHANNEL_2
821 * @arg @ref LL_DMA_CHANNEL_3
822 * @arg @ref LL_DMA_CHANNEL_4
823 * @arg @ref LL_DMA_CHANNEL_5
824 * @arg @ref LL_DMA_CHANNEL_6
825 * @arg @ref LL_DMA_CHANNEL_7
826 * @param Priority This parameter can be one of the following values:
827 * @arg @ref LL_DMA_PRIORITY_LOW
828 * @arg @ref LL_DMA_PRIORITY_MEDIUM
829 * @arg @ref LL_DMA_PRIORITY_HIGH
830 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
831 * @retval None
832 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)833 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
834 {
835 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
836 Priority);
837 }
838
839 /**
840 * @brief Get Channel priority level.
841 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
842 * @param DMAx DMAx Instance
843 * @param Channel This parameter can be one of the following values:
844 * @arg @ref LL_DMA_CHANNEL_1
845 * @arg @ref LL_DMA_CHANNEL_2
846 * @arg @ref LL_DMA_CHANNEL_3
847 * @arg @ref LL_DMA_CHANNEL_4
848 * @arg @ref LL_DMA_CHANNEL_5
849 * @arg @ref LL_DMA_CHANNEL_6
850 * @arg @ref LL_DMA_CHANNEL_7
851 * @retval Returned value can be one of the following values:
852 * @arg @ref LL_DMA_PRIORITY_LOW
853 * @arg @ref LL_DMA_PRIORITY_MEDIUM
854 * @arg @ref LL_DMA_PRIORITY_HIGH
855 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
856 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)857 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
858 {
859 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
860 DMA_CCR_PL));
861 }
862
863 /**
864 * @brief Set Number of data to transfer.
865 * @note This action has no effect if
866 * channel is enabled.
867 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
868 * @param DMAx DMAx Instance
869 * @param Channel This parameter can be one of the following values:
870 * @arg @ref LL_DMA_CHANNEL_1
871 * @arg @ref LL_DMA_CHANNEL_2
872 * @arg @ref LL_DMA_CHANNEL_3
873 * @arg @ref LL_DMA_CHANNEL_4
874 * @arg @ref LL_DMA_CHANNEL_5
875 * @arg @ref LL_DMA_CHANNEL_6
876 * @arg @ref LL_DMA_CHANNEL_7
877 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
878 * @retval None
879 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)880 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
881 {
882 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
883 DMA_CNDTR_NDT, NbData);
884 }
885
886 /**
887 * @brief Get Number of data to transfer.
888 * @note Once the channel is enabled, the return value indicate the
889 * remaining bytes to be transmitted.
890 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
891 * @param DMAx DMAx Instance
892 * @param Channel This parameter can be one of the following values:
893 * @arg @ref LL_DMA_CHANNEL_1
894 * @arg @ref LL_DMA_CHANNEL_2
895 * @arg @ref LL_DMA_CHANNEL_3
896 * @arg @ref LL_DMA_CHANNEL_4
897 * @arg @ref LL_DMA_CHANNEL_5
898 * @arg @ref LL_DMA_CHANNEL_6
899 * @arg @ref LL_DMA_CHANNEL_7
900 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
901 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)902 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
903 {
904 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
905 DMA_CNDTR_NDT));
906 }
907
908 /**
909 * @brief Configure the Source and Destination addresses.
910 * @note This API must not be called when the DMA channel is enabled.
911 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
912 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
913 * CMAR MA LL_DMA_ConfigAddresses
914 * @param DMAx DMAx Instance
915 * @param Channel This parameter can be one of the following values:
916 * @arg @ref LL_DMA_CHANNEL_1
917 * @arg @ref LL_DMA_CHANNEL_2
918 * @arg @ref LL_DMA_CHANNEL_3
919 * @arg @ref LL_DMA_CHANNEL_4
920 * @arg @ref LL_DMA_CHANNEL_5
921 * @arg @ref LL_DMA_CHANNEL_6
922 * @arg @ref LL_DMA_CHANNEL_7
923 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
924 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
925 * @param Direction This parameter can be one of the following values:
926 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
927 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
928 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
929 * @retval None
930 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)931 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
932 uint32_t DstAddress, uint32_t Direction)
933 {
934 /* Direction Memory to Periph */
935 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
936 {
937 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
938 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
939 }
940 /* Direction Periph to Memory and Memory to Memory */
941 else
942 {
943 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
944 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
945 }
946 }
947
948 /**
949 * @brief Set the Memory address.
950 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
951 * @note This API must not be called when the DMA channel is enabled.
952 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
953 * @param DMAx DMAx Instance
954 * @param Channel This parameter can be one of the following values:
955 * @arg @ref LL_DMA_CHANNEL_1
956 * @arg @ref LL_DMA_CHANNEL_2
957 * @arg @ref LL_DMA_CHANNEL_3
958 * @arg @ref LL_DMA_CHANNEL_4
959 * @arg @ref LL_DMA_CHANNEL_5
960 * @arg @ref LL_DMA_CHANNEL_6
961 * @arg @ref LL_DMA_CHANNEL_7
962 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
963 * @retval None
964 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)965 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
966 {
967 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
968 }
969
970 /**
971 * @brief Set the Peripheral address.
972 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
973 * @note This API must not be called when the DMA channel is enabled.
974 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
975 * @param DMAx DMAx Instance
976 * @param Channel This parameter can be one of the following values:
977 * @arg @ref LL_DMA_CHANNEL_1
978 * @arg @ref LL_DMA_CHANNEL_2
979 * @arg @ref LL_DMA_CHANNEL_3
980 * @arg @ref LL_DMA_CHANNEL_4
981 * @arg @ref LL_DMA_CHANNEL_5
982 * @arg @ref LL_DMA_CHANNEL_6
983 * @arg @ref LL_DMA_CHANNEL_7
984 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
985 * @retval None
986 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)987 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
988 {
989 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
990 }
991
992 /**
993 * @brief Get Memory address.
994 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
995 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
996 * @param DMAx DMAx Instance
997 * @param Channel This parameter can be one of the following values:
998 * @arg @ref LL_DMA_CHANNEL_1
999 * @arg @ref LL_DMA_CHANNEL_2
1000 * @arg @ref LL_DMA_CHANNEL_3
1001 * @arg @ref LL_DMA_CHANNEL_4
1002 * @arg @ref LL_DMA_CHANNEL_5
1003 * @arg @ref LL_DMA_CHANNEL_6
1004 * @arg @ref LL_DMA_CHANNEL_7
1005 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1006 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1007 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1008 {
1009 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1010 }
1011
1012 /**
1013 * @brief Get Peripheral address.
1014 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1015 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1016 * @param DMAx DMAx Instance
1017 * @param Channel This parameter can be one of the following values:
1018 * @arg @ref LL_DMA_CHANNEL_1
1019 * @arg @ref LL_DMA_CHANNEL_2
1020 * @arg @ref LL_DMA_CHANNEL_3
1021 * @arg @ref LL_DMA_CHANNEL_4
1022 * @arg @ref LL_DMA_CHANNEL_5
1023 * @arg @ref LL_DMA_CHANNEL_6
1024 * @arg @ref LL_DMA_CHANNEL_7
1025 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1026 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1027 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1028 {
1029 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1030 }
1031
1032 /**
1033 * @brief Set the Memory to Memory Source address.
1034 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1035 * @note This API must not be called when the DMA channel is enabled.
1036 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1037 * @param DMAx DMAx Instance
1038 * @param Channel This parameter can be one of the following values:
1039 * @arg @ref LL_DMA_CHANNEL_1
1040 * @arg @ref LL_DMA_CHANNEL_2
1041 * @arg @ref LL_DMA_CHANNEL_3
1042 * @arg @ref LL_DMA_CHANNEL_4
1043 * @arg @ref LL_DMA_CHANNEL_5
1044 * @arg @ref LL_DMA_CHANNEL_6
1045 * @arg @ref LL_DMA_CHANNEL_7
1046 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1047 * @retval None
1048 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1049 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1050 {
1051 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1052 }
1053
1054 /**
1055 * @brief Set the Memory to Memory Destination address.
1056 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1057 * @note This API must not be called when the DMA channel is enabled.
1058 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1059 * @param DMAx DMAx Instance
1060 * @param Channel This parameter can be one of the following values:
1061 * @arg @ref LL_DMA_CHANNEL_1
1062 * @arg @ref LL_DMA_CHANNEL_2
1063 * @arg @ref LL_DMA_CHANNEL_3
1064 * @arg @ref LL_DMA_CHANNEL_4
1065 * @arg @ref LL_DMA_CHANNEL_5
1066 * @arg @ref LL_DMA_CHANNEL_6
1067 * @arg @ref LL_DMA_CHANNEL_7
1068 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1069 * @retval None
1070 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1071 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1072 {
1073 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1074 }
1075
1076 /**
1077 * @brief Get the Memory to Memory Source address.
1078 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1079 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1080 * @param DMAx DMAx Instance
1081 * @param Channel This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_CHANNEL_1
1083 * @arg @ref LL_DMA_CHANNEL_2
1084 * @arg @ref LL_DMA_CHANNEL_3
1085 * @arg @ref LL_DMA_CHANNEL_4
1086 * @arg @ref LL_DMA_CHANNEL_5
1087 * @arg @ref LL_DMA_CHANNEL_6
1088 * @arg @ref LL_DMA_CHANNEL_7
1089 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1090 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1091 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1092 {
1093 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1094 }
1095
1096 /**
1097 * @brief Get the Memory to Memory Destination address.
1098 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1099 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1100 * @param DMAx DMAx Instance
1101 * @param Channel This parameter can be one of the following values:
1102 * @arg @ref LL_DMA_CHANNEL_1
1103 * @arg @ref LL_DMA_CHANNEL_2
1104 * @arg @ref LL_DMA_CHANNEL_3
1105 * @arg @ref LL_DMA_CHANNEL_4
1106 * @arg @ref LL_DMA_CHANNEL_5
1107 * @arg @ref LL_DMA_CHANNEL_6
1108 * @arg @ref LL_DMA_CHANNEL_7
1109 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1110 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1111 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1112 {
1113 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1114 }
1115
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1121 * @{
1122 */
1123
1124 /**
1125 * @brief Get Channel 1 global interrupt flag.
1126 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1127 * @param DMAx DMAx Instance
1128 * @retval State of bit (1 or 0).
1129 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1130 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1131 {
1132 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1133 }
1134
1135 /**
1136 * @brief Get Channel 2 global interrupt flag.
1137 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1138 * @param DMAx DMAx Instance
1139 * @retval State of bit (1 or 0).
1140 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1141 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1142 {
1143 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1144 }
1145
1146 /**
1147 * @brief Get Channel 3 global interrupt flag.
1148 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1149 * @param DMAx DMAx Instance
1150 * @retval State of bit (1 or 0).
1151 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1152 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1153 {
1154 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1155 }
1156
1157 /**
1158 * @brief Get Channel 4 global interrupt flag.
1159 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1160 * @param DMAx DMAx Instance
1161 * @retval State of bit (1 or 0).
1162 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1163 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1164 {
1165 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1166 }
1167
1168 /**
1169 * @brief Get Channel 5 global interrupt flag.
1170 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1171 * @param DMAx DMAx Instance
1172 * @retval State of bit (1 or 0).
1173 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1174 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1175 {
1176 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1177 }
1178
1179 /**
1180 * @brief Get Channel 6 global interrupt flag.
1181 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1182 * @param DMAx DMAx Instance
1183 * @retval State of bit (1 or 0).
1184 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1185 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1186 {
1187 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1188 }
1189
1190 /**
1191 * @brief Get Channel 7 global interrupt flag.
1192 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1193 * @param DMAx DMAx Instance
1194 * @retval State of bit (1 or 0).
1195 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1196 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1197 {
1198 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1199 }
1200
1201 /**
1202 * @brief Get Channel 1 transfer complete flag.
1203 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1204 * @param DMAx DMAx Instance
1205 * @retval State of bit (1 or 0).
1206 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1207 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1208 {
1209 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1210 }
1211
1212 /**
1213 * @brief Get Channel 2 transfer complete flag.
1214 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1215 * @param DMAx DMAx Instance
1216 * @retval State of bit (1 or 0).
1217 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1218 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1219 {
1220 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1221 }
1222
1223 /**
1224 * @brief Get Channel 3 transfer complete flag.
1225 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1226 * @param DMAx DMAx Instance
1227 * @retval State of bit (1 or 0).
1228 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1229 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1230 {
1231 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1232 }
1233
1234 /**
1235 * @brief Get Channel 4 transfer complete flag.
1236 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1237 * @param DMAx DMAx Instance
1238 * @retval State of bit (1 or 0).
1239 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1240 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1241 {
1242 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1243 }
1244
1245 /**
1246 * @brief Get Channel 5 transfer complete flag.
1247 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1248 * @param DMAx DMAx Instance
1249 * @retval State of bit (1 or 0).
1250 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1251 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1252 {
1253 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1254 }
1255
1256 /**
1257 * @brief Get Channel 6 transfer complete flag.
1258 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1259 * @param DMAx DMAx Instance
1260 * @retval State of bit (1 or 0).
1261 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1262 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1263 {
1264 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1265 }
1266
1267 /**
1268 * @brief Get Channel 7 transfer complete flag.
1269 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1270 * @param DMAx DMAx Instance
1271 * @retval State of bit (1 or 0).
1272 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1273 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1274 {
1275 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1276 }
1277
1278 /**
1279 * @brief Get Channel 1 half transfer flag.
1280 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1281 * @param DMAx DMAx Instance
1282 * @retval State of bit (1 or 0).
1283 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1284 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1285 {
1286 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1287 }
1288
1289 /**
1290 * @brief Get Channel 2 half transfer flag.
1291 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1292 * @param DMAx DMAx Instance
1293 * @retval State of bit (1 or 0).
1294 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1295 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1296 {
1297 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1298 }
1299
1300 /**
1301 * @brief Get Channel 3 half transfer flag.
1302 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1303 * @param DMAx DMAx Instance
1304 * @retval State of bit (1 or 0).
1305 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1306 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1307 {
1308 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1309 }
1310
1311 /**
1312 * @brief Get Channel 4 half transfer flag.
1313 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1314 * @param DMAx DMAx Instance
1315 * @retval State of bit (1 or 0).
1316 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1317 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1318 {
1319 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1320 }
1321
1322 /**
1323 * @brief Get Channel 5 half transfer flag.
1324 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1325 * @param DMAx DMAx Instance
1326 * @retval State of bit (1 or 0).
1327 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1328 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1329 {
1330 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1331 }
1332
1333 /**
1334 * @brief Get Channel 6 half transfer flag.
1335 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1336 * @param DMAx DMAx Instance
1337 * @retval State of bit (1 or 0).
1338 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1339 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1340 {
1341 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1342 }
1343
1344 /**
1345 * @brief Get Channel 7 half transfer flag.
1346 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1347 * @param DMAx DMAx Instance
1348 * @retval State of bit (1 or 0).
1349 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1350 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1351 {
1352 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1353 }
1354
1355 /**
1356 * @brief Get Channel 1 transfer error flag.
1357 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1358 * @param DMAx DMAx Instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1361 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1362 {
1363 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1364 }
1365
1366 /**
1367 * @brief Get Channel 2 transfer error flag.
1368 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1369 * @param DMAx DMAx Instance
1370 * @retval State of bit (1 or 0).
1371 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1372 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1373 {
1374 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1375 }
1376
1377 /**
1378 * @brief Get Channel 3 transfer error flag.
1379 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1380 * @param DMAx DMAx Instance
1381 * @retval State of bit (1 or 0).
1382 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1383 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1384 {
1385 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1386 }
1387
1388 /**
1389 * @brief Get Channel 4 transfer error flag.
1390 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1391 * @param DMAx DMAx Instance
1392 * @retval State of bit (1 or 0).
1393 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1394 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1395 {
1396 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1397 }
1398
1399 /**
1400 * @brief Get Channel 5 transfer error flag.
1401 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1402 * @param DMAx DMAx Instance
1403 * @retval State of bit (1 or 0).
1404 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1405 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1406 {
1407 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1408 }
1409
1410 /**
1411 * @brief Get Channel 6 transfer error flag.
1412 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1413 * @param DMAx DMAx Instance
1414 * @retval State of bit (1 or 0).
1415 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1416 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1417 {
1418 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1419 }
1420
1421 /**
1422 * @brief Get Channel 7 transfer error flag.
1423 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1424 * @param DMAx DMAx Instance
1425 * @retval State of bit (1 or 0).
1426 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1427 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1428 {
1429 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1430 }
1431
1432 /**
1433 * @brief Clear Channel 1 global interrupt flag.
1434 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1435 * @param DMAx DMAx Instance
1436 * @retval None
1437 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1438 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1439 {
1440 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1441 }
1442
1443 /**
1444 * @brief Clear Channel 2 global interrupt flag.
1445 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1446 * @param DMAx DMAx Instance
1447 * @retval None
1448 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1449 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1450 {
1451 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1452 }
1453
1454 /**
1455 * @brief Clear Channel 3 global interrupt flag.
1456 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1457 * @param DMAx DMAx Instance
1458 * @retval None
1459 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1460 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1461 {
1462 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1463 }
1464
1465 /**
1466 * @brief Clear Channel 4 global interrupt flag.
1467 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1468 * @param DMAx DMAx Instance
1469 * @retval None
1470 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1471 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1472 {
1473 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1474 }
1475
1476 /**
1477 * @brief Clear Channel 5 global interrupt flag.
1478 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1479 * @param DMAx DMAx Instance
1480 * @retval None
1481 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1482 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1483 {
1484 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1485 }
1486
1487 /**
1488 * @brief Clear Channel 6 global interrupt flag.
1489 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1490 * @param DMAx DMAx Instance
1491 * @retval None
1492 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1493 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1494 {
1495 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1496 }
1497
1498 /**
1499 * @brief Clear Channel 7 global interrupt flag.
1500 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1501 * @param DMAx DMAx Instance
1502 * @retval None
1503 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1504 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1505 {
1506 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1507 }
1508
1509 /**
1510 * @brief Clear Channel 1 transfer complete flag.
1511 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1512 * @param DMAx DMAx Instance
1513 * @retval None
1514 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1515 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1516 {
1517 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1518 }
1519
1520 /**
1521 * @brief Clear Channel 2 transfer complete flag.
1522 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1523 * @param DMAx DMAx Instance
1524 * @retval None
1525 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1526 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1527 {
1528 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1529 }
1530
1531 /**
1532 * @brief Clear Channel 3 transfer complete flag.
1533 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1534 * @param DMAx DMAx Instance
1535 * @retval None
1536 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1537 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1538 {
1539 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1540 }
1541
1542 /**
1543 * @brief Clear Channel 4 transfer complete flag.
1544 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1545 * @param DMAx DMAx Instance
1546 * @retval None
1547 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1548 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1549 {
1550 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1551 }
1552
1553 /**
1554 * @brief Clear Channel 5 transfer complete flag.
1555 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1556 * @param DMAx DMAx Instance
1557 * @retval None
1558 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1559 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1560 {
1561 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1562 }
1563
1564 /**
1565 * @brief Clear Channel 6 transfer complete flag.
1566 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1567 * @param DMAx DMAx Instance
1568 * @retval None
1569 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1570 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1571 {
1572 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1573 }
1574
1575 /**
1576 * @brief Clear Channel 7 transfer complete flag.
1577 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1578 * @param DMAx DMAx Instance
1579 * @retval None
1580 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1581 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1582 {
1583 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1584 }
1585
1586 /**
1587 * @brief Clear Channel 1 half transfer flag.
1588 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1589 * @param DMAx DMAx Instance
1590 * @retval None
1591 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1592 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1593 {
1594 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1595 }
1596
1597 /**
1598 * @brief Clear Channel 2 half transfer flag.
1599 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1600 * @param DMAx DMAx Instance
1601 * @retval None
1602 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1603 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1604 {
1605 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1606 }
1607
1608 /**
1609 * @brief Clear Channel 3 half transfer flag.
1610 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1611 * @param DMAx DMAx Instance
1612 * @retval None
1613 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1614 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1615 {
1616 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1617 }
1618
1619 /**
1620 * @brief Clear Channel 4 half transfer flag.
1621 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1622 * @param DMAx DMAx Instance
1623 * @retval None
1624 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1625 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1626 {
1627 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1628 }
1629
1630 /**
1631 * @brief Clear Channel 5 half transfer flag.
1632 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1633 * @param DMAx DMAx Instance
1634 * @retval None
1635 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1636 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1637 {
1638 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1639 }
1640
1641 /**
1642 * @brief Clear Channel 6 half transfer flag.
1643 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1644 * @param DMAx DMAx Instance
1645 * @retval None
1646 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1647 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1648 {
1649 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1650 }
1651
1652 /**
1653 * @brief Clear Channel 7 half transfer flag.
1654 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1655 * @param DMAx DMAx Instance
1656 * @retval None
1657 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1658 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1659 {
1660 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1661 }
1662
1663 /**
1664 * @brief Clear Channel 1 transfer error flag.
1665 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1666 * @param DMAx DMAx Instance
1667 * @retval None
1668 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1669 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1670 {
1671 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1672 }
1673
1674 /**
1675 * @brief Clear Channel 2 transfer error flag.
1676 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1677 * @param DMAx DMAx Instance
1678 * @retval None
1679 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1680 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1681 {
1682 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1683 }
1684
1685 /**
1686 * @brief Clear Channel 3 transfer error flag.
1687 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1688 * @param DMAx DMAx Instance
1689 * @retval None
1690 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1691 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1692 {
1693 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1694 }
1695
1696 /**
1697 * @brief Clear Channel 4 transfer error flag.
1698 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1699 * @param DMAx DMAx Instance
1700 * @retval None
1701 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1702 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1703 {
1704 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1705 }
1706
1707 /**
1708 * @brief Clear Channel 5 transfer error flag.
1709 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1710 * @param DMAx DMAx Instance
1711 * @retval None
1712 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1713 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1714 {
1715 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1716 }
1717
1718 /**
1719 * @brief Clear Channel 6 transfer error flag.
1720 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1721 * @param DMAx DMAx Instance
1722 * @retval None
1723 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1724 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1725 {
1726 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1727 }
1728
1729 /**
1730 * @brief Clear Channel 7 transfer error flag.
1731 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1732 * @param DMAx DMAx Instance
1733 * @retval None
1734 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1735 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1736 {
1737 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1738 }
1739
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1745 * @{
1746 */
1747
1748 /**
1749 * @brief Enable Transfer complete interrupt.
1750 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1751 * @param DMAx DMAx Instance
1752 * @param Channel This parameter can be one of the following values:
1753 * @arg @ref LL_DMA_CHANNEL_1
1754 * @arg @ref LL_DMA_CHANNEL_2
1755 * @arg @ref LL_DMA_CHANNEL_3
1756 * @arg @ref LL_DMA_CHANNEL_4
1757 * @arg @ref LL_DMA_CHANNEL_5
1758 * @arg @ref LL_DMA_CHANNEL_6
1759 * @arg @ref LL_DMA_CHANNEL_7
1760 * @retval None
1761 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1762 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1763 {
1764 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1765 }
1766
1767 /**
1768 * @brief Enable Half transfer interrupt.
1769 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1770 * @param DMAx DMAx Instance
1771 * @param Channel This parameter can be one of the following values:
1772 * @arg @ref LL_DMA_CHANNEL_1
1773 * @arg @ref LL_DMA_CHANNEL_2
1774 * @arg @ref LL_DMA_CHANNEL_3
1775 * @arg @ref LL_DMA_CHANNEL_4
1776 * @arg @ref LL_DMA_CHANNEL_5
1777 * @arg @ref LL_DMA_CHANNEL_6
1778 * @arg @ref LL_DMA_CHANNEL_7
1779 * @retval None
1780 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1781 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1782 {
1783 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1784 }
1785
1786 /**
1787 * @brief Enable Transfer error interrupt.
1788 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1789 * @param DMAx DMAx Instance
1790 * @param Channel This parameter can be one of the following values:
1791 * @arg @ref LL_DMA_CHANNEL_1
1792 * @arg @ref LL_DMA_CHANNEL_2
1793 * @arg @ref LL_DMA_CHANNEL_3
1794 * @arg @ref LL_DMA_CHANNEL_4
1795 * @arg @ref LL_DMA_CHANNEL_5
1796 * @arg @ref LL_DMA_CHANNEL_6
1797 * @arg @ref LL_DMA_CHANNEL_7
1798 * @retval None
1799 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1800 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1801 {
1802 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1803 }
1804
1805 /**
1806 * @brief Disable Transfer complete interrupt.
1807 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1808 * @param DMAx DMAx Instance
1809 * @param Channel This parameter can be one of the following values:
1810 * @arg @ref LL_DMA_CHANNEL_1
1811 * @arg @ref LL_DMA_CHANNEL_2
1812 * @arg @ref LL_DMA_CHANNEL_3
1813 * @arg @ref LL_DMA_CHANNEL_4
1814 * @arg @ref LL_DMA_CHANNEL_5
1815 * @arg @ref LL_DMA_CHANNEL_6
1816 * @arg @ref LL_DMA_CHANNEL_7
1817 * @retval None
1818 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1819 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1820 {
1821 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1822 }
1823
1824 /**
1825 * @brief Disable Half transfer interrupt.
1826 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1827 * @param DMAx DMAx Instance
1828 * @param Channel This parameter can be one of the following values:
1829 * @arg @ref LL_DMA_CHANNEL_1
1830 * @arg @ref LL_DMA_CHANNEL_2
1831 * @arg @ref LL_DMA_CHANNEL_3
1832 * @arg @ref LL_DMA_CHANNEL_4
1833 * @arg @ref LL_DMA_CHANNEL_5
1834 * @arg @ref LL_DMA_CHANNEL_6
1835 * @arg @ref LL_DMA_CHANNEL_7
1836 * @retval None
1837 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1838 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1839 {
1840 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1841 }
1842
1843 /**
1844 * @brief Disable Transfer error interrupt.
1845 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1846 * @param DMAx DMAx Instance
1847 * @param Channel This parameter can be one of the following values:
1848 * @arg @ref LL_DMA_CHANNEL_1
1849 * @arg @ref LL_DMA_CHANNEL_2
1850 * @arg @ref LL_DMA_CHANNEL_3
1851 * @arg @ref LL_DMA_CHANNEL_4
1852 * @arg @ref LL_DMA_CHANNEL_5
1853 * @arg @ref LL_DMA_CHANNEL_6
1854 * @arg @ref LL_DMA_CHANNEL_7
1855 * @retval None
1856 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1857 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1858 {
1859 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1860 }
1861
1862 /**
1863 * @brief Check if Transfer complete Interrupt is enabled.
1864 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1865 * @param DMAx DMAx Instance
1866 * @param Channel This parameter can be one of the following values:
1867 * @arg @ref LL_DMA_CHANNEL_1
1868 * @arg @ref LL_DMA_CHANNEL_2
1869 * @arg @ref LL_DMA_CHANNEL_3
1870 * @arg @ref LL_DMA_CHANNEL_4
1871 * @arg @ref LL_DMA_CHANNEL_5
1872 * @arg @ref LL_DMA_CHANNEL_6
1873 * @arg @ref LL_DMA_CHANNEL_7
1874 * @retval State of bit (1 or 0).
1875 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1876 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1877 {
1878 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1879 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1880 }
1881
1882 /**
1883 * @brief Check if Half transfer Interrupt is enabled.
1884 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1885 * @param DMAx DMAx Instance
1886 * @param Channel This parameter can be one of the following values:
1887 * @arg @ref LL_DMA_CHANNEL_1
1888 * @arg @ref LL_DMA_CHANNEL_2
1889 * @arg @ref LL_DMA_CHANNEL_3
1890 * @arg @ref LL_DMA_CHANNEL_4
1891 * @arg @ref LL_DMA_CHANNEL_5
1892 * @arg @ref LL_DMA_CHANNEL_6
1893 * @arg @ref LL_DMA_CHANNEL_7
1894 * @retval State of bit (1 or 0).
1895 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1896 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1897 {
1898 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1899 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1900 }
1901
1902 /**
1903 * @brief Check if Transfer error Interrupt is enabled.
1904 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1905 * @param DMAx DMAx Instance
1906 * @param Channel This parameter can be one of the following values:
1907 * @arg @ref LL_DMA_CHANNEL_1
1908 * @arg @ref LL_DMA_CHANNEL_2
1909 * @arg @ref LL_DMA_CHANNEL_3
1910 * @arg @ref LL_DMA_CHANNEL_4
1911 * @arg @ref LL_DMA_CHANNEL_5
1912 * @arg @ref LL_DMA_CHANNEL_6
1913 * @arg @ref LL_DMA_CHANNEL_7
1914 * @retval State of bit (1 or 0).
1915 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1916 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1917 {
1918 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1919 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1920 }
1921
1922 /**
1923 * @}
1924 */
1925
1926 #if defined(USE_FULL_LL_DRIVER)
1927 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1928 * @{
1929 */
1930
1931 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1932 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1933 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1934
1935 /**
1936 * @}
1937 */
1938 #endif /* USE_FULL_LL_DRIVER */
1939
1940 /**
1941 * @}
1942 */
1943
1944 /**
1945 * @}
1946 */
1947
1948 #endif /* DMA1 || DMA2 */
1949
1950 /**
1951 * @}
1952 */
1953
1954 #ifdef __cplusplus
1955 }
1956 #endif
1957
1958 #endif /* __STM32F1xx_LL_DMA_H */
1959
1960 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1961
