1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_sram.h 4 * @author MCD Application Team 5 * @brief Header file of SRAM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F1xx_HAL_SRAM_H 22 #define STM32F1xx_HAL_SRAM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(FSMC_BANK1) 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f1xx_ll_fsmc.h" 32 33 /** @addtogroup STM32F1xx_HAL_Driver 34 * @{ 35 */ 36 /** @addtogroup SRAM 37 * @{ 38 */ 39 40 /* Exported typedef ----------------------------------------------------------*/ 41 42 /** @defgroup SRAM_Exported_Types SRAM Exported Types 43 * @{ 44 */ 45 /** 46 * @brief HAL SRAM State structures definition 47 */ 48 typedef enum 49 { 50 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 51 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 52 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 53 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 54 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 55 56 } HAL_SRAM_StateTypeDef; 57 58 /** 59 * @brief SRAM handle Structure definition 60 */ 61 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 62 typedef struct __SRAM_HandleTypeDef 63 #else 64 typedef struct 65 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 66 { 67 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 68 69 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 70 71 FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 72 73 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 74 75 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 76 77 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 78 79 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 80 void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ 81 void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ 82 void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ 83 void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ 84 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 85 } SRAM_HandleTypeDef; 86 87 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 88 /** 89 * @brief HAL SRAM Callback ID enumeration definition 90 */ 91 typedef enum 92 { 93 HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ 94 HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ 95 HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ 96 HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ 97 } HAL_SRAM_CallbackIDTypeDef; 98 99 /** 100 * @brief HAL SRAM Callback pointer definition 101 */ 102 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); 103 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); 104 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 105 /** 106 * @} 107 */ 108 109 /* Exported constants --------------------------------------------------------*/ 110 /* Exported macro ------------------------------------------------------------*/ 111 112 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 113 * @{ 114 */ 115 116 /** @brief Reset SRAM handle state 117 * @param __HANDLE__ SRAM handle 118 * @retval None 119 */ 120 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 121 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ 122 (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ 123 (__HANDLE__)->MspInitCallback = NULL; \ 124 (__HANDLE__)->MspDeInitCallback = NULL; \ 125 } while(0) 126 #else 127 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 128 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 129 130 /** 131 * @} 132 */ 133 134 /* Exported functions --------------------------------------------------------*/ 135 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 136 * @{ 137 */ 138 139 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 140 * @{ 141 */ 142 143 /* Initialization/de-initialization functions ********************************/ 144 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, 145 FSMC_NORSRAM_TimingTypeDef *ExtTiming); 146 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 147 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 148 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 149 150 /** 151 * @} 152 */ 153 154 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 155 * @{ 156 */ 157 158 /* I/O operation functions ***************************************************/ 159 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, 160 uint32_t BufferSize); 161 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, 162 uint32_t BufferSize); 163 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, 164 uint32_t BufferSize); 165 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, 166 uint32_t BufferSize); 167 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 168 uint32_t BufferSize); 169 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 170 uint32_t BufferSize); 171 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 172 uint32_t BufferSize); 173 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 174 uint32_t BufferSize); 175 176 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 177 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 178 179 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 180 /* SRAM callback registering/unregistering */ 181 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 182 pSRAM_CallbackTypeDef pCallback); 183 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); 184 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 185 pSRAM_DmaCallbackTypeDef pCallback); 186 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 187 188 /** 189 * @} 190 */ 191 192 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 193 * @{ 194 */ 195 196 /* SRAM Control functions ****************************************************/ 197 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 198 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 199 200 /** 201 * @} 202 */ 203 204 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 205 * @{ 206 */ 207 208 /* SRAM State functions ******************************************************/ 209 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 210 211 /** 212 * @} 213 */ 214 215 /** 216 * @} 217 */ 218 219 /** 220 * @} 221 */ 222 223 /** 224 * @} 225 */ 226 227 #endif /* FSMC_BANK1 */ 228 229 #ifdef __cplusplus 230 } 231 #endif 232 233 #endif /* STM32F1xx_HAL_SRAM_H */ 234 235 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 236
