1 /**
2   ******************************************************************************
3   * @file    stm32f1xx_hal_nor.h
4   * @author  MCD Application Team
5   * @brief   Header file of NOR HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10   * All rights reserved.</center></h2>
11   *
12   * This software component is licensed by ST under BSD 3-Clause license,
13   * the "License"; You may not use this file except in compliance with the
14   * License. You may obtain a copy of the License at:
15   *                       opensource.org/licenses/BSD-3-Clause
16   *
17   ******************************************************************************
18   */
19 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F1xx_HAL_NOR_H
22 #define STM32F1xx_HAL_NOR_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 #if defined(FSMC_BANK1)
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f1xx_ll_fsmc.h"
32 
33 /** @addtogroup STM32F1xx_HAL_Driver
34   * @{
35   */
36 
37 /** @addtogroup NOR
38   * @{
39   */
40 
41 /* Exported typedef ----------------------------------------------------------*/
42 /** @defgroup NOR_Exported_Types NOR Exported Types
43   * @{
44   */
45 
46 /**
47   * @brief  HAL SRAM State structures definition
48   */
49 typedef enum
50 {
51   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
52   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
53   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
54   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
55   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
56 } HAL_NOR_StateTypeDef;
57 
58 /**
59   * @brief  FSMC NOR Status typedef
60   */
61 typedef enum
62 {
63   HAL_NOR_STATUS_SUCCESS  = 0U,
64   HAL_NOR_STATUS_ONGOING,
65   HAL_NOR_STATUS_ERROR,
66   HAL_NOR_STATUS_TIMEOUT
67 } HAL_NOR_StatusTypeDef;
68 
69 /**
70   * @brief  FSMC NOR ID typedef
71   */
72 typedef struct
73 {
74   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
75 
76   uint16_t Device_Code1;
77 
78   uint16_t Device_Code2;
79 
80   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
81                                     These codes can be accessed by performing read operations with specific
82                                     control signals and addresses set.They can also be accessed by issuing
83                                     an Auto Select command                                                   */
84 } NOR_IDTypeDef;
85 
86 /**
87   * @brief  FSMC NOR CFI typedef
88   */
89 typedef struct
90 {
91   /*!< Defines the information stored in the memory's Common flash interface
92        which contains a description of various electrical and timing parameters,
93        density information and functions supported by the memory                   */
94 
95   uint16_t CFI_1;
96 
97   uint16_t CFI_2;
98 
99   uint16_t CFI_3;
100 
101   uint16_t CFI_4;
102 } NOR_CFITypeDef;
103 
104 /**
105   * @brief  NOR handle Structure definition
106   */
107 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
108 typedef struct __NOR_HandleTypeDef
109 #else
110 typedef struct
111 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
112 
113 {
114   FSMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
115 
116   FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
117 
118   FSMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
119 
120   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
121 
122   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
123 
124   uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
125 
126 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
127   void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
128   void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
129 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
130 } NOR_HandleTypeDef;
131 
132 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
133 /**
134   * @brief  HAL NOR Callback ID enumeration definition
135   */
136 typedef enum
137 {
138   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
139   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
140 } HAL_NOR_CallbackIDTypeDef;
141 
142 /**
143   * @brief  HAL NOR Callback pointer definition
144   */
145 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
146 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
147 /**
148   * @}
149   */
150 
151 /* Exported constants --------------------------------------------------------*/
152 /* Exported macro ------------------------------------------------------------*/
153 /** @defgroup NOR_Exported_Macros NOR Exported Macros
154   * @{
155   */
156 /** @brief Reset NOR handle state
157   * @param  __HANDLE__ specifies the NOR handle.
158   * @retval None
159   */
160 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
161 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
162                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
163                                                                (__HANDLE__)->MspInitCallback = NULL;       \
164                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
165                                                              } while(0)
166 #else
167 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
168 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
169 /**
170   * @}
171   */
172 
173 /* Exported functions --------------------------------------------------------*/
174 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
175   * @{
176   */
177 
178 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
179   * @{
180   */
181 
182 /* Initialization/de-initialization functions  ********************************/
183 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
184                                FSMC_NORSRAM_TimingTypeDef *ExtTiming);
185 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
186 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
187 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
188 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
189 /**
190   * @}
191   */
192 
193 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
194   * @{
195   */
196 
197 /* I/O operation functions  ***************************************************/
198 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
199 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
200 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
201 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
202 
203 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
204                                      uint32_t uwBufferSize);
205 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
206                                         uint32_t uwBufferSize);
207 
208 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
209 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
210 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
211 
212 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
213 /* NOR callback registering/unregistering */
214 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
215                                            pNOR_CallbackTypeDef pCallback);
216 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
217 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
218 /**
219   * @}
220   */
221 
222 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
223   * @{
224   */
225 
226 /* NOR Control functions  *****************************************************/
227 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
228 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
229 /**
230   * @}
231   */
232 
233 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
234   * @{
235   */
236 
237 /* NOR State functions ********************************************************/
238 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
239 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
240 /**
241   * @}
242   */
243 
244 /**
245   * @}
246   */
247 
248 /* Private types -------------------------------------------------------------*/
249 /* Private variables ---------------------------------------------------------*/
250 /* Private constants ---------------------------------------------------------*/
251 /** @defgroup NOR_Private_Constants NOR Private Constants
252   * @{
253   */
254 /* NOR device IDs addresses */
255 #define MC_ADDRESS               ((uint16_t)0x0000)
256 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
257 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
258 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
259 
260 /* NOR CFI IDs addresses */
261 #define CFI1_ADDRESS             ((uint16_t)0x0061)
262 #define CFI2_ADDRESS             ((uint16_t)0x0062)
263 #define CFI3_ADDRESS             ((uint16_t)0x0063)
264 #define CFI4_ADDRESS             ((uint16_t)0x0064)
265 
266 /* NOR operation wait timeout */
267 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
268 
269 /* NOR memory data width */
270 #define NOR_MEMORY_8B            ((uint8_t)0x00)
271 #define NOR_MEMORY_16B           ((uint8_t)0x01)
272 
273 /* NOR memory device read/write start address */
274 #define NOR_MEMORY_ADRESS1       (0x60000000U)
275 #define NOR_MEMORY_ADRESS2       (0x64000000U)
276 #define NOR_MEMORY_ADRESS3       (0x68000000U)
277 #define NOR_MEMORY_ADRESS4       (0x6C000000U)
278 /**
279   * @}
280   */
281 
282 /* Private macros ------------------------------------------------------------*/
283 /** @defgroup NOR_Private_Macros NOR Private Macros
284   * @{
285   */
286 /**
287   * @brief  NOR memory address shifting.
288   * @param  __NOR_ADDRESS NOR base address
289   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
290   * @param  __ADDRESS__ NOR memory address
291   * @retval NOR shifted address value
292   */
293 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
294   ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
295               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
296               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
297 
298 /**
299   * @brief  NOR memory write data to specified address.
300   * @param  __ADDRESS__ NOR memory address
301   * @param  __DATA__ Data to write
302   * @retval None
303   */
304 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
305                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
306                                                __DSB();                                                    \
307                                              } while(0)
308 
309 /**
310   * @}
311   */
312 
313 /**
314   * @}
315   */
316 
317 /**
318   * @}
319   */
320 
321 #endif /* FSMC_BANK1 */
322 
323 #ifdef __cplusplus
324 }
325 #endif
326 
327 #endif /* STM32F1xx_HAL_NOR_H */
328 
329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
330