1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32_HAL_LEGACY 23 #define STM32_HAL_LEGACY 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 /* Exported types ------------------------------------------------------------*/ 31 /* Exported constants --------------------------------------------------------*/ 32 33 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 34 * @{ 35 */ 36 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 37 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 38 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 39 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 40 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 41 /** 42 * @} 43 */ 44 45 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 46 * @{ 47 */ 48 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 49 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 50 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 51 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 52 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 53 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 54 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 55 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 56 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 57 #define REGULAR_GROUP ADC_REGULAR_GROUP 58 #define INJECTED_GROUP ADC_INJECTED_GROUP 59 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 60 #define AWD_EVENT ADC_AWD_EVENT 61 #define AWD1_EVENT ADC_AWD1_EVENT 62 #define AWD2_EVENT ADC_AWD2_EVENT 63 #define AWD3_EVENT ADC_AWD3_EVENT 64 #define OVR_EVENT ADC_OVR_EVENT 65 #define JQOVF_EVENT ADC_JQOVF_EVENT 66 #define ALL_CHANNELS ADC_ALL_CHANNELS 67 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 68 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 69 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 70 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 71 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 72 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 73 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 74 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 75 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 76 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 77 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 78 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 79 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 80 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 81 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 82 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 83 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 84 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 85 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 86 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 87 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 88 89 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 90 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 91 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 92 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 93 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 94 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 95 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 96 97 #if defined(STM32H7) 98 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 99 #endif /* STM32H7 */ 100 /** 101 * @} 102 */ 103 104 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 105 * @{ 106 */ 107 108 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 115 * @{ 116 */ 117 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 118 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 119 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 120 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 121 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 122 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 123 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 124 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 125 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 126 #if defined(STM32L0) 127 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 128 #endif 129 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 130 #if defined(STM32F373xC) || defined(STM32F378xx) 131 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 132 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 133 #endif /* STM32F373xC || STM32F378xx */ 134 135 #if defined(STM32L0) || defined(STM32L4) 136 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 137 138 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 139 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 140 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 141 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 142 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 143 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 144 145 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 146 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 147 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 148 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 149 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 150 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 151 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 152 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 153 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 154 #if defined(STM32L0) 155 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 156 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 157 /* to the second dedicated IO (only for COMP2). */ 158 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 159 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 160 #else 161 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 162 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 163 #endif 164 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 165 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 166 167 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 168 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 169 170 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 171 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 172 #if defined(COMP_CSR_LOCK) 173 #define COMP_FLAG_LOCK COMP_CSR_LOCK 174 #elif defined(COMP_CSR_COMP1LOCK) 175 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 176 #elif defined(COMP_CSR_COMPxLOCK) 177 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 178 #endif 179 180 #if defined(STM32L4) 181 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 182 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 183 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 184 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 185 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 186 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 187 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 188 #endif 189 190 #if defined(STM32L0) 191 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 192 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 193 #else 194 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 195 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 196 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 197 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 198 #endif 199 200 #endif 201 /** 202 * @} 203 */ 204 205 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 206 * @{ 207 */ 208 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 209 /** 210 * @} 211 */ 212 213 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 214 * @{ 215 */ 216 217 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 218 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 219 220 /** 221 * @} 222 */ 223 224 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 225 * @{ 226 */ 227 228 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 229 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 230 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 231 #define DAC_WAVE_NONE 0x00000000U 232 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 233 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 234 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 235 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 236 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 237 238 #if defined(STM32G4) || defined(STM32H7) 239 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 240 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 241 #endif 242 243 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 244 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 245 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 246 #endif 247 248 /** 249 * @} 250 */ 251 252 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 253 * @{ 254 */ 255 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 256 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 257 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 258 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 259 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 260 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 261 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 262 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 263 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 264 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 265 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 266 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 267 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 268 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 269 270 #define IS_HAL_REMAPDMA IS_DMA_REMAP 271 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 272 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 273 274 #if defined(STM32L4) 275 276 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 277 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 278 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 279 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 280 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 281 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 282 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 283 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 284 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 285 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 286 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 287 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 288 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 289 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 290 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 291 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 292 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 293 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 294 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 295 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 296 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 297 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 298 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 299 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 300 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 301 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 302 303 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 304 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 305 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 306 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 307 308 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 309 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 310 #endif 311 312 #endif /* STM32L4 */ 313 314 #if defined(STM32G0) 315 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 316 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 317 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 318 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 319 320 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 321 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 322 #endif 323 324 #if defined(STM32H7) 325 326 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 327 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 328 329 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 330 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 331 332 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 333 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 334 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 335 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 336 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 337 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 338 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 339 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 340 341 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 342 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 343 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 344 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 345 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 346 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 347 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 348 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 349 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 350 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 351 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 352 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 353 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 354 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 355 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 356 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 357 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 358 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 359 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 360 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 361 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 362 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 363 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 364 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 365 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 366 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 367 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 368 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 369 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 370 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 371 372 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 373 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 374 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 375 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 376 377 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 378 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 379 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 380 381 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 382 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 383 384 #endif /* STM32H7 */ 385 386 /** 387 * @} 388 */ 389 390 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 391 * @{ 392 */ 393 394 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 395 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 396 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 397 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 398 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 399 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 400 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 401 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 402 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 403 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 404 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 405 #define OBEX_PCROP OPTIONBYTE_PCROP 406 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 407 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 408 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 409 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 410 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 411 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 412 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 413 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 414 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 415 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 416 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 417 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 418 #define PAGESIZE FLASH_PAGE_SIZE 419 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 420 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 421 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 422 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 423 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 424 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 425 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 426 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 427 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 428 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 429 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 430 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 431 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 432 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 433 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 434 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 435 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 436 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 437 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 438 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 439 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 440 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 441 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 442 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 443 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 444 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 445 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 446 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 447 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 448 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 449 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 450 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 451 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 452 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 453 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 454 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 455 #define OB_WDG_SW OB_IWDG_SW 456 #define OB_WDG_HW OB_IWDG_HW 457 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 458 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 459 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 460 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 461 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 462 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 463 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 464 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 465 #if defined(STM32G0) 466 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 467 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 468 #else 469 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 470 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 471 #endif 472 #if defined(STM32H7) 473 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 474 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 475 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 476 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 477 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 478 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 479 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 480 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 481 #endif /* STM32H7 */ 482 483 /** 484 * @} 485 */ 486 487 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 488 * @{ 489 */ 490 491 #if defined(STM32H7) 492 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 493 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 494 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 495 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 496 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 497 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 498 #endif /* STM32H7 */ 499 500 /** 501 * @} 502 */ 503 504 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 505 * @{ 506 */ 507 508 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 509 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 510 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 511 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 512 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 513 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 514 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 515 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 516 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 517 #if defined(STM32G4) 518 519 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 520 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 521 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 522 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 523 #endif /* STM32G4 */ 524 /** 525 * @} 526 */ 527 528 529 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 530 * @{ 531 */ 532 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 533 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 534 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 535 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 536 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 537 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 538 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 539 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 540 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 541 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 542 #endif 543 /** 544 * @} 545 */ 546 547 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 548 * @{ 549 */ 550 551 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 552 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 553 /** 554 * @} 555 */ 556 557 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 558 * @{ 559 */ 560 #define GET_GPIO_SOURCE GPIO_GET_INDEX 561 #define GET_GPIO_INDEX GPIO_GET_INDEX 562 563 #if defined(STM32F4) 564 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 565 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 566 #endif 567 568 #if defined(STM32F7) 569 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 570 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 571 #endif 572 573 #if defined(STM32L4) 574 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 575 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 576 #endif 577 578 #if defined(STM32H7) 579 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 580 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 581 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 582 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 583 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 584 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 585 586 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 587 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 588 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 589 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 590 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 591 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 592 #endif /* STM32H7 */ 593 594 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 595 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 596 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 597 598 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) 599 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 600 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 601 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 602 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 603 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ 604 605 #if defined(STM32L1) 606 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 607 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 608 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 609 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 610 #endif /* STM32L1 */ 611 612 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 613 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 614 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 615 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 616 #endif /* STM32F0 || STM32F3 || STM32F1 */ 617 618 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 619 /** 620 * @} 621 */ 622 623 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 624 * @{ 625 */ 626 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 627 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 628 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 629 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 630 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 631 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 632 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 633 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 634 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 635 636 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 637 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 638 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 639 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 640 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 641 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 642 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 643 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 644 645 #if defined(STM32G4) 646 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 647 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 648 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 649 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 650 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 651 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 652 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 653 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 654 #endif /* STM32G4 */ 655 656 #if defined(STM32H7) 657 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 658 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 659 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 660 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 661 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 662 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 663 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 664 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 665 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 666 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 667 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 668 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 669 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 670 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 671 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 672 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 673 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 674 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 675 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 676 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 677 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 678 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 679 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 680 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 681 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 682 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 683 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 684 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 685 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 686 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 687 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 688 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 689 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 690 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 691 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 692 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 693 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 694 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 695 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 696 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 697 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 698 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 699 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 700 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 701 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 702 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 703 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 704 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 705 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 706 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 707 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 708 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 709 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 710 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 711 712 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 713 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 714 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 715 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 716 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 717 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 718 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 719 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 720 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 721 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 722 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 723 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 724 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 725 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 726 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 727 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 728 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 729 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 730 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 731 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 732 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 733 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 734 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 735 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 736 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 737 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 738 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 739 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 740 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 741 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 742 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 743 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 744 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 745 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 746 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 747 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 748 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 749 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 750 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 751 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 752 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 753 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 754 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 755 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 756 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 757 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 758 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 759 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 760 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 761 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 762 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 763 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 764 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 765 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 766 #endif /* STM32H7 */ 767 768 #if defined(STM32F3) 769 /** @brief Constants defining available sources associated to external events. 770 */ 771 #define HRTIM_EVENTSRC_1 (0x00000000U) 772 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 773 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 774 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 775 776 /** @brief Constants defining the events that can be selected to configure the 777 * set/reset crossbar of a timer output 778 */ 779 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) 780 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) 781 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) 782 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) 783 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) 784 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) 785 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) 786 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) 787 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) 788 789 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) 790 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) 791 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) 792 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) 793 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) 794 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) 795 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) 796 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) 797 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) 798 799 /** @brief Constants defining the event filtering applied to external events 800 * by a timer 801 */ 802 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) 803 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) 804 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) 805 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) 806 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) 807 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) 808 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) 809 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) 810 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) 811 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) 812 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) 813 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) 814 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) 815 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) 816 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) 817 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) 818 819 /** @brief Constants defining the DLL calibration periods (in micro seconds) 820 */ 821 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 822 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 823 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 824 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 825 826 #endif /* STM32F3 */ 827 /** 828 * @} 829 */ 830 831 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 832 * @{ 833 */ 834 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 835 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 836 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 837 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 838 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 839 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 840 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 841 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 842 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 843 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 844 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 845 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 846 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 847 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 848 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 849 #endif 850 /** 851 * @} 852 */ 853 854 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 855 * @{ 856 */ 857 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 858 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 859 860 /** 861 * @} 862 */ 863 864 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 865 * @{ 866 */ 867 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 868 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 869 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 870 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 871 /** 872 * @} 873 */ 874 875 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 876 * @{ 877 */ 878 879 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 880 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 881 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 882 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 883 884 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 885 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 886 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 887 888 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 889 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 890 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 891 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 892 893 /* The following 3 definition have also been present in a temporary version of lptim.h */ 894 /* They need to be renamed also to the right name, just in case */ 895 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 896 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 897 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 898 899 /** 900 * @} 901 */ 902 903 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 904 * @{ 905 */ 906 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 907 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 908 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 909 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 910 911 #define NAND_AddressTypedef NAND_AddressTypeDef 912 913 #define __ARRAY_ADDRESS ARRAY_ADDRESS 914 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 915 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 916 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 917 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 918 /** 919 * @} 920 */ 921 922 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 923 * @{ 924 */ 925 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 926 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 927 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 928 #define NOR_ERROR HAL_NOR_STATUS_ERROR 929 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 930 931 #define __NOR_WRITE NOR_WRITE 932 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 933 /** 934 * @} 935 */ 936 937 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 938 * @{ 939 */ 940 941 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 942 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 943 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 944 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 945 946 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 947 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 948 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 949 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 950 951 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 952 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 953 954 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 955 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 956 957 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 958 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 959 960 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 961 962 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 963 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 964 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 965 966 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 967 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 968 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 969 #endif 970 971 972 /** 973 * @} 974 */ 975 976 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 977 * @{ 978 */ 979 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 980 981 #if defined(STM32H7) 982 #define I2S_IT_TXE I2S_IT_TXP 983 #define I2S_IT_RXNE I2S_IT_RXP 984 985 #define I2S_FLAG_TXE I2S_FLAG_TXP 986 #define I2S_FLAG_RXNE I2S_FLAG_RXP 987 #endif 988 989 #if defined(STM32F7) 990 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 991 #endif 992 /** 993 * @} 994 */ 995 996 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 997 * @{ 998 */ 999 1000 /* Compact Flash-ATA registers description */ 1001 #define CF_DATA ATA_DATA 1002 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1003 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1004 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1005 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1006 #define CF_CARD_HEAD ATA_CARD_HEAD 1007 #define CF_STATUS_CMD ATA_STATUS_CMD 1008 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1009 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1010 1011 /* Compact Flash-ATA commands */ 1012 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1013 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1014 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1015 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1016 1017 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1018 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1019 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1020 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1021 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1022 /** 1023 * @} 1024 */ 1025 1026 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1027 * @{ 1028 */ 1029 1030 #define FORMAT_BIN RTC_FORMAT_BIN 1031 #define FORMAT_BCD RTC_FORMAT_BCD 1032 1033 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1034 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1035 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1036 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1037 1038 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1039 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1040 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1041 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1042 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1043 1044 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1045 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1046 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1047 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1048 1049 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1050 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1051 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1052 1053 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1054 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1055 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1056 1057 #if defined(STM32H7) 1058 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1059 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1060 1061 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1062 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1063 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1064 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL 1065 #endif /* STM32H7 */ 1066 1067 /** 1068 * @} 1069 */ 1070 1071 1072 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1073 * @{ 1074 */ 1075 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1076 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1077 1078 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1079 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1080 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1081 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1082 1083 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1084 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1085 1086 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1087 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1088 /** 1089 * @} 1090 */ 1091 1092 1093 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1094 * @{ 1095 */ 1096 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1097 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1098 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1099 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1100 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1101 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1102 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1103 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1104 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1105 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1106 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1107 /** 1108 * @} 1109 */ 1110 1111 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1112 * @{ 1113 */ 1114 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1115 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1116 1117 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1118 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1119 1120 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1121 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1122 1123 #if defined(STM32H7) 1124 1125 #define SPI_FLAG_TXE SPI_FLAG_TXP 1126 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1127 1128 #define SPI_IT_TXE SPI_IT_TXP 1129 #define SPI_IT_RXNE SPI_IT_RXP 1130 1131 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1132 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1133 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1134 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1135 1136 #endif /* STM32H7 */ 1137 1138 /** 1139 * @} 1140 */ 1141 1142 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1143 * @{ 1144 */ 1145 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1146 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1147 1148 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1149 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1150 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1151 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1152 #define TIM_DMABase_SR TIM_DMABASE_SR 1153 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1154 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1155 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1156 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1157 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1158 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1159 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1160 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1161 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1162 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1163 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1164 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1165 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1166 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1167 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1168 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1169 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1170 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1171 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1172 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1173 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1174 #define TIM_DMABase_OR TIM_DMABASE_OR 1175 1176 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1177 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1178 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1179 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1180 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1181 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1182 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1183 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1184 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1185 1186 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1187 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1188 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1189 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1190 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1191 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1192 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1193 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1194 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1195 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1196 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1197 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1198 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1199 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1200 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1201 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1202 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1203 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1204 1205 #if defined(STM32L0) 1206 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1207 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1208 #endif 1209 1210 #if defined(STM32F3) 1211 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1212 #endif 1213 1214 #if defined(STM32H7) 1215 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1216 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1217 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1218 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1219 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1220 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1221 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1222 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1223 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1224 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1225 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1226 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1227 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1228 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1229 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1230 #endif 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1237 * @{ 1238 */ 1239 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1240 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1241 /** 1242 * @} 1243 */ 1244 1245 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1246 * @{ 1247 */ 1248 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1249 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1250 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1251 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1252 1253 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1254 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1255 1256 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1257 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1258 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1259 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1260 1261 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1262 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1263 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1264 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1265 1266 #define __DIV_LPUART UART_DIV_LPUART 1267 1268 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1269 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1270 1271 /** 1272 * @} 1273 */ 1274 1275 1276 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1277 * @{ 1278 */ 1279 1280 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1281 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1282 1283 #define USARTNACK_ENABLED USART_NACK_ENABLE 1284 #define USARTNACK_DISABLED USART_NACK_DISABLE 1285 /** 1286 * @} 1287 */ 1288 1289 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1290 * @{ 1291 */ 1292 #define CFR_BASE WWDG_CFR_BASE 1293 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1299 * @{ 1300 */ 1301 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1302 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1303 #define CAN_IT_RQCP0 CAN_IT_TME 1304 #define CAN_IT_RQCP1 CAN_IT_TME 1305 #define CAN_IT_RQCP2 CAN_IT_TME 1306 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1307 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1308 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1309 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1310 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1311 1312 /** 1313 * @} 1314 */ 1315 1316 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1317 * @{ 1318 */ 1319 1320 #define VLAN_TAG ETH_VLAN_TAG 1321 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1322 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1323 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1324 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1325 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1326 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1327 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1328 1329 #define ETH_MMCCR 0x00000100U 1330 #define ETH_MMCRIR 0x00000104U 1331 #define ETH_MMCTIR 0x00000108U 1332 #define ETH_MMCRIMR 0x0000010CU 1333 #define ETH_MMCTIMR 0x00000110U 1334 #define ETH_MMCTGFSCCR 0x0000014CU 1335 #define ETH_MMCTGFMSCCR 0x00000150U 1336 #define ETH_MMCTGFCR 0x00000168U 1337 #define ETH_MMCRFCECR 0x00000194U 1338 #define ETH_MMCRFAECR 0x00000198U 1339 #define ETH_MMCRGUFCR 0x000001C4U 1340 1341 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1342 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1343 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1344 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1345 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1346 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1347 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1348 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1349 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1350 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1351 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1352 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1353 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1354 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1355 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1356 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1357 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1358 #if defined(STM32F1) 1359 #else 1360 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1361 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1362 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1363 #endif 1364 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1365 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1366 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1367 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1368 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1369 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1370 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1371 1372 /** 1373 * @} 1374 */ 1375 1376 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1377 * @{ 1378 */ 1379 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1380 #define DCMI_IT_OVF DCMI_IT_OVR 1381 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1382 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1383 1384 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1385 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1386 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1387 1388 /** 1389 * @} 1390 */ 1391 1392 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1393 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1394 || defined(STM32H7) 1395 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1396 * @{ 1397 */ 1398 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1399 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1400 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1401 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1402 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1403 1404 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1405 #define CM_RGB888 DMA2D_INPUT_RGB888 1406 #define CM_RGB565 DMA2D_INPUT_RGB565 1407 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1408 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1409 #define CM_L8 DMA2D_INPUT_L8 1410 #define CM_AL44 DMA2D_INPUT_AL44 1411 #define CM_AL88 DMA2D_INPUT_AL88 1412 #define CM_L4 DMA2D_INPUT_L4 1413 #define CM_A8 DMA2D_INPUT_A8 1414 #define CM_A4 DMA2D_INPUT_A4 1415 /** 1416 * @} 1417 */ 1418 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1419 1420 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1421 * @{ 1422 */ 1423 1424 /** 1425 * @} 1426 */ 1427 1428 /* Exported functions --------------------------------------------------------*/ 1429 1430 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1431 * @{ 1432 */ 1433 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1434 /** 1435 * @} 1436 */ 1437 1438 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1439 * @{ 1440 */ 1441 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1442 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1443 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1444 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1445 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1446 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1447 1448 /*HASH Algorithm Selection*/ 1449 1450 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1451 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1452 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1453 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1454 1455 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1456 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1457 1458 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1459 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1460 1461 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1462 1463 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1464 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1465 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1466 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1467 1468 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1469 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1470 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1471 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1472 1473 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1474 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1475 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1476 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1477 1478 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1479 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1480 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1481 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1482 1483 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1484 /** 1485 * @} 1486 */ 1487 1488 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1489 * @{ 1490 */ 1491 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1492 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1493 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1494 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1495 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1496 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1497 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1498 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1499 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1500 #if defined(STM32L0) 1501 #else 1502 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1503 #endif 1504 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1505 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1506 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1507 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1508 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1509 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1510 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1511 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1512 1513 /** 1514 * @} 1515 */ 1516 1517 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1518 * @{ 1519 */ 1520 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1521 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1522 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1523 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1524 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1525 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1526 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1527 1528 /** 1529 * @} 1530 */ 1531 1532 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1533 * @{ 1534 */ 1535 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1536 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1537 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1538 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1539 1540 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1541 1542 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1543 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1544 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1545 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1546 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1547 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1548 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1549 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1550 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1551 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1552 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1553 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1554 1555 #if defined(STM32F4) 1556 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1557 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1558 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1559 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1560 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1561 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1562 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1563 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1564 #endif /* STM32F4 */ 1565 /** 1566 * @} 1567 */ 1568 1569 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1570 * @{ 1571 */ 1572 1573 #if defined(STM32G0) 1574 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1575 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1576 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1577 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1578 #endif 1579 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1580 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1581 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1582 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1583 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1584 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1585 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1586 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1587 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1588 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1589 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1590 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1591 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1592 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1593 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1594 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1595 1596 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1597 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1598 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1599 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1600 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1601 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1602 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1603 1604 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1605 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1606 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1607 #define CR_PMODE_BB CR_VOS_BB 1608 1609 #define DBP_BitNumber DBP_BIT_NUMBER 1610 #define PVDE_BitNumber PVDE_BIT_NUMBER 1611 #define PMODE_BitNumber PMODE_BIT_NUMBER 1612 #define EWUP_BitNumber EWUP_BIT_NUMBER 1613 #define FPDS_BitNumber FPDS_BIT_NUMBER 1614 #define ODEN_BitNumber ODEN_BIT_NUMBER 1615 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1616 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1617 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1618 #define BRE_BitNumber BRE_BIT_NUMBER 1619 1620 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1621 1622 /** 1623 * @} 1624 */ 1625 1626 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1627 * @{ 1628 */ 1629 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1630 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1631 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1632 /** 1633 * @} 1634 */ 1635 1636 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1637 * @{ 1638 */ 1639 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1640 /** 1641 * @} 1642 */ 1643 1644 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1645 * @{ 1646 */ 1647 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1648 #define HAL_TIM_DMAError TIM_DMAError 1649 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1650 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1651 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1652 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1653 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1654 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1655 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1656 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1657 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1658 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1659 /** 1660 * @} 1661 */ 1662 1663 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1664 * @{ 1665 */ 1666 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1667 /** 1668 * @} 1669 */ 1670 1671 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1672 * @{ 1673 */ 1674 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1675 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1676 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1677 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1678 /** 1679 * @} 1680 */ 1681 1682 1683 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1684 * @{ 1685 */ 1686 1687 /** 1688 * @} 1689 */ 1690 1691 /* Exported macros ------------------------------------------------------------*/ 1692 1693 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1694 * @{ 1695 */ 1696 #define AES_IT_CC CRYP_IT_CC 1697 #define AES_IT_ERR CRYP_IT_ERR 1698 #define AES_FLAG_CCF CRYP_FLAG_CCF 1699 /** 1700 * @} 1701 */ 1702 1703 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1704 * @{ 1705 */ 1706 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1707 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1708 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1709 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1710 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1711 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1712 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1713 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1714 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1715 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1716 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1717 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1718 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1719 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1720 1721 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1722 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1723 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1724 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1725 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1726 1727 /** 1728 * @} 1729 */ 1730 1731 1732 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1733 * @{ 1734 */ 1735 #define __ADC_ENABLE __HAL_ADC_ENABLE 1736 #define __ADC_DISABLE __HAL_ADC_DISABLE 1737 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1738 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1739 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1740 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1741 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1742 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1743 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1744 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1745 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1746 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1747 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1748 1749 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1750 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1751 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1752 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1753 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1754 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1755 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1756 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1757 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1758 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1759 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1760 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1761 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1762 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1763 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1764 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1765 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1766 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1767 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1768 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1769 1770 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1771 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1772 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1773 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1774 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1775 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1776 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1777 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1778 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1779 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1780 1781 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1782 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1783 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1784 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1785 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1786 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1787 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1788 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1789 1790 #define __HAL_ADC_SQR1 ADC_SQR1 1791 #define __HAL_ADC_SMPR1 ADC_SMPR1 1792 #define __HAL_ADC_SMPR2 ADC_SMPR2 1793 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1794 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1795 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1796 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1797 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1798 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1799 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1800 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1801 #define __HAL_ADC_JSQR ADC_JSQR 1802 1803 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1804 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1805 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1806 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1807 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1808 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1809 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1810 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1811 1812 /** 1813 * @} 1814 */ 1815 1816 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1817 * @{ 1818 */ 1819 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1820 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1821 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1822 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1823 1824 /** 1825 * @} 1826 */ 1827 1828 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1829 * @{ 1830 */ 1831 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1832 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1833 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1834 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1835 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1836 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1837 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1838 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1839 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1840 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1841 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1842 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1843 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1844 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1845 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1846 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1847 1848 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1849 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1850 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1851 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1852 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1853 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1854 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1855 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1856 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1857 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1858 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1859 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1860 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1861 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1862 1863 1864 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1865 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1866 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1867 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1868 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1869 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1870 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1871 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1872 #if defined(STM32H7) 1873 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 1874 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 1875 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 1876 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 1877 #else 1878 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1879 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1880 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1881 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1882 #endif /* STM32H7 */ 1883 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1884 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1885 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1886 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1887 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1888 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1889 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1890 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1891 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1892 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1893 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1894 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1895 1896 /** 1897 * @} 1898 */ 1899 1900 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 1901 * @{ 1902 */ 1903 #if defined(STM32F3) 1904 #define COMP_START __HAL_COMP_ENABLE 1905 #define COMP_STOP __HAL_COMP_DISABLE 1906 #define COMP_LOCK __HAL_COMP_LOCK 1907 1908 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1909 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1910 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1911 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1912 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1913 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1914 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1915 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1916 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1917 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1918 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1919 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1920 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1921 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1922 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1923 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1924 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1925 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1926 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1927 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1928 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1929 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1930 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1931 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1932 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1933 # endif 1934 # if defined(STM32F302xE) || defined(STM32F302xC) 1935 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1936 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1937 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1938 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1939 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1940 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1941 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1942 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1943 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1944 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1945 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1946 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1947 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1948 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1949 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1950 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1951 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1952 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1953 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 1954 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 1955 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 1956 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 1957 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 1958 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 1959 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 1960 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 1961 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 1962 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 1963 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 1964 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 1965 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 1966 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 1967 # endif 1968 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 1969 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 1970 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1971 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 1972 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1973 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 1974 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 1975 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 1976 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 1977 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1978 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 1979 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1980 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 1981 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 1982 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 1983 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 1984 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1985 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 1986 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1987 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 1988 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 1989 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 1990 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 1991 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1992 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 1993 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1994 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 1995 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 1996 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 1997 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 1998 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 1999 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2000 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2001 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2002 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2003 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2004 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2005 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2006 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2007 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2008 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2009 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2010 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2011 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2012 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2013 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2014 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2015 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2016 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2017 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2018 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2019 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2020 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2021 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2022 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2023 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2024 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2025 # endif 2026 # if defined(STM32F373xC) ||defined(STM32F378xx) 2027 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2028 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2029 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2030 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2031 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2032 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2033 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2034 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2035 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2036 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2037 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2038 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2039 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2040 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2041 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2042 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2043 # endif 2044 #else 2045 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2046 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2047 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2048 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2049 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2050 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2051 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2052 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2053 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2054 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2055 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2056 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2057 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2058 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2059 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2060 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2061 #endif 2062 2063 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2064 2065 #if defined(STM32L0) || defined(STM32L4) 2066 /* Note: On these STM32 families, the only argument of this macro */ 2067 /* is COMP_FLAG_LOCK. */ 2068 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2069 /* argument. */ 2070 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2071 #endif 2072 /** 2073 * @} 2074 */ 2075 2076 #if defined(STM32L0) || defined(STM32L4) 2077 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2078 * @{ 2079 */ 2080 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2081 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2082 /** 2083 * @} 2084 */ 2085 #endif 2086 2087 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2088 * @{ 2089 */ 2090 2091 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2092 ((WAVE) == DAC_WAVE_NOISE)|| \ 2093 ((WAVE) == DAC_WAVE_TRIANGLE)) 2094 2095 /** 2096 * @} 2097 */ 2098 2099 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2100 * @{ 2101 */ 2102 2103 #define IS_WRPAREA IS_OB_WRPAREA 2104 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2105 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2106 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2107 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2108 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2109 2110 /** 2111 * @} 2112 */ 2113 2114 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2115 * @{ 2116 */ 2117 2118 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2119 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2120 #if defined(STM32F1) 2121 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2122 #else 2123 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2124 #endif /* STM32F1 */ 2125 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2126 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2127 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2128 #define __HAL_I2C_SPEED I2C_SPEED 2129 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2130 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2131 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2132 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2133 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2134 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2135 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2136 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2137 /** 2138 * @} 2139 */ 2140 2141 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2142 * @{ 2143 */ 2144 2145 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2146 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2147 2148 #if defined(STM32H7) 2149 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2150 #endif 2151 2152 /** 2153 * @} 2154 */ 2155 2156 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2157 * @{ 2158 */ 2159 2160 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2161 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2162 2163 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2164 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2165 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2166 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2167 2168 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2169 2170 2171 /** 2172 * @} 2173 */ 2174 2175 2176 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2177 * @{ 2178 */ 2179 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2180 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2181 /** 2182 * @} 2183 */ 2184 2185 2186 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2187 * @{ 2188 */ 2189 2190 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2191 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2192 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2193 2194 /** 2195 * @} 2196 */ 2197 2198 2199 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2200 * @{ 2201 */ 2202 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2203 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2204 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2205 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2206 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2207 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2208 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2209 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2210 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2211 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2212 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2213 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2214 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2215 2216 /** 2217 * @} 2218 */ 2219 2220 2221 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2222 * @{ 2223 */ 2224 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2225 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2226 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2227 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2228 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2229 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2230 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2231 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2232 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2233 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2234 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2235 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2236 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2237 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2238 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2239 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2240 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2241 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2242 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2243 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2244 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2245 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2246 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2247 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2248 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2249 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2250 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2251 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2252 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2253 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2254 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2255 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2256 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2257 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2258 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2259 2260 #if defined (STM32F4) 2261 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2262 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2263 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2264 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2265 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2266 #else 2267 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2268 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2269 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2270 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2271 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2272 #endif /* STM32F4 */ 2273 /** 2274 * @} 2275 */ 2276 2277 2278 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2279 * @{ 2280 */ 2281 2282 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2283 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2284 2285 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2286 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2287 2288 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2289 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2290 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2291 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2292 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2293 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2294 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2295 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2296 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2297 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2298 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2299 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2300 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2301 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2302 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2303 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2304 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2305 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2306 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2307 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2308 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2309 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2310 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2311 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2312 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2313 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2314 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2315 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2316 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2317 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2318 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2319 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2320 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2321 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2322 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2323 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2324 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2325 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2326 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2327 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2328 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2329 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2330 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2331 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2332 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2333 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2334 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2335 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2336 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2337 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2338 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2339 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2340 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2341 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2342 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2343 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2344 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2345 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2346 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2347 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2348 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2349 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2350 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2351 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2352 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2353 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2354 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2355 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2356 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2357 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2358 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2359 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2360 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2361 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2362 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2363 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2364 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2365 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2366 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2367 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2368 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2369 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2370 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2371 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2372 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2373 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2374 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2375 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2376 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2377 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2378 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2379 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2380 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2381 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2382 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2383 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2384 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2385 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2386 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2387 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2388 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2389 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2390 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2391 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2392 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2393 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2394 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2395 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2396 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2397 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2398 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2399 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2400 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2401 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2402 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2403 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2404 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2405 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2406 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2407 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2408 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2409 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2410 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2411 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2412 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2413 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2414 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2415 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2416 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2417 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2418 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2419 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2420 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2421 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2422 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2423 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2424 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2425 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2426 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2427 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2428 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2429 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2430 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2431 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2432 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2433 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2434 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2435 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2436 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2437 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2438 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2439 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2440 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2441 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2442 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2443 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2444 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2445 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2446 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2447 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2448 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2449 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2450 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2451 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2452 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2453 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2454 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2455 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2456 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2457 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2458 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2459 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2460 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2461 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2462 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2463 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2464 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2465 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2466 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2467 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2468 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2469 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2470 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2471 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2472 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2473 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2474 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2475 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2476 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2477 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2478 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2479 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2480 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2481 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2482 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2483 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2484 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2485 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2486 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2487 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2488 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2489 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2490 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2491 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2492 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2493 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2494 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2495 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2496 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2497 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2498 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2499 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2500 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2501 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2502 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2503 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2504 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2505 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2506 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2507 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2508 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2509 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2510 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2511 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2512 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2513 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2514 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2515 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2516 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2517 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2518 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2519 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2520 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2521 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2522 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2523 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2524 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2525 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2526 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2527 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2528 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2529 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2530 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2531 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2532 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2533 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2534 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2535 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2536 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2537 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2538 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2539 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2540 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2541 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2542 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2543 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2544 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2545 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2546 2547 #if defined(STM32WB) 2548 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2549 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2550 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2551 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2552 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2553 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2554 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2555 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2556 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2557 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2558 #define QSPI_IRQHandler QUADSPI_IRQHandler 2559 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2560 2561 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2562 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2563 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2564 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2565 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2566 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2567 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2568 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2569 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2570 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2571 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2572 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2573 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2574 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2575 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2576 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2577 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2578 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2579 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2580 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2581 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2582 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2583 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2584 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2585 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2586 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2587 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2588 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2589 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2590 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2591 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2592 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2593 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2594 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2595 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2596 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2597 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2598 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2599 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2600 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2601 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2602 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2603 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2604 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2605 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2606 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2607 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2608 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2609 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2610 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2611 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2612 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2613 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2614 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2615 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2616 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2617 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2618 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2619 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2620 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2621 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2622 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2623 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2624 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2625 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2626 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2627 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2628 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2629 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2630 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2631 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2632 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2633 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2634 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2635 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2636 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2637 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2638 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2639 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2640 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2641 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2642 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2643 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2644 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2645 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2646 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2647 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2648 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2649 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2650 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2651 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2652 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2653 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2654 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2655 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2656 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2657 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2658 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2659 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2660 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2661 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2662 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2663 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2664 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2665 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2666 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2667 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2668 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2669 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2670 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2671 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2672 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2673 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2674 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2675 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2676 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2677 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2678 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2679 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2680 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2681 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2682 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2683 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2684 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2685 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2686 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2687 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2688 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2689 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2690 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2691 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2692 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2693 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2694 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2695 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2696 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2697 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2698 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2699 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2700 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2701 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2702 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2703 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2704 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2705 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2706 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2707 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2708 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2709 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2710 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2711 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2712 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2713 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2714 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2715 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2716 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2717 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2718 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2719 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2720 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2721 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2722 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2723 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2724 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2725 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2726 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2727 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2728 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2729 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2730 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2731 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2732 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2733 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2734 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2735 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2736 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2737 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2738 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2739 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2740 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2741 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2742 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2743 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2744 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2745 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2746 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2747 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2748 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2749 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2750 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2751 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2752 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2753 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2754 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2755 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2756 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2757 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2758 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2759 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2760 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2761 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2762 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2763 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2764 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2765 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2766 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2767 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2768 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2769 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2770 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2771 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2772 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2773 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2774 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2775 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2776 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2777 2778 #if defined(STM32H7) 2779 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2780 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2781 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2783 2784 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2785 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2786 2787 2788 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2789 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2790 #endif 2791 2792 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2793 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2794 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2795 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2796 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2797 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2798 2799 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2800 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2801 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2802 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2803 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2804 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2805 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2806 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2807 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2808 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2809 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2810 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2811 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2812 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2813 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2814 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2815 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2816 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2817 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2818 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2819 2820 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2821 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2822 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2823 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2824 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2825 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2826 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2827 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2828 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2829 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2830 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2831 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2832 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2833 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2834 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2835 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2836 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2837 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2838 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2839 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2840 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2841 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2842 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2843 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2844 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2845 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2846 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2847 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2848 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2849 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2850 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2851 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2852 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2853 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2854 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2855 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2856 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2857 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2858 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2859 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2860 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2861 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2862 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2863 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2864 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2865 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2866 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2867 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2868 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2869 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2870 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2871 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2872 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2873 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2874 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2875 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2876 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2877 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2878 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2879 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2880 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2881 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2882 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2883 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2884 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2885 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2886 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2887 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2888 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2889 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2890 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2891 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2892 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2893 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2894 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2895 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2896 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2897 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 2898 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 2899 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 2900 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 2901 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 2902 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 2903 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 2904 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 2905 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 2906 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 2907 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 2908 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 2909 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 2910 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 2911 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 2912 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 2913 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 2914 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 2915 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 2916 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2917 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2918 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2919 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2920 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 2921 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 2922 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2923 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2924 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2925 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2926 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 2927 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 2928 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2929 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2930 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2931 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2932 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2933 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2934 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 2935 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 2936 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 2937 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 2938 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 2939 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 2940 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 2941 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 2942 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 2943 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 2944 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 2945 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 2946 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 2947 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 2948 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 2949 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 2950 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 2951 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 2952 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 2953 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 2954 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 2955 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 2956 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 2957 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 2958 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 2959 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 2960 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 2961 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 2962 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 2963 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 2964 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 2965 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 2966 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 2967 2968 /* alias define maintained for legacy */ 2969 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2970 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2971 2972 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 2973 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 2974 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 2975 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 2976 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 2977 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 2978 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 2979 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 2980 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 2981 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 2982 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 2983 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 2984 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 2985 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 2986 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 2987 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 2988 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 2989 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 2990 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 2991 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 2992 2993 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 2994 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 2995 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 2996 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 2997 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 2998 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 2999 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3000 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3001 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3002 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3003 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3004 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3005 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3006 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3007 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3008 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3009 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3010 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3011 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3012 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3013 3014 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3015 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3016 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3017 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3018 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3019 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3020 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3021 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3022 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3023 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3024 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3025 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3026 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3027 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3028 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3029 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3030 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3031 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3032 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3033 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3034 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3035 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3036 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3037 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3038 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3039 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3040 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3041 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3042 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3043 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3044 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3045 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3046 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3047 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3048 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3049 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3050 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3051 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3052 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3053 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3054 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3055 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3056 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3057 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3058 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3059 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3060 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3061 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3062 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3063 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3064 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3065 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3066 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3067 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3068 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3069 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3070 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3071 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3072 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3073 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3074 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3075 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3076 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3077 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3078 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3079 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3080 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3081 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3082 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3083 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3084 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3085 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3086 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3087 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3088 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3089 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3090 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3091 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3092 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3093 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3094 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3095 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3096 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3097 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3098 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3099 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3100 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3101 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3102 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3103 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3104 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3105 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3106 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3107 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3108 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3109 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3110 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3111 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3112 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3113 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3114 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3115 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3116 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3117 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3118 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3119 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3120 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3121 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3122 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3123 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3124 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3125 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3126 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3127 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3128 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3129 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3130 3131 #if defined(STM32L1) 3132 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3133 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3134 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3135 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3136 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3137 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3138 #endif /* STM32L1 */ 3139 3140 #if defined(STM32F4) 3141 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3142 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3143 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3144 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3145 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3146 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3147 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3148 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3149 #define Sdmmc1ClockSelection SdioClockSelection 3150 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3151 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3152 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3153 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3154 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3155 #endif 3156 3157 #if defined(STM32F7) || defined(STM32L4) 3158 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3159 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3160 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3161 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3162 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3163 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3164 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3165 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3166 #define SdioClockSelection Sdmmc1ClockSelection 3167 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3168 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3169 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3170 #endif 3171 3172 #if defined(STM32F7) 3173 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3174 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3175 #endif 3176 3177 #if defined(STM32H7) 3178 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3179 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3180 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3181 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3182 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3183 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3184 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3185 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3186 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3187 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3188 3189 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3190 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3191 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3192 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3193 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3194 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3195 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3196 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3197 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3198 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3199 #endif 3200 3201 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3202 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3203 3204 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3205 3206 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3207 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3208 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3209 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3210 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3211 3212 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3213 3214 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3215 #define RCC_IT_CSSHSE RCC_IT_CSS 3216 3217 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3218 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3219 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3220 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3221 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3222 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3223 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3224 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3225 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3226 3227 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3228 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3229 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3230 3231 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3232 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3233 #define RCC_MCO_NODIV RCC_MCODIV_1 3234 #define RCC_MCO_DIV1 RCC_MCODIV_1 3235 #define RCC_MCO_DIV2 RCC_MCODIV_2 3236 #define RCC_MCO_DIV4 RCC_MCODIV_4 3237 #define RCC_MCO_DIV8 RCC_MCODIV_8 3238 #define RCC_MCO_DIV16 RCC_MCODIV_16 3239 #define RCC_MCO_DIV32 RCC_MCODIV_32 3240 #define RCC_MCO_DIV64 RCC_MCODIV_64 3241 #define RCC_MCO_DIV128 RCC_MCODIV_128 3242 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3243 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3244 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3245 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3246 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3247 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3248 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3249 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3250 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3251 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3252 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3253 3254 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) 3255 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3256 #else 3257 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3258 #endif 3259 3260 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3261 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3262 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3263 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3264 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3265 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3266 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3267 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3268 3269 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3270 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3271 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3272 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3273 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3274 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3275 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3276 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3277 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3278 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3279 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3280 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3281 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3282 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3283 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3284 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3285 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3286 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3287 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3288 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3289 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3290 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3291 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3292 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3293 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3294 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3295 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3296 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3297 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3298 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3299 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3300 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3301 3302 #define CR_HSION_BB RCC_CR_HSION_BB 3303 #define CR_CSSON_BB RCC_CR_CSSON_BB 3304 #define CR_PLLON_BB RCC_CR_PLLON_BB 3305 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3306 #define CR_MSION_BB RCC_CR_MSION_BB 3307 #define CSR_LSION_BB RCC_CSR_LSION_BB 3308 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3309 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3310 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3311 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3312 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3313 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3314 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3315 #define CR_HSEON_BB RCC_CR_HSEON_BB 3316 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3317 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3318 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3319 3320 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3321 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3322 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3323 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3324 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3325 3326 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3327 3328 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3329 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3330 3331 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3332 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3333 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3334 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3335 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3336 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3337 3338 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3339 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3340 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3341 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3342 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3343 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3344 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3345 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3346 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3347 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3348 #define DfsdmClockSelection Dfsdm1ClockSelection 3349 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3350 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3351 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3352 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3353 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3354 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3355 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3356 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3357 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3358 3359 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3360 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3361 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3362 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3363 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3364 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3365 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3366 3367 /** 3368 * @} 3369 */ 3370 3371 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3372 * @{ 3373 */ 3374 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3375 3376 /** 3377 * @} 3378 */ 3379 3380 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3381 * @{ 3382 */ 3383 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) 3384 #else 3385 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3386 #endif 3387 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3388 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3389 3390 #if defined (STM32F1) 3391 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3392 3393 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3394 3395 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3396 3397 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3398 3399 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3400 #else 3401 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3402 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3403 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3404 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3405 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3406 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3407 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3408 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3409 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3410 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3411 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3412 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3413 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3414 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3415 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3416 #endif /* STM32F1 */ 3417 3418 #define IS_ALARM IS_RTC_ALARM 3419 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3420 #define IS_TAMPER IS_RTC_TAMPER 3421 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3422 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3423 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3424 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3425 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3426 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3427 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3428 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3429 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3430 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3431 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3432 3433 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3434 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3435 3436 /** 3437 * @} 3438 */ 3439 3440 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose 3441 * @{ 3442 */ 3443 3444 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3445 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3446 3447 #if defined(STM32F4) || defined(STM32F2) 3448 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3449 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3450 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3451 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3452 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3453 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3454 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3455 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3456 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3457 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3458 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3459 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3460 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3461 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3462 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3463 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3464 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3465 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3466 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3467 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3468 /* alias CMSIS */ 3469 #define SDMMC1_IRQn SDIO_IRQn 3470 #define SDMMC1_IRQHandler SDIO_IRQHandler 3471 #endif 3472 3473 #if defined(STM32F7) || defined(STM32L4) 3474 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3475 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3476 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3477 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3478 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3479 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3480 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3481 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3482 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3483 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3484 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3485 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3486 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3487 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3488 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3489 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3490 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3491 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3492 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3493 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3494 /* alias CMSIS for compatibilities */ 3495 #define SDIO_IRQn SDMMC1_IRQn 3496 #define SDIO_IRQHandler SDMMC1_IRQHandler 3497 #endif 3498 3499 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3500 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3501 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3502 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3503 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3504 #endif 3505 3506 #if defined(STM32H7) || defined(STM32L5) 3507 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3508 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3509 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3510 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3511 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3512 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3513 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3514 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3515 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3516 #endif 3517 /** 3518 * @} 3519 */ 3520 3521 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3522 * @{ 3523 */ 3524 3525 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3526 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3527 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3528 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3529 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3530 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3531 3532 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3533 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3534 3535 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3536 3537 /** 3538 * @} 3539 */ 3540 3541 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3542 * @{ 3543 */ 3544 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3545 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3546 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3547 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3548 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3549 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3550 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3551 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3552 /** 3553 * @} 3554 */ 3555 3556 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3557 * @{ 3558 */ 3559 3560 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3561 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3562 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3563 3564 /** 3565 * @} 3566 */ 3567 3568 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3569 * @{ 3570 */ 3571 3572 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3573 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3574 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3575 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3576 3577 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3578 3579 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3580 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3581 3582 /** 3583 * @} 3584 */ 3585 3586 3587 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3588 * @{ 3589 */ 3590 3591 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3592 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3593 #define __USART_ENABLE __HAL_USART_ENABLE 3594 #define __USART_DISABLE __HAL_USART_DISABLE 3595 3596 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3597 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3598 3599 /** 3600 * @} 3601 */ 3602 3603 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3604 * @{ 3605 */ 3606 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3607 3608 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3609 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3610 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3611 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3612 3613 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3614 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3615 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3616 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3617 3618 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3619 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3620 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3621 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3622 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3623 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3624 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3625 3626 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3627 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3628 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3629 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3630 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3631 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3632 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3633 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3634 3635 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3636 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3637 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3638 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3639 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3640 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3641 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3642 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3643 3644 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3645 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3646 3647 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3648 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3649 /** 3650 * @} 3651 */ 3652 3653 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3654 * @{ 3655 */ 3656 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3657 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3658 3659 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3660 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3661 3662 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3663 3664 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3665 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3666 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3667 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3668 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3669 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3670 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3671 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3672 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3673 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3674 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3675 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3676 3677 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3678 /** 3679 * @} 3680 */ 3681 3682 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3683 * @{ 3684 */ 3685 3686 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3687 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3688 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3689 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3690 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3691 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3692 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3693 3694 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3695 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3696 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3697 /** 3698 * @} 3699 */ 3700 3701 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3702 * @{ 3703 */ 3704 #define __HAL_LTDC_LAYER LTDC_LAYER 3705 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3706 /** 3707 * @} 3708 */ 3709 3710 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3711 * @{ 3712 */ 3713 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3714 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3715 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3716 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3717 #define SAI_STREOMODE SAI_STEREOMODE 3718 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3719 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3720 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3721 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3722 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3723 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3724 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3725 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3726 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3727 /** 3728 * @} 3729 */ 3730 3731 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3732 * @{ 3733 */ 3734 #if defined(STM32H7) 3735 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3736 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3737 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3738 #endif 3739 /** 3740 * @} 3741 */ 3742 3743 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3744 * @{ 3745 */ 3746 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3747 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3748 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3749 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3750 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3751 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3752 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3753 #endif 3754 /** 3755 * @} 3756 */ 3757 3758 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3759 * @{ 3760 */ 3761 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3762 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3763 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3764 /** 3765 * @} 3766 */ 3767 3768 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3769 * @{ 3770 */ 3771 3772 /** 3773 * @} 3774 */ 3775 3776 #ifdef __cplusplus 3777 } 3778 #endif 3779 3780 #endif /* STM32_HAL_LEGACY */ 3781 3782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3783 3784
