1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f0xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27 /** @addtogroup STM32F0xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @defgroup RCC_LL RCC
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39
40 /* Private constants ---------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /** @addtogroup RCC_LL_Private_Macros
43 * @{
44 */
45 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
46 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
49 #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
50 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
52 #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
53 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
55 #else
56 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
57 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
58
59 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
60
61 #if defined(USB)
62 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
63 #endif /* USB */
64
65 #if defined(CEC)
66 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
67 #endif /* CEC */
68
69 /**
70 * @}
71 */
72
73 /* Private function prototypes -----------------------------------------------*/
74 /** @defgroup RCC_LL_Private_Functions RCC Private functions
75 * @{
76 */
77 uint32_t RCC_GetSystemClockFreq(void);
78 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
79 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
80 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
81 /**
82 * @}
83 */
84
85
86 /* Exported functions --------------------------------------------------------*/
87 /** @addtogroup RCC_LL_Exported_Functions
88 * @{
89 */
90
91 /** @addtogroup RCC_LL_EF_Init
92 * @{
93 */
94
95 /**
96 * @brief Reset the RCC clock configuration to the default reset state.
97 * @note The default reset state of the clock configuration is given below:
98 * - HSI ON and used as system clock source
99 * - HSE and PLL OFF
100 * - AHB and APB1 prescaler set to 1.
101 * - CSS, MCO OFF
102 * - All interrupts disabled
103 * @note This function doesn't modify the configuration of the
104 * - Peripheral clocks
105 * - LSI, LSE and RTC clocks
106 * @retval An ErrorStatus enumeration value:
107 * - SUCCESS: RCC registers are de-initialized
108 * - ERROR: not applicable
109 */
LL_RCC_DeInit(void)110 ErrorStatus LL_RCC_DeInit(void)
111 {
112 __IO uint32_t vl_mask;
113
114 /* Set HSION bit */
115 LL_RCC_HSI_Enable();
116
117 /* Wait for HSI READY bit */
118 while(LL_RCC_HSI_IsReady() != 1U)
119 {}
120
121 /* Set HSITRIM bits to the reset value*/
122 LL_RCC_HSI_SetCalibTrimming(0x10U);
123
124 /* Reset SW, HPRE, PPRE and MCOSEL bits */
125 vl_mask = 0xFFFFFFFFU;
126 CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
127
128 /* Write new value in CFGR register */
129 LL_RCC_WriteReg(CFGR, vl_mask);
130
131 /* Wait till system clock source is ready */
132 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
133 {}
134
135 /* Read CR register */
136 vl_mask = LL_RCC_ReadReg(CR);
137
138 /* Reset HSEON, CSSON, PLLON bits */
139 CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
140
141 /* Write new value in CR register */
142 LL_RCC_WriteReg(CR, vl_mask);
143
144 /* Wait for PLL READY bit to be reset */
145 while(LL_RCC_PLL_IsReady() != 0U)
146 {}
147
148 /* Reset HSEBYP bit */
149 LL_RCC_HSE_DisableBypass();
150
151 /* Reset CFGR register */
152 LL_RCC_WriteReg(CFGR, 0x00000000U);
153
154 #if defined(RCC_HSI48_SUPPORT)
155 /* Reset CR2 register */
156 LL_RCC_WriteReg(CR2, 0x00000000U);
157
158 /* Disable HSI48 */
159 LL_RCC_HSI48_Disable();
160
161 #endif /*RCC_HSI48_SUPPORT*/
162 /* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/
163 LL_RCC_HSI14_SetCalibTrimming(0x10U);
164 LL_RCC_HSI14_Disable();
165 LL_RCC_HSI14_EnableADCControl();
166
167 /* Reset CFGR2 register */
168 LL_RCC_WriteReg(CFGR2, 0x00000000U);
169
170 /* Reset CFGR3 register */
171 LL_RCC_WriteReg(CFGR3, 0x00000000U);
172
173 /* Clear pending flags */
174 #if defined(RCC_HSI48_SUPPORT)
175 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
176 LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
177 #else
178 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
179 LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
180 #endif /* RCC_HSI48_SUPPORT */
181
182 /* Write new value in CIR register */
183 LL_RCC_WriteReg(CIR, vl_mask);
184
185 /* Disable all interrupts */
186 LL_RCC_WriteReg(CIR, 0x00000000U);
187
188 /* Clear reset flags */
189 LL_RCC_ClearResetFlags();
190
191 return SUCCESS;
192 }
193
194 /**
195 * @}
196 */
197
198 /** @addtogroup RCC_LL_EF_Get_Freq
199 * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
200 * and different peripheral clocks available on the device.
201 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
202 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
203 * @note If SYSCLK source is PLL, function returns values based on
204 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
205 * @note (**) HSI_VALUE is a defined constant but the real value may vary
206 * depending on the variations in voltage and temperature.
207 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
208 * HSE_VALUE is same as the real frequency of the crystal used.
209 * Otherwise, this function may have wrong result.
210 * @note The result of this function could be incorrect when using fractional
211 * value for HSE crystal.
212 * @note This function can be used by the user application to compute the
213 * baud-rate for the communication peripherals or configure other parameters.
214 * @{
215 */
216
217 /**
218 * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
219 * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
220 * must be called to update structure fields. Otherwise, any
221 * configuration based on this function will be incorrect.
222 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
223 * @retval None
224 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)225 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
226 {
227 /* Get SYSCLK frequency */
228 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
229
230 /* HCLK clock frequency */
231 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
232
233 /* PCLK1 clock frequency */
234 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
235 }
236
237 /**
238 * @brief Return USARTx clock frequency
239 * @param USARTxSource This parameter can be one of the following values:
240 * @arg @ref LL_RCC_USART1_CLKSOURCE
241 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
242 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
243 *
244 * (*) value not defined in all devices.
245 * @retval USART clock frequency (in Hz)
246 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
247 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)248 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
249 {
250 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
251
252 /* Check parameter */
253 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
254 #if defined(RCC_CFGR3_USART1SW)
255 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
256 {
257 /* USART1CLK clock frequency */
258 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
259 {
260 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
261 usart_frequency = RCC_GetSystemClockFreq();
262 break;
263
264 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
265 if (LL_RCC_HSI_IsReady())
266 {
267 usart_frequency = HSI_VALUE;
268 }
269 break;
270
271 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
272 if (LL_RCC_LSE_IsReady())
273 {
274 usart_frequency = LSE_VALUE;
275 }
276 break;
277
278 case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
279 default:
280 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
281 break;
282 }
283 }
284 #endif /* RCC_CFGR3_USART1SW */
285
286 #if defined(RCC_CFGR3_USART2SW)
287 if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
288 {
289 /* USART2CLK clock frequency */
290 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
291 {
292 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
293 usart_frequency = RCC_GetSystemClockFreq();
294 break;
295
296 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
297 if (LL_RCC_HSI_IsReady())
298 {
299 usart_frequency = HSI_VALUE;
300 }
301 break;
302
303 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
304 if (LL_RCC_LSE_IsReady())
305 {
306 usart_frequency = LSE_VALUE;
307 }
308 break;
309
310 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
311 default:
312 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
313 break;
314 }
315 }
316 #endif /* RCC_CFGR3_USART2SW */
317
318 #if defined(RCC_CFGR3_USART3SW)
319 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
320 {
321 /* USART3CLK clock frequency */
322 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
323 {
324 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
325 usart_frequency = RCC_GetSystemClockFreq();
326 break;
327
328 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
329 if (LL_RCC_HSI_IsReady())
330 {
331 usart_frequency = HSI_VALUE;
332 }
333 break;
334
335 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
336 if (LL_RCC_LSE_IsReady())
337 {
338 usart_frequency = LSE_VALUE;
339 }
340 break;
341
342 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
343 default:
344 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
345 break;
346 }
347 }
348
349 #endif /* RCC_CFGR3_USART3SW */
350 return usart_frequency;
351 }
352
353 /**
354 * @brief Return I2Cx clock frequency
355 * @param I2CxSource This parameter can be one of the following values:
356 * @arg @ref LL_RCC_I2C1_CLKSOURCE
357 * @retval I2C clock frequency (in Hz)
358 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
359 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)360 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
361 {
362 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
363
364 /* Check parameter */
365 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
366
367 /* I2C1 CLK clock frequency */
368 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
369 {
370 switch (LL_RCC_GetI2CClockSource(I2CxSource))
371 {
372 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
373 i2c_frequency = RCC_GetSystemClockFreq();
374 break;
375
376 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
377 default:
378 if (LL_RCC_HSI_IsReady())
379 {
380 i2c_frequency = HSI_VALUE;
381 }
382 break;
383 }
384 }
385
386 return i2c_frequency;
387 }
388
389 #if defined(USB)
390 /**
391 * @brief Return USBx clock frequency
392 * @param USBxSource This parameter can be one of the following values:
393 * @arg @ref LL_RCC_USB_CLKSOURCE
394 * @retval USB clock frequency (in Hz)
395 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
396 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
397 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)398 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
399 {
400 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
401
402 /* Check parameter */
403 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
404
405 /* USBCLK clock frequency */
406 switch (LL_RCC_GetUSBClockSource(USBxSource))
407 {
408 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
409 if (LL_RCC_PLL_IsReady())
410 {
411 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
412 }
413 break;
414
415 #if defined(RCC_CFGR3_USBSW_HSI48)
416 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
417 default:
418 if (LL_RCC_HSI48_IsReady())
419 {
420 usb_frequency = HSI48_VALUE;
421 }
422 break;
423 #else
424 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
425 default:
426 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
427 break;
428 #endif /* RCC_CFGR3_USBSW_HSI48 */
429 }
430
431 return usb_frequency;
432 }
433 #endif /* USB */
434
435 #if defined(CEC)
436 /**
437 * @brief Return CECx clock frequency
438 * @param CECxSource This parameter can be one of the following values:
439 * @arg @ref LL_RCC_CEC_CLKSOURCE
440 * @retval CEC clock frequency (in Hz)
441 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
442 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)443 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
444 {
445 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
446
447 /* Check parameter */
448 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
449
450 /* CECCLK clock frequency */
451 switch (LL_RCC_GetCECClockSource(CECxSource))
452 {
453 case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
454 if (LL_RCC_HSI_IsReady())
455 {
456 cec_frequency = HSI_VALUE / 244U;
457 }
458 break;
459
460 case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
461 default:
462 if (LL_RCC_LSE_IsReady())
463 {
464 cec_frequency = LSE_VALUE;
465 }
466 break;
467 }
468
469 return cec_frequency;
470 }
471 #endif /* CEC */
472
473 /**
474 * @}
475 */
476
477 /**
478 * @}
479 */
480
481 /** @addtogroup RCC_LL_Private_Functions
482 * @{
483 */
484
485 /**
486 * @brief Return SYSTEM clock frequency
487 * @retval SYSTEM clock frequency (in Hz)
488 */
RCC_GetSystemClockFreq(void)489 uint32_t RCC_GetSystemClockFreq(void)
490 {
491 uint32_t frequency = 0U;
492
493 /* Get SYSCLK source -------------------------------------------------------*/
494 switch (LL_RCC_GetSysClkSource())
495 {
496 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
497 frequency = HSI_VALUE;
498 break;
499
500 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
501 frequency = HSE_VALUE;
502 break;
503
504 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
505 frequency = RCC_PLL_GetFreqDomain_SYS();
506 break;
507
508 #if defined(RCC_HSI48_SUPPORT)
509 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */
510 frequency = HSI48_VALUE;
511 break;
512 #endif /* RCC_HSI48_SUPPORT */
513
514 default:
515 frequency = HSI_VALUE;
516 break;
517 }
518
519 return frequency;
520 }
521
522 /**
523 * @brief Return HCLK clock frequency
524 * @param SYSCLK_Frequency SYSCLK clock frequency
525 * @retval HCLK clock frequency (in Hz)
526 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)527 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
528 {
529 /* HCLK clock frequency */
530 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
531 }
532
533 /**
534 * @brief Return PCLK1 clock frequency
535 * @param HCLK_Frequency HCLK clock frequency
536 * @retval PCLK1 clock frequency (in Hz)
537 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)538 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
539 {
540 /* PCLK1 clock frequency */
541 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
542 }
543 /**
544 * @brief Return PLL clock frequency used for system domain
545 * @retval PLL clock frequency (in Hz)
546 */
RCC_PLL_GetFreqDomain_SYS(void)547 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
548 {
549 uint32_t pllinputfreq = 0U, pllsource = 0U;
550
551 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
552
553 /* Get PLL source */
554 pllsource = LL_RCC_PLL_GetMainSource();
555
556 switch (pllsource)
557 {
558 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
559 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
560 pllinputfreq = HSI_VALUE;
561 #else
562 case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
563 pllinputfreq = HSI_VALUE / 2U;
564 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
565 break;
566
567 #if defined(RCC_HSI48_SUPPORT)
568 case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */
569 pllinputfreq = HSI48_VALUE;
570 break;
571 #endif /* RCC_HSI48_SUPPORT */
572
573 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
574 pllinputfreq = HSE_VALUE;
575 break;
576
577 default:
578 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
579 pllinputfreq = HSI_VALUE;
580 #else
581 pllinputfreq = HSI_VALUE / 2U;
582 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
583 break;
584 }
585 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
586 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
587 #else
588 return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
589 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
590 }
591 /**
592 * @}
593 */
594
595 /**
596 * @}
597 */
598
599 #endif /* defined(RCC) */
600
601 /**
602 * @}
603 */
604
605 #endif /* USE_FULL_LL_DRIVER */
606
607
