1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f0xx_ll_dma.h"
23 #include "stm32f0xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup DMA_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
49 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
50
51 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
52 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
53
54 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
55 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
56
57 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
58 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
59
60 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
62 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
63
64 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
66 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
67
68 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
69
70 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
71 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
72 ((__VALUE__) == LL_DMA_REQUEST_1) || \
73 ((__VALUE__) == LL_DMA_REQUEST_2) || \
74 ((__VALUE__) == LL_DMA_REQUEST_3) || \
75 ((__VALUE__) == LL_DMA_REQUEST_4) || \
76 ((__VALUE__) == LL_DMA_REQUEST_5) || \
77 ((__VALUE__) == LL_DMA_REQUEST_6) || \
78 ((__VALUE__) == LL_DMA_REQUEST_7) || \
79 ((__VALUE__) == LL_DMA_REQUEST_8) || \
80 ((__VALUE__) == LL_DMA_REQUEST_9) || \
81 ((__VALUE__) == LL_DMA_REQUEST_10) || \
82 ((__VALUE__) == LL_DMA_REQUEST_11) || \
83 ((__VALUE__) == LL_DMA_REQUEST_12) || \
84 ((__VALUE__) == LL_DMA_REQUEST_13) || \
85 ((__VALUE__) == LL_DMA_REQUEST_14) || \
86 ((__VALUE__) == LL_DMA_REQUEST_15))
87 #endif
88
89 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
90 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
91 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
92 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
93
94 #if defined (DMA2)
95 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
96 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
97 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
98 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
99 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
100 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
101 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
102 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
103 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
104 (((INSTANCE) == DMA2) && \
105 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
106 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
107 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
108 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
109 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
110 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
111 ((CHANNEL) == LL_DMA_CHANNEL_7))))
112 #else
113 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
114 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
115 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
116 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
117 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
118 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
119 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
120 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
121 (((INSTANCE) == DMA2) && \
122 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
123 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
124 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
125 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
126 ((CHANNEL) == LL_DMA_CHANNEL_5))))
127 #endif
128 #else
129 #if defined(DMA1_Channel6) && defined(DMA1_Channel7)
130 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
131 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
132 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
133 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
134 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
135 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
136 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
137 ((CHANNEL) == LL_DMA_CHANNEL_7))))
138 #elif defined (DMA1_Channel6)
139 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
140 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
141 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
142 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
143 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
144 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
145 ((CHANNEL) == LL_DMA_CHANNEL_6))))
146 #else
147 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
148 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
149 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
150 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
151 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
152 ((CHANNEL) == LL_DMA_CHANNEL_5))))
153 #endif /* DMA1_Channel6 && DMA1_Channel7 */
154 #endif
155 /**
156 * @}
157 */
158
159 /* Private function prototypes -----------------------------------------------*/
160
161 /* Exported functions --------------------------------------------------------*/
162 /** @addtogroup DMA_LL_Exported_Functions
163 * @{
164 */
165
166 /** @addtogroup DMA_LL_EF_Init
167 * @{
168 */
169
170 /**
171 * @brief De-initialize the DMA registers to their default reset values.
172 * @param DMAx DMAx Instance
173 * @param Channel This parameter can be one of the following values:
174 * @arg @ref LL_DMA_CHANNEL_1
175 * @arg @ref LL_DMA_CHANNEL_2
176 * @arg @ref LL_DMA_CHANNEL_3
177 * @arg @ref LL_DMA_CHANNEL_4
178 * @arg @ref LL_DMA_CHANNEL_5
179 * @arg @ref LL_DMA_CHANNEL_6 (*)
180 * @arg @ref LL_DMA_CHANNEL_7 (*)
181 *
182 * (*) value not defined in all devices
183 * @retval An ErrorStatus enumeration value:
184 * - SUCCESS: DMA registers are de-initialized
185 * - ERROR: DMA registers are not de-initialized
186 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)187 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
188 {
189 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
190 ErrorStatus status = SUCCESS;
191
192 /* Check the DMA Instance DMAx and Channel parameters*/
193 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
194
195 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
196
197 /* Disable the selected DMAx_Channely */
198 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
199
200 /* Reset DMAx_Channely control register */
201 LL_DMA_WriteReg(tmp, CCR, 0U);
202
203 /* Reset DMAx_Channely remaining bytes register */
204 LL_DMA_WriteReg(tmp, CNDTR, 0U);
205
206 /* Reset DMAx_Channely peripheral address register */
207 LL_DMA_WriteReg(tmp, CPAR, 0U);
208
209 /* Reset DMAx_Channely memory address register */
210 LL_DMA_WriteReg(tmp, CMAR, 0U);
211
212 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
213 /* Reset Request register field for DMAx Channel */
214 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
215 #endif
216
217 if (Channel == LL_DMA_CHANNEL_1)
218 {
219 /* Reset interrupt pending bits for DMAx Channel1 */
220 LL_DMA_ClearFlag_GI1(DMAx);
221 }
222 else if (Channel == LL_DMA_CHANNEL_2)
223 {
224 /* Reset interrupt pending bits for DMAx Channel2 */
225 LL_DMA_ClearFlag_GI2(DMAx);
226 }
227 else if (Channel == LL_DMA_CHANNEL_3)
228 {
229 /* Reset interrupt pending bits for DMAx Channel3 */
230 LL_DMA_ClearFlag_GI3(DMAx);
231 }
232 else if (Channel == LL_DMA_CHANNEL_4)
233 {
234 /* Reset interrupt pending bits for DMAx Channel4 */
235 LL_DMA_ClearFlag_GI4(DMAx);
236 }
237 else if (Channel == LL_DMA_CHANNEL_5)
238 {
239 /* Reset interrupt pending bits for DMAx Channel5 */
240 LL_DMA_ClearFlag_GI5(DMAx);
241 }
242
243 #if defined(DMA1_Channel6)
244 else if (Channel == LL_DMA_CHANNEL_6)
245 {
246 /* Reset interrupt pending bits for DMAx Channel6 */
247 LL_DMA_ClearFlag_GI6(DMAx);
248 }
249 #endif
250 #if defined(DMA1_Channel7)
251 else if (Channel == LL_DMA_CHANNEL_7)
252 {
253 /* Reset interrupt pending bits for DMAx Channel7 */
254 LL_DMA_ClearFlag_GI7(DMAx);
255 }
256 #endif
257 else
258 {
259 status = ERROR;
260 }
261
262 return status;
263 }
264
265 /**
266 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
267 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
268 * @arg @ref __LL_DMA_GET_INSTANCE
269 * @arg @ref __LL_DMA_GET_CHANNEL
270 * @param DMAx DMAx Instance
271 * @param Channel This parameter can be one of the following values:
272 * @arg @ref LL_DMA_CHANNEL_1
273 * @arg @ref LL_DMA_CHANNEL_2
274 * @arg @ref LL_DMA_CHANNEL_3
275 * @arg @ref LL_DMA_CHANNEL_4
276 * @arg @ref LL_DMA_CHANNEL_5
277 * @arg @ref LL_DMA_CHANNEL_6 (*)
278 * @arg @ref LL_DMA_CHANNEL_7 (*)
279 *
280 * (*) value not defined in all devices
281 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
282 * @retval An ErrorStatus enumeration value:
283 * - SUCCESS: DMA registers are initialized
284 * - ERROR: Not applicable
285 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)286 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
287 {
288 /* Check the DMA Instance DMAx and Channel parameters*/
289 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
290
291 /* Check the DMA parameters from DMA_InitStruct */
292 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
293 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
294 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
295 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
296 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
297 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
298 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
299 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
300 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
301 #endif
302 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
303
304 /*---------------------------- DMAx CCR Configuration ------------------------
305 * Configure DMAx_Channely: data transfer direction, data transfer mode,
306 * peripheral and memory increment mode,
307 * data size alignment and priority level with parameters :
308 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
309 * - Mode: DMA_CCR_CIRC bit
310 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
311 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
312 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
313 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
314 * - Priority: DMA_CCR_PL[1:0] bits
315 */
316 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
317 DMA_InitStruct->Mode | \
318 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
319 DMA_InitStruct->MemoryOrM2MDstIncMode | \
320 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
321 DMA_InitStruct->MemoryOrM2MDstDataSize | \
322 DMA_InitStruct->Priority);
323
324 /*-------------------------- DMAx CMAR Configuration -------------------------
325 * Configure the memory or destination base address with parameter :
326 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
327 */
328 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
329
330 /*-------------------------- DMAx CPAR Configuration -------------------------
331 * Configure the peripheral or source base address with parameter :
332 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
333 */
334 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
335
336 /*--------------------------- DMAx CNDTR Configuration -----------------------
337 * Configure the peripheral base address with parameter :
338 * - NbData: DMA_CNDTR_NDT[15:0] bits
339 */
340 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
341
342 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
343 /*--------------------------- DMAx CSELR Configuration -----------------------
344 * Configure the DMA request for DMA instance on Channel x with parameter :
345 * - PeriphRequest: DMA_CSELR[31:0] bits
346 */
347 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
348 #endif
349
350 return SUCCESS;
351 }
352
353 /**
354 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
355 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
356 * @retval None
357 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)358 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
359 {
360 /* Set DMA_InitStruct fields to default values */
361 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
362 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
363 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
364 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
365 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
366 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
367 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
368 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
369 DMA_InitStruct->NbData = 0x00000000U;
370 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
371 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
372 #endif
373 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
374 }
375
376 /**
377 * @}
378 */
379
380 /**
381 * @}
382 */
383
384 /**
385 * @}
386 */
387
388 #endif /* DMA1 || DMA2 */
389
390 /**
391 * @}
392 */
393
394 #endif /* USE_FULL_LL_DRIVER */
395
396
