1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f0xx_ll_adc.h"
23 #include "stm32f0xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32F0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup ADC_LL_Private_Constants
45 * @{
46 */
47
48 /* Definitions of ADC hardware constraints delays */
49 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
50 /* not timeout values: */
51 /* Timeout values for ADC operations are dependent to device clock */
52 /* configuration (system clock versus ADC clock), */
53 /* and therefore must be defined in user application. */
54 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
55 /* values definition. */
56 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
57 /* of device clock setting. */
58 /* In user application, ADC timeout values should be defined with */
59 /* temporal values, in function of device clock settings. */
60 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
61 /* - ADC clock from synchronous clock with AHB prescaler 512, */
62 /* APB prescaler 16, ADC prescaler 4. */
63 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
64 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
65 /* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
66 /* Unit: CPU cycles. */
67 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
68 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
69 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
70
71 /**
72 * @}
73 */
74
75 /* Private macros ------------------------------------------------------------*/
76
77 /** @addtogroup ADC_LL_Private_Macros
78 * @{
79 */
80
81 /* Check of parameters for configuration of ADC hierarchical scope: */
82 /* common to several ADC instances. */
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* ADC instance. */
85 #define IS_LL_ADC_CLOCK(__CLOCK__) \
86 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
89 )
90
91 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
92 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
93 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
94 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
95 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
96 )
97
98 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
99 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
100 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
101 )
102
103 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
104 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
105 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
106 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
107 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
108 )
109
110 /* Check of parameters for configuration of ADC hierarchical scope: */
111 /* ADC group regular */
112 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
113 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
119 )
120
121 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
122 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
123 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
124 )
125
126 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
127 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
128 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
129 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
130 )
131
132 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
133 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
134 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
135 )
136
137 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
138 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
139 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
140 )
141
142 /**
143 * @}
144 */
145
146
147 /* Private function prototypes -----------------------------------------------*/
148
149 /* Exported functions --------------------------------------------------------*/
150 /** @addtogroup ADC_LL_Exported_Functions
151 * @{
152 */
153
154 /** @addtogroup ADC_LL_EF_Init
155 * @{
156 */
157
158 /**
159 * @brief De-initialize registers of all ADC instances belonging to
160 * the same ADC common instance to their default reset values.
161 * @note This function is performing a hard reset, using high level
162 * clock source RCC ADC reset.
163 * @param ADCxy_COMMON ADC common instance
164 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
165 * @retval An ErrorStatus enumeration value:
166 * - SUCCESS: ADC common registers are de-initialized
167 * - ERROR: not applicable
168 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)169 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
170 {
171 /* Check the parameters */
172 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
173
174 /* Force reset of ADC clock (core clock) */
175 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
176
177 /* Release reset of ADC clock (core clock) */
178 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
179
180 return SUCCESS;
181 }
182
183
184 /**
185 * @brief De-initialize registers of the selected ADC instance
186 * to their default reset values.
187 * @note To reset all ADC instances quickly (perform a hard reset),
188 * use function @ref LL_ADC_CommonDeInit().
189 * @note If this functions returns error status, it means that ADC instance
190 * is in an unknown state.
191 * In this case, perform a hard reset using high level
192 * clock source RCC ADC reset.
193 * Refer to function @ref LL_ADC_CommonDeInit().
194 * @param ADCx ADC instance
195 * @retval An ErrorStatus enumeration value:
196 * - SUCCESS: ADC registers are de-initialized
197 * - ERROR: ADC registers are not de-initialized
198 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)199 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
200 {
201 ErrorStatus status = SUCCESS;
202
203 __IO uint32_t timeout_cpu_cycles = 0U;
204
205 /* Check the parameters */
206 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
207
208 /* Disable ADC instance if not already disabled. */
209 if(LL_ADC_IsEnabled(ADCx) == 1U)
210 {
211 /* Set ADC group regular trigger source to SW start to ensure to not */
212 /* have an external trigger event occurring during the conversion stop */
213 /* ADC disable process. */
214 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
215
216 /* Stop potential ADC conversion on going on ADC group regular. */
217 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
218 {
219 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
220 {
221 LL_ADC_REG_StopConversion(ADCx);
222 }
223 }
224
225 /* Wait for ADC conversions are effectively stopped */
226 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
227 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
228 {
229 if(timeout_cpu_cycles-- == 0U)
230 {
231 /* Time-out error */
232 status = ERROR;
233 }
234 }
235
236 /* Disable the ADC instance */
237 LL_ADC_Disable(ADCx);
238
239 /* Wait for ADC instance is effectively disabled */
240 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
241 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
242 {
243 if(timeout_cpu_cycles-- == 0U)
244 {
245 /* Time-out error */
246 status = ERROR;
247 }
248 }
249 }
250
251 /* Check whether ADC state is compliant with expected state */
252 if(READ_BIT(ADCx->CR,
253 ( ADC_CR_ADSTP | ADC_CR_ADSTART
254 | ADC_CR_ADDIS | ADC_CR_ADEN )
255 )
256 == 0U)
257 {
258 /* ========== Reset ADC registers ========== */
259 /* Reset register IER */
260 CLEAR_BIT(ADCx->IER,
261 ( LL_ADC_IT_ADRDY
262 | LL_ADC_IT_EOC
263 | LL_ADC_IT_EOS
264 | LL_ADC_IT_OVR
265 | LL_ADC_IT_EOSMP
266 | LL_ADC_IT_AWD1 )
267 );
268
269 /* Reset register ISR */
270 SET_BIT(ADCx->ISR,
271 ( LL_ADC_FLAG_ADRDY
272 | LL_ADC_FLAG_EOC
273 | LL_ADC_FLAG_EOS
274 | LL_ADC_FLAG_OVR
275 | LL_ADC_FLAG_EOSMP
276 | LL_ADC_FLAG_AWD1 )
277 );
278
279 /* Reset register CR */
280 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
281 /* "read-set": no direct reset applicable. */
282 /* No action on register CR */
283
284 /* Reset register CFGR1 */
285 CLEAR_BIT(ADCx->CFGR1,
286 ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
287 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
288 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
289 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
290 );
291
292 /* Reset register CFGR2 */
293 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
294 /* already done above. */
295 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
296
297 /* Reset register SMPR */
298 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
299
300 /* Reset register TR */
301 MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
302
303 /* Reset register CHSELR */
304 #if defined(ADC_CCR_VBATEN)
305 CLEAR_BIT(ADCx->CHSELR,
306 ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
307 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
308 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
309 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
310 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
311 );
312 #else
313 CLEAR_BIT(ADCx->CHSELR,
314 ( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
315 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
316 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
317 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
318 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
319 );
320 #endif
321
322 /* Reset register DR */
323 /* bits in access mode read only, no direct reset applicable */
324
325 }
326 else
327 {
328 /* ADC instance is in an unknown state */
329 /* Need to performing a hard reset of ADC instance, using high level */
330 /* clock source RCC ADC reset. */
331 /* Caution: On this STM32 series, if several ADC instances are available */
332 /* on the selected device, RCC ADC reset will reset */
333 /* all ADC instances belonging to the common ADC instance. */
334 status = ERROR;
335 }
336
337 return status;
338 }
339
340 /**
341 * @brief Initialize some features of ADC instance.
342 * @note These parameters have an impact on ADC scope: ADC instance.
343 * Refer to corresponding unitary functions into
344 * @ref ADC_LL_EF_Configuration_ADC_Instance .
345 * @note The setting of these parameters by function @ref LL_ADC_Init()
346 * is conditioned to ADC state:
347 * ADC instance must be disabled.
348 * This condition is applied to all ADC features, for efficiency
349 * and compatibility over all STM32 families. However, the different
350 * features can be set under different ADC state conditions
351 * (setting possible with ADC enabled without conversion on going,
352 * ADC enabled with conversion on going, ...)
353 * Each feature can be updated afterwards with a unitary function
354 * and potentially with ADC in a different state than disabled,
355 * refer to description of each function for setting
356 * conditioned to ADC state.
357 * @note After using this function, some other features must be configured
358 * using LL unitary functions.
359 * The minimum configuration remaining to be done is:
360 * - Set ADC group regular sequencer:
361 * map channel on rank corresponding to channel number.
362 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
363 * - Set ADC channel sampling time
364 * Refer to function LL_ADC_SetChannelSamplingTime();
365 * @param ADCx ADC instance
366 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
367 * @retval An ErrorStatus enumeration value:
368 * - SUCCESS: ADC registers are initialized
369 * - ERROR: ADC registers are not initialized
370 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)371 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
372 {
373 ErrorStatus status = SUCCESS;
374
375 /* Check the parameters */
376 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
377
378 assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
379 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
380 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
381 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
382
383 /* Note: Hardware constraint (refer to description of this function): */
384 /* ADC instance must be disabled. */
385 if(LL_ADC_IsEnabled(ADCx) == 0U)
386 {
387 /* Configuration of ADC hierarchical scope: */
388 /* - ADC instance */
389 /* - Set ADC data resolution */
390 /* - Set ADC conversion data alignment */
391 /* - Set ADC low power mode */
392 MODIFY_REG(ADCx->CFGR1,
393 ADC_CFGR1_RES
394 | ADC_CFGR1_ALIGN
395 | ADC_CFGR1_WAIT
396 | ADC_CFGR1_AUTOFF
397 ,
398 ADC_InitStruct->Resolution
399 | ADC_InitStruct->DataAlignment
400 | ADC_InitStruct->LowPowerMode
401 );
402
403 MODIFY_REG(ADCx->CFGR2,
404 ADC_CFGR2_CKMODE
405 ,
406 ADC_InitStruct->Clock
407 );
408 }
409 else
410 {
411 /* Initialization error: ADC instance is not disabled. */
412 status = ERROR;
413 }
414 return status;
415 }
416
417 /**
418 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
419 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
420 * whose fields will be set to default values.
421 * @retval None
422 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)423 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
424 {
425 /* Set ADC_InitStruct fields to default values */
426 /* Set fields of ADC instance */
427 ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
428 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
429 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
430 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
431
432 }
433
434 /**
435 * @brief Initialize some features of ADC group regular.
436 * @note These parameters have an impact on ADC scope: ADC group regular.
437 * Refer to corresponding unitary functions into
438 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
439 * (functions with prefix "REG").
440 * @note The setting of these parameters by function @ref LL_ADC_Init()
441 * is conditioned to ADC state:
442 * ADC instance must be disabled.
443 * This condition is applied to all ADC features, for efficiency
444 * and compatibility over all STM32 families. However, the different
445 * features can be set under different ADC state conditions
446 * (setting possible with ADC enabled without conversion on going,
447 * ADC enabled with conversion on going, ...)
448 * Each feature can be updated afterwards with a unitary function
449 * and potentially with ADC in a different state than disabled,
450 * refer to description of each function for setting
451 * conditioned to ADC state.
452 * @note After using this function, other features must be configured
453 * using LL unitary functions.
454 * The minimum configuration remaining to be done is:
455 * - Set ADC group regular sequencer:
456 * map channel on rank corresponding to channel number.
457 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
458 * - Set ADC channel sampling time
459 * Refer to function LL_ADC_SetChannelSamplingTime();
460 * @param ADCx ADC instance
461 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
462 * @retval An ErrorStatus enumeration value:
463 * - SUCCESS: ADC registers are initialized
464 * - ERROR: ADC registers are not initialized
465 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)466 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
467 {
468 ErrorStatus status = SUCCESS;
469
470 /* Check the parameters */
471 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
472 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
473 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
474 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
475 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
476 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
477
478 /* ADC group regular continuous mode and discontinuous mode */
479 /* can not be enabled simultenaeously */
480 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
481 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
482
483 /* Note: Hardware constraint (refer to description of this function): */
484 /* ADC instance must be disabled. */
485 if(LL_ADC_IsEnabled(ADCx) == 0U)
486 {
487 /* Configuration of ADC hierarchical scope: */
488 /* - ADC group regular */
489 /* - Set ADC group regular trigger source */
490 /* - Set ADC group regular sequencer discontinuous mode */
491 /* - Set ADC group regular continuous mode */
492 /* - Set ADC group regular conversion data transfer: no transfer or */
493 /* transfer by DMA, and DMA requests mode */
494 /* - Set ADC group regular overrun behavior */
495 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
496 /* setting of trigger source to SW start. */
497 MODIFY_REG(ADCx->CFGR1,
498 ADC_CFGR1_EXTSEL
499 | ADC_CFGR1_EXTEN
500 | ADC_CFGR1_DISCEN
501 | ADC_CFGR1_CONT
502 | ADC_CFGR1_DMAEN
503 | ADC_CFGR1_DMACFG
504 | ADC_CFGR1_OVRMOD
505 ,
506 ADC_REG_InitStruct->TriggerSource
507 | ADC_REG_InitStruct->SequencerDiscont
508 | ADC_REG_InitStruct->ContinuousMode
509 | ADC_REG_InitStruct->DMATransfer
510 | ADC_REG_InitStruct->Overrun
511 );
512
513 }
514 else
515 {
516 /* Initialization error: ADC instance is not disabled. */
517 status = ERROR;
518 }
519 return status;
520 }
521
522 /**
523 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
524 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
525 * whose fields will be set to default values.
526 * @retval None
527 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)528 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
529 {
530 /* Set ADC_REG_InitStruct fields to default values */
531 /* Set fields of ADC group regular */
532 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
533 /* setting of trigger source to SW start. */
534 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
535 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
536 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
537 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
538 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
539 }
540
541 /**
542 * @}
543 */
544
545 /**
546 * @}
547 */
548
549 /**
550 * @}
551 */
552
553 #endif /* ADC1 */
554
555 /**
556 * @}
557 */
558
559 #endif /* USE_FULL_LL_DRIVER */
560
561
