1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156
157 [..]
158 By default, after the Init and when the state is HAL_TIM_STATE_RESET
159 all interrupt callbacks are set to the corresponding weak functions:
160 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
161
162 [..]
163 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
164 functionalities in the Init / DeInit only when these callbacks are null
165 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
166 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
167
168 [..]
169 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
170 Exception done MspInit / MspDeInit that can be registered / unregistered
171 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
172 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
173 In that case first register the MspInit/MspDeInit user callbacks
174 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
175
176 [..]
177 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
178 not defined, the callback registration feature is not available and all callbacks
179 are set to the corresponding weak functions.
180
181 @endverbatim
182 ******************************************************************************
183 */
184
185 /* Includes ------------------------------------------------------------------*/
186 #include "stm32f0xx_hal.h"
187
188 /** @addtogroup STM32F0xx_HAL_Driver
189 * @{
190 */
191
192 /** @defgroup TIM TIM
193 * @brief TIM HAL module driver
194 * @{
195 */
196
197 #ifdef HAL_TIM_MODULE_ENABLED
198
199 /* Private typedef -----------------------------------------------------------*/
200 /* Private define ------------------------------------------------------------*/
201 /* Private macros ------------------------------------------------------------*/
202 /* Private variables ---------------------------------------------------------*/
203 /* Private function prototypes -----------------------------------------------*/
204 /** @addtogroup TIM_Private_Functions
205 * @{
206 */
207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
211 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
212 uint32_t TIM_ICFilter);
213 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
217 uint32_t TIM_ICFilter);
218 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
219 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
220 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
221 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
224 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
225 const TIM_SlaveConfigTypeDef *sSlaveConfig);
226 /**
227 * @}
228 */
229 /* Exported functions --------------------------------------------------------*/
230
231 /** @defgroup TIM_Exported_Functions TIM Exported Functions
232 * @{
233 */
234
235 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
236 * @brief Time Base functions
237 *
238 @verbatim
239 ==============================================================================
240 ##### Time Base functions #####
241 ==============================================================================
242 [..]
243 This section provides functions allowing to:
244 (+) Initialize and configure the TIM base.
245 (+) De-initialize the TIM base.
246 (+) Start the Time Base.
247 (+) Stop the Time Base.
248 (+) Start the Time Base and enable interrupt.
249 (+) Stop the Time Base and disable interrupt.
250 (+) Start the Time Base and enable DMA transfer.
251 (+) Stop the Time Base and disable DMA transfer.
252
253 @endverbatim
254 * @{
255 */
256 /**
257 * @brief Initializes the TIM Time base Unit according to the specified
258 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
259 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
260 * requires a timer reset to avoid unexpected direction
261 * due to DIR bit readonly in center aligned mode.
262 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
263 * @param htim TIM Base handle
264 * @retval HAL status
265 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)266 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
267 {
268 /* Check the TIM handle allocation */
269 if (htim == NULL)
270 {
271 return HAL_ERROR;
272 }
273
274 /* Check the parameters */
275 assert_param(IS_TIM_INSTANCE(htim->Instance));
276 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
277 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
278 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
279 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
280
281 if (htim->State == HAL_TIM_STATE_RESET)
282 {
283 /* Allocate lock resource and initialize it */
284 htim->Lock = HAL_UNLOCKED;
285
286 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
287 /* Reset interrupt callbacks to legacy weak callbacks */
288 TIM_ResetCallback(htim);
289
290 if (htim->Base_MspInitCallback == NULL)
291 {
292 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
293 }
294 /* Init the low level hardware : GPIO, CLOCK, NVIC */
295 htim->Base_MspInitCallback(htim);
296 #else
297 /* Init the low level hardware : GPIO, CLOCK, NVIC */
298 HAL_TIM_Base_MspInit(htim);
299 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
300 }
301
302 /* Set the TIM state */
303 htim->State = HAL_TIM_STATE_BUSY;
304
305 /* Set the Time Base configuration */
306 TIM_Base_SetConfig(htim->Instance, &htim->Init);
307
308 /* Initialize the DMA burst operation state */
309 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
310
311 /* Initialize the TIM channels state */
312 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
313 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
314
315 /* Initialize the TIM state*/
316 htim->State = HAL_TIM_STATE_READY;
317
318 return HAL_OK;
319 }
320
321 /**
322 * @brief DeInitializes the TIM Base peripheral
323 * @param htim TIM Base handle
324 * @retval HAL status
325 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)326 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
327 {
328 /* Check the parameters */
329 assert_param(IS_TIM_INSTANCE(htim->Instance));
330
331 htim->State = HAL_TIM_STATE_BUSY;
332
333 /* Disable the TIM Peripheral Clock */
334 __HAL_TIM_DISABLE(htim);
335
336 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
337 if (htim->Base_MspDeInitCallback == NULL)
338 {
339 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
340 }
341 /* DeInit the low level hardware */
342 htim->Base_MspDeInitCallback(htim);
343 #else
344 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
345 HAL_TIM_Base_MspDeInit(htim);
346 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
347
348 /* Change the DMA burst operation state */
349 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
350
351 /* Change the TIM channels state */
352 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
353 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
354
355 /* Change TIM state */
356 htim->State = HAL_TIM_STATE_RESET;
357
358 /* Release Lock */
359 __HAL_UNLOCK(htim);
360
361 return HAL_OK;
362 }
363
364 /**
365 * @brief Initializes the TIM Base MSP.
366 * @param htim TIM Base handle
367 * @retval None
368 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)369 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
370 {
371 /* Prevent unused argument(s) compilation warning */
372 UNUSED(htim);
373
374 /* NOTE : This function should not be modified, when the callback is needed,
375 the HAL_TIM_Base_MspInit could be implemented in the user file
376 */
377 }
378
379 /**
380 * @brief DeInitializes TIM Base MSP.
381 * @param htim TIM Base handle
382 * @retval None
383 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
385 {
386 /* Prevent unused argument(s) compilation warning */
387 UNUSED(htim);
388
389 /* NOTE : This function should not be modified, when the callback is needed,
390 the HAL_TIM_Base_MspDeInit could be implemented in the user file
391 */
392 }
393
394
395 /**
396 * @brief Starts the TIM Base generation.
397 * @param htim TIM Base handle
398 * @retval HAL status
399 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)400 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
401 {
402 uint32_t tmpsmcr;
403
404 /* Check the parameters */
405 assert_param(IS_TIM_INSTANCE(htim->Instance));
406
407 /* Check the TIM state */
408 if (htim->State != HAL_TIM_STATE_READY)
409 {
410 return HAL_ERROR;
411 }
412
413 /* Set the TIM state */
414 htim->State = HAL_TIM_STATE_BUSY;
415
416 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
417 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
418 {
419 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
420 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
421 {
422 __HAL_TIM_ENABLE(htim);
423 }
424 }
425 else
426 {
427 __HAL_TIM_ENABLE(htim);
428 }
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Stops the TIM Base generation.
436 * @param htim TIM Base handle
437 * @retval HAL status
438 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)439 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
440 {
441 /* Check the parameters */
442 assert_param(IS_TIM_INSTANCE(htim->Instance));
443
444 /* Disable the Peripheral */
445 __HAL_TIM_DISABLE(htim);
446
447 /* Set the TIM state */
448 htim->State = HAL_TIM_STATE_READY;
449
450 /* Return function status */
451 return HAL_OK;
452 }
453
454 /**
455 * @brief Starts the TIM Base generation in interrupt mode.
456 * @param htim TIM Base handle
457 * @retval HAL status
458 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)459 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
460 {
461 uint32_t tmpsmcr;
462
463 /* Check the parameters */
464 assert_param(IS_TIM_INSTANCE(htim->Instance));
465
466 /* Check the TIM state */
467 if (htim->State != HAL_TIM_STATE_READY)
468 {
469 return HAL_ERROR;
470 }
471
472 /* Set the TIM state */
473 htim->State = HAL_TIM_STATE_BUSY;
474
475 /* Enable the TIM Update interrupt */
476 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
477
478 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
479 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
480 {
481 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
482 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
483 {
484 __HAL_TIM_ENABLE(htim);
485 }
486 }
487 else
488 {
489 __HAL_TIM_ENABLE(htim);
490 }
491
492 /* Return function status */
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Stops the TIM Base generation in interrupt mode.
498 * @param htim TIM Base handle
499 * @retval HAL status
500 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)501 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
502 {
503 /* Check the parameters */
504 assert_param(IS_TIM_INSTANCE(htim->Instance));
505
506 /* Disable the TIM Update interrupt */
507 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
508
509 /* Disable the Peripheral */
510 __HAL_TIM_DISABLE(htim);
511
512 /* Set the TIM state */
513 htim->State = HAL_TIM_STATE_READY;
514
515 /* Return function status */
516 return HAL_OK;
517 }
518
519 /**
520 * @brief Starts the TIM Base generation in DMA mode.
521 * @param htim TIM Base handle
522 * @param pData The source Buffer address.
523 * @param Length The length of data to be transferred from memory to peripheral.
524 * @retval HAL status
525 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)526 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
527 {
528 uint32_t tmpsmcr;
529
530 /* Check the parameters */
531 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
532
533 /* Set the TIM state */
534 if (htim->State == HAL_TIM_STATE_BUSY)
535 {
536 return HAL_BUSY;
537 }
538 else if (htim->State == HAL_TIM_STATE_READY)
539 {
540 if ((pData == NULL) || (Length == 0U))
541 {
542 return HAL_ERROR;
543 }
544 else
545 {
546 htim->State = HAL_TIM_STATE_BUSY;
547 }
548 }
549 else
550 {
551 return HAL_ERROR;
552 }
553
554 /* Set the DMA Period elapsed callbacks */
555 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
556 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
557
558 /* Set the DMA error callback */
559 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
560
561 /* Enable the DMA channel */
562 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
563 Length) != HAL_OK)
564 {
565 /* Return error status */
566 return HAL_ERROR;
567 }
568
569 /* Enable the TIM Update DMA request */
570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
571
572 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
573 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
574 {
575 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
576 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
577 {
578 __HAL_TIM_ENABLE(htim);
579 }
580 }
581 else
582 {
583 __HAL_TIM_ENABLE(htim);
584 }
585
586 /* Return function status */
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Stops the TIM Base generation in DMA mode.
592 * @param htim TIM Base handle
593 * @retval HAL status
594 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)595 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
596 {
597 /* Check the parameters */
598 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
599
600 /* Disable the TIM Update DMA request */
601 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
602
603 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
604
605 /* Disable the Peripheral */
606 __HAL_TIM_DISABLE(htim);
607
608 /* Set the TIM state */
609 htim->State = HAL_TIM_STATE_READY;
610
611 /* Return function status */
612 return HAL_OK;
613 }
614
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
620 * @brief TIM Output Compare functions
621 *
622 @verbatim
623 ==============================================================================
624 ##### TIM Output Compare functions #####
625 ==============================================================================
626 [..]
627 This section provides functions allowing to:
628 (+) Initialize and configure the TIM Output Compare.
629 (+) De-initialize the TIM Output Compare.
630 (+) Start the TIM Output Compare.
631 (+) Stop the TIM Output Compare.
632 (+) Start the TIM Output Compare and enable interrupt.
633 (+) Stop the TIM Output Compare and disable interrupt.
634 (+) Start the TIM Output Compare and enable DMA transfer.
635 (+) Stop the TIM Output Compare and disable DMA transfer.
636
637 @endverbatim
638 * @{
639 */
640 /**
641 * @brief Initializes the TIM Output Compare according to the specified
642 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
643 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
644 * requires a timer reset to avoid unexpected direction
645 * due to DIR bit readonly in center aligned mode.
646 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
647 * @param htim TIM Output Compare handle
648 * @retval HAL status
649 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)650 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
651 {
652 /* Check the TIM handle allocation */
653 if (htim == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_TIM_INSTANCE(htim->Instance));
660 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
661 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
662 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
663 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
664
665 if (htim->State == HAL_TIM_STATE_RESET)
666 {
667 /* Allocate lock resource and initialize it */
668 htim->Lock = HAL_UNLOCKED;
669
670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
671 /* Reset interrupt callbacks to legacy weak callbacks */
672 TIM_ResetCallback(htim);
673
674 if (htim->OC_MspInitCallback == NULL)
675 {
676 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
677 }
678 /* Init the low level hardware : GPIO, CLOCK, NVIC */
679 htim->OC_MspInitCallback(htim);
680 #else
681 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
682 HAL_TIM_OC_MspInit(htim);
683 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
684 }
685
686 /* Set the TIM state */
687 htim->State = HAL_TIM_STATE_BUSY;
688
689 /* Init the base time for the Output Compare */
690 TIM_Base_SetConfig(htim->Instance, &htim->Init);
691
692 /* Initialize the DMA burst operation state */
693 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
694
695 /* Initialize the TIM channels state */
696 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
697 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
698
699 /* Initialize the TIM state*/
700 htim->State = HAL_TIM_STATE_READY;
701
702 return HAL_OK;
703 }
704
705 /**
706 * @brief DeInitializes the TIM peripheral
707 * @param htim TIM Output Compare handle
708 * @retval HAL status
709 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)710 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
711 {
712 /* Check the parameters */
713 assert_param(IS_TIM_INSTANCE(htim->Instance));
714
715 htim->State = HAL_TIM_STATE_BUSY;
716
717 /* Disable the TIM Peripheral Clock */
718 __HAL_TIM_DISABLE(htim);
719
720 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
721 if (htim->OC_MspDeInitCallback == NULL)
722 {
723 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
724 }
725 /* DeInit the low level hardware */
726 htim->OC_MspDeInitCallback(htim);
727 #else
728 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
729 HAL_TIM_OC_MspDeInit(htim);
730 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
731
732 /* Change the DMA burst operation state */
733 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
734
735 /* Change the TIM channels state */
736 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
737 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
738
739 /* Change TIM state */
740 htim->State = HAL_TIM_STATE_RESET;
741
742 /* Release Lock */
743 __HAL_UNLOCK(htim);
744
745 return HAL_OK;
746 }
747
748 /**
749 * @brief Initializes the TIM Output Compare MSP.
750 * @param htim TIM Output Compare handle
751 * @retval None
752 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)753 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
754 {
755 /* Prevent unused argument(s) compilation warning */
756 UNUSED(htim);
757
758 /* NOTE : This function should not be modified, when the callback is needed,
759 the HAL_TIM_OC_MspInit could be implemented in the user file
760 */
761 }
762
763 /**
764 * @brief DeInitializes TIM Output Compare MSP.
765 * @param htim TIM Output Compare handle
766 * @retval None
767 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
769 {
770 /* Prevent unused argument(s) compilation warning */
771 UNUSED(htim);
772
773 /* NOTE : This function should not be modified, when the callback is needed,
774 the HAL_TIM_OC_MspDeInit could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief Starts the TIM Output Compare signal generation.
780 * @param htim TIM Output Compare handle
781 * @param Channel TIM Channel to be enabled
782 * This parameter can be one of the following values:
783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
787 * @retval HAL status
788 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)789 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
790 {
791 uint32_t tmpsmcr;
792
793 /* Check the parameters */
794 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
795
796 /* Check the TIM channel state */
797 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
798 {
799 return HAL_ERROR;
800 }
801
802 /* Set the TIM channel state */
803 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
804
805 /* Enable the Output compare channel */
806 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
807
808 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
809 {
810 /* Enable the main output */
811 __HAL_TIM_MOE_ENABLE(htim);
812 }
813
814 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
815 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
816 {
817 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
818 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
819 {
820 __HAL_TIM_ENABLE(htim);
821 }
822 }
823 else
824 {
825 __HAL_TIM_ENABLE(htim);
826 }
827
828 /* Return function status */
829 return HAL_OK;
830 }
831
832 /**
833 * @brief Stops the TIM Output Compare signal generation.
834 * @param htim TIM Output Compare handle
835 * @param Channel TIM Channel to be disabled
836 * This parameter can be one of the following values:
837 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
838 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
839 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
840 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
841 * @retval HAL status
842 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)843 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
844 {
845 /* Check the parameters */
846 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
847
848 /* Disable the Output compare channel */
849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
850
851 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
852 {
853 /* Disable the Main Output */
854 __HAL_TIM_MOE_DISABLE(htim);
855 }
856
857 /* Disable the Peripheral */
858 __HAL_TIM_DISABLE(htim);
859
860 /* Set the TIM channel state */
861 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
869 * @param htim TIM Output Compare handle
870 * @param Channel TIM Channel to be enabled
871 * This parameter can be one of the following values:
872 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
873 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
874 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
875 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
876 * @retval HAL status
877 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)878 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881 uint32_t tmpsmcr;
882
883 /* Check the parameters */
884 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
885
886 /* Check the TIM channel state */
887 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
888 {
889 return HAL_ERROR;
890 }
891
892 /* Set the TIM channel state */
893 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
894
895 switch (Channel)
896 {
897 case TIM_CHANNEL_1:
898 {
899 /* Enable the TIM Capture/Compare 1 interrupt */
900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
901 break;
902 }
903
904 case TIM_CHANNEL_2:
905 {
906 /* Enable the TIM Capture/Compare 2 interrupt */
907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
908 break;
909 }
910
911 case TIM_CHANNEL_3:
912 {
913 /* Enable the TIM Capture/Compare 3 interrupt */
914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
915 break;
916 }
917
918 case TIM_CHANNEL_4:
919 {
920 /* Enable the TIM Capture/Compare 4 interrupt */
921 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
922 break;
923 }
924
925 default:
926 status = HAL_ERROR;
927 break;
928 }
929
930 if (status == HAL_OK)
931 {
932 /* Enable the Output compare channel */
933 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
934
935 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
936 {
937 /* Enable the main output */
938 __HAL_TIM_MOE_ENABLE(htim);
939 }
940
941 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
942 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
943 {
944 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
945 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
946 {
947 __HAL_TIM_ENABLE(htim);
948 }
949 }
950 else
951 {
952 __HAL_TIM_ENABLE(htim);
953 }
954 }
955
956 /* Return function status */
957 return status;
958 }
959
960 /**
961 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
962 * @param htim TIM Output Compare handle
963 * @param Channel TIM Channel to be disabled
964 * This parameter can be one of the following values:
965 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
966 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
967 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
968 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
969 * @retval HAL status
970 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)971 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
972 {
973 HAL_StatusTypeDef status = HAL_OK;
974
975 /* Check the parameters */
976 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
977
978 switch (Channel)
979 {
980 case TIM_CHANNEL_1:
981 {
982 /* Disable the TIM Capture/Compare 1 interrupt */
983 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
984 break;
985 }
986
987 case TIM_CHANNEL_2:
988 {
989 /* Disable the TIM Capture/Compare 2 interrupt */
990 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
991 break;
992 }
993
994 case TIM_CHANNEL_3:
995 {
996 /* Disable the TIM Capture/Compare 3 interrupt */
997 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
998 break;
999 }
1000
1001 case TIM_CHANNEL_4:
1002 {
1003 /* Disable the TIM Capture/Compare 4 interrupt */
1004 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1005 break;
1006 }
1007
1008 default:
1009 status = HAL_ERROR;
1010 break;
1011 }
1012
1013 if (status == HAL_OK)
1014 {
1015 /* Disable the Output compare channel */
1016 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1017
1018 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1019 {
1020 /* Disable the Main Output */
1021 __HAL_TIM_MOE_DISABLE(htim);
1022 }
1023
1024 /* Disable the Peripheral */
1025 __HAL_TIM_DISABLE(htim);
1026
1027 /* Set the TIM channel state */
1028 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1029 }
1030
1031 /* Return function status */
1032 return status;
1033 }
1034
1035 /**
1036 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1037 * @param htim TIM Output Compare handle
1038 * @param Channel TIM Channel to be enabled
1039 * This parameter can be one of the following values:
1040 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1041 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1042 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1043 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1044 * @param pData The source Buffer address.
1045 * @param Length The length of data to be transferred from memory to TIM peripheral
1046 * @retval HAL status
1047 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1048 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1049 uint16_t Length)
1050 {
1051 HAL_StatusTypeDef status = HAL_OK;
1052 uint32_t tmpsmcr;
1053
1054 /* Check the parameters */
1055 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1056
1057 /* Set the TIM channel state */
1058 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1059 {
1060 return HAL_BUSY;
1061 }
1062 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1063 {
1064 if ((pData == NULL) || (Length == 0U))
1065 {
1066 return HAL_ERROR;
1067 }
1068 else
1069 {
1070 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1071 }
1072 }
1073 else
1074 {
1075 return HAL_ERROR;
1076 }
1077
1078 switch (Channel)
1079 {
1080 case TIM_CHANNEL_1:
1081 {
1082 /* Set the DMA compare callbacks */
1083 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1084 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1085
1086 /* Set the DMA error callback */
1087 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1088
1089 /* Enable the DMA channel */
1090 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1091 Length) != HAL_OK)
1092 {
1093 /* Return error status */
1094 return HAL_ERROR;
1095 }
1096
1097 /* Enable the TIM Capture/Compare 1 DMA request */
1098 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1099 break;
1100 }
1101
1102 case TIM_CHANNEL_2:
1103 {
1104 /* Set the DMA compare callbacks */
1105 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1106 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1107
1108 /* Set the DMA error callback */
1109 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1110
1111 /* Enable the DMA channel */
1112 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1113 Length) != HAL_OK)
1114 {
1115 /* Return error status */
1116 return HAL_ERROR;
1117 }
1118
1119 /* Enable the TIM Capture/Compare 2 DMA request */
1120 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1121 break;
1122 }
1123
1124 case TIM_CHANNEL_3:
1125 {
1126 /* Set the DMA compare callbacks */
1127 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1128 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1129
1130 /* Set the DMA error callback */
1131 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1132
1133 /* Enable the DMA channel */
1134 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1135 Length) != HAL_OK)
1136 {
1137 /* Return error status */
1138 return HAL_ERROR;
1139 }
1140 /* Enable the TIM Capture/Compare 3 DMA request */
1141 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1142 break;
1143 }
1144
1145 case TIM_CHANNEL_4:
1146 {
1147 /* Set the DMA compare callbacks */
1148 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1149 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1150
1151 /* Set the DMA error callback */
1152 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1153
1154 /* Enable the DMA channel */
1155 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1156 Length) != HAL_OK)
1157 {
1158 /* Return error status */
1159 return HAL_ERROR;
1160 }
1161 /* Enable the TIM Capture/Compare 4 DMA request */
1162 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1163 break;
1164 }
1165
1166 default:
1167 status = HAL_ERROR;
1168 break;
1169 }
1170
1171 if (status == HAL_OK)
1172 {
1173 /* Enable the Output compare channel */
1174 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1175
1176 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1177 {
1178 /* Enable the main output */
1179 __HAL_TIM_MOE_ENABLE(htim);
1180 }
1181
1182 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1183 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1184 {
1185 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1186 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1187 {
1188 __HAL_TIM_ENABLE(htim);
1189 }
1190 }
1191 else
1192 {
1193 __HAL_TIM_ENABLE(htim);
1194 }
1195 }
1196
1197 /* Return function status */
1198 return status;
1199 }
1200
1201 /**
1202 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1203 * @param htim TIM Output Compare handle
1204 * @param Channel TIM Channel to be disabled
1205 * This parameter can be one of the following values:
1206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1210 * @retval HAL status
1211 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1212 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1213 {
1214 HAL_StatusTypeDef status = HAL_OK;
1215
1216 /* Check the parameters */
1217 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1218
1219 switch (Channel)
1220 {
1221 case TIM_CHANNEL_1:
1222 {
1223 /* Disable the TIM Capture/Compare 1 DMA request */
1224 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1225 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1226 break;
1227 }
1228
1229 case TIM_CHANNEL_2:
1230 {
1231 /* Disable the TIM Capture/Compare 2 DMA request */
1232 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1233 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1234 break;
1235 }
1236
1237 case TIM_CHANNEL_3:
1238 {
1239 /* Disable the TIM Capture/Compare 3 DMA request */
1240 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1241 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1242 break;
1243 }
1244
1245 case TIM_CHANNEL_4:
1246 {
1247 /* Disable the TIM Capture/Compare 4 interrupt */
1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1249 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1250 break;
1251 }
1252
1253 default:
1254 status = HAL_ERROR;
1255 break;
1256 }
1257
1258 if (status == HAL_OK)
1259 {
1260 /* Disable the Output compare channel */
1261 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1262
1263 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1264 {
1265 /* Disable the Main Output */
1266 __HAL_TIM_MOE_DISABLE(htim);
1267 }
1268
1269 /* Disable the Peripheral */
1270 __HAL_TIM_DISABLE(htim);
1271
1272 /* Set the TIM channel state */
1273 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1274 }
1275
1276 /* Return function status */
1277 return status;
1278 }
1279
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1285 * @brief TIM PWM functions
1286 *
1287 @verbatim
1288 ==============================================================================
1289 ##### TIM PWM functions #####
1290 ==============================================================================
1291 [..]
1292 This section provides functions allowing to:
1293 (+) Initialize and configure the TIM PWM.
1294 (+) De-initialize the TIM PWM.
1295 (+) Start the TIM PWM.
1296 (+) Stop the TIM PWM.
1297 (+) Start the TIM PWM and enable interrupt.
1298 (+) Stop the TIM PWM and disable interrupt.
1299 (+) Start the TIM PWM and enable DMA transfer.
1300 (+) Stop the TIM PWM and disable DMA transfer.
1301
1302 @endverbatim
1303 * @{
1304 */
1305 /**
1306 * @brief Initializes the TIM PWM Time Base according to the specified
1307 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1308 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1309 * requires a timer reset to avoid unexpected direction
1310 * due to DIR bit readonly in center aligned mode.
1311 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1312 * @param htim TIM PWM handle
1313 * @retval HAL status
1314 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1315 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1316 {
1317 /* Check the TIM handle allocation */
1318 if (htim == NULL)
1319 {
1320 return HAL_ERROR;
1321 }
1322
1323 /* Check the parameters */
1324 assert_param(IS_TIM_INSTANCE(htim->Instance));
1325 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1326 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1327 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1328 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1329
1330 if (htim->State == HAL_TIM_STATE_RESET)
1331 {
1332 /* Allocate lock resource and initialize it */
1333 htim->Lock = HAL_UNLOCKED;
1334
1335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1336 /* Reset interrupt callbacks to legacy weak callbacks */
1337 TIM_ResetCallback(htim);
1338
1339 if (htim->PWM_MspInitCallback == NULL)
1340 {
1341 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1342 }
1343 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1344 htim->PWM_MspInitCallback(htim);
1345 #else
1346 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1347 HAL_TIM_PWM_MspInit(htim);
1348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1349 }
1350
1351 /* Set the TIM state */
1352 htim->State = HAL_TIM_STATE_BUSY;
1353
1354 /* Init the base time for the PWM */
1355 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1356
1357 /* Initialize the DMA burst operation state */
1358 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1359
1360 /* Initialize the TIM channels state */
1361 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1362 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1363
1364 /* Initialize the TIM state*/
1365 htim->State = HAL_TIM_STATE_READY;
1366
1367 return HAL_OK;
1368 }
1369
1370 /**
1371 * @brief DeInitializes the TIM peripheral
1372 * @param htim TIM PWM handle
1373 * @retval HAL status
1374 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1375 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1376 {
1377 /* Check the parameters */
1378 assert_param(IS_TIM_INSTANCE(htim->Instance));
1379
1380 htim->State = HAL_TIM_STATE_BUSY;
1381
1382 /* Disable the TIM Peripheral Clock */
1383 __HAL_TIM_DISABLE(htim);
1384
1385 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1386 if (htim->PWM_MspDeInitCallback == NULL)
1387 {
1388 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1389 }
1390 /* DeInit the low level hardware */
1391 htim->PWM_MspDeInitCallback(htim);
1392 #else
1393 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1394 HAL_TIM_PWM_MspDeInit(htim);
1395 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1396
1397 /* Change the DMA burst operation state */
1398 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1399
1400 /* Change the TIM channels state */
1401 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1402 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1403
1404 /* Change TIM state */
1405 htim->State = HAL_TIM_STATE_RESET;
1406
1407 /* Release Lock */
1408 __HAL_UNLOCK(htim);
1409
1410 return HAL_OK;
1411 }
1412
1413 /**
1414 * @brief Initializes the TIM PWM MSP.
1415 * @param htim TIM PWM handle
1416 * @retval None
1417 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1418 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1419 {
1420 /* Prevent unused argument(s) compilation warning */
1421 UNUSED(htim);
1422
1423 /* NOTE : This function should not be modified, when the callback is needed,
1424 the HAL_TIM_PWM_MspInit could be implemented in the user file
1425 */
1426 }
1427
1428 /**
1429 * @brief DeInitializes TIM PWM MSP.
1430 * @param htim TIM PWM handle
1431 * @retval None
1432 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1433 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1434 {
1435 /* Prevent unused argument(s) compilation warning */
1436 UNUSED(htim);
1437
1438 /* NOTE : This function should not be modified, when the callback is needed,
1439 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1440 */
1441 }
1442
1443 /**
1444 * @brief Starts the PWM signal generation.
1445 * @param htim TIM handle
1446 * @param Channel TIM Channels to be enabled
1447 * This parameter can be one of the following values:
1448 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1449 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1450 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1451 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1452 * @retval HAL status
1453 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1454 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1455 {
1456 uint32_t tmpsmcr;
1457
1458 /* Check the parameters */
1459 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1460
1461 /* Check the TIM channel state */
1462 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1463 {
1464 return HAL_ERROR;
1465 }
1466
1467 /* Set the TIM channel state */
1468 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1469
1470 /* Enable the Capture compare channel */
1471 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1472
1473 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1474 {
1475 /* Enable the main output */
1476 __HAL_TIM_MOE_ENABLE(htim);
1477 }
1478
1479 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1480 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1481 {
1482 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1483 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1484 {
1485 __HAL_TIM_ENABLE(htim);
1486 }
1487 }
1488 else
1489 {
1490 __HAL_TIM_ENABLE(htim);
1491 }
1492
1493 /* Return function status */
1494 return HAL_OK;
1495 }
1496
1497 /**
1498 * @brief Stops the PWM signal generation.
1499 * @param htim TIM PWM handle
1500 * @param Channel TIM Channels to be disabled
1501 * This parameter can be one of the following values:
1502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1504 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1505 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1506 * @retval HAL status
1507 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1508 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1509 {
1510 /* Check the parameters */
1511 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1512
1513 /* Disable the Capture compare channel */
1514 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1515
1516 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1517 {
1518 /* Disable the Main Output */
1519 __HAL_TIM_MOE_DISABLE(htim);
1520 }
1521
1522 /* Disable the Peripheral */
1523 __HAL_TIM_DISABLE(htim);
1524
1525 /* Set the TIM channel state */
1526 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1527
1528 /* Return function status */
1529 return HAL_OK;
1530 }
1531
1532 /**
1533 * @brief Starts the PWM signal generation in interrupt mode.
1534 * @param htim TIM PWM handle
1535 * @param Channel TIM Channel to be enabled
1536 * This parameter can be one of the following values:
1537 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1538 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1539 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1540 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1541 * @retval HAL status
1542 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1543 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1544 {
1545 HAL_StatusTypeDef status = HAL_OK;
1546 uint32_t tmpsmcr;
1547
1548 /* Check the parameters */
1549 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1550
1551 /* Check the TIM channel state */
1552 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1553 {
1554 return HAL_ERROR;
1555 }
1556
1557 /* Set the TIM channel state */
1558 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1559
1560 switch (Channel)
1561 {
1562 case TIM_CHANNEL_1:
1563 {
1564 /* Enable the TIM Capture/Compare 1 interrupt */
1565 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1566 break;
1567 }
1568
1569 case TIM_CHANNEL_2:
1570 {
1571 /* Enable the TIM Capture/Compare 2 interrupt */
1572 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1573 break;
1574 }
1575
1576 case TIM_CHANNEL_3:
1577 {
1578 /* Enable the TIM Capture/Compare 3 interrupt */
1579 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1580 break;
1581 }
1582
1583 case TIM_CHANNEL_4:
1584 {
1585 /* Enable the TIM Capture/Compare 4 interrupt */
1586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1587 break;
1588 }
1589
1590 default:
1591 status = HAL_ERROR;
1592 break;
1593 }
1594
1595 if (status == HAL_OK)
1596 {
1597 /* Enable the Capture compare channel */
1598 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1599
1600 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1601 {
1602 /* Enable the main output */
1603 __HAL_TIM_MOE_ENABLE(htim);
1604 }
1605
1606 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1607 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1608 {
1609 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1610 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1611 {
1612 __HAL_TIM_ENABLE(htim);
1613 }
1614 }
1615 else
1616 {
1617 __HAL_TIM_ENABLE(htim);
1618 }
1619 }
1620
1621 /* Return function status */
1622 return status;
1623 }
1624
1625 /**
1626 * @brief Stops the PWM signal generation in interrupt mode.
1627 * @param htim TIM PWM handle
1628 * @param Channel TIM Channels to be disabled
1629 * This parameter can be one of the following values:
1630 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1631 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1632 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1633 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1634 * @retval HAL status
1635 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1636 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1637 {
1638 HAL_StatusTypeDef status = HAL_OK;
1639
1640 /* Check the parameters */
1641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1642
1643 switch (Channel)
1644 {
1645 case TIM_CHANNEL_1:
1646 {
1647 /* Disable the TIM Capture/Compare 1 interrupt */
1648 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1649 break;
1650 }
1651
1652 case TIM_CHANNEL_2:
1653 {
1654 /* Disable the TIM Capture/Compare 2 interrupt */
1655 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1656 break;
1657 }
1658
1659 case TIM_CHANNEL_3:
1660 {
1661 /* Disable the TIM Capture/Compare 3 interrupt */
1662 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1663 break;
1664 }
1665
1666 case TIM_CHANNEL_4:
1667 {
1668 /* Disable the TIM Capture/Compare 4 interrupt */
1669 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1670 break;
1671 }
1672
1673 default:
1674 status = HAL_ERROR;
1675 break;
1676 }
1677
1678 if (status == HAL_OK)
1679 {
1680 /* Disable the Capture compare channel */
1681 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1682
1683 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1684 {
1685 /* Disable the Main Output */
1686 __HAL_TIM_MOE_DISABLE(htim);
1687 }
1688
1689 /* Disable the Peripheral */
1690 __HAL_TIM_DISABLE(htim);
1691
1692 /* Set the TIM channel state */
1693 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1694 }
1695
1696 /* Return function status */
1697 return status;
1698 }
1699
1700 /**
1701 * @brief Starts the TIM PWM signal generation in DMA mode.
1702 * @param htim TIM PWM handle
1703 * @param Channel TIM Channels to be enabled
1704 * This parameter can be one of the following values:
1705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1709 * @param pData The source Buffer address.
1710 * @param Length The length of data to be transferred from memory to TIM peripheral
1711 * @retval HAL status
1712 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1713 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1714 uint16_t Length)
1715 {
1716 HAL_StatusTypeDef status = HAL_OK;
1717 uint32_t tmpsmcr;
1718
1719 /* Check the parameters */
1720 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1721
1722 /* Set the TIM channel state */
1723 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1724 {
1725 return HAL_BUSY;
1726 }
1727 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1728 {
1729 if ((pData == NULL) || (Length == 0U))
1730 {
1731 return HAL_ERROR;
1732 }
1733 else
1734 {
1735 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1736 }
1737 }
1738 else
1739 {
1740 return HAL_ERROR;
1741 }
1742
1743 switch (Channel)
1744 {
1745 case TIM_CHANNEL_1:
1746 {
1747 /* Set the DMA compare callbacks */
1748 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1749 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1750
1751 /* Set the DMA error callback */
1752 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1753
1754 /* Enable the DMA channel */
1755 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1756 Length) != HAL_OK)
1757 {
1758 /* Return error status */
1759 return HAL_ERROR;
1760 }
1761
1762 /* Enable the TIM Capture/Compare 1 DMA request */
1763 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1764 break;
1765 }
1766
1767 case TIM_CHANNEL_2:
1768 {
1769 /* Set the DMA compare callbacks */
1770 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1771 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1772
1773 /* Set the DMA error callback */
1774 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1775
1776 /* Enable the DMA channel */
1777 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1778 Length) != HAL_OK)
1779 {
1780 /* Return error status */
1781 return HAL_ERROR;
1782 }
1783 /* Enable the TIM Capture/Compare 2 DMA request */
1784 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1785 break;
1786 }
1787
1788 case TIM_CHANNEL_3:
1789 {
1790 /* Set the DMA compare callbacks */
1791 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1792 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1793
1794 /* Set the DMA error callback */
1795 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1796
1797 /* Enable the DMA channel */
1798 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1799 Length) != HAL_OK)
1800 {
1801 /* Return error status */
1802 return HAL_ERROR;
1803 }
1804 /* Enable the TIM Output Capture/Compare 3 request */
1805 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1806 break;
1807 }
1808
1809 case TIM_CHANNEL_4:
1810 {
1811 /* Set the DMA compare callbacks */
1812 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1813 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1814
1815 /* Set the DMA error callback */
1816 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1817
1818 /* Enable the DMA channel */
1819 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1820 Length) != HAL_OK)
1821 {
1822 /* Return error status */
1823 return HAL_ERROR;
1824 }
1825 /* Enable the TIM Capture/Compare 4 DMA request */
1826 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1827 break;
1828 }
1829
1830 default:
1831 status = HAL_ERROR;
1832 break;
1833 }
1834
1835 if (status == HAL_OK)
1836 {
1837 /* Enable the Capture compare channel */
1838 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1839
1840 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1841 {
1842 /* Enable the main output */
1843 __HAL_TIM_MOE_ENABLE(htim);
1844 }
1845
1846 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1847 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1848 {
1849 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1850 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1851 {
1852 __HAL_TIM_ENABLE(htim);
1853 }
1854 }
1855 else
1856 {
1857 __HAL_TIM_ENABLE(htim);
1858 }
1859 }
1860
1861 /* Return function status */
1862 return status;
1863 }
1864
1865 /**
1866 * @brief Stops the TIM PWM signal generation in DMA mode.
1867 * @param htim TIM PWM handle
1868 * @param Channel TIM Channels to be disabled
1869 * This parameter can be one of the following values:
1870 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1871 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1872 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1873 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1874 * @retval HAL status
1875 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1876 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1877 {
1878 HAL_StatusTypeDef status = HAL_OK;
1879
1880 /* Check the parameters */
1881 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1882
1883 switch (Channel)
1884 {
1885 case TIM_CHANNEL_1:
1886 {
1887 /* Disable the TIM Capture/Compare 1 DMA request */
1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1889 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1890 break;
1891 }
1892
1893 case TIM_CHANNEL_2:
1894 {
1895 /* Disable the TIM Capture/Compare 2 DMA request */
1896 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1897 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1898 break;
1899 }
1900
1901 case TIM_CHANNEL_3:
1902 {
1903 /* Disable the TIM Capture/Compare 3 DMA request */
1904 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1905 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1906 break;
1907 }
1908
1909 case TIM_CHANNEL_4:
1910 {
1911 /* Disable the TIM Capture/Compare 4 interrupt */
1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1913 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1914 break;
1915 }
1916
1917 default:
1918 status = HAL_ERROR;
1919 break;
1920 }
1921
1922 if (status == HAL_OK)
1923 {
1924 /* Disable the Capture compare channel */
1925 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1926
1927 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1928 {
1929 /* Disable the Main Output */
1930 __HAL_TIM_MOE_DISABLE(htim);
1931 }
1932
1933 /* Disable the Peripheral */
1934 __HAL_TIM_DISABLE(htim);
1935
1936 /* Set the TIM channel state */
1937 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1938 }
1939
1940 /* Return function status */
1941 return status;
1942 }
1943
1944 /**
1945 * @}
1946 */
1947
1948 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1949 * @brief TIM Input Capture functions
1950 *
1951 @verbatim
1952 ==============================================================================
1953 ##### TIM Input Capture functions #####
1954 ==============================================================================
1955 [..]
1956 This section provides functions allowing to:
1957 (+) Initialize and configure the TIM Input Capture.
1958 (+) De-initialize the TIM Input Capture.
1959 (+) Start the TIM Input Capture.
1960 (+) Stop the TIM Input Capture.
1961 (+) Start the TIM Input Capture and enable interrupt.
1962 (+) Stop the TIM Input Capture and disable interrupt.
1963 (+) Start the TIM Input Capture and enable DMA transfer.
1964 (+) Stop the TIM Input Capture and disable DMA transfer.
1965
1966 @endverbatim
1967 * @{
1968 */
1969 /**
1970 * @brief Initializes the TIM Input Capture Time base according to the specified
1971 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1972 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1973 * requires a timer reset to avoid unexpected direction
1974 * due to DIR bit readonly in center aligned mode.
1975 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1976 * @param htim TIM Input Capture handle
1977 * @retval HAL status
1978 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1979 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1980 {
1981 /* Check the TIM handle allocation */
1982 if (htim == NULL)
1983 {
1984 return HAL_ERROR;
1985 }
1986
1987 /* Check the parameters */
1988 assert_param(IS_TIM_INSTANCE(htim->Instance));
1989 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1990 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1991 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1992 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1993
1994 if (htim->State == HAL_TIM_STATE_RESET)
1995 {
1996 /* Allocate lock resource and initialize it */
1997 htim->Lock = HAL_UNLOCKED;
1998
1999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2000 /* Reset interrupt callbacks to legacy weak callbacks */
2001 TIM_ResetCallback(htim);
2002
2003 if (htim->IC_MspInitCallback == NULL)
2004 {
2005 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2006 }
2007 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2008 htim->IC_MspInitCallback(htim);
2009 #else
2010 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2011 HAL_TIM_IC_MspInit(htim);
2012 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2013 }
2014
2015 /* Set the TIM state */
2016 htim->State = HAL_TIM_STATE_BUSY;
2017
2018 /* Init the base time for the input capture */
2019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2020
2021 /* Initialize the DMA burst operation state */
2022 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2023
2024 /* Initialize the TIM channels state */
2025 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2026 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2027
2028 /* Initialize the TIM state*/
2029 htim->State = HAL_TIM_STATE_READY;
2030
2031 return HAL_OK;
2032 }
2033
2034 /**
2035 * @brief DeInitializes the TIM peripheral
2036 * @param htim TIM Input Capture handle
2037 * @retval HAL status
2038 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2039 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2040 {
2041 /* Check the parameters */
2042 assert_param(IS_TIM_INSTANCE(htim->Instance));
2043
2044 htim->State = HAL_TIM_STATE_BUSY;
2045
2046 /* Disable the TIM Peripheral Clock */
2047 __HAL_TIM_DISABLE(htim);
2048
2049 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2050 if (htim->IC_MspDeInitCallback == NULL)
2051 {
2052 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2053 }
2054 /* DeInit the low level hardware */
2055 htim->IC_MspDeInitCallback(htim);
2056 #else
2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2058 HAL_TIM_IC_MspDeInit(htim);
2059 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2060
2061 /* Change the DMA burst operation state */
2062 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2063
2064 /* Change the TIM channels state */
2065 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2066 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2067
2068 /* Change TIM state */
2069 htim->State = HAL_TIM_STATE_RESET;
2070
2071 /* Release Lock */
2072 __HAL_UNLOCK(htim);
2073
2074 return HAL_OK;
2075 }
2076
2077 /**
2078 * @brief Initializes the TIM Input Capture MSP.
2079 * @param htim TIM Input Capture handle
2080 * @retval None
2081 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2082 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2083 {
2084 /* Prevent unused argument(s) compilation warning */
2085 UNUSED(htim);
2086
2087 /* NOTE : This function should not be modified, when the callback is needed,
2088 the HAL_TIM_IC_MspInit could be implemented in the user file
2089 */
2090 }
2091
2092 /**
2093 * @brief DeInitializes TIM Input Capture MSP.
2094 * @param htim TIM handle
2095 * @retval None
2096 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2097 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2098 {
2099 /* Prevent unused argument(s) compilation warning */
2100 UNUSED(htim);
2101
2102 /* NOTE : This function should not be modified, when the callback is needed,
2103 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2104 */
2105 }
2106
2107 /**
2108 * @brief Starts the TIM Input Capture measurement.
2109 * @param htim TIM Input Capture handle
2110 * @param Channel TIM Channels to be enabled
2111 * This parameter can be one of the following values:
2112 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2113 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2114 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2115 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2116 * @retval HAL status
2117 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2118 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2119 {
2120 uint32_t tmpsmcr;
2121 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2122 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2123
2124 /* Check the parameters */
2125 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2126
2127 /* Check the TIM channel state */
2128 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2129 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2130 {
2131 return HAL_ERROR;
2132 }
2133
2134 /* Set the TIM channel state */
2135 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2136 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2137
2138 /* Enable the Input Capture channel */
2139 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2140
2141 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2142 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2143 {
2144 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2145 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2146 {
2147 __HAL_TIM_ENABLE(htim);
2148 }
2149 }
2150 else
2151 {
2152 __HAL_TIM_ENABLE(htim);
2153 }
2154
2155 /* Return function status */
2156 return HAL_OK;
2157 }
2158
2159 /**
2160 * @brief Stops the TIM Input Capture measurement.
2161 * @param htim TIM Input Capture handle
2162 * @param Channel TIM Channels to be disabled
2163 * This parameter can be one of the following values:
2164 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2165 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2166 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2167 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2168 * @retval HAL status
2169 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2170 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2171 {
2172 /* Check the parameters */
2173 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2174
2175 /* Disable the Input Capture channel */
2176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2177
2178 /* Disable the Peripheral */
2179 __HAL_TIM_DISABLE(htim);
2180
2181 /* Set the TIM channel state */
2182 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2183 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2184
2185 /* Return function status */
2186 return HAL_OK;
2187 }
2188
2189 /**
2190 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2191 * @param htim TIM Input Capture handle
2192 * @param Channel TIM Channels to be enabled
2193 * This parameter can be one of the following values:
2194 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2195 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2196 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2197 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2198 * @retval HAL status
2199 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2200 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2201 {
2202 HAL_StatusTypeDef status = HAL_OK;
2203 uint32_t tmpsmcr;
2204
2205 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2206 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2207
2208 /* Check the parameters */
2209 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2210
2211 /* Check the TIM channel state */
2212 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2213 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2214 {
2215 return HAL_ERROR;
2216 }
2217
2218 /* Set the TIM channel state */
2219 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2220 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2221
2222 switch (Channel)
2223 {
2224 case TIM_CHANNEL_1:
2225 {
2226 /* Enable the TIM Capture/Compare 1 interrupt */
2227 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_2:
2232 {
2233 /* Enable the TIM Capture/Compare 2 interrupt */
2234 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2235 break;
2236 }
2237
2238 case TIM_CHANNEL_3:
2239 {
2240 /* Enable the TIM Capture/Compare 3 interrupt */
2241 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2242 break;
2243 }
2244
2245 case TIM_CHANNEL_4:
2246 {
2247 /* Enable the TIM Capture/Compare 4 interrupt */
2248 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2249 break;
2250 }
2251
2252 default:
2253 status = HAL_ERROR;
2254 break;
2255 }
2256
2257 if (status == HAL_OK)
2258 {
2259 /* Enable the Input Capture channel */
2260 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2261
2262 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2263 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2264 {
2265 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2266 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2267 {
2268 __HAL_TIM_ENABLE(htim);
2269 }
2270 }
2271 else
2272 {
2273 __HAL_TIM_ENABLE(htim);
2274 }
2275 }
2276
2277 /* Return function status */
2278 return status;
2279 }
2280
2281 /**
2282 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2283 * @param htim TIM Input Capture handle
2284 * @param Channel TIM Channels to be disabled
2285 * This parameter can be one of the following values:
2286 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2287 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2288 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2289 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2290 * @retval HAL status
2291 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2292 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2293 {
2294 HAL_StatusTypeDef status = HAL_OK;
2295
2296 /* Check the parameters */
2297 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2298
2299 switch (Channel)
2300 {
2301 case TIM_CHANNEL_1:
2302 {
2303 /* Disable the TIM Capture/Compare 1 interrupt */
2304 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2305 break;
2306 }
2307
2308 case TIM_CHANNEL_2:
2309 {
2310 /* Disable the TIM Capture/Compare 2 interrupt */
2311 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2312 break;
2313 }
2314
2315 case TIM_CHANNEL_3:
2316 {
2317 /* Disable the TIM Capture/Compare 3 interrupt */
2318 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2319 break;
2320 }
2321
2322 case TIM_CHANNEL_4:
2323 {
2324 /* Disable the TIM Capture/Compare 4 interrupt */
2325 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2326 break;
2327 }
2328
2329 default:
2330 status = HAL_ERROR;
2331 break;
2332 }
2333
2334 if (status == HAL_OK)
2335 {
2336 /* Disable the Input Capture channel */
2337 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2338
2339 /* Disable the Peripheral */
2340 __HAL_TIM_DISABLE(htim);
2341
2342 /* Set the TIM channel state */
2343 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2344 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2345 }
2346
2347 /* Return function status */
2348 return status;
2349 }
2350
2351 /**
2352 * @brief Starts the TIM Input Capture measurement in DMA mode.
2353 * @param htim TIM Input Capture handle
2354 * @param Channel TIM Channels to be enabled
2355 * This parameter can be one of the following values:
2356 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2357 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2358 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2359 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2360 * @param pData The destination Buffer address.
2361 * @param Length The length of data to be transferred from TIM peripheral to memory.
2362 * @retval HAL status
2363 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2364 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2365 {
2366 HAL_StatusTypeDef status = HAL_OK;
2367 uint32_t tmpsmcr;
2368
2369 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2370 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2371
2372 /* Check the parameters */
2373 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2374 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2375
2376 /* Set the TIM channel state */
2377 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2378 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2379 {
2380 return HAL_BUSY;
2381 }
2382 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2383 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2384 {
2385 if ((pData == NULL) || (Length == 0U))
2386 {
2387 return HAL_ERROR;
2388 }
2389 else
2390 {
2391 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2392 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2393 }
2394 }
2395 else
2396 {
2397 return HAL_ERROR;
2398 }
2399
2400 /* Enable the Input Capture channel */
2401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2402
2403 switch (Channel)
2404 {
2405 case TIM_CHANNEL_1:
2406 {
2407 /* Set the DMA capture callbacks */
2408 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2409 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2410
2411 /* Set the DMA error callback */
2412 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2413
2414 /* Enable the DMA channel */
2415 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2416 Length) != HAL_OK)
2417 {
2418 /* Return error status */
2419 return HAL_ERROR;
2420 }
2421 /* Enable the TIM Capture/Compare 1 DMA request */
2422 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2423 break;
2424 }
2425
2426 case TIM_CHANNEL_2:
2427 {
2428 /* Set the DMA capture callbacks */
2429 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2430 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2431
2432 /* Set the DMA error callback */
2433 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2434
2435 /* Enable the DMA channel */
2436 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2437 Length) != HAL_OK)
2438 {
2439 /* Return error status */
2440 return HAL_ERROR;
2441 }
2442 /* Enable the TIM Capture/Compare 2 DMA request */
2443 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2444 break;
2445 }
2446
2447 case TIM_CHANNEL_3:
2448 {
2449 /* Set the DMA capture callbacks */
2450 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2451 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2452
2453 /* Set the DMA error callback */
2454 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2455
2456 /* Enable the DMA channel */
2457 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2458 Length) != HAL_OK)
2459 {
2460 /* Return error status */
2461 return HAL_ERROR;
2462 }
2463 /* Enable the TIM Capture/Compare 3 DMA request */
2464 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2465 break;
2466 }
2467
2468 case TIM_CHANNEL_4:
2469 {
2470 /* Set the DMA capture callbacks */
2471 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2472 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2473
2474 /* Set the DMA error callback */
2475 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2476
2477 /* Enable the DMA channel */
2478 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2479 Length) != HAL_OK)
2480 {
2481 /* Return error status */
2482 return HAL_ERROR;
2483 }
2484 /* Enable the TIM Capture/Compare 4 DMA request */
2485 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2486 break;
2487 }
2488
2489 default:
2490 status = HAL_ERROR;
2491 break;
2492 }
2493
2494 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2495 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2496 {
2497 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2498 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2499 {
2500 __HAL_TIM_ENABLE(htim);
2501 }
2502 }
2503 else
2504 {
2505 __HAL_TIM_ENABLE(htim);
2506 }
2507
2508 /* Return function status */
2509 return status;
2510 }
2511
2512 /**
2513 * @brief Stops the TIM Input Capture measurement in DMA mode.
2514 * @param htim TIM Input Capture handle
2515 * @param Channel TIM Channels to be disabled
2516 * This parameter can be one of the following values:
2517 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2518 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2519 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2520 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2521 * @retval HAL status
2522 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2523 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2524 {
2525 HAL_StatusTypeDef status = HAL_OK;
2526
2527 /* Check the parameters */
2528 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2529 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2530
2531 /* Disable the Input Capture channel */
2532 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2533
2534 switch (Channel)
2535 {
2536 case TIM_CHANNEL_1:
2537 {
2538 /* Disable the TIM Capture/Compare 1 DMA request */
2539 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2540 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2541 break;
2542 }
2543
2544 case TIM_CHANNEL_2:
2545 {
2546 /* Disable the TIM Capture/Compare 2 DMA request */
2547 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2548 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2549 break;
2550 }
2551
2552 case TIM_CHANNEL_3:
2553 {
2554 /* Disable the TIM Capture/Compare 3 DMA request */
2555 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2556 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2557 break;
2558 }
2559
2560 case TIM_CHANNEL_4:
2561 {
2562 /* Disable the TIM Capture/Compare 4 DMA request */
2563 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2564 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2565 break;
2566 }
2567
2568 default:
2569 status = HAL_ERROR;
2570 break;
2571 }
2572
2573 if (status == HAL_OK)
2574 {
2575 /* Disable the Peripheral */
2576 __HAL_TIM_DISABLE(htim);
2577
2578 /* Set the TIM channel state */
2579 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2580 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2581 }
2582
2583 /* Return function status */
2584 return status;
2585 }
2586 /**
2587 * @}
2588 */
2589
2590 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2591 * @brief TIM One Pulse functions
2592 *
2593 @verbatim
2594 ==============================================================================
2595 ##### TIM One Pulse functions #####
2596 ==============================================================================
2597 [..]
2598 This section provides functions allowing to:
2599 (+) Initialize and configure the TIM One Pulse.
2600 (+) De-initialize the TIM One Pulse.
2601 (+) Start the TIM One Pulse.
2602 (+) Stop the TIM One Pulse.
2603 (+) Start the TIM One Pulse and enable interrupt.
2604 (+) Stop the TIM One Pulse and disable interrupt.
2605 (+) Start the TIM One Pulse and enable DMA transfer.
2606 (+) Stop the TIM One Pulse and disable DMA transfer.
2607
2608 @endverbatim
2609 * @{
2610 */
2611 /**
2612 * @brief Initializes the TIM One Pulse Time Base according to the specified
2613 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2614 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2615 * requires a timer reset to avoid unexpected direction
2616 * due to DIR bit readonly in center aligned mode.
2617 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2618 * @note When the timer instance is initialized in One Pulse mode, timer
2619 * channels 1 and channel 2 are reserved and cannot be used for other
2620 * purpose.
2621 * @param htim TIM One Pulse handle
2622 * @param OnePulseMode Select the One pulse mode.
2623 * This parameter can be one of the following values:
2624 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2625 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2626 * @retval HAL status
2627 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2628 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2629 {
2630 /* Check the TIM handle allocation */
2631 if (htim == NULL)
2632 {
2633 return HAL_ERROR;
2634 }
2635
2636 /* Check the parameters */
2637 assert_param(IS_TIM_INSTANCE(htim->Instance));
2638 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2639 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2640 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2641 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2642 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2643
2644 if (htim->State == HAL_TIM_STATE_RESET)
2645 {
2646 /* Allocate lock resource and initialize it */
2647 htim->Lock = HAL_UNLOCKED;
2648
2649 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2650 /* Reset interrupt callbacks to legacy weak callbacks */
2651 TIM_ResetCallback(htim);
2652
2653 if (htim->OnePulse_MspInitCallback == NULL)
2654 {
2655 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2656 }
2657 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2658 htim->OnePulse_MspInitCallback(htim);
2659 #else
2660 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2661 HAL_TIM_OnePulse_MspInit(htim);
2662 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2663 }
2664
2665 /* Set the TIM state */
2666 htim->State = HAL_TIM_STATE_BUSY;
2667
2668 /* Configure the Time base in the One Pulse Mode */
2669 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2670
2671 /* Reset the OPM Bit */
2672 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2673
2674 /* Configure the OPM Mode */
2675 htim->Instance->CR1 |= OnePulseMode;
2676
2677 /* Initialize the DMA burst operation state */
2678 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2679
2680 /* Initialize the TIM channels state */
2681 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2682 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2683 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2684 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2685
2686 /* Initialize the TIM state*/
2687 htim->State = HAL_TIM_STATE_READY;
2688
2689 return HAL_OK;
2690 }
2691
2692 /**
2693 * @brief DeInitializes the TIM One Pulse
2694 * @param htim TIM One Pulse handle
2695 * @retval HAL status
2696 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2697 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2698 {
2699 /* Check the parameters */
2700 assert_param(IS_TIM_INSTANCE(htim->Instance));
2701
2702 htim->State = HAL_TIM_STATE_BUSY;
2703
2704 /* Disable the TIM Peripheral Clock */
2705 __HAL_TIM_DISABLE(htim);
2706
2707 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2708 if (htim->OnePulse_MspDeInitCallback == NULL)
2709 {
2710 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2711 }
2712 /* DeInit the low level hardware */
2713 htim->OnePulse_MspDeInitCallback(htim);
2714 #else
2715 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2716 HAL_TIM_OnePulse_MspDeInit(htim);
2717 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2718
2719 /* Change the DMA burst operation state */
2720 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2721
2722 /* Set the TIM channel state */
2723 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2724 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2725 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2726 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2727
2728 /* Change TIM state */
2729 htim->State = HAL_TIM_STATE_RESET;
2730
2731 /* Release Lock */
2732 __HAL_UNLOCK(htim);
2733
2734 return HAL_OK;
2735 }
2736
2737 /**
2738 * @brief Initializes the TIM One Pulse MSP.
2739 * @param htim TIM One Pulse handle
2740 * @retval None
2741 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2742 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2743 {
2744 /* Prevent unused argument(s) compilation warning */
2745 UNUSED(htim);
2746
2747 /* NOTE : This function should not be modified, when the callback is needed,
2748 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2749 */
2750 }
2751
2752 /**
2753 * @brief DeInitializes TIM One Pulse MSP.
2754 * @param htim TIM One Pulse handle
2755 * @retval None
2756 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2757 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2758 {
2759 /* Prevent unused argument(s) compilation warning */
2760 UNUSED(htim);
2761
2762 /* NOTE : This function should not be modified, when the callback is needed,
2763 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2764 */
2765 }
2766
2767 /**
2768 * @brief Starts the TIM One Pulse signal generation.
2769 * @note Though OutputChannel parameter is deprecated and ignored by the function
2770 * it has been kept to avoid HAL_TIM API compatibility break.
2771 * @note The pulse output channel is determined when calling
2772 * @ref HAL_TIM_OnePulse_ConfigChannel().
2773 * @param htim TIM One Pulse handle
2774 * @param OutputChannel See note above
2775 * @retval HAL status
2776 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2777 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2778 {
2779 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2780 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2781 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2782 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2783
2784 /* Prevent unused argument(s) compilation warning */
2785 UNUSED(OutputChannel);
2786
2787 /* Check the TIM channels state */
2788 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2789 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2790 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2791 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2792 {
2793 return HAL_ERROR;
2794 }
2795
2796 /* Set the TIM channels state */
2797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2800 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2801
2802 /* Enable the Capture compare and the Input Capture channels
2803 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2804 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2805 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2806 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2807
2808 No need to enable the counter, it's enabled automatically by hardware
2809 (the counter starts in response to a stimulus and generate a pulse */
2810
2811 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2812 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2813
2814 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2815 {
2816 /* Enable the main output */
2817 __HAL_TIM_MOE_ENABLE(htim);
2818 }
2819
2820 /* Return function status */
2821 return HAL_OK;
2822 }
2823
2824 /**
2825 * @brief Stops the TIM One Pulse signal generation.
2826 * @note Though OutputChannel parameter is deprecated and ignored by the function
2827 * it has been kept to avoid HAL_TIM API compatibility break.
2828 * @note The pulse output channel is determined when calling
2829 * @ref HAL_TIM_OnePulse_ConfigChannel().
2830 * @param htim TIM One Pulse handle
2831 * @param OutputChannel See note above
2832 * @retval HAL status
2833 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2834 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2835 {
2836 /* Prevent unused argument(s) compilation warning */
2837 UNUSED(OutputChannel);
2838
2839 /* Disable the Capture compare and the Input Capture channels
2840 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2841 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2842 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2843 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2844
2845 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2846 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2847
2848 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2849 {
2850 /* Disable the Main Output */
2851 __HAL_TIM_MOE_DISABLE(htim);
2852 }
2853
2854 /* Disable the Peripheral */
2855 __HAL_TIM_DISABLE(htim);
2856
2857 /* Set the TIM channels state */
2858 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2859 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2860 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2861 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2862
2863 /* Return function status */
2864 return HAL_OK;
2865 }
2866
2867 /**
2868 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2869 * @note Though OutputChannel parameter is deprecated and ignored by the function
2870 * it has been kept to avoid HAL_TIM API compatibility break.
2871 * @note The pulse output channel is determined when calling
2872 * @ref HAL_TIM_OnePulse_ConfigChannel().
2873 * @param htim TIM One Pulse handle
2874 * @param OutputChannel See note above
2875 * @retval HAL status
2876 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2877 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2878 {
2879 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2880 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2881 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2882 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2883
2884 /* Prevent unused argument(s) compilation warning */
2885 UNUSED(OutputChannel);
2886
2887 /* Check the TIM channels state */
2888 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2889 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2890 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2891 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2892 {
2893 return HAL_ERROR;
2894 }
2895
2896 /* Set the TIM channels state */
2897 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2898 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2899 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2900 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2901
2902 /* Enable the Capture compare and the Input Capture channels
2903 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2904 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2905 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2906 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2907
2908 No need to enable the counter, it's enabled automatically by hardware
2909 (the counter starts in response to a stimulus and generate a pulse */
2910
2911 /* Enable the TIM Capture/Compare 1 interrupt */
2912 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2913
2914 /* Enable the TIM Capture/Compare 2 interrupt */
2915 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2916
2917 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2918 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2919
2920 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2921 {
2922 /* Enable the main output */
2923 __HAL_TIM_MOE_ENABLE(htim);
2924 }
2925
2926 /* Return function status */
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2932 * @note Though OutputChannel parameter is deprecated and ignored by the function
2933 * it has been kept to avoid HAL_TIM API compatibility break.
2934 * @note The pulse output channel is determined when calling
2935 * @ref HAL_TIM_OnePulse_ConfigChannel().
2936 * @param htim TIM One Pulse handle
2937 * @param OutputChannel See note above
2938 * @retval HAL status
2939 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2940 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2941 {
2942 /* Prevent unused argument(s) compilation warning */
2943 UNUSED(OutputChannel);
2944
2945 /* Disable the TIM Capture/Compare 1 interrupt */
2946 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2947
2948 /* Disable the TIM Capture/Compare 2 interrupt */
2949 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2950
2951 /* Disable the Capture compare and the Input Capture channels
2952 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2953 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2954 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2955 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2956 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2957 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2958
2959 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2960 {
2961 /* Disable the Main Output */
2962 __HAL_TIM_MOE_DISABLE(htim);
2963 }
2964
2965 /* Disable the Peripheral */
2966 __HAL_TIM_DISABLE(htim);
2967
2968 /* Set the TIM channels state */
2969 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2970 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2971 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2972 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2973
2974 /* Return function status */
2975 return HAL_OK;
2976 }
2977
2978 /**
2979 * @}
2980 */
2981
2982 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2983 * @brief TIM Encoder functions
2984 *
2985 @verbatim
2986 ==============================================================================
2987 ##### TIM Encoder functions #####
2988 ==============================================================================
2989 [..]
2990 This section provides functions allowing to:
2991 (+) Initialize and configure the TIM Encoder.
2992 (+) De-initialize the TIM Encoder.
2993 (+) Start the TIM Encoder.
2994 (+) Stop the TIM Encoder.
2995 (+) Start the TIM Encoder and enable interrupt.
2996 (+) Stop the TIM Encoder and disable interrupt.
2997 (+) Start the TIM Encoder and enable DMA transfer.
2998 (+) Stop the TIM Encoder and disable DMA transfer.
2999
3000 @endverbatim
3001 * @{
3002 */
3003 /**
3004 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3005 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3006 * requires a timer reset to avoid unexpected direction
3007 * due to DIR bit readonly in center aligned mode.
3008 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3009 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3010 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3011 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3012 * @note When the timer instance is initialized in Encoder mode, timer
3013 * channels 1 and channel 2 are reserved and cannot be used for other
3014 * purpose.
3015 * @param htim TIM Encoder Interface handle
3016 * @param sConfig TIM Encoder Interface configuration structure
3017 * @retval HAL status
3018 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3019 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3020 {
3021 uint32_t tmpsmcr;
3022 uint32_t tmpccmr1;
3023 uint32_t tmpccer;
3024
3025 /* Check the TIM handle allocation */
3026 if (htim == NULL)
3027 {
3028 return HAL_ERROR;
3029 }
3030
3031 /* Check the parameters */
3032 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3033 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3034 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3035 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3036 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3037 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3038 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3039 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3040 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3041 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3042 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3043 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3044 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3045 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3046
3047 if (htim->State == HAL_TIM_STATE_RESET)
3048 {
3049 /* Allocate lock resource and initialize it */
3050 htim->Lock = HAL_UNLOCKED;
3051
3052 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3053 /* Reset interrupt callbacks to legacy weak callbacks */
3054 TIM_ResetCallback(htim);
3055
3056 if (htim->Encoder_MspInitCallback == NULL)
3057 {
3058 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3059 }
3060 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3061 htim->Encoder_MspInitCallback(htim);
3062 #else
3063 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3064 HAL_TIM_Encoder_MspInit(htim);
3065 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3066 }
3067
3068 /* Set the TIM state */
3069 htim->State = HAL_TIM_STATE_BUSY;
3070
3071 /* Reset the SMS and ECE bits */
3072 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3073
3074 /* Configure the Time base in the Encoder Mode */
3075 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3076
3077 /* Get the TIMx SMCR register value */
3078 tmpsmcr = htim->Instance->SMCR;
3079
3080 /* Get the TIMx CCMR1 register value */
3081 tmpccmr1 = htim->Instance->CCMR1;
3082
3083 /* Get the TIMx CCER register value */
3084 tmpccer = htim->Instance->CCER;
3085
3086 /* Set the encoder Mode */
3087 tmpsmcr |= sConfig->EncoderMode;
3088
3089 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3090 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3091 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3092
3093 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3094 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3095 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3096 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3097 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3098
3099 /* Set the TI1 and the TI2 Polarities */
3100 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3101 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3102 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3103
3104 /* Write to TIMx SMCR */
3105 htim->Instance->SMCR = tmpsmcr;
3106
3107 /* Write to TIMx CCMR1 */
3108 htim->Instance->CCMR1 = tmpccmr1;
3109
3110 /* Write to TIMx CCER */
3111 htim->Instance->CCER = tmpccer;
3112
3113 /* Initialize the DMA burst operation state */
3114 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3115
3116 /* Set the TIM channels state */
3117 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3118 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3119 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3120 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3121
3122 /* Initialize the TIM state*/
3123 htim->State = HAL_TIM_STATE_READY;
3124
3125 return HAL_OK;
3126 }
3127
3128
3129 /**
3130 * @brief DeInitializes the TIM Encoder interface
3131 * @param htim TIM Encoder Interface handle
3132 * @retval HAL status
3133 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3134 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3135 {
3136 /* Check the parameters */
3137 assert_param(IS_TIM_INSTANCE(htim->Instance));
3138
3139 htim->State = HAL_TIM_STATE_BUSY;
3140
3141 /* Disable the TIM Peripheral Clock */
3142 __HAL_TIM_DISABLE(htim);
3143
3144 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3145 if (htim->Encoder_MspDeInitCallback == NULL)
3146 {
3147 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3148 }
3149 /* DeInit the low level hardware */
3150 htim->Encoder_MspDeInitCallback(htim);
3151 #else
3152 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3153 HAL_TIM_Encoder_MspDeInit(htim);
3154 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3155
3156 /* Change the DMA burst operation state */
3157 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3158
3159 /* Set the TIM channels state */
3160 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3161 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3162 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3163 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3164
3165 /* Change TIM state */
3166 htim->State = HAL_TIM_STATE_RESET;
3167
3168 /* Release Lock */
3169 __HAL_UNLOCK(htim);
3170
3171 return HAL_OK;
3172 }
3173
3174 /**
3175 * @brief Initializes the TIM Encoder Interface MSP.
3176 * @param htim TIM Encoder Interface handle
3177 * @retval None
3178 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3179 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3180 {
3181 /* Prevent unused argument(s) compilation warning */
3182 UNUSED(htim);
3183
3184 /* NOTE : This function should not be modified, when the callback is needed,
3185 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3186 */
3187 }
3188
3189 /**
3190 * @brief DeInitializes TIM Encoder Interface MSP.
3191 * @param htim TIM Encoder Interface handle
3192 * @retval None
3193 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3194 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3195 {
3196 /* Prevent unused argument(s) compilation warning */
3197 UNUSED(htim);
3198
3199 /* NOTE : This function should not be modified, when the callback is needed,
3200 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3201 */
3202 }
3203
3204 /**
3205 * @brief Starts the TIM Encoder Interface.
3206 * @param htim TIM Encoder Interface handle
3207 * @param Channel TIM Channels to be enabled
3208 * This parameter can be one of the following values:
3209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3211 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3212 * @retval HAL status
3213 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3214 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3215 {
3216 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3217 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3218 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3219 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3220
3221 /* Check the parameters */
3222 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3223
3224 /* Set the TIM channel(s) state */
3225 if (Channel == TIM_CHANNEL_1)
3226 {
3227 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3228 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3229 {
3230 return HAL_ERROR;
3231 }
3232 else
3233 {
3234 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3235 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3236 }
3237 }
3238 else if (Channel == TIM_CHANNEL_2)
3239 {
3240 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3241 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3242 {
3243 return HAL_ERROR;
3244 }
3245 else
3246 {
3247 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3248 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3249 }
3250 }
3251 else
3252 {
3253 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3254 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3255 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3256 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3257 {
3258 return HAL_ERROR;
3259 }
3260 else
3261 {
3262 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3263 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3264 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3265 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3266 }
3267 }
3268
3269 /* Enable the encoder interface channels */
3270 switch (Channel)
3271 {
3272 case TIM_CHANNEL_1:
3273 {
3274 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3275 break;
3276 }
3277
3278 case TIM_CHANNEL_2:
3279 {
3280 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3281 break;
3282 }
3283
3284 default :
3285 {
3286 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3287 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3288 break;
3289 }
3290 }
3291 /* Enable the Peripheral */
3292 __HAL_TIM_ENABLE(htim);
3293
3294 /* Return function status */
3295 return HAL_OK;
3296 }
3297
3298 /**
3299 * @brief Stops the TIM Encoder Interface.
3300 * @param htim TIM Encoder Interface handle
3301 * @param Channel TIM Channels to be disabled
3302 * This parameter can be one of the following values:
3303 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3304 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3305 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3306 * @retval HAL status
3307 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3308 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3309 {
3310 /* Check the parameters */
3311 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3312
3313 /* Disable the Input Capture channels 1 and 2
3314 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3315 switch (Channel)
3316 {
3317 case TIM_CHANNEL_1:
3318 {
3319 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3320 break;
3321 }
3322
3323 case TIM_CHANNEL_2:
3324 {
3325 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3326 break;
3327 }
3328
3329 default :
3330 {
3331 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3332 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3333 break;
3334 }
3335 }
3336
3337 /* Disable the Peripheral */
3338 __HAL_TIM_DISABLE(htim);
3339
3340 /* Set the TIM channel(s) state */
3341 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3342 {
3343 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3344 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3345 }
3346 else
3347 {
3348 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3349 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3350 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3351 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3352 }
3353
3354 /* Return function status */
3355 return HAL_OK;
3356 }
3357
3358 /**
3359 * @brief Starts the TIM Encoder Interface in interrupt mode.
3360 * @param htim TIM Encoder Interface handle
3361 * @param Channel TIM Channels to be enabled
3362 * This parameter can be one of the following values:
3363 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3364 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3365 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3366 * @retval HAL status
3367 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3368 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3369 {
3370 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3371 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3372 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3373 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3374
3375 /* Check the parameters */
3376 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3377
3378 /* Set the TIM channel(s) state */
3379 if (Channel == TIM_CHANNEL_1)
3380 {
3381 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3382 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3383 {
3384 return HAL_ERROR;
3385 }
3386 else
3387 {
3388 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3389 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3390 }
3391 }
3392 else if (Channel == TIM_CHANNEL_2)
3393 {
3394 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3395 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3396 {
3397 return HAL_ERROR;
3398 }
3399 else
3400 {
3401 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3402 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3403 }
3404 }
3405 else
3406 {
3407 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3408 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3409 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3410 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3411 {
3412 return HAL_ERROR;
3413 }
3414 else
3415 {
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3417 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3418 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3419 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3420 }
3421 }
3422
3423 /* Enable the encoder interface channels */
3424 /* Enable the capture compare Interrupts 1 and/or 2 */
3425 switch (Channel)
3426 {
3427 case TIM_CHANNEL_1:
3428 {
3429 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3430 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3431 break;
3432 }
3433
3434 case TIM_CHANNEL_2:
3435 {
3436 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3438 break;
3439 }
3440
3441 default :
3442 {
3443 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3446 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3447 break;
3448 }
3449 }
3450
3451 /* Enable the Peripheral */
3452 __HAL_TIM_ENABLE(htim);
3453
3454 /* Return function status */
3455 return HAL_OK;
3456 }
3457
3458 /**
3459 * @brief Stops the TIM Encoder Interface in interrupt mode.
3460 * @param htim TIM Encoder Interface handle
3461 * @param Channel TIM Channels to be disabled
3462 * This parameter can be one of the following values:
3463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3465 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3466 * @retval HAL status
3467 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3468 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3469 {
3470 /* Check the parameters */
3471 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3472
3473 /* Disable the Input Capture channels 1 and 2
3474 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3475 if (Channel == TIM_CHANNEL_1)
3476 {
3477 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3478
3479 /* Disable the capture compare Interrupts 1 */
3480 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3481 }
3482 else if (Channel == TIM_CHANNEL_2)
3483 {
3484 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3485
3486 /* Disable the capture compare Interrupts 2 */
3487 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3488 }
3489 else
3490 {
3491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3493
3494 /* Disable the capture compare Interrupts 1 and 2 */
3495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3496 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3497 }
3498
3499 /* Disable the Peripheral */
3500 __HAL_TIM_DISABLE(htim);
3501
3502 /* Set the TIM channel(s) state */
3503 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3504 {
3505 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3506 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3507 }
3508 else
3509 {
3510 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3511 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3512 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3513 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3514 }
3515
3516 /* Return function status */
3517 return HAL_OK;
3518 }
3519
3520 /**
3521 * @brief Starts the TIM Encoder Interface in DMA mode.
3522 * @param htim TIM Encoder Interface handle
3523 * @param Channel TIM Channels to be enabled
3524 * This parameter can be one of the following values:
3525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3527 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3528 * @param pData1 The destination Buffer address for IC1.
3529 * @param pData2 The destination Buffer address for IC2.
3530 * @param Length The length of data to be transferred from TIM peripheral to memory.
3531 * @retval HAL status
3532 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3533 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3534 uint32_t *pData2, uint16_t Length)
3535 {
3536 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3537 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3538 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3539 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3540
3541 /* Check the parameters */
3542 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3543
3544 /* Set the TIM channel(s) state */
3545 if (Channel == TIM_CHANNEL_1)
3546 {
3547 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3548 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3549 {
3550 return HAL_BUSY;
3551 }
3552 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3553 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3554 {
3555 if ((pData1 == NULL) || (Length == 0U))
3556 {
3557 return HAL_ERROR;
3558 }
3559 else
3560 {
3561 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3562 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3563 }
3564 }
3565 else
3566 {
3567 return HAL_ERROR;
3568 }
3569 }
3570 else if (Channel == TIM_CHANNEL_2)
3571 {
3572 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3573 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3574 {
3575 return HAL_BUSY;
3576 }
3577 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3578 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3579 {
3580 if ((pData2 == NULL) || (Length == 0U))
3581 {
3582 return HAL_ERROR;
3583 }
3584 else
3585 {
3586 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3587 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3588 }
3589 }
3590 else
3591 {
3592 return HAL_ERROR;
3593 }
3594 }
3595 else
3596 {
3597 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3598 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3599 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3600 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3601 {
3602 return HAL_BUSY;
3603 }
3604 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3605 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3606 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3607 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3608 {
3609 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3610 {
3611 return HAL_ERROR;
3612 }
3613 else
3614 {
3615 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3616 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3617 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3618 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3619 }
3620 }
3621 else
3622 {
3623 return HAL_ERROR;
3624 }
3625 }
3626
3627 switch (Channel)
3628 {
3629 case TIM_CHANNEL_1:
3630 {
3631 /* Set the DMA capture callbacks */
3632 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3633 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3634
3635 /* Set the DMA error callback */
3636 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3637
3638 /* Enable the DMA channel */
3639 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3640 Length) != HAL_OK)
3641 {
3642 /* Return error status */
3643 return HAL_ERROR;
3644 }
3645 /* Enable the TIM Input Capture DMA request */
3646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3647
3648 /* Enable the Capture compare channel */
3649 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3650
3651 /* Enable the Peripheral */
3652 __HAL_TIM_ENABLE(htim);
3653
3654 break;
3655 }
3656
3657 case TIM_CHANNEL_2:
3658 {
3659 /* Set the DMA capture callbacks */
3660 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3661 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3662
3663 /* Set the DMA error callback */
3664 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3665 /* Enable the DMA channel */
3666 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3667 Length) != HAL_OK)
3668 {
3669 /* Return error status */
3670 return HAL_ERROR;
3671 }
3672 /* Enable the TIM Input Capture DMA request */
3673 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3674
3675 /* Enable the Capture compare channel */
3676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3677
3678 /* Enable the Peripheral */
3679 __HAL_TIM_ENABLE(htim);
3680
3681 break;
3682 }
3683
3684 default:
3685 {
3686 /* Set the DMA capture callbacks */
3687 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3688 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3689
3690 /* Set the DMA error callback */
3691 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3692
3693 /* Enable the DMA channel */
3694 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3695 Length) != HAL_OK)
3696 {
3697 /* Return error status */
3698 return HAL_ERROR;
3699 }
3700
3701 /* Set the DMA capture callbacks */
3702 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3703 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3704
3705 /* Set the DMA error callback */
3706 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3707
3708 /* Enable the DMA channel */
3709 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3710 Length) != HAL_OK)
3711 {
3712 /* Return error status */
3713 return HAL_ERROR;
3714 }
3715
3716 /* Enable the TIM Input Capture DMA request */
3717 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3718 /* Enable the TIM Input Capture DMA request */
3719 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3720
3721 /* Enable the Capture compare channel */
3722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3723 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3724
3725 /* Enable the Peripheral */
3726 __HAL_TIM_ENABLE(htim);
3727
3728 break;
3729 }
3730 }
3731
3732 /* Return function status */
3733 return HAL_OK;
3734 }
3735
3736 /**
3737 * @brief Stops the TIM Encoder Interface in DMA mode.
3738 * @param htim TIM Encoder Interface handle
3739 * @param Channel TIM Channels to be enabled
3740 * This parameter can be one of the following values:
3741 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3742 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3743 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3744 * @retval HAL status
3745 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3746 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3747 {
3748 /* Check the parameters */
3749 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3750
3751 /* Disable the Input Capture channels 1 and 2
3752 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3753 if (Channel == TIM_CHANNEL_1)
3754 {
3755 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3756
3757 /* Disable the capture compare DMA Request 1 */
3758 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3759 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3760 }
3761 else if (Channel == TIM_CHANNEL_2)
3762 {
3763 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3764
3765 /* Disable the capture compare DMA Request 2 */
3766 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3767 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3768 }
3769 else
3770 {
3771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3772 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3773
3774 /* Disable the capture compare DMA Request 1 and 2 */
3775 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3776 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3777 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3779 }
3780
3781 /* Disable the Peripheral */
3782 __HAL_TIM_DISABLE(htim);
3783
3784 /* Set the TIM channel(s) state */
3785 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3786 {
3787 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3788 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3789 }
3790 else
3791 {
3792 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3793 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3794 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3795 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3796 }
3797
3798 /* Return function status */
3799 return HAL_OK;
3800 }
3801
3802 /**
3803 * @}
3804 */
3805 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3806 * @brief TIM IRQ handler management
3807 *
3808 @verbatim
3809 ==============================================================================
3810 ##### IRQ handler management #####
3811 ==============================================================================
3812 [..]
3813 This section provides Timer IRQ handler function.
3814
3815 @endverbatim
3816 * @{
3817 */
3818 /**
3819 * @brief This function handles TIM interrupts requests.
3820 * @param htim TIM handle
3821 * @retval None
3822 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3823 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3824 {
3825 /* Capture compare 1 event */
3826 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3827 {
3828 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3829 {
3830 {
3831 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3832 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3833
3834 /* Input capture event */
3835 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3836 {
3837 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3838 htim->IC_CaptureCallback(htim);
3839 #else
3840 HAL_TIM_IC_CaptureCallback(htim);
3841 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3842 }
3843 /* Output compare event */
3844 else
3845 {
3846 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3847 htim->OC_DelayElapsedCallback(htim);
3848 htim->PWM_PulseFinishedCallback(htim);
3849 #else
3850 HAL_TIM_OC_DelayElapsedCallback(htim);
3851 HAL_TIM_PWM_PulseFinishedCallback(htim);
3852 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3853 }
3854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3855 }
3856 }
3857 }
3858 /* Capture compare 2 event */
3859 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3860 {
3861 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3862 {
3863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3865 /* Input capture event */
3866 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3867 {
3868 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3869 htim->IC_CaptureCallback(htim);
3870 #else
3871 HAL_TIM_IC_CaptureCallback(htim);
3872 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3873 }
3874 /* Output compare event */
3875 else
3876 {
3877 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3878 htim->OC_DelayElapsedCallback(htim);
3879 htim->PWM_PulseFinishedCallback(htim);
3880 #else
3881 HAL_TIM_OC_DelayElapsedCallback(htim);
3882 HAL_TIM_PWM_PulseFinishedCallback(htim);
3883 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3884 }
3885 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3886 }
3887 }
3888 /* Capture compare 3 event */
3889 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3890 {
3891 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3892 {
3893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3894 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3895 /* Input capture event */
3896 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3897 {
3898 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3899 htim->IC_CaptureCallback(htim);
3900 #else
3901 HAL_TIM_IC_CaptureCallback(htim);
3902 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3903 }
3904 /* Output compare event */
3905 else
3906 {
3907 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3908 htim->OC_DelayElapsedCallback(htim);
3909 htim->PWM_PulseFinishedCallback(htim);
3910 #else
3911 HAL_TIM_OC_DelayElapsedCallback(htim);
3912 HAL_TIM_PWM_PulseFinishedCallback(htim);
3913 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3914 }
3915 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3916 }
3917 }
3918 /* Capture compare 4 event */
3919 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3920 {
3921 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3922 {
3923 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3924 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3925 /* Input capture event */
3926 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3927 {
3928 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3929 htim->IC_CaptureCallback(htim);
3930 #else
3931 HAL_TIM_IC_CaptureCallback(htim);
3932 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3933 }
3934 /* Output compare event */
3935 else
3936 {
3937 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3938 htim->OC_DelayElapsedCallback(htim);
3939 htim->PWM_PulseFinishedCallback(htim);
3940 #else
3941 HAL_TIM_OC_DelayElapsedCallback(htim);
3942 HAL_TIM_PWM_PulseFinishedCallback(htim);
3943 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3944 }
3945 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3946 }
3947 }
3948 /* TIM Update event */
3949 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3950 {
3951 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3952 {
3953 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3955 htim->PeriodElapsedCallback(htim);
3956 #else
3957 HAL_TIM_PeriodElapsedCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959 }
3960 }
3961 /* TIM Break input event */
3962 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3963 {
3964 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3965 {
3966 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3967 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3968 htim->BreakCallback(htim);
3969 #else
3970 HAL_TIMEx_BreakCallback(htim);
3971 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3972 }
3973 }
3974 /* TIM Trigger detection event */
3975 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3976 {
3977 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3978 {
3979 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3981 htim->TriggerCallback(htim);
3982 #else
3983 HAL_TIM_TriggerCallback(htim);
3984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3985 }
3986 }
3987 /* TIM commutation event */
3988 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3989 {
3990 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3991 {
3992 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3993 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3994 htim->CommutationCallback(htim);
3995 #else
3996 HAL_TIMEx_CommutCallback(htim);
3997 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3998 }
3999 }
4000 }
4001
4002 /**
4003 * @}
4004 */
4005
4006 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4007 * @brief TIM Peripheral Control functions
4008 *
4009 @verbatim
4010 ==============================================================================
4011 ##### Peripheral Control functions #####
4012 ==============================================================================
4013 [..]
4014 This section provides functions allowing to:
4015 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4016 (+) Configure External Clock source.
4017 (+) Configure Complementary channels, break features and dead time.
4018 (+) Configure Master and the Slave synchronization.
4019 (+) Configure the DMA Burst Mode.
4020
4021 @endverbatim
4022 * @{
4023 */
4024
4025 /**
4026 * @brief Initializes the TIM Output Compare Channels according to the specified
4027 * parameters in the TIM_OC_InitTypeDef.
4028 * @param htim TIM Output Compare handle
4029 * @param sConfig TIM Output Compare configuration structure
4030 * @param Channel TIM Channels to configure
4031 * This parameter can be one of the following values:
4032 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4033 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4034 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4035 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4036 * @retval HAL status
4037 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4038 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4039 const TIM_OC_InitTypeDef *sConfig,
4040 uint32_t Channel)
4041 {
4042 HAL_StatusTypeDef status = HAL_OK;
4043
4044 /* Check the parameters */
4045 assert_param(IS_TIM_CHANNELS(Channel));
4046 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
4047 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4048
4049 /* Process Locked */
4050 __HAL_LOCK(htim);
4051
4052 switch (Channel)
4053 {
4054 case TIM_CHANNEL_1:
4055 {
4056 /* Check the parameters */
4057 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4058
4059 /* Configure the TIM Channel 1 in Output Compare */
4060 TIM_OC1_SetConfig(htim->Instance, sConfig);
4061 break;
4062 }
4063
4064 case TIM_CHANNEL_2:
4065 {
4066 /* Check the parameters */
4067 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4068
4069 /* Configure the TIM Channel 2 in Output Compare */
4070 TIM_OC2_SetConfig(htim->Instance, sConfig);
4071 break;
4072 }
4073
4074 case TIM_CHANNEL_3:
4075 {
4076 /* Check the parameters */
4077 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4078
4079 /* Configure the TIM Channel 3 in Output Compare */
4080 TIM_OC3_SetConfig(htim->Instance, sConfig);
4081 break;
4082 }
4083
4084 case TIM_CHANNEL_4:
4085 {
4086 /* Check the parameters */
4087 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4088
4089 /* Configure the TIM Channel 4 in Output Compare */
4090 TIM_OC4_SetConfig(htim->Instance, sConfig);
4091 break;
4092 }
4093
4094 default:
4095 status = HAL_ERROR;
4096 break;
4097 }
4098
4099 __HAL_UNLOCK(htim);
4100
4101 return status;
4102 }
4103
4104 /**
4105 * @brief Initializes the TIM Input Capture Channels according to the specified
4106 * parameters in the TIM_IC_InitTypeDef.
4107 * @param htim TIM IC handle
4108 * @param sConfig TIM Input Capture configuration structure
4109 * @param Channel TIM Channel to configure
4110 * This parameter can be one of the following values:
4111 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4112 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4113 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4114 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4115 * @retval HAL status
4116 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4117 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4118 {
4119 HAL_StatusTypeDef status = HAL_OK;
4120
4121 /* Check the parameters */
4122 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4123 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4124 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4125 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4126 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4127
4128 /* Process Locked */
4129 __HAL_LOCK(htim);
4130
4131 if (Channel == TIM_CHANNEL_1)
4132 {
4133 /* TI1 Configuration */
4134 TIM_TI1_SetConfig(htim->Instance,
4135 sConfig->ICPolarity,
4136 sConfig->ICSelection,
4137 sConfig->ICFilter);
4138
4139 /* Reset the IC1PSC Bits */
4140 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4141
4142 /* Set the IC1PSC value */
4143 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4144 }
4145 else if (Channel == TIM_CHANNEL_2)
4146 {
4147 /* TI2 Configuration */
4148 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4149
4150 TIM_TI2_SetConfig(htim->Instance,
4151 sConfig->ICPolarity,
4152 sConfig->ICSelection,
4153 sConfig->ICFilter);
4154
4155 /* Reset the IC2PSC Bits */
4156 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4157
4158 /* Set the IC2PSC value */
4159 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4160 }
4161 else if (Channel == TIM_CHANNEL_3)
4162 {
4163 /* TI3 Configuration */
4164 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4165
4166 TIM_TI3_SetConfig(htim->Instance,
4167 sConfig->ICPolarity,
4168 sConfig->ICSelection,
4169 sConfig->ICFilter);
4170
4171 /* Reset the IC3PSC Bits */
4172 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4173
4174 /* Set the IC3PSC value */
4175 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4176 }
4177 else if (Channel == TIM_CHANNEL_4)
4178 {
4179 /* TI4 Configuration */
4180 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4181
4182 TIM_TI4_SetConfig(htim->Instance,
4183 sConfig->ICPolarity,
4184 sConfig->ICSelection,
4185 sConfig->ICFilter);
4186
4187 /* Reset the IC4PSC Bits */
4188 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4189
4190 /* Set the IC4PSC value */
4191 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4192 }
4193 else
4194 {
4195 status = HAL_ERROR;
4196 }
4197
4198 __HAL_UNLOCK(htim);
4199
4200 return status;
4201 }
4202
4203 /**
4204 * @brief Initializes the TIM PWM channels according to the specified
4205 * parameters in the TIM_OC_InitTypeDef.
4206 * @param htim TIM PWM handle
4207 * @param sConfig TIM PWM configuration structure
4208 * @param Channel TIM Channels to be configured
4209 * This parameter can be one of the following values:
4210 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4211 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4212 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4213 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4214 * @retval HAL status
4215 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4216 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4217 const TIM_OC_InitTypeDef *sConfig,
4218 uint32_t Channel)
4219 {
4220 HAL_StatusTypeDef status = HAL_OK;
4221
4222 /* Check the parameters */
4223 assert_param(IS_TIM_CHANNELS(Channel));
4224 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4225 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4226 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4227
4228 /* Process Locked */
4229 __HAL_LOCK(htim);
4230
4231 switch (Channel)
4232 {
4233 case TIM_CHANNEL_1:
4234 {
4235 /* Check the parameters */
4236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4237
4238 /* Configure the Channel 1 in PWM mode */
4239 TIM_OC1_SetConfig(htim->Instance, sConfig);
4240
4241 /* Set the Preload enable bit for channel1 */
4242 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4243
4244 /* Configure the Output Fast mode */
4245 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4246 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4247 break;
4248 }
4249
4250 case TIM_CHANNEL_2:
4251 {
4252 /* Check the parameters */
4253 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4254
4255 /* Configure the Channel 2 in PWM mode */
4256 TIM_OC2_SetConfig(htim->Instance, sConfig);
4257
4258 /* Set the Preload enable bit for channel2 */
4259 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4260
4261 /* Configure the Output Fast mode */
4262 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4263 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4264 break;
4265 }
4266
4267 case TIM_CHANNEL_3:
4268 {
4269 /* Check the parameters */
4270 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4271
4272 /* Configure the Channel 3 in PWM mode */
4273 TIM_OC3_SetConfig(htim->Instance, sConfig);
4274
4275 /* Set the Preload enable bit for channel3 */
4276 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4277
4278 /* Configure the Output Fast mode */
4279 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4280 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4281 break;
4282 }
4283
4284 case TIM_CHANNEL_4:
4285 {
4286 /* Check the parameters */
4287 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4288
4289 /* Configure the Channel 4 in PWM mode */
4290 TIM_OC4_SetConfig(htim->Instance, sConfig);
4291
4292 /* Set the Preload enable bit for channel4 */
4293 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4294
4295 /* Configure the Output Fast mode */
4296 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4297 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4298 break;
4299 }
4300
4301 default:
4302 status = HAL_ERROR;
4303 break;
4304 }
4305
4306 __HAL_UNLOCK(htim);
4307
4308 return status;
4309 }
4310
4311 /**
4312 * @brief Initializes the TIM One Pulse Channels according to the specified
4313 * parameters in the TIM_OnePulse_InitTypeDef.
4314 * @param htim TIM One Pulse handle
4315 * @param sConfig TIM One Pulse configuration structure
4316 * @param OutputChannel TIM output channel to configure
4317 * This parameter can be one of the following values:
4318 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4319 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4320 * @param InputChannel TIM input Channel to configure
4321 * This parameter can be one of the following values:
4322 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4323 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4324 * @note To output a waveform with a minimum delay user can enable the fast
4325 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4326 * output is forced in response to the edge detection on TIx input,
4327 * without taking in account the comparison.
4328 * @retval HAL status
4329 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4330 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4331 uint32_t OutputChannel, uint32_t InputChannel)
4332 {
4333 HAL_StatusTypeDef status = HAL_OK;
4334 TIM_OC_InitTypeDef temp1;
4335
4336 /* Check the parameters */
4337 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4338 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4339
4340 if (OutputChannel != InputChannel)
4341 {
4342 /* Process Locked */
4343 __HAL_LOCK(htim);
4344
4345 htim->State = HAL_TIM_STATE_BUSY;
4346
4347 /* Extract the Output compare configuration from sConfig structure */
4348 temp1.OCMode = sConfig->OCMode;
4349 temp1.Pulse = sConfig->Pulse;
4350 temp1.OCPolarity = sConfig->OCPolarity;
4351 temp1.OCNPolarity = sConfig->OCNPolarity;
4352 temp1.OCIdleState = sConfig->OCIdleState;
4353 temp1.OCNIdleState = sConfig->OCNIdleState;
4354
4355 switch (OutputChannel)
4356 {
4357 case TIM_CHANNEL_1:
4358 {
4359 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4360
4361 TIM_OC1_SetConfig(htim->Instance, &temp1);
4362 break;
4363 }
4364
4365 case TIM_CHANNEL_2:
4366 {
4367 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4368
4369 TIM_OC2_SetConfig(htim->Instance, &temp1);
4370 break;
4371 }
4372
4373 default:
4374 status = HAL_ERROR;
4375 break;
4376 }
4377
4378 if (status == HAL_OK)
4379 {
4380 switch (InputChannel)
4381 {
4382 case TIM_CHANNEL_1:
4383 {
4384 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4385
4386 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4387 sConfig->ICSelection, sConfig->ICFilter);
4388
4389 /* Reset the IC1PSC Bits */
4390 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4391
4392 /* Select the Trigger source */
4393 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4394 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4395
4396 /* Select the Slave Mode */
4397 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4398 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4399 break;
4400 }
4401
4402 case TIM_CHANNEL_2:
4403 {
4404 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4405
4406 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4407 sConfig->ICSelection, sConfig->ICFilter);
4408
4409 /* Reset the IC2PSC Bits */
4410 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4411
4412 /* Select the Trigger source */
4413 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4414 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4415
4416 /* Select the Slave Mode */
4417 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4418 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4419 break;
4420 }
4421
4422 default:
4423 status = HAL_ERROR;
4424 break;
4425 }
4426 }
4427
4428 htim->State = HAL_TIM_STATE_READY;
4429
4430 __HAL_UNLOCK(htim);
4431
4432 return status;
4433 }
4434 else
4435 {
4436 return HAL_ERROR;
4437 }
4438 }
4439
4440 /**
4441 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4442 * @param htim TIM handle
4443 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4444 * This parameter can be one of the following values:
4445 * @arg TIM_DMABASE_CR1
4446 * @arg TIM_DMABASE_CR2
4447 * @arg TIM_DMABASE_SMCR
4448 * @arg TIM_DMABASE_DIER
4449 * @arg TIM_DMABASE_SR
4450 * @arg TIM_DMABASE_EGR
4451 * @arg TIM_DMABASE_CCMR1
4452 * @arg TIM_DMABASE_CCMR2
4453 * @arg TIM_DMABASE_CCER
4454 * @arg TIM_DMABASE_CNT
4455 * @arg TIM_DMABASE_PSC
4456 * @arg TIM_DMABASE_ARR
4457 * @arg TIM_DMABASE_RCR
4458 * @arg TIM_DMABASE_CCR1
4459 * @arg TIM_DMABASE_CCR2
4460 * @arg TIM_DMABASE_CCR3
4461 * @arg TIM_DMABASE_CCR4
4462 * @arg TIM_DMABASE_BDTR
4463 * @param BurstRequestSrc TIM DMA Request sources
4464 * This parameter can be one of the following values:
4465 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4466 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4467 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4468 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4469 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4470 * @arg TIM_DMA_COM: TIM Commutation DMA source
4471 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4472 * @param BurstBuffer The Buffer address.
4473 * @param BurstLength DMA Burst length. This parameter can be one value
4474 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4475 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4476 * @retval HAL status
4477 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4478 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4479 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4480 {
4481 HAL_StatusTypeDef status;
4482
4483 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4484 ((BurstLength) >> 8U) + 1U);
4485
4486
4487
4488 return status;
4489 }
4490
4491 /**
4492 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4493 * @param htim TIM handle
4494 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4495 * This parameter can be one of the following values:
4496 * @arg TIM_DMABASE_CR1
4497 * @arg TIM_DMABASE_CR2
4498 * @arg TIM_DMABASE_SMCR
4499 * @arg TIM_DMABASE_DIER
4500 * @arg TIM_DMABASE_SR
4501 * @arg TIM_DMABASE_EGR
4502 * @arg TIM_DMABASE_CCMR1
4503 * @arg TIM_DMABASE_CCMR2
4504 * @arg TIM_DMABASE_CCER
4505 * @arg TIM_DMABASE_CNT
4506 * @arg TIM_DMABASE_PSC
4507 * @arg TIM_DMABASE_ARR
4508 * @arg TIM_DMABASE_RCR
4509 * @arg TIM_DMABASE_CCR1
4510 * @arg TIM_DMABASE_CCR2
4511 * @arg TIM_DMABASE_CCR3
4512 * @arg TIM_DMABASE_CCR4
4513 * @arg TIM_DMABASE_BDTR
4514 * @param BurstRequestSrc TIM DMA Request sources
4515 * This parameter can be one of the following values:
4516 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4517 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4518 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4519 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4520 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4521 * @arg TIM_DMA_COM: TIM Commutation DMA source
4522 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4523 * @param BurstBuffer The Buffer address.
4524 * @param BurstLength DMA Burst length. This parameter can be one value
4525 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4526 * @param DataLength Data length. This parameter can be one value
4527 * between 1 and 0xFFFF.
4528 * @retval HAL status
4529 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4530 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4531 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4532 uint32_t BurstLength, uint32_t DataLength)
4533 {
4534 HAL_StatusTypeDef status = HAL_OK;
4535
4536 /* Check the parameters */
4537 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4538 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4539 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4540 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4541 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4542
4543 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4544 {
4545 return HAL_BUSY;
4546 }
4547 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4548 {
4549 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4550 {
4551 return HAL_ERROR;
4552 }
4553 else
4554 {
4555 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4556 }
4557 }
4558 else
4559 {
4560 /* nothing to do */
4561 }
4562
4563 switch (BurstRequestSrc)
4564 {
4565 case TIM_DMA_UPDATE:
4566 {
4567 /* Set the DMA Period elapsed callbacks */
4568 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4569 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4570
4571 /* Set the DMA error callback */
4572 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4573
4574 /* Enable the DMA channel */
4575 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4576 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4577 {
4578 /* Return error status */
4579 return HAL_ERROR;
4580 }
4581 break;
4582 }
4583 case TIM_DMA_CC1:
4584 {
4585 /* Set the DMA compare callbacks */
4586 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4587 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4588
4589 /* Set the DMA error callback */
4590 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4591
4592 /* Enable the DMA channel */
4593 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4594 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4595 {
4596 /* Return error status */
4597 return HAL_ERROR;
4598 }
4599 break;
4600 }
4601 case TIM_DMA_CC2:
4602 {
4603 /* Set the DMA compare callbacks */
4604 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4605 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4606
4607 /* Set the DMA error callback */
4608 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4609
4610 /* Enable the DMA channel */
4611 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4612 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4613 {
4614 /* Return error status */
4615 return HAL_ERROR;
4616 }
4617 break;
4618 }
4619 case TIM_DMA_CC3:
4620 {
4621 /* Set the DMA compare callbacks */
4622 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4623 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4624
4625 /* Set the DMA error callback */
4626 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4627
4628 /* Enable the DMA channel */
4629 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4630 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4631 {
4632 /* Return error status */
4633 return HAL_ERROR;
4634 }
4635 break;
4636 }
4637 case TIM_DMA_CC4:
4638 {
4639 /* Set the DMA compare callbacks */
4640 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4641 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4642
4643 /* Set the DMA error callback */
4644 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4645
4646 /* Enable the DMA channel */
4647 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4648 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4649 {
4650 /* Return error status */
4651 return HAL_ERROR;
4652 }
4653 break;
4654 }
4655 case TIM_DMA_COM:
4656 {
4657 /* Set the DMA commutation callbacks */
4658 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4659 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4660
4661 /* Set the DMA error callback */
4662 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4663
4664 /* Enable the DMA channel */
4665 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4666 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4667 {
4668 /* Return error status */
4669 return HAL_ERROR;
4670 }
4671 break;
4672 }
4673 case TIM_DMA_TRIGGER:
4674 {
4675 /* Set the DMA trigger callbacks */
4676 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4677 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4678
4679 /* Set the DMA error callback */
4680 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4681
4682 /* Enable the DMA channel */
4683 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4684 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4685 {
4686 /* Return error status */
4687 return HAL_ERROR;
4688 }
4689 break;
4690 }
4691 default:
4692 status = HAL_ERROR;
4693 break;
4694 }
4695
4696 if (status == HAL_OK)
4697 {
4698 /* Configure the DMA Burst Mode */
4699 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4700 /* Enable the TIM DMA Request */
4701 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4702 }
4703
4704 /* Return function status */
4705 return status;
4706 }
4707
4708 /**
4709 * @brief Stops the TIM DMA Burst mode
4710 * @param htim TIM handle
4711 * @param BurstRequestSrc TIM DMA Request sources to disable
4712 * @retval HAL status
4713 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4714 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4715 {
4716 HAL_StatusTypeDef status = HAL_OK;
4717
4718 /* Check the parameters */
4719 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4720
4721 /* Abort the DMA transfer (at least disable the DMA channel) */
4722 switch (BurstRequestSrc)
4723 {
4724 case TIM_DMA_UPDATE:
4725 {
4726 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4727 break;
4728 }
4729 case TIM_DMA_CC1:
4730 {
4731 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4732 break;
4733 }
4734 case TIM_DMA_CC2:
4735 {
4736 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4737 break;
4738 }
4739 case TIM_DMA_CC3:
4740 {
4741 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4742 break;
4743 }
4744 case TIM_DMA_CC4:
4745 {
4746 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4747 break;
4748 }
4749 case TIM_DMA_COM:
4750 {
4751 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4752 break;
4753 }
4754 case TIM_DMA_TRIGGER:
4755 {
4756 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4757 break;
4758 }
4759 default:
4760 status = HAL_ERROR;
4761 break;
4762 }
4763
4764 if (status == HAL_OK)
4765 {
4766 /* Disable the TIM Update DMA request */
4767 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4768
4769 /* Change the DMA burst operation state */
4770 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4771 }
4772
4773 /* Return function status */
4774 return status;
4775 }
4776
4777 /**
4778 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4779 * @param htim TIM handle
4780 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4781 * This parameter can be one of the following values:
4782 * @arg TIM_DMABASE_CR1
4783 * @arg TIM_DMABASE_CR2
4784 * @arg TIM_DMABASE_SMCR
4785 * @arg TIM_DMABASE_DIER
4786 * @arg TIM_DMABASE_SR
4787 * @arg TIM_DMABASE_EGR
4788 * @arg TIM_DMABASE_CCMR1
4789 * @arg TIM_DMABASE_CCMR2
4790 * @arg TIM_DMABASE_CCER
4791 * @arg TIM_DMABASE_CNT
4792 * @arg TIM_DMABASE_PSC
4793 * @arg TIM_DMABASE_ARR
4794 * @arg TIM_DMABASE_RCR
4795 * @arg TIM_DMABASE_CCR1
4796 * @arg TIM_DMABASE_CCR2
4797 * @arg TIM_DMABASE_CCR3
4798 * @arg TIM_DMABASE_CCR4
4799 * @arg TIM_DMABASE_BDTR
4800 * @param BurstRequestSrc TIM DMA Request sources
4801 * This parameter can be one of the following values:
4802 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4803 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4804 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4805 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4806 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4807 * @arg TIM_DMA_COM: TIM Commutation DMA source
4808 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4809 * @param BurstBuffer The Buffer address.
4810 * @param BurstLength DMA Burst length. This parameter can be one value
4811 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4812 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4813 * @retval HAL status
4814 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4815 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4816 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4817 {
4818 HAL_StatusTypeDef status;
4819
4820 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4821 ((BurstLength) >> 8U) + 1U);
4822
4823
4824 return status;
4825 }
4826
4827 /**
4828 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4829 * @param htim TIM handle
4830 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4831 * This parameter can be one of the following values:
4832 * @arg TIM_DMABASE_CR1
4833 * @arg TIM_DMABASE_CR2
4834 * @arg TIM_DMABASE_SMCR
4835 * @arg TIM_DMABASE_DIER
4836 * @arg TIM_DMABASE_SR
4837 * @arg TIM_DMABASE_EGR
4838 * @arg TIM_DMABASE_CCMR1
4839 * @arg TIM_DMABASE_CCMR2
4840 * @arg TIM_DMABASE_CCER
4841 * @arg TIM_DMABASE_CNT
4842 * @arg TIM_DMABASE_PSC
4843 * @arg TIM_DMABASE_ARR
4844 * @arg TIM_DMABASE_RCR
4845 * @arg TIM_DMABASE_CCR1
4846 * @arg TIM_DMABASE_CCR2
4847 * @arg TIM_DMABASE_CCR3
4848 * @arg TIM_DMABASE_CCR4
4849 * @arg TIM_DMABASE_BDTR
4850 * @param BurstRequestSrc TIM DMA Request sources
4851 * This parameter can be one of the following values:
4852 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4853 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4854 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4855 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4856 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4857 * @arg TIM_DMA_COM: TIM Commutation DMA source
4858 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4859 * @param BurstBuffer The Buffer address.
4860 * @param BurstLength DMA Burst length. This parameter can be one value
4861 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4862 * @param DataLength Data length. This parameter can be one value
4863 * between 1 and 0xFFFF.
4864 * @retval HAL status
4865 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4866 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4867 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4868 uint32_t BurstLength, uint32_t DataLength)
4869 {
4870 HAL_StatusTypeDef status = HAL_OK;
4871
4872 /* Check the parameters */
4873 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4874 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4875 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4876 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4877 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4878
4879 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4880 {
4881 return HAL_BUSY;
4882 }
4883 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4884 {
4885 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4886 {
4887 return HAL_ERROR;
4888 }
4889 else
4890 {
4891 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4892 }
4893 }
4894 else
4895 {
4896 /* nothing to do */
4897 }
4898 switch (BurstRequestSrc)
4899 {
4900 case TIM_DMA_UPDATE:
4901 {
4902 /* Set the DMA Period elapsed callbacks */
4903 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4904 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4905
4906 /* Set the DMA error callback */
4907 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4908
4909 /* Enable the DMA channel */
4910 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4911 DataLength) != HAL_OK)
4912 {
4913 /* Return error status */
4914 return HAL_ERROR;
4915 }
4916 break;
4917 }
4918 case TIM_DMA_CC1:
4919 {
4920 /* Set the DMA capture callbacks */
4921 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4922 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4923
4924 /* Set the DMA error callback */
4925 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4926
4927 /* Enable the DMA channel */
4928 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4929 DataLength) != HAL_OK)
4930 {
4931 /* Return error status */
4932 return HAL_ERROR;
4933 }
4934 break;
4935 }
4936 case TIM_DMA_CC2:
4937 {
4938 /* Set the DMA capture callbacks */
4939 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4940 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4941
4942 /* Set the DMA error callback */
4943 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4944
4945 /* Enable the DMA channel */
4946 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4947 DataLength) != HAL_OK)
4948 {
4949 /* Return error status */
4950 return HAL_ERROR;
4951 }
4952 break;
4953 }
4954 case TIM_DMA_CC3:
4955 {
4956 /* Set the DMA capture callbacks */
4957 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4958 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4959
4960 /* Set the DMA error callback */
4961 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4962
4963 /* Enable the DMA channel */
4964 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4965 DataLength) != HAL_OK)
4966 {
4967 /* Return error status */
4968 return HAL_ERROR;
4969 }
4970 break;
4971 }
4972 case TIM_DMA_CC4:
4973 {
4974 /* Set the DMA capture callbacks */
4975 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4976 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4977
4978 /* Set the DMA error callback */
4979 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4980
4981 /* Enable the DMA channel */
4982 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4983 DataLength) != HAL_OK)
4984 {
4985 /* Return error status */
4986 return HAL_ERROR;
4987 }
4988 break;
4989 }
4990 case TIM_DMA_COM:
4991 {
4992 /* Set the DMA commutation callbacks */
4993 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4994 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4995
4996 /* Set the DMA error callback */
4997 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4998
4999 /* Enable the DMA channel */
5000 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5001 DataLength) != HAL_OK)
5002 {
5003 /* Return error status */
5004 return HAL_ERROR;
5005 }
5006 break;
5007 }
5008 case TIM_DMA_TRIGGER:
5009 {
5010 /* Set the DMA trigger callbacks */
5011 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5012 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5013
5014 /* Set the DMA error callback */
5015 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5016
5017 /* Enable the DMA channel */
5018 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5019 DataLength) != HAL_OK)
5020 {
5021 /* Return error status */
5022 return HAL_ERROR;
5023 }
5024 break;
5025 }
5026 default:
5027 status = HAL_ERROR;
5028 break;
5029 }
5030
5031 if (status == HAL_OK)
5032 {
5033 /* Configure the DMA Burst Mode */
5034 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
5035
5036 /* Enable the TIM DMA Request */
5037 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5038 }
5039
5040 /* Return function status */
5041 return status;
5042 }
5043
5044 /**
5045 * @brief Stop the DMA burst reading
5046 * @param htim TIM handle
5047 * @param BurstRequestSrc TIM DMA Request sources to disable.
5048 * @retval HAL status
5049 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5050 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5051 {
5052 HAL_StatusTypeDef status = HAL_OK;
5053
5054 /* Check the parameters */
5055 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5056
5057 /* Abort the DMA transfer (at least disable the DMA channel) */
5058 switch (BurstRequestSrc)
5059 {
5060 case TIM_DMA_UPDATE:
5061 {
5062 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5063 break;
5064 }
5065 case TIM_DMA_CC1:
5066 {
5067 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5068 break;
5069 }
5070 case TIM_DMA_CC2:
5071 {
5072 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5073 break;
5074 }
5075 case TIM_DMA_CC3:
5076 {
5077 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5078 break;
5079 }
5080 case TIM_DMA_CC4:
5081 {
5082 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5083 break;
5084 }
5085 case TIM_DMA_COM:
5086 {
5087 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5088 break;
5089 }
5090 case TIM_DMA_TRIGGER:
5091 {
5092 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5093 break;
5094 }
5095 default:
5096 status = HAL_ERROR;
5097 break;
5098 }
5099
5100 if (status == HAL_OK)
5101 {
5102 /* Disable the TIM Update DMA request */
5103 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5104
5105 /* Change the DMA burst operation state */
5106 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5107 }
5108
5109 /* Return function status */
5110 return status;
5111 }
5112
5113 /**
5114 * @brief Generate a software event
5115 * @param htim TIM handle
5116 * @param EventSource specifies the event source.
5117 * This parameter can be one of the following values:
5118 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5119 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5120 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5121 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5122 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5123 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5124 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5125 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5126 * @note Basic timers can only generate an update event.
5127 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5128 * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
5129 * supporting a break input.
5130 * @retval HAL status
5131 */
5132
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5133 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5134 {
5135 /* Check the parameters */
5136 assert_param(IS_TIM_INSTANCE(htim->Instance));
5137 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5138
5139 /* Process Locked */
5140 __HAL_LOCK(htim);
5141
5142 /* Change the TIM state */
5143 htim->State = HAL_TIM_STATE_BUSY;
5144
5145 /* Set the event sources */
5146 htim->Instance->EGR = EventSource;
5147
5148 /* Change the TIM state */
5149 htim->State = HAL_TIM_STATE_READY;
5150
5151 __HAL_UNLOCK(htim);
5152
5153 /* Return function status */
5154 return HAL_OK;
5155 }
5156
5157 /**
5158 * @brief Configures the OCRef clear feature
5159 * @param htim TIM handle
5160 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5161 * contains the OCREF clear feature and parameters for the TIM peripheral.
5162 * @param Channel specifies the TIM Channel
5163 * This parameter can be one of the following values:
5164 * @arg TIM_CHANNEL_1: TIM Channel 1
5165 * @arg TIM_CHANNEL_2: TIM Channel 2
5166 * @arg TIM_CHANNEL_3: TIM Channel 3
5167 * @arg TIM_CHANNEL_4: TIM Channel 4
5168 * @retval HAL status
5169 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5170 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5171 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5172 uint32_t Channel)
5173 {
5174 HAL_StatusTypeDef status = HAL_OK;
5175
5176 /* Check the parameters */
5177 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5178 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5179
5180 /* Process Locked */
5181 __HAL_LOCK(htim);
5182
5183 htim->State = HAL_TIM_STATE_BUSY;
5184
5185 switch (sClearInputConfig->ClearInputSource)
5186 {
5187 case TIM_CLEARINPUTSOURCE_NONE:
5188 {
5189 /* Clear the OCREF clear selection bit and the the ETR Bits */
5190 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5191 break;
5192 }
5193 case TIM_CLEARINPUTSOURCE_OCREFCLR:
5194 {
5195 /* Clear the OCREF clear selection bit */
5196 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5197 break;
5198 }
5199
5200 case TIM_CLEARINPUTSOURCE_ETR:
5201 {
5202 /* Check the parameters */
5203 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5204 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5205 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5206
5207 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5208 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5209 {
5210 htim->State = HAL_TIM_STATE_READY;
5211 __HAL_UNLOCK(htim);
5212 return HAL_ERROR;
5213 }
5214
5215 TIM_ETR_SetConfig(htim->Instance,
5216 sClearInputConfig->ClearInputPrescaler,
5217 sClearInputConfig->ClearInputPolarity,
5218 sClearInputConfig->ClearInputFilter);
5219
5220 /* Set the OCREF clear selection bit */
5221 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5222 break;
5223 }
5224
5225 default:
5226 status = HAL_ERROR;
5227 break;
5228 }
5229
5230 if (status == HAL_OK)
5231 {
5232 switch (Channel)
5233 {
5234 case TIM_CHANNEL_1:
5235 {
5236 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5237 {
5238 /* Enable the OCREF clear feature for Channel 1 */
5239 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5240 }
5241 else
5242 {
5243 /* Disable the OCREF clear feature for Channel 1 */
5244 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5245 }
5246 break;
5247 }
5248 case TIM_CHANNEL_2:
5249 {
5250 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5251 {
5252 /* Enable the OCREF clear feature for Channel 2 */
5253 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5254 }
5255 else
5256 {
5257 /* Disable the OCREF clear feature for Channel 2 */
5258 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5259 }
5260 break;
5261 }
5262 case TIM_CHANNEL_3:
5263 {
5264 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5265 {
5266 /* Enable the OCREF clear feature for Channel 3 */
5267 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5268 }
5269 else
5270 {
5271 /* Disable the OCREF clear feature for Channel 3 */
5272 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5273 }
5274 break;
5275 }
5276 case TIM_CHANNEL_4:
5277 {
5278 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5279 {
5280 /* Enable the OCREF clear feature for Channel 4 */
5281 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5282 }
5283 else
5284 {
5285 /* Disable the OCREF clear feature for Channel 4 */
5286 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5287 }
5288 break;
5289 }
5290 default:
5291 break;
5292 }
5293 }
5294
5295 htim->State = HAL_TIM_STATE_READY;
5296
5297 __HAL_UNLOCK(htim);
5298
5299 return status;
5300 }
5301
5302 /**
5303 * @brief Configures the clock source to be used
5304 * @param htim TIM handle
5305 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5306 * contains the clock source information for the TIM peripheral.
5307 * @retval HAL status
5308 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5309 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5310 {
5311 HAL_StatusTypeDef status = HAL_OK;
5312 uint32_t tmpsmcr;
5313
5314 /* Process Locked */
5315 __HAL_LOCK(htim);
5316
5317 htim->State = HAL_TIM_STATE_BUSY;
5318
5319 /* Check the parameters */
5320 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5321
5322 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5323 tmpsmcr = htim->Instance->SMCR;
5324 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5325 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5326 htim->Instance->SMCR = tmpsmcr;
5327
5328 switch (sClockSourceConfig->ClockSource)
5329 {
5330 case TIM_CLOCKSOURCE_INTERNAL:
5331 {
5332 assert_param(IS_TIM_INSTANCE(htim->Instance));
5333 break;
5334 }
5335
5336 case TIM_CLOCKSOURCE_ETRMODE1:
5337 {
5338 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5339 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5340
5341 /* Check ETR input conditioning related parameters */
5342 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5343 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5344 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5345
5346 /* Configure the ETR Clock source */
5347 TIM_ETR_SetConfig(htim->Instance,
5348 sClockSourceConfig->ClockPrescaler,
5349 sClockSourceConfig->ClockPolarity,
5350 sClockSourceConfig->ClockFilter);
5351
5352 /* Select the External clock mode1 and the ETRF trigger */
5353 tmpsmcr = htim->Instance->SMCR;
5354 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5355 /* Write to TIMx SMCR */
5356 htim->Instance->SMCR = tmpsmcr;
5357 break;
5358 }
5359
5360 case TIM_CLOCKSOURCE_ETRMODE2:
5361 {
5362 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5363 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5364
5365 /* Check ETR input conditioning related parameters */
5366 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5367 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5368 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5369
5370 /* Configure the ETR Clock source */
5371 TIM_ETR_SetConfig(htim->Instance,
5372 sClockSourceConfig->ClockPrescaler,
5373 sClockSourceConfig->ClockPolarity,
5374 sClockSourceConfig->ClockFilter);
5375 /* Enable the External clock mode2 */
5376 htim->Instance->SMCR |= TIM_SMCR_ECE;
5377 break;
5378 }
5379
5380 case TIM_CLOCKSOURCE_TI1:
5381 {
5382 /* Check whether or not the timer instance supports external clock mode 1 */
5383 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5384
5385 /* Check TI1 input conditioning related parameters */
5386 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5387 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5388
5389 TIM_TI1_ConfigInputStage(htim->Instance,
5390 sClockSourceConfig->ClockPolarity,
5391 sClockSourceConfig->ClockFilter);
5392 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5393 break;
5394 }
5395
5396 case TIM_CLOCKSOURCE_TI2:
5397 {
5398 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5399 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5400
5401 /* Check TI2 input conditioning related parameters */
5402 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5403 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5404
5405 TIM_TI2_ConfigInputStage(htim->Instance,
5406 sClockSourceConfig->ClockPolarity,
5407 sClockSourceConfig->ClockFilter);
5408 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5409 break;
5410 }
5411
5412 case TIM_CLOCKSOURCE_TI1ED:
5413 {
5414 /* Check whether or not the timer instance supports external clock mode 1 */
5415 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5416
5417 /* Check TI1 input conditioning related parameters */
5418 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5419 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5420
5421 TIM_TI1_ConfigInputStage(htim->Instance,
5422 sClockSourceConfig->ClockPolarity,
5423 sClockSourceConfig->ClockFilter);
5424 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5425 break;
5426 }
5427
5428 case TIM_CLOCKSOURCE_ITR0:
5429 case TIM_CLOCKSOURCE_ITR1:
5430 case TIM_CLOCKSOURCE_ITR2:
5431 case TIM_CLOCKSOURCE_ITR3:
5432 {
5433 /* Check whether or not the timer instance supports internal trigger input */
5434 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5435
5436 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5437 break;
5438 }
5439
5440 default:
5441 status = HAL_ERROR;
5442 break;
5443 }
5444 htim->State = HAL_TIM_STATE_READY;
5445
5446 __HAL_UNLOCK(htim);
5447
5448 return status;
5449 }
5450
5451 /**
5452 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5453 * or a XOR combination between CH1_input, CH2_input & CH3_input
5454 * @param htim TIM handle.
5455 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5456 * output of a XOR gate.
5457 * This parameter can be one of the following values:
5458 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5459 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5460 * pins are connected to the TI1 input (XOR combination)
5461 * @retval HAL status
5462 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5463 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5464 {
5465 uint32_t tmpcr2;
5466
5467 /* Check the parameters */
5468 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5469 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5470
5471 /* Get the TIMx CR2 register value */
5472 tmpcr2 = htim->Instance->CR2;
5473
5474 /* Reset the TI1 selection */
5475 tmpcr2 &= ~TIM_CR2_TI1S;
5476
5477 /* Set the TI1 selection */
5478 tmpcr2 |= TI1_Selection;
5479
5480 /* Write to TIMxCR2 */
5481 htim->Instance->CR2 = tmpcr2;
5482
5483 return HAL_OK;
5484 }
5485
5486 /**
5487 * @brief Configures the TIM in Slave mode
5488 * @param htim TIM handle.
5489 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5490 * contains the selected trigger (internal trigger input, filtered
5491 * timer input or external trigger input) and the Slave mode
5492 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5493 * @retval HAL status
5494 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5495 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5496 {
5497 /* Check the parameters */
5498 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5499 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5500 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5501
5502 __HAL_LOCK(htim);
5503
5504 htim->State = HAL_TIM_STATE_BUSY;
5505
5506 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5507 {
5508 htim->State = HAL_TIM_STATE_READY;
5509 __HAL_UNLOCK(htim);
5510 return HAL_ERROR;
5511 }
5512
5513 /* Disable Trigger Interrupt */
5514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5515
5516 /* Disable Trigger DMA request */
5517 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5518
5519 htim->State = HAL_TIM_STATE_READY;
5520
5521 __HAL_UNLOCK(htim);
5522
5523 return HAL_OK;
5524 }
5525
5526 /**
5527 * @brief Configures the TIM in Slave mode in interrupt mode
5528 * @param htim TIM handle.
5529 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5530 * contains the selected trigger (internal trigger input, filtered
5531 * timer input or external trigger input) and the Slave mode
5532 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5533 * @retval HAL status
5534 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5535 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5536 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5537 {
5538 /* Check the parameters */
5539 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5540 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5541 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5542
5543 __HAL_LOCK(htim);
5544
5545 htim->State = HAL_TIM_STATE_BUSY;
5546
5547 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5548 {
5549 htim->State = HAL_TIM_STATE_READY;
5550 __HAL_UNLOCK(htim);
5551 return HAL_ERROR;
5552 }
5553
5554 /* Enable Trigger Interrupt */
5555 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5556
5557 /* Disable Trigger DMA request */
5558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5559
5560 htim->State = HAL_TIM_STATE_READY;
5561
5562 __HAL_UNLOCK(htim);
5563
5564 return HAL_OK;
5565 }
5566
5567 /**
5568 * @brief Read the captured value from Capture Compare unit
5569 * @param htim TIM handle.
5570 * @param Channel TIM Channels to be enabled
5571 * This parameter can be one of the following values:
5572 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5573 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5574 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5575 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5576 * @retval Captured value
5577 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5578 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5579 {
5580 uint32_t tmpreg = 0U;
5581
5582 switch (Channel)
5583 {
5584 case TIM_CHANNEL_1:
5585 {
5586 /* Check the parameters */
5587 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5588
5589 /* Return the capture 1 value */
5590 tmpreg = htim->Instance->CCR1;
5591
5592 break;
5593 }
5594 case TIM_CHANNEL_2:
5595 {
5596 /* Check the parameters */
5597 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5598
5599 /* Return the capture 2 value */
5600 tmpreg = htim->Instance->CCR2;
5601
5602 break;
5603 }
5604
5605 case TIM_CHANNEL_3:
5606 {
5607 /* Check the parameters */
5608 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5609
5610 /* Return the capture 3 value */
5611 tmpreg = htim->Instance->CCR3;
5612
5613 break;
5614 }
5615
5616 case TIM_CHANNEL_4:
5617 {
5618 /* Check the parameters */
5619 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5620
5621 /* Return the capture 4 value */
5622 tmpreg = htim->Instance->CCR4;
5623
5624 break;
5625 }
5626
5627 default:
5628 break;
5629 }
5630
5631 return tmpreg;
5632 }
5633
5634 /**
5635 * @}
5636 */
5637
5638 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5639 * @brief TIM Callbacks functions
5640 *
5641 @verbatim
5642 ==============================================================================
5643 ##### TIM Callbacks functions #####
5644 ==============================================================================
5645 [..]
5646 This section provides TIM callback functions:
5647 (+) TIM Period elapsed callback
5648 (+) TIM Output Compare callback
5649 (+) TIM Input capture callback
5650 (+) TIM Trigger callback
5651 (+) TIM Error callback
5652
5653 @endverbatim
5654 * @{
5655 */
5656
5657 /**
5658 * @brief Period elapsed callback in non-blocking mode
5659 * @param htim TIM handle
5660 * @retval None
5661 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5662 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5663 {
5664 /* Prevent unused argument(s) compilation warning */
5665 UNUSED(htim);
5666
5667 /* NOTE : This function should not be modified, when the callback is needed,
5668 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5669 */
5670 }
5671
5672 /**
5673 * @brief Period elapsed half complete callback in non-blocking mode
5674 * @param htim TIM handle
5675 * @retval None
5676 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5677 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5678 {
5679 /* Prevent unused argument(s) compilation warning */
5680 UNUSED(htim);
5681
5682 /* NOTE : This function should not be modified, when the callback is needed,
5683 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5684 */
5685 }
5686
5687 /**
5688 * @brief Output Compare callback in non-blocking mode
5689 * @param htim TIM OC handle
5690 * @retval None
5691 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5692 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5693 {
5694 /* Prevent unused argument(s) compilation warning */
5695 UNUSED(htim);
5696
5697 /* NOTE : This function should not be modified, when the callback is needed,
5698 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5699 */
5700 }
5701
5702 /**
5703 * @brief Input Capture callback in non-blocking mode
5704 * @param htim TIM IC handle
5705 * @retval None
5706 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5707 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5708 {
5709 /* Prevent unused argument(s) compilation warning */
5710 UNUSED(htim);
5711
5712 /* NOTE : This function should not be modified, when the callback is needed,
5713 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5714 */
5715 }
5716
5717 /**
5718 * @brief Input Capture half complete callback in non-blocking mode
5719 * @param htim TIM IC handle
5720 * @retval None
5721 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5722 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5723 {
5724 /* Prevent unused argument(s) compilation warning */
5725 UNUSED(htim);
5726
5727 /* NOTE : This function should not be modified, when the callback is needed,
5728 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5729 */
5730 }
5731
5732 /**
5733 * @brief PWM Pulse finished callback in non-blocking mode
5734 * @param htim TIM handle
5735 * @retval None
5736 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5737 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5738 {
5739 /* Prevent unused argument(s) compilation warning */
5740 UNUSED(htim);
5741
5742 /* NOTE : This function should not be modified, when the callback is needed,
5743 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5744 */
5745 }
5746
5747 /**
5748 * @brief PWM Pulse finished half complete callback in non-blocking mode
5749 * @param htim TIM handle
5750 * @retval None
5751 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5752 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5753 {
5754 /* Prevent unused argument(s) compilation warning */
5755 UNUSED(htim);
5756
5757 /* NOTE : This function should not be modified, when the callback is needed,
5758 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5759 */
5760 }
5761
5762 /**
5763 * @brief Hall Trigger detection callback in non-blocking mode
5764 * @param htim TIM handle
5765 * @retval None
5766 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5767 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5768 {
5769 /* Prevent unused argument(s) compilation warning */
5770 UNUSED(htim);
5771
5772 /* NOTE : This function should not be modified, when the callback is needed,
5773 the HAL_TIM_TriggerCallback could be implemented in the user file
5774 */
5775 }
5776
5777 /**
5778 * @brief Hall Trigger detection half complete callback in non-blocking mode
5779 * @param htim TIM handle
5780 * @retval None
5781 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5782 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5783 {
5784 /* Prevent unused argument(s) compilation warning */
5785 UNUSED(htim);
5786
5787 /* NOTE : This function should not be modified, when the callback is needed,
5788 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5789 */
5790 }
5791
5792 /**
5793 * @brief Timer error callback in non-blocking mode
5794 * @param htim TIM handle
5795 * @retval None
5796 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5797 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5798 {
5799 /* Prevent unused argument(s) compilation warning */
5800 UNUSED(htim);
5801
5802 /* NOTE : This function should not be modified, when the callback is needed,
5803 the HAL_TIM_ErrorCallback could be implemented in the user file
5804 */
5805 }
5806
5807 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5808 /**
5809 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5810 * @param htim tim handle
5811 * @param CallbackID ID of the callback to be registered
5812 * This parameter can be one of the following values:
5813 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5814 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5815 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5816 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5817 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5818 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5819 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5820 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5821 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5822 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5823 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5824 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5825 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5826 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5827 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5828 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5829 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5830 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5831 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5832 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5833 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5834 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5835 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5836 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5837 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5838 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5839 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5840 * @param pCallback pointer to the callback function
5841 * @retval status
5842 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5843 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5844 pTIM_CallbackTypeDef pCallback)
5845 {
5846 HAL_StatusTypeDef status = HAL_OK;
5847
5848 if (pCallback == NULL)
5849 {
5850 return HAL_ERROR;
5851 }
5852
5853 if (htim->State == HAL_TIM_STATE_READY)
5854 {
5855 switch (CallbackID)
5856 {
5857 case HAL_TIM_BASE_MSPINIT_CB_ID :
5858 htim->Base_MspInitCallback = pCallback;
5859 break;
5860
5861 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5862 htim->Base_MspDeInitCallback = pCallback;
5863 break;
5864
5865 case HAL_TIM_IC_MSPINIT_CB_ID :
5866 htim->IC_MspInitCallback = pCallback;
5867 break;
5868
5869 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5870 htim->IC_MspDeInitCallback = pCallback;
5871 break;
5872
5873 case HAL_TIM_OC_MSPINIT_CB_ID :
5874 htim->OC_MspInitCallback = pCallback;
5875 break;
5876
5877 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5878 htim->OC_MspDeInitCallback = pCallback;
5879 break;
5880
5881 case HAL_TIM_PWM_MSPINIT_CB_ID :
5882 htim->PWM_MspInitCallback = pCallback;
5883 break;
5884
5885 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5886 htim->PWM_MspDeInitCallback = pCallback;
5887 break;
5888
5889 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5890 htim->OnePulse_MspInitCallback = pCallback;
5891 break;
5892
5893 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5894 htim->OnePulse_MspDeInitCallback = pCallback;
5895 break;
5896
5897 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5898 htim->Encoder_MspInitCallback = pCallback;
5899 break;
5900
5901 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5902 htim->Encoder_MspDeInitCallback = pCallback;
5903 break;
5904
5905 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5906 htim->HallSensor_MspInitCallback = pCallback;
5907 break;
5908
5909 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5910 htim->HallSensor_MspDeInitCallback = pCallback;
5911 break;
5912
5913 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5914 htim->PeriodElapsedCallback = pCallback;
5915 break;
5916
5917 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5918 htim->PeriodElapsedHalfCpltCallback = pCallback;
5919 break;
5920
5921 case HAL_TIM_TRIGGER_CB_ID :
5922 htim->TriggerCallback = pCallback;
5923 break;
5924
5925 case HAL_TIM_TRIGGER_HALF_CB_ID :
5926 htim->TriggerHalfCpltCallback = pCallback;
5927 break;
5928
5929 case HAL_TIM_IC_CAPTURE_CB_ID :
5930 htim->IC_CaptureCallback = pCallback;
5931 break;
5932
5933 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5934 htim->IC_CaptureHalfCpltCallback = pCallback;
5935 break;
5936
5937 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5938 htim->OC_DelayElapsedCallback = pCallback;
5939 break;
5940
5941 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5942 htim->PWM_PulseFinishedCallback = pCallback;
5943 break;
5944
5945 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5946 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5947 break;
5948
5949 case HAL_TIM_ERROR_CB_ID :
5950 htim->ErrorCallback = pCallback;
5951 break;
5952
5953 case HAL_TIM_COMMUTATION_CB_ID :
5954 htim->CommutationCallback = pCallback;
5955 break;
5956
5957 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5958 htim->CommutationHalfCpltCallback = pCallback;
5959 break;
5960
5961 case HAL_TIM_BREAK_CB_ID :
5962 htim->BreakCallback = pCallback;
5963 break;
5964
5965 default :
5966 /* Return error status */
5967 status = HAL_ERROR;
5968 break;
5969 }
5970 }
5971 else if (htim->State == HAL_TIM_STATE_RESET)
5972 {
5973 switch (CallbackID)
5974 {
5975 case HAL_TIM_BASE_MSPINIT_CB_ID :
5976 htim->Base_MspInitCallback = pCallback;
5977 break;
5978
5979 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5980 htim->Base_MspDeInitCallback = pCallback;
5981 break;
5982
5983 case HAL_TIM_IC_MSPINIT_CB_ID :
5984 htim->IC_MspInitCallback = pCallback;
5985 break;
5986
5987 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5988 htim->IC_MspDeInitCallback = pCallback;
5989 break;
5990
5991 case HAL_TIM_OC_MSPINIT_CB_ID :
5992 htim->OC_MspInitCallback = pCallback;
5993 break;
5994
5995 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5996 htim->OC_MspDeInitCallback = pCallback;
5997 break;
5998
5999 case HAL_TIM_PWM_MSPINIT_CB_ID :
6000 htim->PWM_MspInitCallback = pCallback;
6001 break;
6002
6003 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6004 htim->PWM_MspDeInitCallback = pCallback;
6005 break;
6006
6007 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6008 htim->OnePulse_MspInitCallback = pCallback;
6009 break;
6010
6011 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6012 htim->OnePulse_MspDeInitCallback = pCallback;
6013 break;
6014
6015 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6016 htim->Encoder_MspInitCallback = pCallback;
6017 break;
6018
6019 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6020 htim->Encoder_MspDeInitCallback = pCallback;
6021 break;
6022
6023 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6024 htim->HallSensor_MspInitCallback = pCallback;
6025 break;
6026
6027 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6028 htim->HallSensor_MspDeInitCallback = pCallback;
6029 break;
6030
6031 default :
6032 /* Return error status */
6033 status = HAL_ERROR;
6034 break;
6035 }
6036 }
6037 else
6038 {
6039 /* Return error status */
6040 status = HAL_ERROR;
6041 }
6042
6043 return status;
6044 }
6045
6046 /**
6047 * @brief Unregister a TIM callback
6048 * TIM callback is redirected to the weak predefined callback
6049 * @param htim tim handle
6050 * @param CallbackID ID of the callback to be unregistered
6051 * This parameter can be one of the following values:
6052 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6053 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6054 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6055 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6056 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6057 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6058 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6059 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6060 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6061 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6062 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6063 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6064 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6065 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6066 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6067 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6068 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6069 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6070 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6071 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6072 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6073 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6074 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6075 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6076 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6077 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6078 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6079 * @retval status
6080 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6081 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6082 {
6083 HAL_StatusTypeDef status = HAL_OK;
6084
6085 if (htim->State == HAL_TIM_STATE_READY)
6086 {
6087 switch (CallbackID)
6088 {
6089 case HAL_TIM_BASE_MSPINIT_CB_ID :
6090 /* Legacy weak Base MspInit Callback */
6091 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6092 break;
6093
6094 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6095 /* Legacy weak Base Msp DeInit Callback */
6096 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6097 break;
6098
6099 case HAL_TIM_IC_MSPINIT_CB_ID :
6100 /* Legacy weak IC Msp Init Callback */
6101 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6102 break;
6103
6104 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6105 /* Legacy weak IC Msp DeInit Callback */
6106 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6107 break;
6108
6109 case HAL_TIM_OC_MSPINIT_CB_ID :
6110 /* Legacy weak OC Msp Init Callback */
6111 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6112 break;
6113
6114 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6115 /* Legacy weak OC Msp DeInit Callback */
6116 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6117 break;
6118
6119 case HAL_TIM_PWM_MSPINIT_CB_ID :
6120 /* Legacy weak PWM Msp Init Callback */
6121 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6122 break;
6123
6124 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6125 /* Legacy weak PWM Msp DeInit Callback */
6126 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6127 break;
6128
6129 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6130 /* Legacy weak One Pulse Msp Init Callback */
6131 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6132 break;
6133
6134 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6135 /* Legacy weak One Pulse Msp DeInit Callback */
6136 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6137 break;
6138
6139 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6140 /* Legacy weak Encoder Msp Init Callback */
6141 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6142 break;
6143
6144 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6145 /* Legacy weak Encoder Msp DeInit Callback */
6146 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6147 break;
6148
6149 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6150 /* Legacy weak Hall Sensor Msp Init Callback */
6151 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6152 break;
6153
6154 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6155 /* Legacy weak Hall Sensor Msp DeInit Callback */
6156 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6157 break;
6158
6159 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6160 /* Legacy weak Period Elapsed Callback */
6161 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6162 break;
6163
6164 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6165 /* Legacy weak Period Elapsed half complete Callback */
6166 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6167 break;
6168
6169 case HAL_TIM_TRIGGER_CB_ID :
6170 /* Legacy weak Trigger Callback */
6171 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6172 break;
6173
6174 case HAL_TIM_TRIGGER_HALF_CB_ID :
6175 /* Legacy weak Trigger half complete Callback */
6176 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6177 break;
6178
6179 case HAL_TIM_IC_CAPTURE_CB_ID :
6180 /* Legacy weak IC Capture Callback */
6181 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6182 break;
6183
6184 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6185 /* Legacy weak IC Capture half complete Callback */
6186 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6187 break;
6188
6189 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6190 /* Legacy weak OC Delay Elapsed Callback */
6191 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6192 break;
6193
6194 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6195 /* Legacy weak PWM Pulse Finished Callback */
6196 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6197 break;
6198
6199 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6200 /* Legacy weak PWM Pulse Finished half complete Callback */
6201 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6202 break;
6203
6204 case HAL_TIM_ERROR_CB_ID :
6205 /* Legacy weak Error Callback */
6206 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6207 break;
6208
6209 case HAL_TIM_COMMUTATION_CB_ID :
6210 /* Legacy weak Commutation Callback */
6211 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6212 break;
6213
6214 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6215 /* Legacy weak Commutation half complete Callback */
6216 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6217 break;
6218
6219 case HAL_TIM_BREAK_CB_ID :
6220 /* Legacy weak Break Callback */
6221 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6222 break;
6223
6224 default :
6225 /* Return error status */
6226 status = HAL_ERROR;
6227 break;
6228 }
6229 }
6230 else if (htim->State == HAL_TIM_STATE_RESET)
6231 {
6232 switch (CallbackID)
6233 {
6234 case HAL_TIM_BASE_MSPINIT_CB_ID :
6235 /* Legacy weak Base MspInit Callback */
6236 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6237 break;
6238
6239 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6240 /* Legacy weak Base Msp DeInit Callback */
6241 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6242 break;
6243
6244 case HAL_TIM_IC_MSPINIT_CB_ID :
6245 /* Legacy weak IC Msp Init Callback */
6246 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6247 break;
6248
6249 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6250 /* Legacy weak IC Msp DeInit Callback */
6251 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6252 break;
6253
6254 case HAL_TIM_OC_MSPINIT_CB_ID :
6255 /* Legacy weak OC Msp Init Callback */
6256 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6257 break;
6258
6259 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6260 /* Legacy weak OC Msp DeInit Callback */
6261 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6262 break;
6263
6264 case HAL_TIM_PWM_MSPINIT_CB_ID :
6265 /* Legacy weak PWM Msp Init Callback */
6266 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6267 break;
6268
6269 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6270 /* Legacy weak PWM Msp DeInit Callback */
6271 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6272 break;
6273
6274 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6275 /* Legacy weak One Pulse Msp Init Callback */
6276 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6277 break;
6278
6279 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6280 /* Legacy weak One Pulse Msp DeInit Callback */
6281 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6282 break;
6283
6284 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6285 /* Legacy weak Encoder Msp Init Callback */
6286 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6287 break;
6288
6289 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6290 /* Legacy weak Encoder Msp DeInit Callback */
6291 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6292 break;
6293
6294 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6295 /* Legacy weak Hall Sensor Msp Init Callback */
6296 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6297 break;
6298
6299 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6300 /* Legacy weak Hall Sensor Msp DeInit Callback */
6301 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6302 break;
6303
6304 default :
6305 /* Return error status */
6306 status = HAL_ERROR;
6307 break;
6308 }
6309 }
6310 else
6311 {
6312 /* Return error status */
6313 status = HAL_ERROR;
6314 }
6315
6316 return status;
6317 }
6318 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6319
6320 /**
6321 * @}
6322 */
6323
6324 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6325 * @brief TIM Peripheral State functions
6326 *
6327 @verbatim
6328 ==============================================================================
6329 ##### Peripheral State functions #####
6330 ==============================================================================
6331 [..]
6332 This subsection permits to get in run-time the status of the peripheral
6333 and the data flow.
6334
6335 @endverbatim
6336 * @{
6337 */
6338
6339 /**
6340 * @brief Return the TIM Base handle state.
6341 * @param htim TIM Base handle
6342 * @retval HAL state
6343 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6344 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6345 {
6346 return htim->State;
6347 }
6348
6349 /**
6350 * @brief Return the TIM OC handle state.
6351 * @param htim TIM Output Compare handle
6352 * @retval HAL state
6353 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6354 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6355 {
6356 return htim->State;
6357 }
6358
6359 /**
6360 * @brief Return the TIM PWM handle state.
6361 * @param htim TIM handle
6362 * @retval HAL state
6363 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6364 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6365 {
6366 return htim->State;
6367 }
6368
6369 /**
6370 * @brief Return the TIM Input Capture handle state.
6371 * @param htim TIM IC handle
6372 * @retval HAL state
6373 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6374 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6375 {
6376 return htim->State;
6377 }
6378
6379 /**
6380 * @brief Return the TIM One Pulse Mode handle state.
6381 * @param htim TIM OPM handle
6382 * @retval HAL state
6383 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6384 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6385 {
6386 return htim->State;
6387 }
6388
6389 /**
6390 * @brief Return the TIM Encoder Mode handle state.
6391 * @param htim TIM Encoder Interface handle
6392 * @retval HAL state
6393 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6394 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6395 {
6396 return htim->State;
6397 }
6398
6399 /**
6400 * @brief Return the TIM Encoder Mode handle state.
6401 * @param htim TIM handle
6402 * @retval Active channel
6403 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6404 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6405 {
6406 return htim->Channel;
6407 }
6408
6409 /**
6410 * @brief Return actual state of the TIM channel.
6411 * @param htim TIM handle
6412 * @param Channel TIM Channel
6413 * This parameter can be one of the following values:
6414 * @arg TIM_CHANNEL_1: TIM Channel 1
6415 * @arg TIM_CHANNEL_2: TIM Channel 2
6416 * @arg TIM_CHANNEL_3: TIM Channel 3
6417 * @arg TIM_CHANNEL_4: TIM Channel 4
6418 * @arg TIM_CHANNEL_5: TIM Channel 5
6419 * @arg TIM_CHANNEL_6: TIM Channel 6
6420 * @retval TIM Channel state
6421 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6422 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6423 {
6424 HAL_TIM_ChannelStateTypeDef channel_state;
6425
6426 /* Check the parameters */
6427 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6428
6429 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6430
6431 return channel_state;
6432 }
6433
6434 /**
6435 * @brief Return actual state of a DMA burst operation.
6436 * @param htim TIM handle
6437 * @retval DMA burst state
6438 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6439 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6440 {
6441 /* Check the parameters */
6442 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6443
6444 return htim->DMABurstState;
6445 }
6446
6447 /**
6448 * @}
6449 */
6450
6451 /**
6452 * @}
6453 */
6454
6455 /** @defgroup TIM_Private_Functions TIM Private Functions
6456 * @{
6457 */
6458
6459 /**
6460 * @brief TIM DMA error callback
6461 * @param hdma pointer to DMA handle.
6462 * @retval None
6463 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6464 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6465 {
6466 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6467
6468 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6469 {
6470 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6471 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6472 }
6473 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6474 {
6475 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6476 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6477 }
6478 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6479 {
6480 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6481 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6482 }
6483 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6484 {
6485 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6486 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6487 }
6488 else
6489 {
6490 htim->State = HAL_TIM_STATE_READY;
6491 }
6492
6493 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6494 htim->ErrorCallback(htim);
6495 #else
6496 HAL_TIM_ErrorCallback(htim);
6497 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6498
6499 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6500 }
6501
6502 /**
6503 * @brief TIM DMA Delay Pulse complete callback.
6504 * @param hdma pointer to DMA handle.
6505 * @retval None
6506 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6507 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6508 {
6509 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6510
6511 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6512 {
6513 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6514
6515 if (hdma->Init.Mode == DMA_NORMAL)
6516 {
6517 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6518 }
6519 }
6520 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6521 {
6522 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6523
6524 if (hdma->Init.Mode == DMA_NORMAL)
6525 {
6526 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6527 }
6528 }
6529 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6530 {
6531 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6532
6533 if (hdma->Init.Mode == DMA_NORMAL)
6534 {
6535 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6536 }
6537 }
6538 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6539 {
6540 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6541
6542 if (hdma->Init.Mode == DMA_NORMAL)
6543 {
6544 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6545 }
6546 }
6547 else
6548 {
6549 /* nothing to do */
6550 }
6551
6552 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6553 htim->PWM_PulseFinishedCallback(htim);
6554 #else
6555 HAL_TIM_PWM_PulseFinishedCallback(htim);
6556 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6557
6558 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6559 }
6560
6561 /**
6562 * @brief TIM DMA Delay Pulse half complete callback.
6563 * @param hdma pointer to DMA handle.
6564 * @retval None
6565 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6566 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6567 {
6568 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6569
6570 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6571 {
6572 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6573 }
6574 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6575 {
6576 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6577 }
6578 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6579 {
6580 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6581 }
6582 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6583 {
6584 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6585 }
6586 else
6587 {
6588 /* nothing to do */
6589 }
6590
6591 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6592 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6593 #else
6594 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6595 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6596
6597 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6598 }
6599
6600 /**
6601 * @brief TIM DMA Capture complete callback.
6602 * @param hdma pointer to DMA handle.
6603 * @retval None
6604 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6605 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6606 {
6607 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6608
6609 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6610 {
6611 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6612
6613 if (hdma->Init.Mode == DMA_NORMAL)
6614 {
6615 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6616 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6617 }
6618 }
6619 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6620 {
6621 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6622
6623 if (hdma->Init.Mode == DMA_NORMAL)
6624 {
6625 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6626 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6627 }
6628 }
6629 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6630 {
6631 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6632
6633 if (hdma->Init.Mode == DMA_NORMAL)
6634 {
6635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6637 }
6638 }
6639 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6640 {
6641 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6642
6643 if (hdma->Init.Mode == DMA_NORMAL)
6644 {
6645 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6646 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6647 }
6648 }
6649 else
6650 {
6651 /* nothing to do */
6652 }
6653
6654 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6655 htim->IC_CaptureCallback(htim);
6656 #else
6657 HAL_TIM_IC_CaptureCallback(htim);
6658 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6659
6660 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6661 }
6662
6663 /**
6664 * @brief TIM DMA Capture half complete callback.
6665 * @param hdma pointer to DMA handle.
6666 * @retval None
6667 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6668 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6669 {
6670 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6671
6672 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6673 {
6674 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6675 }
6676 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6677 {
6678 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6679 }
6680 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6681 {
6682 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6683 }
6684 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6685 {
6686 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6687 }
6688 else
6689 {
6690 /* nothing to do */
6691 }
6692
6693 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6694 htim->IC_CaptureHalfCpltCallback(htim);
6695 #else
6696 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6697 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6698
6699 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6700 }
6701
6702 /**
6703 * @brief TIM DMA Period Elapse complete callback.
6704 * @param hdma pointer to DMA handle.
6705 * @retval None
6706 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6707 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6708 {
6709 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6710
6711 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6712 {
6713 htim->State = HAL_TIM_STATE_READY;
6714 }
6715
6716 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6717 htim->PeriodElapsedCallback(htim);
6718 #else
6719 HAL_TIM_PeriodElapsedCallback(htim);
6720 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6721 }
6722
6723 /**
6724 * @brief TIM DMA Period Elapse half complete callback.
6725 * @param hdma pointer to DMA handle.
6726 * @retval None
6727 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6728 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6729 {
6730 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6731
6732 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6733 htim->PeriodElapsedHalfCpltCallback(htim);
6734 #else
6735 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6737 }
6738
6739 /**
6740 * @brief TIM DMA Trigger callback.
6741 * @param hdma pointer to DMA handle.
6742 * @retval None
6743 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6744 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6745 {
6746 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6747
6748 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6749 {
6750 htim->State = HAL_TIM_STATE_READY;
6751 }
6752
6753 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6754 htim->TriggerCallback(htim);
6755 #else
6756 HAL_TIM_TriggerCallback(htim);
6757 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6758 }
6759
6760 /**
6761 * @brief TIM DMA Trigger half complete callback.
6762 * @param hdma pointer to DMA handle.
6763 * @retval None
6764 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6765 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6766 {
6767 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6768
6769 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6770 htim->TriggerHalfCpltCallback(htim);
6771 #else
6772 HAL_TIM_TriggerHalfCpltCallback(htim);
6773 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6774 }
6775
6776 /**
6777 * @brief Time Base configuration
6778 * @param TIMx TIM peripheral
6779 * @param Structure TIM Base configuration structure
6780 * @retval None
6781 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6782 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6783 {
6784 uint32_t tmpcr1;
6785 tmpcr1 = TIMx->CR1;
6786
6787 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6788 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6789 {
6790 /* Select the Counter Mode */
6791 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6792 tmpcr1 |= Structure->CounterMode;
6793 }
6794
6795 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6796 {
6797 /* Set the clock division */
6798 tmpcr1 &= ~TIM_CR1_CKD;
6799 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6800 }
6801
6802 /* Set the auto-reload preload */
6803 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6804
6805 TIMx->CR1 = tmpcr1;
6806
6807 /* Set the Autoreload value */
6808 TIMx->ARR = (uint32_t)Structure->Period ;
6809
6810 /* Set the Prescaler value */
6811 TIMx->PSC = Structure->Prescaler;
6812
6813 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6814 {
6815 /* Set the Repetition Counter value */
6816 TIMx->RCR = Structure->RepetitionCounter;
6817 }
6818
6819 /* Generate an update event to reload the Prescaler
6820 and the repetition counter (only for advanced timer) value immediately */
6821 TIMx->EGR = TIM_EGR_UG;
6822 }
6823
6824 /**
6825 * @brief Timer Output Compare 1 configuration
6826 * @param TIMx to select the TIM peripheral
6827 * @param OC_Config The output configuration structure
6828 * @retval None
6829 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6830 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6831 {
6832 uint32_t tmpccmrx;
6833 uint32_t tmpccer;
6834 uint32_t tmpcr2;
6835
6836 /* Disable the Channel 1: Reset the CC1E Bit */
6837 TIMx->CCER &= ~TIM_CCER_CC1E;
6838
6839 /* Get the TIMx CCER register value */
6840 tmpccer = TIMx->CCER;
6841 /* Get the TIMx CR2 register value */
6842 tmpcr2 = TIMx->CR2;
6843
6844 /* Get the TIMx CCMR1 register value */
6845 tmpccmrx = TIMx->CCMR1;
6846
6847 /* Reset the Output Compare Mode Bits */
6848 tmpccmrx &= ~TIM_CCMR1_OC1M;
6849 tmpccmrx &= ~TIM_CCMR1_CC1S;
6850 /* Select the Output Compare Mode */
6851 tmpccmrx |= OC_Config->OCMode;
6852
6853 /* Reset the Output Polarity level */
6854 tmpccer &= ~TIM_CCER_CC1P;
6855 /* Set the Output Compare Polarity */
6856 tmpccer |= OC_Config->OCPolarity;
6857
6858 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6859 {
6860 /* Check parameters */
6861 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6862
6863 /* Reset the Output N Polarity level */
6864 tmpccer &= ~TIM_CCER_CC1NP;
6865 /* Set the Output N Polarity */
6866 tmpccer |= OC_Config->OCNPolarity;
6867 /* Reset the Output N State */
6868 tmpccer &= ~TIM_CCER_CC1NE;
6869 }
6870
6871 if (IS_TIM_BREAK_INSTANCE(TIMx))
6872 {
6873 /* Check parameters */
6874 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6875 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6876
6877 /* Reset the Output Compare and Output Compare N IDLE State */
6878 tmpcr2 &= ~TIM_CR2_OIS1;
6879 tmpcr2 &= ~TIM_CR2_OIS1N;
6880 /* Set the Output Idle state */
6881 tmpcr2 |= OC_Config->OCIdleState;
6882 /* Set the Output N Idle state */
6883 tmpcr2 |= OC_Config->OCNIdleState;
6884 }
6885
6886 /* Write to TIMx CR2 */
6887 TIMx->CR2 = tmpcr2;
6888
6889 /* Write to TIMx CCMR1 */
6890 TIMx->CCMR1 = tmpccmrx;
6891
6892 /* Set the Capture Compare Register value */
6893 TIMx->CCR1 = OC_Config->Pulse;
6894
6895 /* Write to TIMx CCER */
6896 TIMx->CCER = tmpccer;
6897 }
6898
6899 /**
6900 * @brief Timer Output Compare 2 configuration
6901 * @param TIMx to select the TIM peripheral
6902 * @param OC_Config The output configuration structure
6903 * @retval None
6904 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6905 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6906 {
6907 uint32_t tmpccmrx;
6908 uint32_t tmpccer;
6909 uint32_t tmpcr2;
6910
6911 /* Disable the Channel 2: Reset the CC2E Bit */
6912 TIMx->CCER &= ~TIM_CCER_CC2E;
6913
6914 /* Get the TIMx CCER register value */
6915 tmpccer = TIMx->CCER;
6916 /* Get the TIMx CR2 register value */
6917 tmpcr2 = TIMx->CR2;
6918
6919 /* Get the TIMx CCMR1 register value */
6920 tmpccmrx = TIMx->CCMR1;
6921
6922 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6923 tmpccmrx &= ~TIM_CCMR1_OC2M;
6924 tmpccmrx &= ~TIM_CCMR1_CC2S;
6925
6926 /* Select the Output Compare Mode */
6927 tmpccmrx |= (OC_Config->OCMode << 8U);
6928
6929 /* Reset the Output Polarity level */
6930 tmpccer &= ~TIM_CCER_CC2P;
6931 /* Set the Output Compare Polarity */
6932 tmpccer |= (OC_Config->OCPolarity << 4U);
6933
6934 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6935 {
6936 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6937
6938 /* Reset the Output N Polarity level */
6939 tmpccer &= ~TIM_CCER_CC2NP;
6940 /* Set the Output N Polarity */
6941 tmpccer |= (OC_Config->OCNPolarity << 4U);
6942 /* Reset the Output N State */
6943 tmpccer &= ~TIM_CCER_CC2NE;
6944
6945 }
6946
6947 if (IS_TIM_BREAK_INSTANCE(TIMx))
6948 {
6949 /* Check parameters */
6950 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6951 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6952
6953 /* Reset the Output Compare and Output Compare N IDLE State */
6954 tmpcr2 &= ~TIM_CR2_OIS2;
6955 tmpcr2 &= ~TIM_CR2_OIS2N;
6956 /* Set the Output Idle state */
6957 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6958 /* Set the Output N Idle state */
6959 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6960 }
6961
6962 /* Write to TIMx CR2 */
6963 TIMx->CR2 = tmpcr2;
6964
6965 /* Write to TIMx CCMR1 */
6966 TIMx->CCMR1 = tmpccmrx;
6967
6968 /* Set the Capture Compare Register value */
6969 TIMx->CCR2 = OC_Config->Pulse;
6970
6971 /* Write to TIMx CCER */
6972 TIMx->CCER = tmpccer;
6973 }
6974
6975 /**
6976 * @brief Timer Output Compare 3 configuration
6977 * @param TIMx to select the TIM peripheral
6978 * @param OC_Config The output configuration structure
6979 * @retval None
6980 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6981 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6982 {
6983 uint32_t tmpccmrx;
6984 uint32_t tmpccer;
6985 uint32_t tmpcr2;
6986
6987 /* Disable the Channel 3: Reset the CC2E Bit */
6988 TIMx->CCER &= ~TIM_CCER_CC3E;
6989
6990 /* Get the TIMx CCER register value */
6991 tmpccer = TIMx->CCER;
6992 /* Get the TIMx CR2 register value */
6993 tmpcr2 = TIMx->CR2;
6994
6995 /* Get the TIMx CCMR2 register value */
6996 tmpccmrx = TIMx->CCMR2;
6997
6998 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6999 tmpccmrx &= ~TIM_CCMR2_OC3M;
7000 tmpccmrx &= ~TIM_CCMR2_CC3S;
7001 /* Select the Output Compare Mode */
7002 tmpccmrx |= OC_Config->OCMode;
7003
7004 /* Reset the Output Polarity level */
7005 tmpccer &= ~TIM_CCER_CC3P;
7006 /* Set the Output Compare Polarity */
7007 tmpccer |= (OC_Config->OCPolarity << 8U);
7008
7009 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7010 {
7011 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7012
7013 /* Reset the Output N Polarity level */
7014 tmpccer &= ~TIM_CCER_CC3NP;
7015 /* Set the Output N Polarity */
7016 tmpccer |= (OC_Config->OCNPolarity << 8U);
7017 /* Reset the Output N State */
7018 tmpccer &= ~TIM_CCER_CC3NE;
7019 }
7020
7021 if (IS_TIM_BREAK_INSTANCE(TIMx))
7022 {
7023 /* Check parameters */
7024 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7025 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7026
7027 /* Reset the Output Compare and Output Compare N IDLE State */
7028 tmpcr2 &= ~TIM_CR2_OIS3;
7029 tmpcr2 &= ~TIM_CR2_OIS3N;
7030 /* Set the Output Idle state */
7031 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7032 /* Set the Output N Idle state */
7033 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7034 }
7035
7036 /* Write to TIMx CR2 */
7037 TIMx->CR2 = tmpcr2;
7038
7039 /* Write to TIMx CCMR2 */
7040 TIMx->CCMR2 = tmpccmrx;
7041
7042 /* Set the Capture Compare Register value */
7043 TIMx->CCR3 = OC_Config->Pulse;
7044
7045 /* Write to TIMx CCER */
7046 TIMx->CCER = tmpccer;
7047 }
7048
7049 /**
7050 * @brief Timer Output Compare 4 configuration
7051 * @param TIMx to select the TIM peripheral
7052 * @param OC_Config The output configuration structure
7053 * @retval None
7054 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7055 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7056 {
7057 uint32_t tmpccmrx;
7058 uint32_t tmpccer;
7059 uint32_t tmpcr2;
7060
7061 /* Disable the Channel 4: Reset the CC4E Bit */
7062 TIMx->CCER &= ~TIM_CCER_CC4E;
7063
7064 /* Get the TIMx CCER register value */
7065 tmpccer = TIMx->CCER;
7066 /* Get the TIMx CR2 register value */
7067 tmpcr2 = TIMx->CR2;
7068
7069 /* Get the TIMx CCMR2 register value */
7070 tmpccmrx = TIMx->CCMR2;
7071
7072 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7073 tmpccmrx &= ~TIM_CCMR2_OC4M;
7074 tmpccmrx &= ~TIM_CCMR2_CC4S;
7075
7076 /* Select the Output Compare Mode */
7077 tmpccmrx |= (OC_Config->OCMode << 8U);
7078
7079 /* Reset the Output Polarity level */
7080 tmpccer &= ~TIM_CCER_CC4P;
7081 /* Set the Output Compare Polarity */
7082 tmpccer |= (OC_Config->OCPolarity << 12U);
7083
7084 if (IS_TIM_BREAK_INSTANCE(TIMx))
7085 {
7086 /* Check parameters */
7087 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7088
7089 /* Reset the Output Compare IDLE State */
7090 tmpcr2 &= ~TIM_CR2_OIS4;
7091
7092 /* Set the Output Idle state */
7093 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7094 }
7095
7096 /* Write to TIMx CR2 */
7097 TIMx->CR2 = tmpcr2;
7098
7099 /* Write to TIMx CCMR2 */
7100 TIMx->CCMR2 = tmpccmrx;
7101
7102 /* Set the Capture Compare Register value */
7103 TIMx->CCR4 = OC_Config->Pulse;
7104
7105 /* Write to TIMx CCER */
7106 TIMx->CCER = tmpccer;
7107 }
7108
7109 /**
7110 * @brief Slave Timer configuration function
7111 * @param htim TIM handle
7112 * @param sSlaveConfig Slave timer configuration
7113 * @retval None
7114 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7115 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7116 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7117 {
7118 HAL_StatusTypeDef status = HAL_OK;
7119 uint32_t tmpsmcr;
7120 uint32_t tmpccmr1;
7121 uint32_t tmpccer;
7122
7123 /* Get the TIMx SMCR register value */
7124 tmpsmcr = htim->Instance->SMCR;
7125
7126 /* Reset the Trigger Selection Bits */
7127 tmpsmcr &= ~TIM_SMCR_TS;
7128 /* Set the Input Trigger source */
7129 tmpsmcr |= sSlaveConfig->InputTrigger;
7130
7131 /* Reset the slave mode Bits */
7132 tmpsmcr &= ~TIM_SMCR_SMS;
7133 /* Set the slave mode */
7134 tmpsmcr |= sSlaveConfig->SlaveMode;
7135
7136 /* Write to TIMx SMCR */
7137 htim->Instance->SMCR = tmpsmcr;
7138
7139 /* Configure the trigger prescaler, filter, and polarity */
7140 switch (sSlaveConfig->InputTrigger)
7141 {
7142 case TIM_TS_ETRF:
7143 {
7144 /* Check the parameters */
7145 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7146 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7147 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7148 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7149 /* Configure the ETR Trigger source */
7150 TIM_ETR_SetConfig(htim->Instance,
7151 sSlaveConfig->TriggerPrescaler,
7152 sSlaveConfig->TriggerPolarity,
7153 sSlaveConfig->TriggerFilter);
7154 break;
7155 }
7156
7157 case TIM_TS_TI1F_ED:
7158 {
7159 /* Check the parameters */
7160 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7161 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7162
7163 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7164 {
7165 return HAL_ERROR;
7166 }
7167
7168 /* Disable the Channel 1: Reset the CC1E Bit */
7169 tmpccer = htim->Instance->CCER;
7170 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7171 tmpccmr1 = htim->Instance->CCMR1;
7172
7173 /* Set the filter */
7174 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7175 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7176
7177 /* Write to TIMx CCMR1 and CCER registers */
7178 htim->Instance->CCMR1 = tmpccmr1;
7179 htim->Instance->CCER = tmpccer;
7180 break;
7181 }
7182
7183 case TIM_TS_TI1FP1:
7184 {
7185 /* Check the parameters */
7186 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7187 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7188 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7189
7190 /* Configure TI1 Filter and Polarity */
7191 TIM_TI1_ConfigInputStage(htim->Instance,
7192 sSlaveConfig->TriggerPolarity,
7193 sSlaveConfig->TriggerFilter);
7194 break;
7195 }
7196
7197 case TIM_TS_TI2FP2:
7198 {
7199 /* Check the parameters */
7200 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7201 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7202 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7203
7204 /* Configure TI2 Filter and Polarity */
7205 TIM_TI2_ConfigInputStage(htim->Instance,
7206 sSlaveConfig->TriggerPolarity,
7207 sSlaveConfig->TriggerFilter);
7208 break;
7209 }
7210
7211 case TIM_TS_ITR0:
7212 case TIM_TS_ITR1:
7213 case TIM_TS_ITR2:
7214 case TIM_TS_ITR3:
7215 {
7216 /* Check the parameter */
7217 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7218 break;
7219 }
7220
7221 default:
7222 status = HAL_ERROR;
7223 break;
7224 }
7225
7226 return status;
7227 }
7228
7229 /**
7230 * @brief Configure the TI1 as Input.
7231 * @param TIMx to select the TIM peripheral.
7232 * @param TIM_ICPolarity The Input Polarity.
7233 * This parameter can be one of the following values:
7234 * @arg TIM_ICPOLARITY_RISING
7235 * @arg TIM_ICPOLARITY_FALLING
7236 * @arg TIM_ICPOLARITY_BOTHEDGE
7237 * @param TIM_ICSelection specifies the input to be used.
7238 * This parameter can be one of the following values:
7239 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7240 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7241 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7242 * @param TIM_ICFilter Specifies the Input Capture Filter.
7243 * This parameter must be a value between 0x00 and 0x0F.
7244 * @retval None
7245 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7246 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7247 * protected against un-initialized filter and polarity values.
7248 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7249 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7250 uint32_t TIM_ICFilter)
7251 {
7252 uint32_t tmpccmr1;
7253 uint32_t tmpccer;
7254
7255 /* Disable the Channel 1: Reset the CC1E Bit */
7256 TIMx->CCER &= ~TIM_CCER_CC1E;
7257 tmpccmr1 = TIMx->CCMR1;
7258 tmpccer = TIMx->CCER;
7259
7260 /* Select the Input */
7261 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7262 {
7263 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7264 tmpccmr1 |= TIM_ICSelection;
7265 }
7266 else
7267 {
7268 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7269 }
7270
7271 /* Set the filter */
7272 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7273 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7274
7275 /* Select the Polarity and set the CC1E Bit */
7276 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7277 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7278
7279 /* Write to TIMx CCMR1 and CCER registers */
7280 TIMx->CCMR1 = tmpccmr1;
7281 TIMx->CCER = tmpccer;
7282 }
7283
7284 /**
7285 * @brief Configure the Polarity and Filter for TI1.
7286 * @param TIMx to select the TIM peripheral.
7287 * @param TIM_ICPolarity The Input Polarity.
7288 * This parameter can be one of the following values:
7289 * @arg TIM_ICPOLARITY_RISING
7290 * @arg TIM_ICPOLARITY_FALLING
7291 * @arg TIM_ICPOLARITY_BOTHEDGE
7292 * @param TIM_ICFilter Specifies the Input Capture Filter.
7293 * This parameter must be a value between 0x00 and 0x0F.
7294 * @retval None
7295 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7296 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7297 {
7298 uint32_t tmpccmr1;
7299 uint32_t tmpccer;
7300
7301 /* Disable the Channel 1: Reset the CC1E Bit */
7302 tmpccer = TIMx->CCER;
7303 TIMx->CCER &= ~TIM_CCER_CC1E;
7304 tmpccmr1 = TIMx->CCMR1;
7305
7306 /* Set the filter */
7307 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7308 tmpccmr1 |= (TIM_ICFilter << 4U);
7309
7310 /* Select the Polarity and set the CC1E Bit */
7311 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7312 tmpccer |= TIM_ICPolarity;
7313
7314 /* Write to TIMx CCMR1 and CCER registers */
7315 TIMx->CCMR1 = tmpccmr1;
7316 TIMx->CCER = tmpccer;
7317 }
7318
7319 /**
7320 * @brief Configure the TI2 as Input.
7321 * @param TIMx to select the TIM peripheral
7322 * @param TIM_ICPolarity The Input Polarity.
7323 * This parameter can be one of the following values:
7324 * @arg TIM_ICPOLARITY_RISING
7325 * @arg TIM_ICPOLARITY_FALLING
7326 * @arg TIM_ICPOLARITY_BOTHEDGE
7327 * @param TIM_ICSelection specifies the input to be used.
7328 * This parameter can be one of the following values:
7329 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7330 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7331 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7332 * @param TIM_ICFilter Specifies the Input Capture Filter.
7333 * This parameter must be a value between 0x00 and 0x0F.
7334 * @retval None
7335 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7336 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7337 * protected against un-initialized filter and polarity values.
7338 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7339 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7340 uint32_t TIM_ICFilter)
7341 {
7342 uint32_t tmpccmr1;
7343 uint32_t tmpccer;
7344
7345 /* Disable the Channel 2: Reset the CC2E Bit */
7346 TIMx->CCER &= ~TIM_CCER_CC2E;
7347 tmpccmr1 = TIMx->CCMR1;
7348 tmpccer = TIMx->CCER;
7349
7350 /* Select the Input */
7351 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7352 tmpccmr1 |= (TIM_ICSelection << 8U);
7353
7354 /* Set the filter */
7355 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7356 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7357
7358 /* Select the Polarity and set the CC2E Bit */
7359 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7360 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7361
7362 /* Write to TIMx CCMR1 and CCER registers */
7363 TIMx->CCMR1 = tmpccmr1 ;
7364 TIMx->CCER = tmpccer;
7365 }
7366
7367 /**
7368 * @brief Configure the Polarity and Filter for TI2.
7369 * @param TIMx to select the TIM peripheral.
7370 * @param TIM_ICPolarity The Input Polarity.
7371 * This parameter can be one of the following values:
7372 * @arg TIM_ICPOLARITY_RISING
7373 * @arg TIM_ICPOLARITY_FALLING
7374 * @arg TIM_ICPOLARITY_BOTHEDGE
7375 * @param TIM_ICFilter Specifies the Input Capture Filter.
7376 * This parameter must be a value between 0x00 and 0x0F.
7377 * @retval None
7378 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7379 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7380 {
7381 uint32_t tmpccmr1;
7382 uint32_t tmpccer;
7383
7384 /* Disable the Channel 2: Reset the CC2E Bit */
7385 TIMx->CCER &= ~TIM_CCER_CC2E;
7386 tmpccmr1 = TIMx->CCMR1;
7387 tmpccer = TIMx->CCER;
7388
7389 /* Set the filter */
7390 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7391 tmpccmr1 |= (TIM_ICFilter << 12U);
7392
7393 /* Select the Polarity and set the CC2E Bit */
7394 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7395 tmpccer |= (TIM_ICPolarity << 4U);
7396
7397 /* Write to TIMx CCMR1 and CCER registers */
7398 TIMx->CCMR1 = tmpccmr1 ;
7399 TIMx->CCER = tmpccer;
7400 }
7401
7402 /**
7403 * @brief Configure the TI3 as Input.
7404 * @param TIMx to select the TIM peripheral
7405 * @param TIM_ICPolarity The Input Polarity.
7406 * This parameter can be one of the following values:
7407 * @arg TIM_ICPOLARITY_RISING
7408 * @arg TIM_ICPOLARITY_FALLING
7409 * @arg TIM_ICPOLARITY_BOTHEDGE
7410 * @param TIM_ICSelection specifies the input to be used.
7411 * This parameter can be one of the following values:
7412 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7413 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7414 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7415 * @param TIM_ICFilter Specifies the Input Capture Filter.
7416 * This parameter must be a value between 0x00 and 0x0F.
7417 * @retval None
7418 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7419 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7420 * protected against un-initialized filter and polarity values.
7421 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7422 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7423 uint32_t TIM_ICFilter)
7424 {
7425 uint32_t tmpccmr2;
7426 uint32_t tmpccer;
7427
7428 /* Disable the Channel 3: Reset the CC3E Bit */
7429 TIMx->CCER &= ~TIM_CCER_CC3E;
7430 tmpccmr2 = TIMx->CCMR2;
7431 tmpccer = TIMx->CCER;
7432
7433 /* Select the Input */
7434 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7435 tmpccmr2 |= TIM_ICSelection;
7436
7437 /* Set the filter */
7438 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7439 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7440
7441 /* Select the Polarity and set the CC3E Bit */
7442 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7443 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7444
7445 /* Write to TIMx CCMR2 and CCER registers */
7446 TIMx->CCMR2 = tmpccmr2;
7447 TIMx->CCER = tmpccer;
7448 }
7449
7450 /**
7451 * @brief Configure the TI4 as Input.
7452 * @param TIMx to select the TIM peripheral
7453 * @param TIM_ICPolarity The Input Polarity.
7454 * This parameter can be one of the following values:
7455 * @arg TIM_ICPOLARITY_RISING
7456 * @arg TIM_ICPOLARITY_FALLING
7457 * @arg TIM_ICPOLARITY_BOTHEDGE
7458 * @param TIM_ICSelection specifies the input to be used.
7459 * This parameter can be one of the following values:
7460 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7461 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7462 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7463 * @param TIM_ICFilter Specifies the Input Capture Filter.
7464 * This parameter must be a value between 0x00 and 0x0F.
7465 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7466 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7467 * protected against un-initialized filter and polarity values.
7468 * @retval None
7469 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7470 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7471 uint32_t TIM_ICFilter)
7472 {
7473 uint32_t tmpccmr2;
7474 uint32_t tmpccer;
7475
7476 /* Disable the Channel 4: Reset the CC4E Bit */
7477 TIMx->CCER &= ~TIM_CCER_CC4E;
7478 tmpccmr2 = TIMx->CCMR2;
7479 tmpccer = TIMx->CCER;
7480
7481 /* Select the Input */
7482 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7483 tmpccmr2 |= (TIM_ICSelection << 8U);
7484
7485 /* Set the filter */
7486 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7487 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7488
7489 /* Select the Polarity and set the CC4E Bit */
7490 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7491 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7492
7493 /* Write to TIMx CCMR2 and CCER registers */
7494 TIMx->CCMR2 = tmpccmr2;
7495 TIMx->CCER = tmpccer ;
7496 }
7497
7498 /**
7499 * @brief Selects the Input Trigger source
7500 * @param TIMx to select the TIM peripheral
7501 * @param InputTriggerSource The Input Trigger source.
7502 * This parameter can be one of the following values:
7503 * @arg TIM_TS_ITR0: Internal Trigger 0
7504 * @arg TIM_TS_ITR1: Internal Trigger 1
7505 * @arg TIM_TS_ITR2: Internal Trigger 2
7506 * @arg TIM_TS_ITR3: Internal Trigger 3
7507 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7508 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7509 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7510 * @arg TIM_TS_ETRF: External Trigger input
7511 * @retval None
7512 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7513 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7514 {
7515 uint32_t tmpsmcr;
7516
7517 /* Get the TIMx SMCR register value */
7518 tmpsmcr = TIMx->SMCR;
7519 /* Reset the TS Bits */
7520 tmpsmcr &= ~TIM_SMCR_TS;
7521 /* Set the Input Trigger source and the slave mode*/
7522 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7523 /* Write to TIMx SMCR */
7524 TIMx->SMCR = tmpsmcr;
7525 }
7526 /**
7527 * @brief Configures the TIMx External Trigger (ETR).
7528 * @param TIMx to select the TIM peripheral
7529 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7530 * This parameter can be one of the following values:
7531 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7532 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7533 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7534 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7535 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7536 * This parameter can be one of the following values:
7537 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7538 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7539 * @param ExtTRGFilter External Trigger Filter.
7540 * This parameter must be a value between 0x00 and 0x0F
7541 * @retval None
7542 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7543 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7544 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7545 {
7546 uint32_t tmpsmcr;
7547
7548 tmpsmcr = TIMx->SMCR;
7549
7550 /* Reset the ETR Bits */
7551 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7552
7553 /* Set the Prescaler, the Filter value and the Polarity */
7554 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7555
7556 /* Write to TIMx SMCR */
7557 TIMx->SMCR = tmpsmcr;
7558 }
7559
7560 /**
7561 * @brief Enables or disables the TIM Capture Compare Channel x.
7562 * @param TIMx to select the TIM peripheral
7563 * @param Channel specifies the TIM Channel
7564 * This parameter can be one of the following values:
7565 * @arg TIM_CHANNEL_1: TIM Channel 1
7566 * @arg TIM_CHANNEL_2: TIM Channel 2
7567 * @arg TIM_CHANNEL_3: TIM Channel 3
7568 * @arg TIM_CHANNEL_4: TIM Channel 4
7569 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7570 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7571 * @retval None
7572 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7573 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7574 {
7575 uint32_t tmp;
7576
7577 /* Check the parameters */
7578 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7579 assert_param(IS_TIM_CHANNELS(Channel));
7580
7581 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7582
7583 /* Reset the CCxE Bit */
7584 TIMx->CCER &= ~tmp;
7585
7586 /* Set or reset the CCxE Bit */
7587 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7588 }
7589
7590 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7591 /**
7592 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7593 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7594 * the configuration information for TIM module.
7595 * @retval None
7596 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7597 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7598 {
7599 /* Reset the TIM callback to the legacy weak callbacks */
7600 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7601 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7602 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7603 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7604 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7605 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7606 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7607 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7608 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7609 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7610 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
7611 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
7612 htim->BreakCallback = HAL_TIMEx_BreakCallback;
7613 }
7614 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7615
7616 /**
7617 * @}
7618 */
7619
7620 #endif /* HAL_TIM_MODULE_ENABLED */
7621 /**
7622 * @}
7623 */
7624
7625 /**
7626 * @}
7627 */
7628
