1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The SPI HAL driver can be used as follows:
29
30 (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 SPI_HandleTypeDef hspi;
32
33 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 (##) Enable the SPIx interface clock
35 (##) SPI pins configuration
36 (+++) Enable the clock for the SPI GPIOs
37 (+++) Configure these SPI pins as alternate function push-pull
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the SPIx interrupt priority
40 (+++) Enable the NVIC SPI IRQ handle
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 (+++) Enable the DMAx clock
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx Stream/Channel
46 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48
49 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51
52 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 by calling the customized HAL_SPI_MspInit() API.
55 [..]
56 Circular mode restriction:
57 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 (##) Master 2Lines RxOnly
59 (##) Master 1Line Rx
60 (#) The CRC feature is not managed when the DMA circular mode is enabled
61 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 [..]
64 Master Receive mode restriction:
65 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 does not initiate a new transfer the following procedure has to be respected:
68 (##) HAL_SPI_DeInit()
69 (##) HAL_SPI_Init()
70 [..]
71 Callback registration:
72
73 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 allows the user to configure dynamically the driver callbacks.
75 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76
77 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 (++) TxCpltCallback : SPI Tx Completed callback
79 (++) RxCpltCallback : SPI Rx Completed callback
80 (++) TxRxCpltCallback : SPI TxRx Completed callback
81 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
82 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
83 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
84 (++) ErrorCallback : SPI Error callback
85 (++) AbortCpltCallback : SPI Abort callback
86 (++) MspInitCallback : SPI Msp Init callback
87 (++) MspDeInitCallback : SPI Msp DeInit callback
88 This function takes as parameters the HAL peripheral handle, the Callback ID
89 and a pointer to the user callback function.
90
91
92 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 weak function.
94 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 and the Callback ID.
96 This function allows to reset following callbacks:
97 (++) TxCpltCallback : SPI Tx Completed callback
98 (++) RxCpltCallback : SPI Rx Completed callback
99 (++) TxRxCpltCallback : SPI TxRx Completed callback
100 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
101 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
102 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
103 (++) ErrorCallback : SPI Error callback
104 (++) AbortCpltCallback : SPI Abort callback
105 (++) MspInitCallback : SPI Msp Init callback
106 (++) MspDeInitCallback : SPI Msp DeInit callback
107
108 [..]
109 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 all callbacks are set to the corresponding weak functions:
111 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 Exception done for MspInit and MspDeInit functions that are
113 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 these callbacks are null (not registered beforehand).
115 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117
118 [..]
119 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 Then, the user first registers the MspInit/MspDeInit user callbacks
124 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 or HAL_SPI_Init() function.
126
127 [..]
128 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 not defined, the callback registering feature is not available
130 and weak (surcharged) callbacks are used.
131
132 [..]
133 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136
137 @endverbatim
138
139 Additional table :
140
141 DataSize = SPI_DATASIZE_8BIT:
142 +----------------------------------------------------------------------------------------------+
143 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
144 | Process | Transfer mode |---------------------|----------------------|----------------------|
145 | | | Master | Slave | Master | Slave | Master | Slave |
146 |==============================================================================================|
147 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
148 | X |----------------|----------|----------|-----------|----------|-----------|----------|
149 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
150 | R |----------------|----------|----------|-----------|----------|-----------|----------|
151 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
152 |=========|================|==========|==========|===========|==========|===========|==========|
153 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
154 | |----------------|----------|----------|-----------|----------|-----------|----------|
155 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
156 | X |----------------|----------|----------|-----------|----------|-----------|----------|
157 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
158 |=========|================|==========|==========|===========|==========|===========|==========|
159 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
160 | |----------------|----------|----------|-----------|----------|-----------|----------|
161 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
162 | X |----------------|----------|----------|-----------|----------|-----------|----------|
163 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
164 +----------------------------------------------------------------------------------------------+
165
166 DataSize = SPI_DATASIZE_16BIT:
167 +----------------------------------------------------------------------------------------------+
168 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
169 | Process | Transfer mode |---------------------|----------------------|----------------------|
170 | | | Master | Slave | Master | Slave | Master | Slave |
171 |==============================================================================================|
172 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
173 | X |----------------|----------|----------|-----------|----------|-----------|----------|
174 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
175 | R |----------------|----------|----------|-----------|----------|-----------|----------|
176 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
177 |=========|================|==========|==========|===========|==========|===========|==========|
178 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
179 | |----------------|----------|----------|-----------|----------|-----------|----------|
180 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
181 | X |----------------|----------|----------|-----------|----------|-----------|----------|
182 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
183 |=========|================|==========|==========|===========|==========|===========|==========|
184 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
185 | |----------------|----------|----------|-----------|----------|-----------|----------|
186 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
187 | X |----------------|----------|----------|-----------|----------|-----------|----------|
188 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
189 +----------------------------------------------------------------------------------------------+
190 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
191 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 @note
193 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196
197 */
198
199 /* Includes ------------------------------------------------------------------*/
200 #include "stm32f0xx_hal.h"
201
202 /** @addtogroup STM32F0xx_HAL_Driver
203 * @{
204 */
205
206 /** @defgroup SPI SPI
207 * @brief SPI HAL module driver
208 * @{
209 */
210 #ifdef HAL_SPI_MODULE_ENABLED
211
212 /* Private typedef -----------------------------------------------------------*/
213 /* Private defines -----------------------------------------------------------*/
214 /** @defgroup SPI_Private_Constants SPI Private Constants
215 * @{
216 */
217 #define SPI_DEFAULT_TIMEOUT 100U
218 /**
219 * @}
220 */
221
222 /* Private macros ------------------------------------------------------------*/
223 /* Private variables ---------------------------------------------------------*/
224 /* Private function prototypes -----------------------------------------------*/
225 /** @defgroup SPI_Private_Functions SPI Private Functions
226 * @{
227 */
228 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
236 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
237 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
238 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
239 uint32_t Timeout, uint32_t Tickstart);
240 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
250 #if (USE_SPI_CRC != 0U)
251 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 #endif /* USE_SPI_CRC */
256 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
261 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
263 /**
264 * @}
265 */
266
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup SPI_Exported_Functions SPI Exported Functions
269 * @{
270 */
271
272 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
273 * @brief Initialization and Configuration functions
274 *
275 @verbatim
276 ===============================================================================
277 ##### Initialization and de-initialization functions #####
278 ===============================================================================
279 [..] This subsection provides a set of functions allowing to initialize and
280 de-initialize the SPIx peripheral:
281
282 (+) User must implement HAL_SPI_MspInit() function in which he configures
283 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
284
285 (+) Call the function HAL_SPI_Init() to configure the selected device with
286 the selected configuration:
287 (++) Mode
288 (++) Direction
289 (++) Data Size
290 (++) Clock Polarity and Phase
291 (++) NSS Management
292 (++) BaudRate Prescaler
293 (++) FirstBit
294 (++) TIMode
295 (++) CRC Calculation
296 (++) CRC Polynomial if CRC enabled
297 (++) CRC Length, used only with Data8 and Data16
298 (++) FIFO reception threshold
299
300 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
301 of the selected SPIx peripheral.
302
303 @endverbatim
304 * @{
305 */
306
307 /**
308 * @brief Initialize the SPI according to the specified parameters
309 * in the SPI_InitTypeDef and initialize the associated handle.
310 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
311 * the configuration information for SPI module.
312 * @retval HAL status
313 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)314 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
315 {
316 uint32_t frxth;
317
318 /* Check the SPI handle allocation */
319 if (hspi == NULL)
320 {
321 return HAL_ERROR;
322 }
323
324 /* Check the parameters */
325 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
326 assert_param(IS_SPI_MODE(hspi->Init.Mode));
327 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
328 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
329 assert_param(IS_SPI_NSS(hspi->Init.NSS));
330 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
331 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
332 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
333 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
334 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
335 {
336 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
337 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
338
339 if (hspi->Init.Mode == SPI_MODE_MASTER)
340 {
341 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
342 }
343 else
344 {
345 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
346 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
347 }
348 }
349 else
350 {
351 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
352
353 /* Force polarity and phase to TI protocaol requirements */
354 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
355 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
356 }
357 #if (USE_SPI_CRC != 0U)
358 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
359 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
360 {
361 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
362 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
363 }
364 #else
365 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
366 #endif /* USE_SPI_CRC */
367
368 if (hspi->State == HAL_SPI_STATE_RESET)
369 {
370 /* Allocate lock resource and initialize it */
371 hspi->Lock = HAL_UNLOCKED;
372
373 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
374 /* Init the SPI Callback settings */
375 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
376 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
377 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
378 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
379 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
380 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
381 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
382 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
383
384 if (hspi->MspInitCallback == NULL)
385 {
386 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
387 }
388
389 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
390 hspi->MspInitCallback(hspi);
391 #else
392 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
393 HAL_SPI_MspInit(hspi);
394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
395 }
396
397 hspi->State = HAL_SPI_STATE_BUSY;
398
399 /* Disable the selected SPI peripheral */
400 __HAL_SPI_DISABLE(hspi);
401
402 /* Align by default the rs fifo threshold on the data size */
403 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
404 {
405 frxth = SPI_RXFIFO_THRESHOLD_HF;
406 }
407 else
408 {
409 frxth = SPI_RXFIFO_THRESHOLD_QF;
410 }
411
412 /* CRC calculation is valid only for 16Bit and 8 Bit */
413 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
414 {
415 /* CRC must be disabled */
416 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
417 }
418
419 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
420 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
421 Communication speed, First bit and CRC calculation state */
422 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
423 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
424 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
425 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
426 (hspi->Init.NSS & SPI_CR1_SSM) |
427 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
428 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
429 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
430 #if (USE_SPI_CRC != 0U)
431 /*---------------------------- SPIx CRCL Configuration -------------------*/
432 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
433 {
434 /* Align the CRC Length on the data size */
435 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
436 {
437 /* CRC Length aligned on the data size : value set by default */
438 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
439 {
440 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
441 }
442 else
443 {
444 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
445 }
446 }
447
448 /* Configure : CRC Length */
449 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
450 {
451 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
452 }
453 }
454 #endif /* USE_SPI_CRC */
455
456 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
457 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
458 (hspi->Init.TIMode & SPI_CR2_FRF) |
459 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
460 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
461 (frxth & SPI_CR2_FRXTH)));
462
463 #if (USE_SPI_CRC != 0U)
464 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
465 /* Configure : CRC Polynomial */
466 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
467 {
468 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
469 }
470 #endif /* USE_SPI_CRC */
471
472 #if defined(SPI_I2SCFGR_I2SMOD)
473 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
474 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
475 #endif /* SPI_I2SCFGR_I2SMOD */
476
477 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
478 hspi->State = HAL_SPI_STATE_READY;
479
480 return HAL_OK;
481 }
482
483 /**
484 * @brief De-Initialize the SPI peripheral.
485 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
486 * the configuration information for SPI module.
487 * @retval HAL status
488 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)489 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
490 {
491 /* Check the SPI handle allocation */
492 if (hspi == NULL)
493 {
494 return HAL_ERROR;
495 }
496
497 /* Check SPI Instance parameter */
498 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
499
500 hspi->State = HAL_SPI_STATE_BUSY;
501
502 /* Disable the SPI Peripheral Clock */
503 __HAL_SPI_DISABLE(hspi);
504
505 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
506 if (hspi->MspDeInitCallback == NULL)
507 {
508 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
509 }
510
511 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
512 hspi->MspDeInitCallback(hspi);
513 #else
514 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
515 HAL_SPI_MspDeInit(hspi);
516 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
517
518 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
519 hspi->State = HAL_SPI_STATE_RESET;
520
521 /* Release Lock */
522 __HAL_UNLOCK(hspi);
523
524 return HAL_OK;
525 }
526
527 /**
528 * @brief Initialize the SPI MSP.
529 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
530 * the configuration information for SPI module.
531 * @retval None
532 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)533 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
534 {
535 /* Prevent unused argument(s) compilation warning */
536 UNUSED(hspi);
537
538 /* NOTE : This function should not be modified, when the callback is needed,
539 the HAL_SPI_MspInit should be implemented in the user file
540 */
541 }
542
543 /**
544 * @brief De-Initialize the SPI MSP.
545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
546 * the configuration information for SPI module.
547 * @retval None
548 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)549 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
550 {
551 /* Prevent unused argument(s) compilation warning */
552 UNUSED(hspi);
553
554 /* NOTE : This function should not be modified, when the callback is needed,
555 the HAL_SPI_MspDeInit should be implemented in the user file
556 */
557 }
558
559 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
560 /**
561 * @brief Register a User SPI Callback
562 * To be used instead of the weak predefined callback
563 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
564 * the configuration information for the specified SPI.
565 * @param CallbackID ID of the callback to be registered
566 * @param pCallback pointer to the Callback function
567 * @retval HAL status
568 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)569 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
570 pSPI_CallbackTypeDef pCallback)
571 {
572 HAL_StatusTypeDef status = HAL_OK;
573
574 if (pCallback == NULL)
575 {
576 /* Update the error code */
577 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
578
579 return HAL_ERROR;
580 }
581 /* Process locked */
582 __HAL_LOCK(hspi);
583
584 if (HAL_SPI_STATE_READY == hspi->State)
585 {
586 switch (CallbackID)
587 {
588 case HAL_SPI_TX_COMPLETE_CB_ID :
589 hspi->TxCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_RX_COMPLETE_CB_ID :
593 hspi->RxCpltCallback = pCallback;
594 break;
595
596 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
597 hspi->TxRxCpltCallback = pCallback;
598 break;
599
600 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
601 hspi->TxHalfCpltCallback = pCallback;
602 break;
603
604 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
605 hspi->RxHalfCpltCallback = pCallback;
606 break;
607
608 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
609 hspi->TxRxHalfCpltCallback = pCallback;
610 break;
611
612 case HAL_SPI_ERROR_CB_ID :
613 hspi->ErrorCallback = pCallback;
614 break;
615
616 case HAL_SPI_ABORT_CB_ID :
617 hspi->AbortCpltCallback = pCallback;
618 break;
619
620 case HAL_SPI_MSPINIT_CB_ID :
621 hspi->MspInitCallback = pCallback;
622 break;
623
624 case HAL_SPI_MSPDEINIT_CB_ID :
625 hspi->MspDeInitCallback = pCallback;
626 break;
627
628 default :
629 /* Update the error code */
630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
631
632 /* Return error status */
633 status = HAL_ERROR;
634 break;
635 }
636 }
637 else if (HAL_SPI_STATE_RESET == hspi->State)
638 {
639 switch (CallbackID)
640 {
641 case HAL_SPI_MSPINIT_CB_ID :
642 hspi->MspInitCallback = pCallback;
643 break;
644
645 case HAL_SPI_MSPDEINIT_CB_ID :
646 hspi->MspDeInitCallback = pCallback;
647 break;
648
649 default :
650 /* Update the error code */
651 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
652
653 /* Return error status */
654 status = HAL_ERROR;
655 break;
656 }
657 }
658 else
659 {
660 /* Update the error code */
661 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
662
663 /* Return error status */
664 status = HAL_ERROR;
665 }
666
667 /* Release Lock */
668 __HAL_UNLOCK(hspi);
669 return status;
670 }
671
672 /**
673 * @brief Unregister an SPI Callback
674 * SPI callback is redirected to the weak predefined callback
675 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
676 * the configuration information for the specified SPI.
677 * @param CallbackID ID of the callback to be unregistered
678 * @retval HAL status
679 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)680 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
681 {
682 HAL_StatusTypeDef status = HAL_OK;
683
684 /* Process locked */
685 __HAL_LOCK(hspi);
686
687 if (HAL_SPI_STATE_READY == hspi->State)
688 {
689 switch (CallbackID)
690 {
691 case HAL_SPI_TX_COMPLETE_CB_ID :
692 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
693 break;
694
695 case HAL_SPI_RX_COMPLETE_CB_ID :
696 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
697 break;
698
699 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
700 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
701 break;
702
703 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
704 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
705 break;
706
707 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
708 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
709 break;
710
711 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
712 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
713 break;
714
715 case HAL_SPI_ERROR_CB_ID :
716 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
717 break;
718
719 case HAL_SPI_ABORT_CB_ID :
720 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
721 break;
722
723 case HAL_SPI_MSPINIT_CB_ID :
724 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
725 break;
726
727 case HAL_SPI_MSPDEINIT_CB_ID :
728 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
729 break;
730
731 default :
732 /* Update the error code */
733 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 break;
738 }
739 }
740 else if (HAL_SPI_STATE_RESET == hspi->State)
741 {
742 switch (CallbackID)
743 {
744 case HAL_SPI_MSPINIT_CB_ID :
745 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
746 break;
747
748 case HAL_SPI_MSPDEINIT_CB_ID :
749 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
750 break;
751
752 default :
753 /* Update the error code */
754 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
755
756 /* Return error status */
757 status = HAL_ERROR;
758 break;
759 }
760 }
761 else
762 {
763 /* Update the error code */
764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
765
766 /* Return error status */
767 status = HAL_ERROR;
768 }
769
770 /* Release Lock */
771 __HAL_UNLOCK(hspi);
772 return status;
773 }
774 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
775 /**
776 * @}
777 */
778
779 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
780 * @brief Data transfers functions
781 *
782 @verbatim
783 ==============================================================================
784 ##### IO operation functions #####
785 ===============================================================================
786 [..]
787 This subsection provides a set of functions allowing to manage the SPI
788 data transfers.
789
790 [..] The SPI supports master and slave mode :
791
792 (#) There are two modes of transfer:
793 (++) Blocking mode: The communication is performed in polling mode.
794 The HAL status of all data processing is returned by the same function
795 after finishing transfer.
796 (++) No-Blocking mode: The communication is performed using Interrupts
797 or DMA, These APIs return the HAL status.
798 The end of the data processing will be indicated through the
799 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
800 using DMA mode.
801 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
802 will be executed respectively at the end of the transmit or Receive process
803 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
804
805 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
806 exist for 1Line (simplex) and 2Lines (full duplex) modes.
807
808 @endverbatim
809 * @{
810 */
811
812 /**
813 * @brief Transmit an amount of data in blocking mode.
814 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
815 * the configuration information for SPI module.
816 * @param pData pointer to data buffer
817 * @param Size amount of data to be sent
818 * @param Timeout Timeout duration
819 * @retval HAL status
820 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)821 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
822 {
823 uint32_t tickstart;
824 HAL_StatusTypeDef errorcode = HAL_OK;
825 uint16_t initial_TxXferCount;
826
827 /* Check Direction parameter */
828 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
829
830 /* Process Locked */
831 __HAL_LOCK(hspi);
832
833 /* Init tickstart for timeout management*/
834 tickstart = HAL_GetTick();
835 initial_TxXferCount = Size;
836
837 if (hspi->State != HAL_SPI_STATE_READY)
838 {
839 errorcode = HAL_BUSY;
840 goto error;
841 }
842
843 if ((pData == NULL) || (Size == 0U))
844 {
845 errorcode = HAL_ERROR;
846 goto error;
847 }
848
849 /* Set the transaction information */
850 hspi->State = HAL_SPI_STATE_BUSY_TX;
851 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
852 hspi->pTxBuffPtr = (uint8_t *)pData;
853 hspi->TxXferSize = Size;
854 hspi->TxXferCount = Size;
855
856 /*Init field not used in handle to zero */
857 hspi->pRxBuffPtr = (uint8_t *)NULL;
858 hspi->RxXferSize = 0U;
859 hspi->RxXferCount = 0U;
860 hspi->TxISR = NULL;
861 hspi->RxISR = NULL;
862
863 /* Configure communication direction : 1Line */
864 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
865 {
866 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
867 __HAL_SPI_DISABLE(hspi);
868 SPI_1LINE_TX(hspi);
869 }
870
871 #if (USE_SPI_CRC != 0U)
872 /* Reset CRC Calculation */
873 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
874 {
875 SPI_RESET_CRC(hspi);
876 }
877 #endif /* USE_SPI_CRC */
878
879 /* Check if the SPI is already enabled */
880 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
881 {
882 /* Enable SPI peripheral */
883 __HAL_SPI_ENABLE(hspi);
884 }
885
886 /* Transmit data in 16 Bit mode */
887 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
888 {
889 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
890 {
891 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount--;
894 }
895 /* Transmit data in 16 Bit mode */
896 while (hspi->TxXferCount > 0U)
897 {
898 /* Wait until TXE flag is set to send data */
899 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
900 {
901 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
902 hspi->pTxBuffPtr += sizeof(uint16_t);
903 hspi->TxXferCount--;
904 }
905 else
906 {
907 /* Timeout management */
908 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
909 {
910 errorcode = HAL_TIMEOUT;
911 hspi->State = HAL_SPI_STATE_READY;
912 goto error;
913 }
914 }
915 }
916 }
917 /* Transmit data in 8 Bit mode */
918 else
919 {
920 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
921 {
922 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
923 hspi->pTxBuffPtr += sizeof(uint8_t);
924 hspi->TxXferCount--;
925 }
926 while (hspi->TxXferCount > 0U)
927 {
928 /* Wait until TXE flag is set to send data */
929 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
930 {
931 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
932 hspi->pTxBuffPtr += sizeof(uint8_t);
933 hspi->TxXferCount--;
934 }
935 else
936 {
937 /* Timeout management */
938 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
939 {
940 errorcode = HAL_TIMEOUT;
941 hspi->State = HAL_SPI_STATE_READY;
942 goto error;
943 }
944 }
945 }
946 }
947 #if (USE_SPI_CRC != 0U)
948 /* Enable CRC Transmission */
949 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
950 {
951 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
952 }
953 #endif /* USE_SPI_CRC */
954
955 /* Check the end of the transaction */
956 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
957 {
958 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
959 }
960
961 /* Clear overrun flag in 2 Lines communication mode because received is not read */
962 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
963 {
964 __HAL_SPI_CLEAR_OVRFLAG(hspi);
965 }
966
967 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
968 {
969 errorcode = HAL_ERROR;
970 }
971 else
972 {
973 hspi->State = HAL_SPI_STATE_READY;
974 }
975
976 error:
977 /* Process Unlocked */
978 __HAL_UNLOCK(hspi);
979 return errorcode;
980 }
981
982 /**
983 * @brief Receive an amount of data in blocking mode.
984 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
985 * the configuration information for SPI module.
986 * @param pData pointer to data buffer
987 * @param Size amount of data to be received
988 * @param Timeout Timeout duration
989 * @retval HAL status
990 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)991 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
992 {
993 #if (USE_SPI_CRC != 0U)
994 __IO uint32_t tmpreg = 0U;
995 __IO uint8_t *ptmpreg8;
996 __IO uint8_t tmpreg8 = 0;
997 #endif /* USE_SPI_CRC */
998 uint32_t tickstart;
999 HAL_StatusTypeDef errorcode = HAL_OK;
1000
1001 if (hspi->State != HAL_SPI_STATE_READY)
1002 {
1003 errorcode = HAL_BUSY;
1004 goto error;
1005 }
1006
1007 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1008 {
1009 hspi->State = HAL_SPI_STATE_BUSY_RX;
1010 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1011 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1012 }
1013
1014 /* Process Locked */
1015 __HAL_LOCK(hspi);
1016
1017 /* Init tickstart for timeout management*/
1018 tickstart = HAL_GetTick();
1019
1020 if ((pData == NULL) || (Size == 0U))
1021 {
1022 errorcode = HAL_ERROR;
1023 goto error;
1024 }
1025
1026 /* Set the transaction information */
1027 hspi->State = HAL_SPI_STATE_BUSY_RX;
1028 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1029 hspi->pRxBuffPtr = (uint8_t *)pData;
1030 hspi->RxXferSize = Size;
1031 hspi->RxXferCount = Size;
1032
1033 /*Init field not used in handle to zero */
1034 hspi->pTxBuffPtr = (uint8_t *)NULL;
1035 hspi->TxXferSize = 0U;
1036 hspi->TxXferCount = 0U;
1037 hspi->RxISR = NULL;
1038 hspi->TxISR = NULL;
1039
1040 #if (USE_SPI_CRC != 0U)
1041 /* Reset CRC Calculation */
1042 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1043 {
1044 SPI_RESET_CRC(hspi);
1045 /* this is done to handle the CRCNEXT before the latest data */
1046 hspi->RxXferCount--;
1047 }
1048 #endif /* USE_SPI_CRC */
1049
1050 /* Set the Rx Fifo threshold */
1051 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1052 {
1053 /* Set RX Fifo threshold according the reception data length: 16bit */
1054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1055 }
1056 else
1057 {
1058 /* Set RX Fifo threshold according the reception data length: 8bit */
1059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1060 }
1061
1062 /* Configure communication direction: 1Line */
1063 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1064 {
1065 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1066 __HAL_SPI_DISABLE(hspi);
1067 SPI_1LINE_RX(hspi);
1068 }
1069
1070 /* Check if the SPI is already enabled */
1071 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1072 {
1073 /* Enable SPI peripheral */
1074 __HAL_SPI_ENABLE(hspi);
1075 }
1076
1077 /* Receive data in 8 Bit mode */
1078 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1079 {
1080 /* Transfer loop */
1081 while (hspi->RxXferCount > 0U)
1082 {
1083 /* Check the RXNE flag */
1084 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1085 {
1086 /* read the received data */
1087 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1088 hspi->pRxBuffPtr += sizeof(uint8_t);
1089 hspi->RxXferCount--;
1090 }
1091 else
1092 {
1093 /* Timeout management */
1094 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1095 {
1096 errorcode = HAL_TIMEOUT;
1097 hspi->State = HAL_SPI_STATE_READY;
1098 goto error;
1099 }
1100 }
1101 }
1102 }
1103 else
1104 {
1105 /* Transfer loop */
1106 while (hspi->RxXferCount > 0U)
1107 {
1108 /* Check the RXNE flag */
1109 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1110 {
1111 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1112 hspi->pRxBuffPtr += sizeof(uint16_t);
1113 hspi->RxXferCount--;
1114 }
1115 else
1116 {
1117 /* Timeout management */
1118 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1119 {
1120 errorcode = HAL_TIMEOUT;
1121 hspi->State = HAL_SPI_STATE_READY;
1122 goto error;
1123 }
1124 }
1125 }
1126 }
1127
1128 #if (USE_SPI_CRC != 0U)
1129 /* Handle the CRC Transmission */
1130 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1131 {
1132 /* freeze the CRC before the latest data */
1133 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1134
1135 /* Read the latest data */
1136 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1137 {
1138 /* the latest data has not been received */
1139 errorcode = HAL_TIMEOUT;
1140 goto error;
1141 }
1142
1143 /* Receive last data in 16 Bit mode */
1144 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1145 {
1146 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1147 }
1148 /* Receive last data in 8 Bit mode */
1149 else
1150 {
1151 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1152 }
1153
1154 /* Wait the CRC data */
1155 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1156 {
1157 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1158 errorcode = HAL_TIMEOUT;
1159 goto error;
1160 }
1161
1162 /* Read CRC to Flush DR and RXNE flag */
1163 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1164 {
1165 /* Read 16bit CRC */
1166 tmpreg = READ_REG(hspi->Instance->DR);
1167 /* To avoid GCC warning */
1168 UNUSED(tmpreg);
1169 }
1170 else
1171 {
1172 /* Initialize the 8bit temporary pointer */
1173 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1174 /* Read 8bit CRC */
1175 tmpreg8 = *ptmpreg8;
1176 /* To avoid GCC warning */
1177 UNUSED(tmpreg8);
1178
1179 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1180 {
1181 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1182 {
1183 /* Error on the CRC reception */
1184 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1185 errorcode = HAL_TIMEOUT;
1186 goto error;
1187 }
1188 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1189 tmpreg8 = *ptmpreg8;
1190 /* To avoid GCC warning */
1191 UNUSED(tmpreg8);
1192 }
1193 }
1194 }
1195 #endif /* USE_SPI_CRC */
1196
1197 /* Check the end of the transaction */
1198 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1199 {
1200 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1201 }
1202
1203 #if (USE_SPI_CRC != 0U)
1204 /* Check if CRC error occurred */
1205 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1206 {
1207 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1208 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1209 }
1210 #endif /* USE_SPI_CRC */
1211
1212 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1213 {
1214 errorcode = HAL_ERROR;
1215 }
1216 else
1217 {
1218 hspi->State = HAL_SPI_STATE_READY;
1219 }
1220
1221 error :
1222 __HAL_UNLOCK(hspi);
1223 return errorcode;
1224 }
1225
1226 /**
1227 * @brief Transmit and Receive an amount of data in blocking mode.
1228 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1229 * the configuration information for SPI module.
1230 * @param pTxData pointer to transmission data buffer
1231 * @param pRxData pointer to reception data buffer
1232 * @param Size amount of data to be sent and received
1233 * @param Timeout Timeout duration
1234 * @retval HAL status
1235 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1236 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1237 uint32_t Timeout)
1238 {
1239 uint16_t initial_TxXferCount;
1240 uint32_t tmp_mode;
1241 HAL_SPI_StateTypeDef tmp_state;
1242 uint32_t tickstart;
1243 #if (USE_SPI_CRC != 0U)
1244 __IO uint32_t tmpreg = 0U;
1245 uint32_t spi_cr1;
1246 uint32_t spi_cr2;
1247 __IO uint8_t *ptmpreg8;
1248 __IO uint8_t tmpreg8 = 0;
1249 #endif /* USE_SPI_CRC */
1250
1251 /* Variable used to alternate Rx and Tx during transfer */
1252 uint32_t txallowed = 1U;
1253 HAL_StatusTypeDef errorcode = HAL_OK;
1254
1255 /* Check Direction parameter */
1256 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1257
1258 /* Process Locked */
1259 __HAL_LOCK(hspi);
1260
1261 /* Init tickstart for timeout management*/
1262 tickstart = HAL_GetTick();
1263
1264 /* Init temporary variables */
1265 tmp_state = hspi->State;
1266 tmp_mode = hspi->Init.Mode;
1267 initial_TxXferCount = Size;
1268 #if (USE_SPI_CRC != 0U)
1269 spi_cr1 = READ_REG(hspi->Instance->CR1);
1270 spi_cr2 = READ_REG(hspi->Instance->CR2);
1271 #endif /* USE_SPI_CRC */
1272
1273 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1274 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1275 {
1276 errorcode = HAL_BUSY;
1277 goto error;
1278 }
1279
1280 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1281 {
1282 errorcode = HAL_ERROR;
1283 goto error;
1284 }
1285
1286 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1287 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1288 {
1289 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1290 }
1291
1292 /* Set the transaction information */
1293 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1294 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1295 hspi->RxXferCount = Size;
1296 hspi->RxXferSize = Size;
1297 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1298 hspi->TxXferCount = Size;
1299 hspi->TxXferSize = Size;
1300
1301 /*Init field not used in handle to zero */
1302 hspi->RxISR = NULL;
1303 hspi->TxISR = NULL;
1304
1305 #if (USE_SPI_CRC != 0U)
1306 /* Reset CRC Calculation */
1307 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1308 {
1309 SPI_RESET_CRC(hspi);
1310 }
1311 #endif /* USE_SPI_CRC */
1312
1313 /* Set the Rx Fifo threshold */
1314 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1315 {
1316 /* Set fiforxthreshold according the reception data length: 16bit */
1317 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1318 }
1319 else
1320 {
1321 /* Set fiforxthreshold according the reception data length: 8bit */
1322 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1323 }
1324
1325 /* Check if the SPI is already enabled */
1326 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1327 {
1328 /* Enable SPI peripheral */
1329 __HAL_SPI_ENABLE(hspi);
1330 }
1331
1332 /* Transmit and Receive data in 16 Bit mode */
1333 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1334 {
1335 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1336 {
1337 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1338 hspi->pTxBuffPtr += sizeof(uint16_t);
1339 hspi->TxXferCount--;
1340 }
1341 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1342 {
1343 /* Check TXE flag */
1344 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1345 {
1346 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1347 hspi->pTxBuffPtr += sizeof(uint16_t);
1348 hspi->TxXferCount--;
1349 /* Next Data is a reception (Rx). Tx not allowed */
1350 txallowed = 0U;
1351
1352 #if (USE_SPI_CRC != 0U)
1353 /* Enable CRC Transmission */
1354 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1355 {
1356 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1357 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1358 {
1359 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1360 }
1361 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1362 }
1363 #endif /* USE_SPI_CRC */
1364 }
1365
1366 /* Check RXNE flag */
1367 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1368 {
1369 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1370 hspi->pRxBuffPtr += sizeof(uint16_t);
1371 hspi->RxXferCount--;
1372 /* Next Data is a Transmission (Tx). Tx is allowed */
1373 txallowed = 1U;
1374 }
1375 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1376 {
1377 errorcode = HAL_TIMEOUT;
1378 hspi->State = HAL_SPI_STATE_READY;
1379 goto error;
1380 }
1381 }
1382 }
1383 /* Transmit and Receive data in 8 Bit mode */
1384 else
1385 {
1386 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1387 {
1388 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1389 hspi->pTxBuffPtr += sizeof(uint8_t);
1390 hspi->TxXferCount--;
1391 }
1392 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1393 {
1394 /* Check TXE flag */
1395 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1396 {
1397 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1398 hspi->pTxBuffPtr++;
1399 hspi->TxXferCount--;
1400 /* Next Data is a reception (Rx). Tx not allowed */
1401 txallowed = 0U;
1402
1403 #if (USE_SPI_CRC != 0U)
1404 /* Enable CRC Transmission */
1405 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1406 {
1407 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1408 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1409 {
1410 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1411 }
1412 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1413 }
1414 #endif /* USE_SPI_CRC */
1415 }
1416
1417 /* Wait until RXNE flag is reset */
1418 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1419 {
1420 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1421 hspi->pRxBuffPtr++;
1422 hspi->RxXferCount--;
1423 /* Next Data is a Transmission (Tx). Tx is allowed */
1424 txallowed = 1U;
1425 }
1426 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1427 {
1428 errorcode = HAL_TIMEOUT;
1429 hspi->State = HAL_SPI_STATE_READY;
1430 goto error;
1431 }
1432 }
1433 }
1434
1435 #if (USE_SPI_CRC != 0U)
1436 /* Read CRC from DR to close CRC calculation process */
1437 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1438 {
1439 /* Wait until TXE flag */
1440 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1441 {
1442 /* Error on the CRC reception */
1443 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1444 errorcode = HAL_TIMEOUT;
1445 goto error;
1446 }
1447 /* Read CRC */
1448 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1449 {
1450 /* Read 16bit CRC */
1451 tmpreg = READ_REG(hspi->Instance->DR);
1452 /* To avoid GCC warning */
1453 UNUSED(tmpreg);
1454 }
1455 else
1456 {
1457 /* Initialize the 8bit temporary pointer */
1458 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
1459 /* Read 8bit CRC */
1460 tmpreg8 = *ptmpreg8;
1461 /* To avoid GCC warning */
1462 UNUSED(tmpreg8);
1463
1464 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1465 {
1466 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1467 {
1468 /* Error on the CRC reception */
1469 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1470 errorcode = HAL_TIMEOUT;
1471 goto error;
1472 }
1473 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1474 tmpreg8 = *ptmpreg8;
1475 /* To avoid GCC warning */
1476 UNUSED(tmpreg8);
1477 }
1478 }
1479 }
1480
1481 /* Check if CRC error occurred */
1482 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1483 {
1484 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1485 /* Clear CRC Flag */
1486 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1487
1488 errorcode = HAL_ERROR;
1489 }
1490 #endif /* USE_SPI_CRC */
1491
1492 /* Check the end of the transaction */
1493 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1494 {
1495 errorcode = HAL_ERROR;
1496 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1497 }
1498
1499 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1500 {
1501 errorcode = HAL_ERROR;
1502 }
1503 else
1504 {
1505 hspi->State = HAL_SPI_STATE_READY;
1506 }
1507
1508 error :
1509 __HAL_UNLOCK(hspi);
1510 return errorcode;
1511 }
1512
1513 /**
1514 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1515 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1516 * the configuration information for SPI module.
1517 * @param pData pointer to data buffer
1518 * @param Size amount of data to be sent
1519 * @retval HAL status
1520 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1521 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1522 {
1523 HAL_StatusTypeDef errorcode = HAL_OK;
1524
1525 /* Check Direction parameter */
1526 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1527
1528 /* Process Locked */
1529 __HAL_LOCK(hspi);
1530
1531 if ((pData == NULL) || (Size == 0U))
1532 {
1533 errorcode = HAL_ERROR;
1534 goto error;
1535 }
1536
1537 if (hspi->State != HAL_SPI_STATE_READY)
1538 {
1539 errorcode = HAL_BUSY;
1540 goto error;
1541 }
1542
1543 /* Set the transaction information */
1544 hspi->State = HAL_SPI_STATE_BUSY_TX;
1545 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1546 hspi->pTxBuffPtr = (uint8_t *)pData;
1547 hspi->TxXferSize = Size;
1548 hspi->TxXferCount = Size;
1549
1550 /* Init field not used in handle to zero */
1551 hspi->pRxBuffPtr = (uint8_t *)NULL;
1552 hspi->RxXferSize = 0U;
1553 hspi->RxXferCount = 0U;
1554 hspi->RxISR = NULL;
1555
1556 /* Set the function for IT treatment */
1557 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1558 {
1559 hspi->TxISR = SPI_TxISR_16BIT;
1560 }
1561 else
1562 {
1563 hspi->TxISR = SPI_TxISR_8BIT;
1564 }
1565
1566 /* Configure communication direction : 1Line */
1567 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1568 {
1569 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1570 __HAL_SPI_DISABLE(hspi);
1571 SPI_1LINE_TX(hspi);
1572 }
1573
1574 #if (USE_SPI_CRC != 0U)
1575 /* Reset CRC Calculation */
1576 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1577 {
1578 SPI_RESET_CRC(hspi);
1579 }
1580 #endif /* USE_SPI_CRC */
1581
1582 /* Enable TXE and ERR interrupt */
1583 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1584
1585
1586 /* Check if the SPI is already enabled */
1587 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1588 {
1589 /* Enable SPI peripheral */
1590 __HAL_SPI_ENABLE(hspi);
1591 }
1592
1593 error :
1594 __HAL_UNLOCK(hspi);
1595 return errorcode;
1596 }
1597
1598 /**
1599 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1600 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1601 * the configuration information for SPI module.
1602 * @param pData pointer to data buffer
1603 * @param Size amount of data to be sent
1604 * @retval HAL status
1605 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1606 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1607 {
1608 HAL_StatusTypeDef errorcode = HAL_OK;
1609
1610
1611 if (hspi->State != HAL_SPI_STATE_READY)
1612 {
1613 errorcode = HAL_BUSY;
1614 goto error;
1615 }
1616
1617 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1618 {
1619 hspi->State = HAL_SPI_STATE_BUSY_RX;
1620 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1621 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1622 }
1623
1624 /* Process Locked */
1625 __HAL_LOCK(hspi);
1626
1627 if ((pData == NULL) || (Size == 0U))
1628 {
1629 errorcode = HAL_ERROR;
1630 goto error;
1631 }
1632
1633 /* Set the transaction information */
1634 hspi->State = HAL_SPI_STATE_BUSY_RX;
1635 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1636 hspi->pRxBuffPtr = (uint8_t *)pData;
1637 hspi->RxXferSize = Size;
1638 hspi->RxXferCount = Size;
1639
1640 /* Init field not used in handle to zero */
1641 hspi->pTxBuffPtr = (uint8_t *)NULL;
1642 hspi->TxXferSize = 0U;
1643 hspi->TxXferCount = 0U;
1644 hspi->TxISR = NULL;
1645
1646 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1647 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1648 {
1649 /* Set RX Fifo threshold according the reception data length: 16 bit */
1650 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1651 hspi->RxISR = SPI_RxISR_16BIT;
1652 }
1653 else
1654 {
1655 /* Set RX Fifo threshold according the reception data length: 8 bit */
1656 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1657 hspi->RxISR = SPI_RxISR_8BIT;
1658 }
1659
1660 /* Configure communication direction : 1Line */
1661 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1662 {
1663 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1664 __HAL_SPI_DISABLE(hspi);
1665 SPI_1LINE_RX(hspi);
1666 }
1667
1668 #if (USE_SPI_CRC != 0U)
1669 /* Reset CRC Calculation */
1670 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1671 {
1672 hspi->CRCSize = 1U;
1673 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1674 {
1675 hspi->CRCSize = 2U;
1676 }
1677 SPI_RESET_CRC(hspi);
1678 }
1679 else
1680 {
1681 hspi->CRCSize = 0U;
1682 }
1683 #endif /* USE_SPI_CRC */
1684
1685 /* Enable TXE and ERR interrupt */
1686 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1687
1688 /* Note : The SPI must be enabled after unlocking current process
1689 to avoid the risk of SPI interrupt handle execution before current
1690 process unlock */
1691
1692 /* Check if the SPI is already enabled */
1693 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1694 {
1695 /* Enable SPI peripheral */
1696 __HAL_SPI_ENABLE(hspi);
1697 }
1698
1699 error :
1700 /* Process Unlocked */
1701 __HAL_UNLOCK(hspi);
1702 return errorcode;
1703 }
1704
1705 /**
1706 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1707 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1708 * the configuration information for SPI module.
1709 * @param pTxData pointer to transmission data buffer
1710 * @param pRxData pointer to reception data buffer
1711 * @param Size amount of data to be sent and received
1712 * @retval HAL status
1713 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1714 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1715 {
1716 uint32_t tmp_mode;
1717 HAL_SPI_StateTypeDef tmp_state;
1718 HAL_StatusTypeDef errorcode = HAL_OK;
1719
1720 /* Check Direction parameter */
1721 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1722
1723 /* Process locked */
1724 __HAL_LOCK(hspi);
1725
1726 /* Init temporary variables */
1727 tmp_state = hspi->State;
1728 tmp_mode = hspi->Init.Mode;
1729
1730 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1731 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1732 {
1733 errorcode = HAL_BUSY;
1734 goto error;
1735 }
1736
1737 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1738 {
1739 errorcode = HAL_ERROR;
1740 goto error;
1741 }
1742
1743 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1744 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1745 {
1746 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1747 }
1748
1749 /* Set the transaction information */
1750 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1751 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1752 hspi->TxXferSize = Size;
1753 hspi->TxXferCount = Size;
1754 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1755 hspi->RxXferSize = Size;
1756 hspi->RxXferCount = Size;
1757
1758 /* Set the function for IT treatment */
1759 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1760 {
1761 hspi->RxISR = SPI_2linesRxISR_16BIT;
1762 hspi->TxISR = SPI_2linesTxISR_16BIT;
1763 }
1764 else
1765 {
1766 hspi->RxISR = SPI_2linesRxISR_8BIT;
1767 hspi->TxISR = SPI_2linesTxISR_8BIT;
1768 }
1769
1770 #if (USE_SPI_CRC != 0U)
1771 /* Reset CRC Calculation */
1772 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1773 {
1774 hspi->CRCSize = 1U;
1775 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1776 {
1777 hspi->CRCSize = 2U;
1778 }
1779 SPI_RESET_CRC(hspi);
1780 }
1781 else
1782 {
1783 hspi->CRCSize = 0U;
1784 }
1785 #endif /* USE_SPI_CRC */
1786
1787 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1788 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1789 {
1790 /* Set RX Fifo threshold according the reception data length: 16 bit */
1791 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1792 }
1793 else
1794 {
1795 /* Set RX Fifo threshold according the reception data length: 8 bit */
1796 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1797 }
1798
1799 /* Enable TXE, RXNE and ERR interrupt */
1800 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1801
1802 /* Check if the SPI is already enabled */
1803 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1804 {
1805 /* Enable SPI peripheral */
1806 __HAL_SPI_ENABLE(hspi);
1807 }
1808
1809 error :
1810 /* Process Unlocked */
1811 __HAL_UNLOCK(hspi);
1812 return errorcode;
1813 }
1814
1815 /**
1816 * @brief Transmit an amount of data in non-blocking mode with DMA.
1817 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1818 * the configuration information for SPI module.
1819 * @param pData pointer to data buffer
1820 * @param Size amount of data to be sent
1821 * @retval HAL status
1822 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1823 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1824 {
1825 HAL_StatusTypeDef errorcode = HAL_OK;
1826
1827 /* Check tx dma handle */
1828 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1829
1830 /* Check Direction parameter */
1831 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1832
1833 /* Process Locked */
1834 __HAL_LOCK(hspi);
1835
1836 if (hspi->State != HAL_SPI_STATE_READY)
1837 {
1838 errorcode = HAL_BUSY;
1839 goto error;
1840 }
1841
1842 if ((pData == NULL) || (Size == 0U))
1843 {
1844 errorcode = HAL_ERROR;
1845 goto error;
1846 }
1847
1848 /* Set the transaction information */
1849 hspi->State = HAL_SPI_STATE_BUSY_TX;
1850 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1851 hspi->pTxBuffPtr = (uint8_t *)pData;
1852 hspi->TxXferSize = Size;
1853 hspi->TxXferCount = Size;
1854
1855 /* Init field not used in handle to zero */
1856 hspi->pRxBuffPtr = (uint8_t *)NULL;
1857 hspi->TxISR = NULL;
1858 hspi->RxISR = NULL;
1859 hspi->RxXferSize = 0U;
1860 hspi->RxXferCount = 0U;
1861
1862 /* Configure communication direction : 1Line */
1863 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1864 {
1865 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1866 __HAL_SPI_DISABLE(hspi);
1867 SPI_1LINE_TX(hspi);
1868 }
1869
1870 #if (USE_SPI_CRC != 0U)
1871 /* Reset CRC Calculation */
1872 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1873 {
1874 SPI_RESET_CRC(hspi);
1875 }
1876 #endif /* USE_SPI_CRC */
1877
1878 /* Set the SPI TxDMA Half transfer complete callback */
1879 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1880
1881 /* Set the SPI TxDMA transfer complete callback */
1882 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1883
1884 /* Set the DMA error callback */
1885 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1886
1887 /* Set the DMA AbortCpltCallback */
1888 hspi->hdmatx->XferAbortCallback = NULL;
1889
1890 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1891 /* Packing mode is enabled only if the DMA setting is HALWORD */
1892 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1893 {
1894 /* Check the even/odd of the data size + crc if enabled */
1895 if ((hspi->TxXferCount & 0x1U) == 0U)
1896 {
1897 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1898 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1899 }
1900 else
1901 {
1902 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1903 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1904 }
1905 }
1906
1907 /* Enable the Tx DMA Stream/Channel */
1908 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1909 hspi->TxXferCount))
1910 {
1911 /* Update SPI error code */
1912 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1913 errorcode = HAL_ERROR;
1914
1915 goto error;
1916 }
1917
1918 /* Check if the SPI is already enabled */
1919 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1920 {
1921 /* Enable SPI peripheral */
1922 __HAL_SPI_ENABLE(hspi);
1923 }
1924
1925 /* Enable the SPI Error Interrupt Bit */
1926 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1927
1928 /* Enable Tx DMA Request */
1929 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1930
1931 error :
1932 /* Process Unlocked */
1933 __HAL_UNLOCK(hspi);
1934 return errorcode;
1935 }
1936
1937 /**
1938 * @brief Receive an amount of data in non-blocking mode with DMA.
1939 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1940 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1941 * the configuration information for SPI module.
1942 * @param pData pointer to data buffer
1943 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1944 * @param Size amount of data to be sent
1945 * @retval HAL status
1946 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1947 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1948 {
1949 HAL_StatusTypeDef errorcode = HAL_OK;
1950
1951 /* Check rx dma handle */
1952 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1953
1954 if (hspi->State != HAL_SPI_STATE_READY)
1955 {
1956 errorcode = HAL_BUSY;
1957 goto error;
1958 }
1959
1960 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1961 {
1962 hspi->State = HAL_SPI_STATE_BUSY_RX;
1963
1964 /* Check tx dma handle */
1965 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1966
1967 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1968 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1969 }
1970
1971 /* Process Locked */
1972 __HAL_LOCK(hspi);
1973
1974 if ((pData == NULL) || (Size == 0U))
1975 {
1976 errorcode = HAL_ERROR;
1977 goto error;
1978 }
1979
1980 /* Set the transaction information */
1981 hspi->State = HAL_SPI_STATE_BUSY_RX;
1982 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1983 hspi->pRxBuffPtr = (uint8_t *)pData;
1984 hspi->RxXferSize = Size;
1985 hspi->RxXferCount = Size;
1986
1987 /*Init field not used in handle to zero */
1988 hspi->RxISR = NULL;
1989 hspi->TxISR = NULL;
1990 hspi->TxXferSize = 0U;
1991 hspi->TxXferCount = 0U;
1992
1993 /* Configure communication direction : 1Line */
1994 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1995 {
1996 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1997 __HAL_SPI_DISABLE(hspi);
1998 SPI_1LINE_RX(hspi);
1999 }
2000
2001 #if (USE_SPI_CRC != 0U)
2002 /* Reset CRC Calculation */
2003 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2004 {
2005 SPI_RESET_CRC(hspi);
2006 }
2007 #endif /* USE_SPI_CRC */
2008
2009 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
2010 /* Packing mode management is enabled by the DMA settings */
2011 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2012 {
2013 /* Restriction the DMA data received is not allowed in this mode */
2014 errorcode = HAL_ERROR;
2015 goto error;
2016 }
2017 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
2018
2019 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2020 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2021 {
2022 /* Set RX Fifo threshold according the reception data length: 16bit */
2023 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2024 }
2025 else
2026 {
2027 /* Set RX Fifo threshold according the reception data length: 8bit */
2028 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2029
2030 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2031 {
2032 /* Set RX Fifo threshold according the reception data length: 16bit */
2033 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2034
2035 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2036 {
2037 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2038 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2039 }
2040 else
2041 {
2042 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2043 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2044 }
2045 }
2046 }
2047
2048 /* Set the SPI RxDMA Half transfer complete callback */
2049 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2050
2051 /* Set the SPI Rx DMA transfer complete callback */
2052 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2053
2054 /* Set the DMA error callback */
2055 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2056
2057 /* Set the DMA AbortCpltCallback */
2058 hspi->hdmarx->XferAbortCallback = NULL;
2059
2060 /* Enable the Rx DMA Stream/Channel */
2061 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2062 hspi->RxXferCount))
2063 {
2064 /* Update SPI error code */
2065 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2066 errorcode = HAL_ERROR;
2067
2068 goto error;
2069 }
2070
2071 /* Check if the SPI is already enabled */
2072 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2073 {
2074 /* Enable SPI peripheral */
2075 __HAL_SPI_ENABLE(hspi);
2076 }
2077
2078 /* Enable the SPI Error Interrupt Bit */
2079 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2080
2081 /* Enable Rx DMA Request */
2082 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2083
2084 error:
2085 /* Process Unlocked */
2086 __HAL_UNLOCK(hspi);
2087 return errorcode;
2088 }
2089
2090 /**
2091 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2092 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2093 * the configuration information for SPI module.
2094 * @param pTxData pointer to transmission data buffer
2095 * @param pRxData pointer to reception data buffer
2096 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2097 * @param Size amount of data to be sent
2098 * @retval HAL status
2099 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2100 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2101 uint16_t Size)
2102 {
2103 uint32_t tmp_mode;
2104 HAL_SPI_StateTypeDef tmp_state;
2105 HAL_StatusTypeDef errorcode = HAL_OK;
2106
2107 /* Check rx & tx dma handles */
2108 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2109 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2110
2111 /* Check Direction parameter */
2112 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2113
2114 /* Process locked */
2115 __HAL_LOCK(hspi);
2116
2117 /* Init temporary variables */
2118 tmp_state = hspi->State;
2119 tmp_mode = hspi->Init.Mode;
2120
2121 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2122 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2123 {
2124 errorcode = HAL_BUSY;
2125 goto error;
2126 }
2127
2128 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2129 {
2130 errorcode = HAL_ERROR;
2131 goto error;
2132 }
2133
2134 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2135 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2136 {
2137 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2138 }
2139
2140 /* Set the transaction information */
2141 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2142 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2143 hspi->TxXferSize = Size;
2144 hspi->TxXferCount = Size;
2145 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2146 hspi->RxXferSize = Size;
2147 hspi->RxXferCount = Size;
2148
2149 /* Init field not used in handle to zero */
2150 hspi->RxISR = NULL;
2151 hspi->TxISR = NULL;
2152
2153 #if (USE_SPI_CRC != 0U)
2154 /* Reset CRC Calculation */
2155 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2156 {
2157 SPI_RESET_CRC(hspi);
2158 }
2159 #endif /* USE_SPI_CRC */
2160
2161 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
2162 /* Packing mode management is enabled by the DMA settings */
2163 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
2164 {
2165 /* Restriction the DMA data received is not allowed in this mode */
2166 errorcode = HAL_ERROR;
2167 goto error;
2168 }
2169 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F058xx */
2170
2171 /* Reset the threshold bit */
2172 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2173
2174 /* The packing mode management is enabled by the DMA settings according the spi data size */
2175 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2176 {
2177 /* Set fiforxthreshold according the reception data length: 16bit */
2178 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2179 }
2180 else
2181 {
2182 /* Set RX Fifo threshold according the reception data length: 8bit */
2183 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2184
2185 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2186 {
2187 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2188 {
2189 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2190 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2191 }
2192 else
2193 {
2194 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2195 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2196 }
2197 }
2198
2199 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2200 {
2201 /* Set RX Fifo threshold according the reception data length: 16bit */
2202 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2203
2204 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2205 {
2206 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2207 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2208 }
2209 else
2210 {
2211 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2212 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2213 }
2214 }
2215 }
2216
2217 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2218 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2219 {
2220 /* Set the SPI Rx DMA Half transfer complete callback */
2221 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2222 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2223 }
2224 else
2225 {
2226 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2227 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2228 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2229 }
2230
2231 /* Set the DMA error callback */
2232 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2233
2234 /* Set the DMA AbortCpltCallback */
2235 hspi->hdmarx->XferAbortCallback = NULL;
2236
2237 /* Enable the Rx DMA Stream/Channel */
2238 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2239 hspi->RxXferCount))
2240 {
2241 /* Update SPI error code */
2242 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2243 errorcode = HAL_ERROR;
2244
2245 goto error;
2246 }
2247
2248 /* Enable Rx DMA Request */
2249 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2250
2251 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2252 is performed in DMA reception complete callback */
2253 hspi->hdmatx->XferHalfCpltCallback = NULL;
2254 hspi->hdmatx->XferCpltCallback = NULL;
2255 hspi->hdmatx->XferErrorCallback = NULL;
2256 hspi->hdmatx->XferAbortCallback = NULL;
2257
2258 /* Enable the Tx DMA Stream/Channel */
2259 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2260 hspi->TxXferCount))
2261 {
2262 /* Update SPI error code */
2263 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2264 errorcode = HAL_ERROR;
2265
2266 goto error;
2267 }
2268
2269 /* Check if the SPI is already enabled */
2270 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2271 {
2272 /* Enable SPI peripheral */
2273 __HAL_SPI_ENABLE(hspi);
2274 }
2275 /* Enable the SPI Error Interrupt Bit */
2276 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2277
2278 /* Enable Tx DMA Request */
2279 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2280
2281 error :
2282 /* Process Unlocked */
2283 __HAL_UNLOCK(hspi);
2284 return errorcode;
2285 }
2286
2287 /**
2288 * @brief Abort ongoing transfer (blocking mode).
2289 * @param hspi SPI handle.
2290 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2291 * started in Interrupt or DMA mode.
2292 * This procedure performs following operations :
2293 * - Disable SPI Interrupts (depending of transfer direction)
2294 * - Disable the DMA transfer in the peripheral register (if enabled)
2295 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2296 * - Set handle State to READY
2297 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2298 * @retval HAL status
2299 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2300 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2301 {
2302 HAL_StatusTypeDef errorcode;
2303 __IO uint32_t count;
2304 __IO uint32_t resetcount;
2305
2306 /* Initialized local variable */
2307 errorcode = HAL_OK;
2308 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2309 count = resetcount;
2310
2311 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2312 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2313
2314 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2315 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2316 {
2317 hspi->TxISR = SPI_AbortTx_ISR;
2318 /* Wait HAL_SPI_STATE_ABORT state */
2319 do
2320 {
2321 if (count == 0U)
2322 {
2323 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2324 break;
2325 }
2326 count--;
2327 } while (hspi->State != HAL_SPI_STATE_ABORT);
2328 /* Reset Timeout Counter */
2329 count = resetcount;
2330 }
2331
2332 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2333 {
2334 hspi->RxISR = SPI_AbortRx_ISR;
2335 /* Wait HAL_SPI_STATE_ABORT state */
2336 do
2337 {
2338 if (count == 0U)
2339 {
2340 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2341 break;
2342 }
2343 count--;
2344 } while (hspi->State != HAL_SPI_STATE_ABORT);
2345 /* Reset Timeout Counter */
2346 count = resetcount;
2347 }
2348
2349 /* Disable the SPI DMA Tx request if enabled */
2350 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2351 {
2352 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2353 if (hspi->hdmatx != NULL)
2354 {
2355 /* Set the SPI DMA Abort callback :
2356 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2357 hspi->hdmatx->XferAbortCallback = NULL;
2358
2359 /* Abort DMA Tx Handle linked to SPI Peripheral */
2360 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2361 {
2362 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2363 }
2364
2365 /* Disable Tx DMA Request */
2366 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2367
2368 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2369 {
2370 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2371 }
2372
2373 /* Disable SPI Peripheral */
2374 __HAL_SPI_DISABLE(hspi);
2375
2376 /* Empty the FRLVL fifo */
2377 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2378 {
2379 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2380 }
2381 }
2382 }
2383
2384 /* Disable the SPI DMA Rx request if enabled */
2385 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2386 {
2387 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2388 if (hspi->hdmarx != NULL)
2389 {
2390 /* Set the SPI DMA Abort callback :
2391 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2392 hspi->hdmarx->XferAbortCallback = NULL;
2393
2394 /* Abort DMA Rx Handle linked to SPI Peripheral */
2395 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2396 {
2397 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2398 }
2399
2400 /* Disable peripheral */
2401 __HAL_SPI_DISABLE(hspi);
2402
2403 /* Control the BSY flag */
2404 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2405 {
2406 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2407 }
2408
2409 /* Empty the FRLVL fifo */
2410 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2411 {
2412 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2413 }
2414
2415 /* Disable Rx DMA Request */
2416 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2417 }
2418 }
2419 /* Reset Tx and Rx transfer counters */
2420 hspi->RxXferCount = 0U;
2421 hspi->TxXferCount = 0U;
2422
2423 /* Check error during Abort procedure */
2424 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2425 {
2426 /* return HAL_Error in case of error during Abort procedure */
2427 errorcode = HAL_ERROR;
2428 }
2429 else
2430 {
2431 /* Reset errorCode */
2432 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2433 }
2434
2435 /* Clear the Error flags in the SR register */
2436 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2437 __HAL_SPI_CLEAR_FREFLAG(hspi);
2438
2439 /* Restore hspi->state to ready */
2440 hspi->State = HAL_SPI_STATE_READY;
2441
2442 return errorcode;
2443 }
2444
2445 /**
2446 * @brief Abort ongoing transfer (Interrupt mode).
2447 * @param hspi SPI handle.
2448 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2449 * started in Interrupt or DMA mode.
2450 * This procedure performs following operations :
2451 * - Disable SPI Interrupts (depending of transfer direction)
2452 * - Disable the DMA transfer in the peripheral register (if enabled)
2453 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2454 * - Set handle State to READY
2455 * - At abort completion, call user abort complete callback
2456 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2457 * considered as completed only when user abort complete callback is executed (not when exiting function).
2458 * @retval HAL status
2459 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2460 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2461 {
2462 HAL_StatusTypeDef errorcode;
2463 uint32_t abortcplt ;
2464 __IO uint32_t count;
2465 __IO uint32_t resetcount;
2466
2467 /* Initialized local variable */
2468 errorcode = HAL_OK;
2469 abortcplt = 1U;
2470 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2471 count = resetcount;
2472
2473 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2474 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2475
2476 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2477 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2478 {
2479 hspi->TxISR = SPI_AbortTx_ISR;
2480 /* Wait HAL_SPI_STATE_ABORT state */
2481 do
2482 {
2483 if (count == 0U)
2484 {
2485 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2486 break;
2487 }
2488 count--;
2489 } while (hspi->State != HAL_SPI_STATE_ABORT);
2490 /* Reset Timeout Counter */
2491 count = resetcount;
2492 }
2493
2494 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2495 {
2496 hspi->RxISR = SPI_AbortRx_ISR;
2497 /* Wait HAL_SPI_STATE_ABORT state */
2498 do
2499 {
2500 if (count == 0U)
2501 {
2502 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2503 break;
2504 }
2505 count--;
2506 } while (hspi->State != HAL_SPI_STATE_ABORT);
2507 /* Reset Timeout Counter */
2508 count = resetcount;
2509 }
2510
2511 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2512 before any call to DMA Abort functions */
2513 /* DMA Tx Handle is valid */
2514 if (hspi->hdmatx != NULL)
2515 {
2516 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2517 Otherwise, set it to NULL */
2518 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2519 {
2520 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2521 }
2522 else
2523 {
2524 hspi->hdmatx->XferAbortCallback = NULL;
2525 }
2526 }
2527 /* DMA Rx Handle is valid */
2528 if (hspi->hdmarx != NULL)
2529 {
2530 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2531 Otherwise, set it to NULL */
2532 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2533 {
2534 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2535 }
2536 else
2537 {
2538 hspi->hdmarx->XferAbortCallback = NULL;
2539 }
2540 }
2541
2542 /* Disable the SPI DMA Tx request if enabled */
2543 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2544 {
2545 /* Abort the SPI DMA Tx Stream/Channel */
2546 if (hspi->hdmatx != NULL)
2547 {
2548 /* Abort DMA Tx Handle linked to SPI Peripheral */
2549 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2550 {
2551 hspi->hdmatx->XferAbortCallback = NULL;
2552 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2553 }
2554 else
2555 {
2556 abortcplt = 0U;
2557 }
2558 }
2559 }
2560 /* Disable the SPI DMA Rx request if enabled */
2561 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2562 {
2563 /* Abort the SPI DMA Rx Stream/Channel */
2564 if (hspi->hdmarx != NULL)
2565 {
2566 /* Abort DMA Rx Handle linked to SPI Peripheral */
2567 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2568 {
2569 hspi->hdmarx->XferAbortCallback = NULL;
2570 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2571 }
2572 else
2573 {
2574 abortcplt = 0U;
2575 }
2576 }
2577 }
2578
2579 if (abortcplt == 1U)
2580 {
2581 /* Reset Tx and Rx transfer counters */
2582 hspi->RxXferCount = 0U;
2583 hspi->TxXferCount = 0U;
2584
2585 /* Check error during Abort procedure */
2586 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2587 {
2588 /* return HAL_Error in case of error during Abort procedure */
2589 errorcode = HAL_ERROR;
2590 }
2591 else
2592 {
2593 /* Reset errorCode */
2594 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2595 }
2596
2597 /* Clear the Error flags in the SR register */
2598 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2599 __HAL_SPI_CLEAR_FREFLAG(hspi);
2600
2601 /* Restore hspi->State to Ready */
2602 hspi->State = HAL_SPI_STATE_READY;
2603
2604 /* As no DMA to be aborted, call directly user Abort complete callback */
2605 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2606 hspi->AbortCpltCallback(hspi);
2607 #else
2608 HAL_SPI_AbortCpltCallback(hspi);
2609 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2610 }
2611
2612 return errorcode;
2613 }
2614
2615 /**
2616 * @brief Pause the DMA Transfer.
2617 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2618 * the configuration information for the specified SPI module.
2619 * @retval HAL status
2620 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2621 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2622 {
2623 /* Process Locked */
2624 __HAL_LOCK(hspi);
2625
2626 /* Disable the SPI DMA Tx & Rx requests */
2627 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2628
2629 /* Process Unlocked */
2630 __HAL_UNLOCK(hspi);
2631
2632 return HAL_OK;
2633 }
2634
2635 /**
2636 * @brief Resume the DMA Transfer.
2637 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2638 * the configuration information for the specified SPI module.
2639 * @retval HAL status
2640 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2641 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2642 {
2643 /* Process Locked */
2644 __HAL_LOCK(hspi);
2645
2646 /* Enable the SPI DMA Tx & Rx requests */
2647 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2648
2649 /* Process Unlocked */
2650 __HAL_UNLOCK(hspi);
2651
2652 return HAL_OK;
2653 }
2654
2655 /**
2656 * @brief Stop the DMA Transfer.
2657 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2658 * the configuration information for the specified SPI module.
2659 * @retval HAL status
2660 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2661 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2662 {
2663 HAL_StatusTypeDef errorcode = HAL_OK;
2664 /* The Lock is not implemented on this API to allow the user application
2665 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2666 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2667 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2668 */
2669
2670 /* Abort the SPI DMA tx Stream/Channel */
2671 if (hspi->hdmatx != NULL)
2672 {
2673 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2674 {
2675 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2676 errorcode = HAL_ERROR;
2677 }
2678 }
2679 /* Abort the SPI DMA rx Stream/Channel */
2680 if (hspi->hdmarx != NULL)
2681 {
2682 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2683 {
2684 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2685 errorcode = HAL_ERROR;
2686 }
2687 }
2688
2689 /* Disable the SPI DMA Tx & Rx requests */
2690 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2691 hspi->State = HAL_SPI_STATE_READY;
2692 return errorcode;
2693 }
2694
2695 /**
2696 * @brief Handle SPI interrupt request.
2697 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2698 * the configuration information for the specified SPI module.
2699 * @retval None
2700 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2701 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2702 {
2703 uint32_t itsource = hspi->Instance->CR2;
2704 uint32_t itflag = hspi->Instance->SR;
2705
2706 /* SPI in mode Receiver ----------------------------------------------------*/
2707 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2708 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2709 {
2710 hspi->RxISR(hspi);
2711 return;
2712 }
2713
2714 /* SPI in mode Transmitter -------------------------------------------------*/
2715 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2716 {
2717 hspi->TxISR(hspi);
2718 return;
2719 }
2720
2721 /* SPI in Error Treatment --------------------------------------------------*/
2722 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2723 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2724 {
2725 /* SPI Overrun error interrupt occurred ----------------------------------*/
2726 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2727 {
2728 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2729 {
2730 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2731 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2732 }
2733 else
2734 {
2735 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2736 return;
2737 }
2738 }
2739
2740 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2741 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2742 {
2743 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2744 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2745 }
2746
2747 /* SPI Frame error interrupt occurred ------------------------------------*/
2748 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2749 {
2750 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2751 __HAL_SPI_CLEAR_FREFLAG(hspi);
2752 }
2753
2754 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2755 {
2756 /* Disable all interrupts */
2757 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2758
2759 hspi->State = HAL_SPI_STATE_READY;
2760 /* Disable the SPI DMA requests if enabled */
2761 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2762 {
2763 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2764
2765 /* Abort the SPI DMA Rx channel */
2766 if (hspi->hdmarx != NULL)
2767 {
2768 /* Set the SPI DMA Abort callback :
2769 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2770 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2771 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2772 {
2773 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2774 }
2775 }
2776 /* Abort the SPI DMA Tx channel */
2777 if (hspi->hdmatx != NULL)
2778 {
2779 /* Set the SPI DMA Abort callback :
2780 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2781 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2782 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2783 {
2784 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2785 }
2786 }
2787 }
2788 else
2789 {
2790 /* Call user error callback */
2791 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2792 hspi->ErrorCallback(hspi);
2793 #else
2794 HAL_SPI_ErrorCallback(hspi);
2795 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2796 }
2797 }
2798 return;
2799 }
2800 }
2801
2802 /**
2803 * @brief Tx Transfer completed callback.
2804 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2805 * the configuration information for SPI module.
2806 * @retval None
2807 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2808 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2809 {
2810 /* Prevent unused argument(s) compilation warning */
2811 UNUSED(hspi);
2812
2813 /* NOTE : This function should not be modified, when the callback is needed,
2814 the HAL_SPI_TxCpltCallback should be implemented in the user file
2815 */
2816 }
2817
2818 /**
2819 * @brief Rx Transfer completed callback.
2820 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2821 * the configuration information for SPI module.
2822 * @retval None
2823 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2824 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2825 {
2826 /* Prevent unused argument(s) compilation warning */
2827 UNUSED(hspi);
2828
2829 /* NOTE : This function should not be modified, when the callback is needed,
2830 the HAL_SPI_RxCpltCallback should be implemented in the user file
2831 */
2832 }
2833
2834 /**
2835 * @brief Tx and Rx Transfer completed callback.
2836 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2837 * the configuration information for SPI module.
2838 * @retval None
2839 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2840 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2841 {
2842 /* Prevent unused argument(s) compilation warning */
2843 UNUSED(hspi);
2844
2845 /* NOTE : This function should not be modified, when the callback is needed,
2846 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2847 */
2848 }
2849
2850 /**
2851 * @brief Tx Half Transfer completed callback.
2852 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2853 * the configuration information for SPI module.
2854 * @retval None
2855 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2856 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2857 {
2858 /* Prevent unused argument(s) compilation warning */
2859 UNUSED(hspi);
2860
2861 /* NOTE : This function should not be modified, when the callback is needed,
2862 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2863 */
2864 }
2865
2866 /**
2867 * @brief Rx Half Transfer completed callback.
2868 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2869 * the configuration information for SPI module.
2870 * @retval None
2871 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2872 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2873 {
2874 /* Prevent unused argument(s) compilation warning */
2875 UNUSED(hspi);
2876
2877 /* NOTE : This function should not be modified, when the callback is needed,
2878 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2879 */
2880 }
2881
2882 /**
2883 * @brief Tx and Rx Half Transfer callback.
2884 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2885 * the configuration information for SPI module.
2886 * @retval None
2887 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2888 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2889 {
2890 /* Prevent unused argument(s) compilation warning */
2891 UNUSED(hspi);
2892
2893 /* NOTE : This function should not be modified, when the callback is needed,
2894 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2895 */
2896 }
2897
2898 /**
2899 * @brief SPI error callback.
2900 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2901 * the configuration information for SPI module.
2902 * @retval None
2903 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2904 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2905 {
2906 /* Prevent unused argument(s) compilation warning */
2907 UNUSED(hspi);
2908
2909 /* NOTE : This function should not be modified, when the callback is needed,
2910 the HAL_SPI_ErrorCallback should be implemented in the user file
2911 */
2912 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2913 and user can use HAL_SPI_GetError() API to check the latest error occurred
2914 */
2915 }
2916
2917 /**
2918 * @brief SPI Abort Complete callback.
2919 * @param hspi SPI handle.
2920 * @retval None
2921 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2922 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2923 {
2924 /* Prevent unused argument(s) compilation warning */
2925 UNUSED(hspi);
2926
2927 /* NOTE : This function should not be modified, when the callback is needed,
2928 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2929 */
2930 }
2931
2932 /**
2933 * @}
2934 */
2935
2936 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2937 * @brief SPI control functions
2938 *
2939 @verbatim
2940 ===============================================================================
2941 ##### Peripheral State and Errors functions #####
2942 ===============================================================================
2943 [..]
2944 This subsection provides a set of functions allowing to control the SPI.
2945 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2946 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2947 @endverbatim
2948 * @{
2949 */
2950
2951 /**
2952 * @brief Return the SPI handle state.
2953 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2954 * the configuration information for SPI module.
2955 * @retval SPI state
2956 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2957 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2958 {
2959 /* Return SPI handle state */
2960 return hspi->State;
2961 }
2962
2963 /**
2964 * @brief Return the SPI error code.
2965 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2966 * the configuration information for SPI module.
2967 * @retval SPI error code in bitmap format
2968 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2969 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2970 {
2971 /* Return SPI ErrorCode */
2972 return hspi->ErrorCode;
2973 }
2974
2975 /**
2976 * @}
2977 */
2978
2979 /**
2980 * @}
2981 */
2982
2983 /** @addtogroup SPI_Private_Functions
2984 * @brief Private functions
2985 * @{
2986 */
2987
2988 /**
2989 * @brief DMA SPI transmit process complete callback.
2990 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2991 * the configuration information for the specified DMA module.
2992 * @retval None
2993 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2994 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2995 {
2996 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2997 uint32_t tickstart;
2998
2999 /* Init tickstart for timeout management*/
3000 tickstart = HAL_GetTick();
3001
3002 /* DMA Normal Mode */
3003 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3004 {
3005 /* Disable ERR interrupt */
3006 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3007
3008 /* Disable Tx DMA Request */
3009 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3010
3011 /* Check the end of the transaction */
3012 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3013 {
3014 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3015 }
3016
3017 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3018 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3019 {
3020 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3021 }
3022
3023 hspi->TxXferCount = 0U;
3024 hspi->State = HAL_SPI_STATE_READY;
3025
3026 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3027 {
3028 /* Call user error callback */
3029 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3030 hspi->ErrorCallback(hspi);
3031 #else
3032 HAL_SPI_ErrorCallback(hspi);
3033 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3034 return;
3035 }
3036 }
3037 /* Call user Tx complete callback */
3038 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3039 hspi->TxCpltCallback(hspi);
3040 #else
3041 HAL_SPI_TxCpltCallback(hspi);
3042 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3043 }
3044
3045 /**
3046 * @brief DMA SPI receive process complete callback.
3047 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3048 * the configuration information for the specified DMA module.
3049 * @retval None
3050 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3051 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3052 {
3053 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3054 uint32_t tickstart;
3055 #if (USE_SPI_CRC != 0U)
3056 __IO uint32_t tmpreg = 0U;
3057 __IO uint8_t *ptmpreg8;
3058 __IO uint8_t tmpreg8 = 0;
3059 #endif /* USE_SPI_CRC */
3060
3061 /* Init tickstart for timeout management*/
3062 tickstart = HAL_GetTick();
3063
3064 /* DMA Normal Mode */
3065 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3066 {
3067 /* Disable ERR interrupt */
3068 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3069
3070 #if (USE_SPI_CRC != 0U)
3071 /* CRC handling */
3072 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3073 {
3074 /* Wait until RXNE flag */
3075 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3076 {
3077 /* Error on the CRC reception */
3078 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3079 }
3080 /* Read CRC */
3081 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3082 {
3083 /* Read 16bit CRC */
3084 tmpreg = READ_REG(hspi->Instance->DR);
3085 /* To avoid GCC warning */
3086 UNUSED(tmpreg);
3087 }
3088 else
3089 {
3090 /* Initialize the 8bit temporary pointer */
3091 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3092 /* Read 8bit CRC */
3093 tmpreg8 = *ptmpreg8;
3094 /* To avoid GCC warning */
3095 UNUSED(tmpreg8);
3096
3097 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3098 {
3099 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3100 {
3101 /* Error on the CRC reception */
3102 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3103 }
3104 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3105 tmpreg8 = *ptmpreg8;
3106 /* To avoid GCC warning */
3107 UNUSED(tmpreg8);
3108 }
3109 }
3110 }
3111 #endif /* USE_SPI_CRC */
3112
3113 /* Check if we are in Master RX 2 line mode */
3114 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3115 {
3116 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3117 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3118 }
3119 else
3120 {
3121 /* Normal case */
3122 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3123 }
3124
3125 /* Check the end of the transaction */
3126 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3127 {
3128 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3129 }
3130
3131 hspi->RxXferCount = 0U;
3132 hspi->State = HAL_SPI_STATE_READY;
3133
3134 #if (USE_SPI_CRC != 0U)
3135 /* Check if CRC error occurred */
3136 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3137 {
3138 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3139 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3140 }
3141 #endif /* USE_SPI_CRC */
3142
3143 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3144 {
3145 /* Call user error callback */
3146 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3147 hspi->ErrorCallback(hspi);
3148 #else
3149 HAL_SPI_ErrorCallback(hspi);
3150 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3151 return;
3152 }
3153 }
3154 /* Call user Rx complete callback */
3155 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3156 hspi->RxCpltCallback(hspi);
3157 #else
3158 HAL_SPI_RxCpltCallback(hspi);
3159 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3160 }
3161
3162 /**
3163 * @brief DMA SPI transmit receive process complete callback.
3164 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3165 * the configuration information for the specified DMA module.
3166 * @retval None
3167 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3168 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3169 {
3170 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3171 uint32_t tickstart;
3172 #if (USE_SPI_CRC != 0U)
3173 __IO uint32_t tmpreg = 0U;
3174 __IO uint8_t *ptmpreg8;
3175 __IO uint8_t tmpreg8 = 0;
3176 #endif /* USE_SPI_CRC */
3177
3178 /* Init tickstart for timeout management*/
3179 tickstart = HAL_GetTick();
3180
3181 /* DMA Normal Mode */
3182 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3183 {
3184 /* Disable ERR interrupt */
3185 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3186
3187 #if (USE_SPI_CRC != 0U)
3188 /* CRC handling */
3189 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3190 {
3191 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3192 {
3193 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3194 tickstart) != HAL_OK)
3195 {
3196 /* Error on the CRC reception */
3197 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3198 }
3199 /* Initialize the 8bit temporary pointer */
3200 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3201 /* Read 8bit CRC */
3202 tmpreg8 = *ptmpreg8;
3203 /* To avoid GCC warning */
3204 UNUSED(tmpreg8);
3205 }
3206 else
3207 {
3208 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3209 {
3210 /* Error on the CRC reception */
3211 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3212 }
3213 /* Read CRC to Flush DR and RXNE flag */
3214 tmpreg = READ_REG(hspi->Instance->DR);
3215 /* To avoid GCC warning */
3216 UNUSED(tmpreg);
3217 }
3218 }
3219 #endif /* USE_SPI_CRC */
3220
3221 /* Check the end of the transaction */
3222 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3223 {
3224 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3225 }
3226
3227 /* Disable Rx/Tx DMA Request */
3228 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3229
3230 hspi->TxXferCount = 0U;
3231 hspi->RxXferCount = 0U;
3232 hspi->State = HAL_SPI_STATE_READY;
3233
3234 #if (USE_SPI_CRC != 0U)
3235 /* Check if CRC error occurred */
3236 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3237 {
3238 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3239 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3240 }
3241 #endif /* USE_SPI_CRC */
3242
3243 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3244 {
3245 /* Call user error callback */
3246 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3247 hspi->ErrorCallback(hspi);
3248 #else
3249 HAL_SPI_ErrorCallback(hspi);
3250 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3251 return;
3252 }
3253 }
3254 /* Call user TxRx complete callback */
3255 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3256 hspi->TxRxCpltCallback(hspi);
3257 #else
3258 HAL_SPI_TxRxCpltCallback(hspi);
3259 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3260 }
3261
3262 /**
3263 * @brief DMA SPI half transmit process complete callback.
3264 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3265 * the configuration information for the specified DMA module.
3266 * @retval None
3267 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3268 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3269 {
3270 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3271
3272 /* Call user Tx half complete callback */
3273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3274 hspi->TxHalfCpltCallback(hspi);
3275 #else
3276 HAL_SPI_TxHalfCpltCallback(hspi);
3277 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3278 }
3279
3280 /**
3281 * @brief DMA SPI half receive process complete callback
3282 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3283 * the configuration information for the specified DMA module.
3284 * @retval None
3285 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3286 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3287 {
3288 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3289
3290 /* Call user Rx half complete callback */
3291 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3292 hspi->RxHalfCpltCallback(hspi);
3293 #else
3294 HAL_SPI_RxHalfCpltCallback(hspi);
3295 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3296 }
3297
3298 /**
3299 * @brief DMA SPI half transmit receive process complete callback.
3300 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3301 * the configuration information for the specified DMA module.
3302 * @retval None
3303 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3304 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3305 {
3306 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3307
3308 /* Call user TxRx half complete callback */
3309 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3310 hspi->TxRxHalfCpltCallback(hspi);
3311 #else
3312 HAL_SPI_TxRxHalfCpltCallback(hspi);
3313 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3314 }
3315
3316 /**
3317 * @brief DMA SPI communication error callback.
3318 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3319 * the configuration information for the specified DMA module.
3320 * @retval None
3321 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3322 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3323 {
3324 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3325
3326 /* Stop the disable DMA transfer on SPI side */
3327 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3328
3329 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3330 hspi->State = HAL_SPI_STATE_READY;
3331 /* Call user error callback */
3332 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3333 hspi->ErrorCallback(hspi);
3334 #else
3335 HAL_SPI_ErrorCallback(hspi);
3336 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3337 }
3338
3339 /**
3340 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3341 * (To be called at end of DMA Abort procedure following error occurrence).
3342 * @param hdma DMA handle.
3343 * @retval None
3344 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3345 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3346 {
3347 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3348 hspi->RxXferCount = 0U;
3349 hspi->TxXferCount = 0U;
3350
3351 /* Call user error callback */
3352 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3353 hspi->ErrorCallback(hspi);
3354 #else
3355 HAL_SPI_ErrorCallback(hspi);
3356 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3357 }
3358
3359 /**
3360 * @brief DMA SPI Tx communication abort callback, when initiated by user
3361 * (To be called at end of DMA Tx Abort procedure following user abort request).
3362 * @note When this callback is executed, User Abort complete call back is called only if no
3363 * Abort still ongoing for Rx DMA Handle.
3364 * @param hdma DMA handle.
3365 * @retval None
3366 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3367 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3368 {
3369 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3370
3371 hspi->hdmatx->XferAbortCallback = NULL;
3372
3373 /* Disable Tx DMA Request */
3374 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3375
3376 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3377 {
3378 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3379 }
3380
3381 /* Disable SPI Peripheral */
3382 __HAL_SPI_DISABLE(hspi);
3383
3384 /* Empty the FRLVL fifo */
3385 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3386 {
3387 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3388 }
3389
3390 /* Check if an Abort process is still ongoing */
3391 if (hspi->hdmarx != NULL)
3392 {
3393 if (hspi->hdmarx->XferAbortCallback != NULL)
3394 {
3395 return;
3396 }
3397 }
3398
3399 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3400 hspi->RxXferCount = 0U;
3401 hspi->TxXferCount = 0U;
3402
3403 /* Check no error during Abort procedure */
3404 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3405 {
3406 /* Reset errorCode */
3407 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3408 }
3409
3410 /* Clear the Error flags in the SR register */
3411 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3412 __HAL_SPI_CLEAR_FREFLAG(hspi);
3413
3414 /* Restore hspi->State to Ready */
3415 hspi->State = HAL_SPI_STATE_READY;
3416
3417 /* Call user Abort complete callback */
3418 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3419 hspi->AbortCpltCallback(hspi);
3420 #else
3421 HAL_SPI_AbortCpltCallback(hspi);
3422 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3423 }
3424
3425 /**
3426 * @brief DMA SPI Rx communication abort callback, when initiated by user
3427 * (To be called at end of DMA Rx Abort procedure following user abort request).
3428 * @note When this callback is executed, User Abort complete call back is called only if no
3429 * Abort still ongoing for Tx DMA Handle.
3430 * @param hdma DMA handle.
3431 * @retval None
3432 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3433 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3434 {
3435 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3436
3437 /* Disable SPI Peripheral */
3438 __HAL_SPI_DISABLE(hspi);
3439
3440 hspi->hdmarx->XferAbortCallback = NULL;
3441
3442 /* Disable Rx DMA Request */
3443 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3444
3445 /* Control the BSY flag */
3446 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3447 {
3448 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3449 }
3450
3451 /* Empty the FRLVL fifo */
3452 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3453 {
3454 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3455 }
3456
3457 /* Check if an Abort process is still ongoing */
3458 if (hspi->hdmatx != NULL)
3459 {
3460 if (hspi->hdmatx->XferAbortCallback != NULL)
3461 {
3462 return;
3463 }
3464 }
3465
3466 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3467 hspi->RxXferCount = 0U;
3468 hspi->TxXferCount = 0U;
3469
3470 /* Check no error during Abort procedure */
3471 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3472 {
3473 /* Reset errorCode */
3474 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3475 }
3476
3477 /* Clear the Error flags in the SR register */
3478 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3479 __HAL_SPI_CLEAR_FREFLAG(hspi);
3480
3481 /* Restore hspi->State to Ready */
3482 hspi->State = HAL_SPI_STATE_READY;
3483
3484 /* Call user Abort complete callback */
3485 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3486 hspi->AbortCpltCallback(hspi);
3487 #else
3488 HAL_SPI_AbortCpltCallback(hspi);
3489 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3490 }
3491
3492 /**
3493 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3494 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3495 * the configuration information for SPI module.
3496 * @retval None
3497 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3498 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3499 {
3500 /* Receive data in packing mode */
3501 if (hspi->RxXferCount > 1U)
3502 {
3503 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3504 hspi->pRxBuffPtr += sizeof(uint16_t);
3505 hspi->RxXferCount -= 2U;
3506 if (hspi->RxXferCount == 1U)
3507 {
3508 /* Set RX Fifo threshold according the reception data length: 8bit */
3509 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3510 }
3511 }
3512 /* Receive data in 8 Bit mode */
3513 else
3514 {
3515 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3516 hspi->pRxBuffPtr++;
3517 hspi->RxXferCount--;
3518 }
3519
3520 /* Check end of the reception */
3521 if (hspi->RxXferCount == 0U)
3522 {
3523 #if (USE_SPI_CRC != 0U)
3524 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3525 {
3526 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3527 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3528 return;
3529 }
3530 #endif /* USE_SPI_CRC */
3531
3532 /* Disable RXNE and ERR interrupt */
3533 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3534
3535 if (hspi->TxXferCount == 0U)
3536 {
3537 SPI_CloseRxTx_ISR(hspi);
3538 }
3539 }
3540 }
3541
3542 #if (USE_SPI_CRC != 0U)
3543 /**
3544 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3546 * the configuration information for SPI module.
3547 * @retval None
3548 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3549 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3550 {
3551 __IO uint8_t *ptmpreg8;
3552 __IO uint8_t tmpreg8 = 0;
3553
3554 /* Initialize the 8bit temporary pointer */
3555 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3556 /* Read 8bit CRC to flush Data Register */
3557 tmpreg8 = *ptmpreg8;
3558 /* To avoid GCC warning */
3559 UNUSED(tmpreg8);
3560
3561 hspi->CRCSize--;
3562
3563 /* Check end of the reception */
3564 if (hspi->CRCSize == 0U)
3565 {
3566 /* Disable RXNE and ERR interrupt */
3567 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3568
3569 if (hspi->TxXferCount == 0U)
3570 {
3571 SPI_CloseRxTx_ISR(hspi);
3572 }
3573 }
3574 }
3575 #endif /* USE_SPI_CRC */
3576
3577 /**
3578 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3579 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3580 * the configuration information for SPI module.
3581 * @retval None
3582 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3583 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3584 {
3585 /* Transmit data in packing Bit mode */
3586 if (hspi->TxXferCount >= 2U)
3587 {
3588 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3589 hspi->pTxBuffPtr += sizeof(uint16_t);
3590 hspi->TxXferCount -= 2U;
3591 }
3592 /* Transmit data in 8 Bit mode */
3593 else
3594 {
3595 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3596 hspi->pTxBuffPtr++;
3597 hspi->TxXferCount--;
3598 }
3599
3600 /* Check the end of the transmission */
3601 if (hspi->TxXferCount == 0U)
3602 {
3603 #if (USE_SPI_CRC != 0U)
3604 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3605 {
3606 /* Set CRC Next Bit to send CRC */
3607 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3608 /* Disable TXE interrupt */
3609 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3610 return;
3611 }
3612 #endif /* USE_SPI_CRC */
3613
3614 /* Disable TXE interrupt */
3615 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3616
3617 if (hspi->RxXferCount == 0U)
3618 {
3619 SPI_CloseRxTx_ISR(hspi);
3620 }
3621 }
3622 }
3623
3624 /**
3625 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3626 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3627 * the configuration information for SPI module.
3628 * @retval None
3629 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3630 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3631 {
3632 /* Receive data in 16 Bit mode */
3633 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3634 hspi->pRxBuffPtr += sizeof(uint16_t);
3635 hspi->RxXferCount--;
3636
3637 if (hspi->RxXferCount == 0U)
3638 {
3639 #if (USE_SPI_CRC != 0U)
3640 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3641 {
3642 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3643 return;
3644 }
3645 #endif /* USE_SPI_CRC */
3646
3647 /* Disable RXNE interrupt */
3648 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3649
3650 if (hspi->TxXferCount == 0U)
3651 {
3652 SPI_CloseRxTx_ISR(hspi);
3653 }
3654 }
3655 }
3656
3657 #if (USE_SPI_CRC != 0U)
3658 /**
3659 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3660 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3661 * the configuration information for SPI module.
3662 * @retval None
3663 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3664 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3665 {
3666 __IO uint32_t tmpreg = 0U;
3667
3668 /* Read 16bit CRC to flush Data Register */
3669 tmpreg = READ_REG(hspi->Instance->DR);
3670 /* To avoid GCC warning */
3671 UNUSED(tmpreg);
3672
3673 /* Disable RXNE interrupt */
3674 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3675
3676 SPI_CloseRxTx_ISR(hspi);
3677 }
3678 #endif /* USE_SPI_CRC */
3679
3680 /**
3681 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3682 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3683 * the configuration information for SPI module.
3684 * @retval None
3685 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3686 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3687 {
3688 /* Transmit data in 16 Bit mode */
3689 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3690 hspi->pTxBuffPtr += sizeof(uint16_t);
3691 hspi->TxXferCount--;
3692
3693 /* Enable CRC Transmission */
3694 if (hspi->TxXferCount == 0U)
3695 {
3696 #if (USE_SPI_CRC != 0U)
3697 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3698 {
3699 /* Set CRC Next Bit to send CRC */
3700 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3701 /* Disable TXE interrupt */
3702 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3703 return;
3704 }
3705 #endif /* USE_SPI_CRC */
3706
3707 /* Disable TXE interrupt */
3708 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3709
3710 if (hspi->RxXferCount == 0U)
3711 {
3712 SPI_CloseRxTx_ISR(hspi);
3713 }
3714 }
3715 }
3716
3717 #if (USE_SPI_CRC != 0U)
3718 /**
3719 * @brief Manage the CRC 8-bit receive in Interrupt context.
3720 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3721 * the configuration information for SPI module.
3722 * @retval None
3723 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3724 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3725 {
3726 __IO uint8_t *ptmpreg8;
3727 __IO uint8_t tmpreg8 = 0;
3728
3729 /* Initialize the 8bit temporary pointer */
3730 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3731 /* Read 8bit CRC to flush Data Register */
3732 tmpreg8 = *ptmpreg8;
3733 /* To avoid GCC warning */
3734 UNUSED(tmpreg8);
3735
3736 hspi->CRCSize--;
3737
3738 if (hspi->CRCSize == 0U)
3739 {
3740 SPI_CloseRx_ISR(hspi);
3741 }
3742 }
3743 #endif /* USE_SPI_CRC */
3744
3745 /**
3746 * @brief Manage the receive 8-bit in Interrupt context.
3747 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3748 * the configuration information for SPI module.
3749 * @retval None
3750 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3751 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3752 {
3753 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3754 hspi->pRxBuffPtr++;
3755 hspi->RxXferCount--;
3756
3757 #if (USE_SPI_CRC != 0U)
3758 /* Enable CRC Transmission */
3759 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3760 {
3761 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3762 }
3763 #endif /* USE_SPI_CRC */
3764
3765 if (hspi->RxXferCount == 0U)
3766 {
3767 #if (USE_SPI_CRC != 0U)
3768 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3769 {
3770 hspi->RxISR = SPI_RxISR_8BITCRC;
3771 return;
3772 }
3773 #endif /* USE_SPI_CRC */
3774 SPI_CloseRx_ISR(hspi);
3775 }
3776 }
3777
3778 #if (USE_SPI_CRC != 0U)
3779 /**
3780 * @brief Manage the CRC 16-bit receive in Interrupt context.
3781 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3782 * the configuration information for SPI module.
3783 * @retval None
3784 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3785 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3786 {
3787 __IO uint32_t tmpreg = 0U;
3788
3789 /* Read 16bit CRC to flush Data Register */
3790 tmpreg = READ_REG(hspi->Instance->DR);
3791 /* To avoid GCC warning */
3792 UNUSED(tmpreg);
3793
3794 /* Disable RXNE and ERR interrupt */
3795 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3796
3797 SPI_CloseRx_ISR(hspi);
3798 }
3799 #endif /* USE_SPI_CRC */
3800
3801 /**
3802 * @brief Manage the 16-bit receive in Interrupt context.
3803 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3804 * the configuration information for SPI module.
3805 * @retval None
3806 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3807 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3808 {
3809 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3810 hspi->pRxBuffPtr += sizeof(uint16_t);
3811 hspi->RxXferCount--;
3812
3813 #if (USE_SPI_CRC != 0U)
3814 /* Enable CRC Transmission */
3815 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3816 {
3817 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3818 }
3819 #endif /* USE_SPI_CRC */
3820
3821 if (hspi->RxXferCount == 0U)
3822 {
3823 #if (USE_SPI_CRC != 0U)
3824 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3825 {
3826 hspi->RxISR = SPI_RxISR_16BITCRC;
3827 return;
3828 }
3829 #endif /* USE_SPI_CRC */
3830 SPI_CloseRx_ISR(hspi);
3831 }
3832 }
3833
3834 /**
3835 * @brief Handle the data 8-bit transmit in Interrupt mode.
3836 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3837 * the configuration information for SPI module.
3838 * @retval None
3839 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3840 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3841 {
3842 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3843 hspi->pTxBuffPtr++;
3844 hspi->TxXferCount--;
3845
3846 if (hspi->TxXferCount == 0U)
3847 {
3848 #if (USE_SPI_CRC != 0U)
3849 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3850 {
3851 /* Enable CRC Transmission */
3852 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3853 }
3854 #endif /* USE_SPI_CRC */
3855 SPI_CloseTx_ISR(hspi);
3856 }
3857 }
3858
3859 /**
3860 * @brief Handle the data 16-bit transmit in Interrupt mode.
3861 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3862 * the configuration information for SPI module.
3863 * @retval None
3864 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3865 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3866 {
3867 /* Transmit data in 16 Bit mode */
3868 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3869 hspi->pTxBuffPtr += sizeof(uint16_t);
3870 hspi->TxXferCount--;
3871
3872 if (hspi->TxXferCount == 0U)
3873 {
3874 #if (USE_SPI_CRC != 0U)
3875 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3876 {
3877 /* Enable CRC Transmission */
3878 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3879 }
3880 #endif /* USE_SPI_CRC */
3881 SPI_CloseTx_ISR(hspi);
3882 }
3883 }
3884
3885 /**
3886 * @brief Handle SPI Communication Timeout.
3887 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3888 * the configuration information for SPI module.
3889 * @param Flag SPI flag to check
3890 * @param State flag state to check
3891 * @param Timeout Timeout duration
3892 * @param Tickstart tick start value
3893 * @retval HAL status
3894 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3895 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3896 uint32_t Timeout, uint32_t Tickstart)
3897 {
3898 __IO uint32_t count;
3899 uint32_t tmp_timeout;
3900 uint32_t tmp_tickstart;
3901
3902 /* Adjust Timeout value in case of end of transfer */
3903 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3904 tmp_tickstart = HAL_GetTick();
3905
3906 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3907 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3908
3909 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3910 {
3911 if (Timeout != HAL_MAX_DELAY)
3912 {
3913 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3914 {
3915 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3916 on both master and slave sides in order to resynchronize the master
3917 and slave for their respective CRC calculation */
3918
3919 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3920 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3921
3922 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3923 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3924 {
3925 /* Disable SPI peripheral */
3926 __HAL_SPI_DISABLE(hspi);
3927 }
3928
3929 /* Reset CRC Calculation */
3930 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3931 {
3932 SPI_RESET_CRC(hspi);
3933 }
3934
3935 hspi->State = HAL_SPI_STATE_READY;
3936
3937 /* Process Unlocked */
3938 __HAL_UNLOCK(hspi);
3939
3940 return HAL_TIMEOUT;
3941 }
3942 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3943 if (count == 0U)
3944 {
3945 tmp_timeout = 0U;
3946 }
3947 count--;
3948 }
3949 }
3950
3951 return HAL_OK;
3952 }
3953
3954 /**
3955 * @brief Handle SPI FIFO Communication Timeout.
3956 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3957 * the configuration information for SPI module.
3958 * @param Fifo Fifo to check
3959 * @param State Fifo state to check
3960 * @param Timeout Timeout duration
3961 * @param Tickstart tick start value
3962 * @retval HAL status
3963 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3964 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3965 uint32_t Timeout, uint32_t Tickstart)
3966 {
3967 __IO uint32_t count;
3968 uint32_t tmp_timeout;
3969 uint32_t tmp_tickstart;
3970 __IO uint8_t *ptmpreg8;
3971 __IO uint8_t tmpreg8 = 0;
3972
3973 /* Adjust Timeout value in case of end of transfer */
3974 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3975 tmp_tickstart = HAL_GetTick();
3976
3977 /* Initialize the 8bit temporary pointer */
3978 ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3979
3980 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3981 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
3982
3983 while ((hspi->Instance->SR & Fifo) != State)
3984 {
3985 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3986 {
3987 /* Flush Data Register by a blank read */
3988 tmpreg8 = *ptmpreg8;
3989 /* To avoid GCC warning */
3990 UNUSED(tmpreg8);
3991 }
3992
3993 if (Timeout != HAL_MAX_DELAY)
3994 {
3995 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3996 {
3997 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3998 on both master and slave sides in order to resynchronize the master
3999 and slave for their respective CRC calculation */
4000
4001 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
4002 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
4003
4004 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4005 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4006 {
4007 /* Disable SPI peripheral */
4008 __HAL_SPI_DISABLE(hspi);
4009 }
4010
4011 /* Reset CRC Calculation */
4012 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4013 {
4014 SPI_RESET_CRC(hspi);
4015 }
4016
4017 hspi->State = HAL_SPI_STATE_READY;
4018
4019 /* Process Unlocked */
4020 __HAL_UNLOCK(hspi);
4021
4022 return HAL_TIMEOUT;
4023 }
4024 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4025 if (count == 0U)
4026 {
4027 tmp_timeout = 0U;
4028 }
4029 count--;
4030 }
4031 }
4032
4033 return HAL_OK;
4034 }
4035
4036 /**
4037 * @brief Handle the check of the RX transaction complete.
4038 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4039 * the configuration information for SPI module.
4040 * @param Timeout Timeout duration
4041 * @param Tickstart tick start value
4042 * @retval HAL status
4043 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4044 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4045 {
4046 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4047 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4048 {
4049 /* Disable SPI peripheral */
4050 __HAL_SPI_DISABLE(hspi);
4051 }
4052
4053 /* Control the BSY flag */
4054 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4055 {
4056 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4057 return HAL_TIMEOUT;
4058 }
4059
4060 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4061 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4062 {
4063 /* Empty the FRLVL fifo */
4064 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4065 {
4066 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4067 return HAL_TIMEOUT;
4068 }
4069 }
4070 return HAL_OK;
4071 }
4072
4073 /**
4074 * @brief Handle the check of the RXTX or TX transaction complete.
4075 * @param hspi SPI handle
4076 * @param Timeout Timeout duration
4077 * @param Tickstart tick start value
4078 * @retval HAL status
4079 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4080 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4081 {
4082 /* Control if the TX fifo is empty */
4083 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4084 {
4085 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4086 return HAL_TIMEOUT;
4087 }
4088
4089 /* Control the BSY flag */
4090 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4091 {
4092 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4093 return HAL_TIMEOUT;
4094 }
4095
4096 /* Control if the RX fifo is empty */
4097 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4098 {
4099 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4100 return HAL_TIMEOUT;
4101 }
4102
4103 return HAL_OK;
4104 }
4105
4106 /**
4107 * @brief Handle the end of the RXTX transaction.
4108 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4109 * the configuration information for SPI module.
4110 * @retval None
4111 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4112 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4113 {
4114 uint32_t tickstart;
4115
4116 /* Init tickstart for timeout management */
4117 tickstart = HAL_GetTick();
4118
4119 /* Disable ERR interrupt */
4120 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4121
4122 /* Check the end of the transaction */
4123 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4124 {
4125 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4126 }
4127
4128 #if (USE_SPI_CRC != 0U)
4129 /* Check if CRC error occurred */
4130 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4131 {
4132 hspi->State = HAL_SPI_STATE_READY;
4133 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4134 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4135 /* Call user error callback */
4136 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4137 hspi->ErrorCallback(hspi);
4138 #else
4139 HAL_SPI_ErrorCallback(hspi);
4140 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4141 }
4142 else
4143 {
4144 #endif /* USE_SPI_CRC */
4145 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4146 {
4147 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4148 {
4149 hspi->State = HAL_SPI_STATE_READY;
4150 /* Call user Rx complete callback */
4151 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4152 hspi->RxCpltCallback(hspi);
4153 #else
4154 HAL_SPI_RxCpltCallback(hspi);
4155 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4156 }
4157 else
4158 {
4159 hspi->State = HAL_SPI_STATE_READY;
4160 /* Call user TxRx complete callback */
4161 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4162 hspi->TxRxCpltCallback(hspi);
4163 #else
4164 HAL_SPI_TxRxCpltCallback(hspi);
4165 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4166 }
4167 }
4168 else
4169 {
4170 hspi->State = HAL_SPI_STATE_READY;
4171 /* Call user error callback */
4172 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4173 hspi->ErrorCallback(hspi);
4174 #else
4175 HAL_SPI_ErrorCallback(hspi);
4176 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4177 }
4178 #if (USE_SPI_CRC != 0U)
4179 }
4180 #endif /* USE_SPI_CRC */
4181 }
4182
4183 /**
4184 * @brief Handle the end of the RX transaction.
4185 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4186 * the configuration information for SPI module.
4187 * @retval None
4188 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4189 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4190 {
4191 /* Disable RXNE and ERR interrupt */
4192 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4193
4194 /* Check the end of the transaction */
4195 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4196 {
4197 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4198 }
4199 hspi->State = HAL_SPI_STATE_READY;
4200
4201 #if (USE_SPI_CRC != 0U)
4202 /* Check if CRC error occurred */
4203 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4204 {
4205 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4206 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4207 /* Call user error callback */
4208 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4209 hspi->ErrorCallback(hspi);
4210 #else
4211 HAL_SPI_ErrorCallback(hspi);
4212 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4213 }
4214 else
4215 {
4216 #endif /* USE_SPI_CRC */
4217 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4218 {
4219 /* Call user Rx complete callback */
4220 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4221 hspi->RxCpltCallback(hspi);
4222 #else
4223 HAL_SPI_RxCpltCallback(hspi);
4224 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4225 }
4226 else
4227 {
4228 /* Call user error callback */
4229 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4230 hspi->ErrorCallback(hspi);
4231 #else
4232 HAL_SPI_ErrorCallback(hspi);
4233 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4234 }
4235 #if (USE_SPI_CRC != 0U)
4236 }
4237 #endif /* USE_SPI_CRC */
4238 }
4239
4240 /**
4241 * @brief Handle the end of the TX transaction.
4242 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4243 * the configuration information for SPI module.
4244 * @retval None
4245 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4246 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4247 {
4248 uint32_t tickstart;
4249
4250 /* Init tickstart for timeout management*/
4251 tickstart = HAL_GetTick();
4252
4253 /* Disable TXE and ERR interrupt */
4254 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4255
4256 /* Check the end of the transaction */
4257 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4258 {
4259 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4260 }
4261
4262 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4263 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4264 {
4265 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4266 }
4267
4268 hspi->State = HAL_SPI_STATE_READY;
4269 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4270 {
4271 /* Call user error callback */
4272 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4273 hspi->ErrorCallback(hspi);
4274 #else
4275 HAL_SPI_ErrorCallback(hspi);
4276 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4277 }
4278 else
4279 {
4280 /* Call user Rx complete callback */
4281 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4282 hspi->TxCpltCallback(hspi);
4283 #else
4284 HAL_SPI_TxCpltCallback(hspi);
4285 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4286 }
4287 }
4288
4289 /**
4290 * @brief Handle abort a Rx transaction.
4291 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4292 * the configuration information for SPI module.
4293 * @retval None
4294 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4295 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4296 {
4297 __IO uint32_t count;
4298
4299 /* Disable SPI Peripheral */
4300 __HAL_SPI_DISABLE(hspi);
4301
4302 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4303
4304 /* Disable RXNEIE interrupt */
4305 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4306
4307 /* Check RXNEIE is disabled */
4308 do
4309 {
4310 if (count == 0U)
4311 {
4312 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4313 break;
4314 }
4315 count--;
4316 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4317
4318 /* Control the BSY flag */
4319 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4320 {
4321 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4322 }
4323
4324 /* Empty the FRLVL fifo */
4325 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4326 {
4327 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4328 }
4329
4330 hspi->State = HAL_SPI_STATE_ABORT;
4331 }
4332
4333 /**
4334 * @brief Handle abort a Tx or Rx/Tx transaction.
4335 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4336 * the configuration information for SPI module.
4337 * @retval None
4338 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4339 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4340 {
4341 __IO uint32_t count;
4342
4343 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4344
4345 /* Disable TXEIE interrupt */
4346 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4347
4348 /* Check TXEIE is disabled */
4349 do
4350 {
4351 if (count == 0U)
4352 {
4353 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4354 break;
4355 }
4356 count--;
4357 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4358
4359 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4360 {
4361 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4362 }
4363
4364 /* Disable SPI Peripheral */
4365 __HAL_SPI_DISABLE(hspi);
4366
4367 /* Empty the FRLVL fifo */
4368 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4369 {
4370 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4371 }
4372
4373 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4374 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4375 {
4376 /* Disable RXNEIE interrupt */
4377 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4378
4379 /* Check RXNEIE is disabled */
4380 do
4381 {
4382 if (count == 0U)
4383 {
4384 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4385 break;
4386 }
4387 count--;
4388 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4389
4390 /* Control the BSY flag */
4391 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4392 {
4393 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4394 }
4395
4396 /* Empty the FRLVL fifo */
4397 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4398 {
4399 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4400 }
4401 }
4402 hspi->State = HAL_SPI_STATE_ABORT;
4403 }
4404
4405 /**
4406 * @}
4407 */
4408
4409 #endif /* HAL_SPI_MODULE_ENABLED */
4410
4411 /**
4412 * @}
4413 */
4414
4415 /**
4416 * @}
4417 */
4418
4419
