1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_PWR_H
21 #define __STM32F0xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
47 * @{
48 */
49
50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
51 * @brief Flags defines which can be used with LL_PWR_WriteReg function
52 * @{
53 */
54 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
55 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
56 /**
57 * @}
58 */
59
60 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
61 * @brief Flags defines which can be used with LL_PWR_ReadReg function
62 * @{
63 */
64 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
65 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
66 #if defined(PWR_PVD_SUPPORT)
67 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
68 #endif /* PWR_PVD_SUPPORT */
69 #if defined(PWR_CSR_VREFINTRDYF)
70 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
71 #endif /* PWR_CSR_VREFINTRDYF */
72 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
73 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
74 #if defined(PWR_CSR_EWUP3)
75 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
76 #endif /* PWR_CSR_EWUP3 */
77 #if defined(PWR_CSR_EWUP4)
78 #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */
79 #endif /* PWR_CSR_EWUP4 */
80 #if defined(PWR_CSR_EWUP5)
81 #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */
82 #endif /* PWR_CSR_EWUP5 */
83 #if defined(PWR_CSR_EWUP6)
84 #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */
85 #endif /* PWR_CSR_EWUP6 */
86 #if defined(PWR_CSR_EWUP7)
87 #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */
88 #endif /* PWR_CSR_EWUP7 */
89 #if defined(PWR_CSR_EWUP8)
90 #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */
91 #endif /* PWR_CSR_EWUP8 */
92 /**
93 * @}
94 */
95
96
97 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
98 * @{
99 */
100 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
101 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
102 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
103 /**
104 * @}
105 */
106
107 #if defined(PWR_CR_LPDS)
108 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
109 * @{
110 */
111 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
112 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
113 /**
114 * @}
115 */
116 #endif /* PWR_CR_LPDS */
117
118 #if defined(PWR_PVD_SUPPORT)
119 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
120 * @{
121 */
122 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */
123 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */
124 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */
125 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */
126 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */
127 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */
128 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */
129 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */
130 /**
131 * @}
132 */
133 #endif /* PWR_PVD_SUPPORT */
134 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
135 * @{
136 */
137 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
138 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
139 #if defined(PWR_CSR_EWUP3)
140 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
141 #endif /* PWR_CSR_EWUP3 */
142 #if defined(PWR_CSR_EWUP4)
143 #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : PA2 */
144 #endif /* PWR_CSR_EWUP4 */
145 #if defined(PWR_CSR_EWUP5)
146 #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : PC5 */
147 #endif /* PWR_CSR_EWUP5 */
148 #if defined(PWR_CSR_EWUP6)
149 #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : PB5 */
150 #endif /* PWR_CSR_EWUP6 */
151 #if defined(PWR_CSR_EWUP7)
152 #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : PB15 */
153 #endif /* PWR_CSR_EWUP7 */
154 #if defined(PWR_CSR_EWUP8)
155 #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : PF2 */
156 #endif /* PWR_CSR_EWUP8 */
157 /**
158 * @}
159 */
160
161 /**
162 * @}
163 */
164
165
166 /* Exported macro ------------------------------------------------------------*/
167 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
168 * @{
169 */
170
171 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
172 * @{
173 */
174
175 /**
176 * @brief Write a value in PWR register
177 * @param __REG__ Register to be written
178 * @param __VALUE__ Value to be written in the register
179 * @retval None
180 */
181 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
182
183 /**
184 * @brief Read a value in PWR register
185 * @param __REG__ Register to be read
186 * @retval Register value
187 */
188 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Exported functions --------------------------------------------------------*/
198 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
199 * @{
200 */
201
202 /** @defgroup PWR_LL_EF_Configuration Configuration
203 * @{
204 */
205
206 /**
207 * @brief Enable access to the backup domain
208 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
209 * @retval None
210 */
LL_PWR_EnableBkUpAccess(void)211 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
212 {
213 SET_BIT(PWR->CR, PWR_CR_DBP);
214 }
215
216 /**
217 * @brief Disable access to the backup domain
218 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
219 * @retval None
220 */
LL_PWR_DisableBkUpAccess(void)221 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
222 {
223 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
224 }
225
226 /**
227 * @brief Check if the backup domain is enabled
228 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
229 * @retval State of bit (1 or 0).
230 */
LL_PWR_IsEnabledBkUpAccess(void)231 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
232 {
233 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
234 }
235
236 #if defined(PWR_CR_LPDS)
237 /**
238 * @brief Set voltage Regulator mode during deep sleep mode
239 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
240 * @param RegulMode This parameter can be one of the following values:
241 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
242 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
243 * @retval None
244 */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)245 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
246 {
247 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
248 }
249
250 /**
251 * @brief Get voltage Regulator mode during deep sleep mode
252 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
253 * @retval Returned value can be one of the following values:
254 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
255 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
256 */
LL_PWR_GetRegulModeDS(void)257 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
258 {
259 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
260 }
261 #endif /* PWR_CR_LPDS */
262
263 /**
264 * @brief Set Power Down mode when CPU enters deepsleep
265 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
266 * @rmtoll CR LPDS LL_PWR_SetPowerMode
267 * @param PDMode This parameter can be one of the following values:
268 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
269 * @arg @ref LL_PWR_MODE_STOP_LPREGU
270 * @arg @ref LL_PWR_MODE_STANDBY
271 * @retval None
272 */
LL_PWR_SetPowerMode(uint32_t PDMode)273 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
274 {
275 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
276 }
277
278 /**
279 * @brief Get Power Down mode when CPU enters deepsleep
280 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
281 * @rmtoll CR LPDS LL_PWR_GetPowerMode
282 * @retval Returned value can be one of the following values:
283 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
284 * @arg @ref LL_PWR_MODE_STOP_LPREGU
285 * @arg @ref LL_PWR_MODE_STANDBY
286 */
LL_PWR_GetPowerMode(void)287 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
288 {
289 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
290 }
291
292 #if defined(PWR_PVD_SUPPORT)
293 /**
294 * @brief Configure the voltage threshold detected by the Power Voltage Detector
295 * @rmtoll CR PLS LL_PWR_SetPVDLevel
296 * @param PVDLevel This parameter can be one of the following values:
297 * @arg @ref LL_PWR_PVDLEVEL_0
298 * @arg @ref LL_PWR_PVDLEVEL_1
299 * @arg @ref LL_PWR_PVDLEVEL_2
300 * @arg @ref LL_PWR_PVDLEVEL_3
301 * @arg @ref LL_PWR_PVDLEVEL_4
302 * @arg @ref LL_PWR_PVDLEVEL_5
303 * @arg @ref LL_PWR_PVDLEVEL_6
304 * @arg @ref LL_PWR_PVDLEVEL_7
305 * @retval None
306 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)307 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
308 {
309 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
310 }
311
312 /**
313 * @brief Get the voltage threshold detection
314 * @rmtoll CR PLS LL_PWR_GetPVDLevel
315 * @retval Returned value can be one of the following values:
316 * @arg @ref LL_PWR_PVDLEVEL_0
317 * @arg @ref LL_PWR_PVDLEVEL_1
318 * @arg @ref LL_PWR_PVDLEVEL_2
319 * @arg @ref LL_PWR_PVDLEVEL_3
320 * @arg @ref LL_PWR_PVDLEVEL_4
321 * @arg @ref LL_PWR_PVDLEVEL_5
322 * @arg @ref LL_PWR_PVDLEVEL_6
323 * @arg @ref LL_PWR_PVDLEVEL_7
324 */
LL_PWR_GetPVDLevel(void)325 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
326 {
327 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
328 }
329
330 /**
331 * @brief Enable Power Voltage Detector
332 * @rmtoll CR PVDE LL_PWR_EnablePVD
333 * @retval None
334 */
LL_PWR_EnablePVD(void)335 __STATIC_INLINE void LL_PWR_EnablePVD(void)
336 {
337 SET_BIT(PWR->CR, PWR_CR_PVDE);
338 }
339
340 /**
341 * @brief Disable Power Voltage Detector
342 * @rmtoll CR PVDE LL_PWR_DisablePVD
343 * @retval None
344 */
LL_PWR_DisablePVD(void)345 __STATIC_INLINE void LL_PWR_DisablePVD(void)
346 {
347 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
348 }
349
350 /**
351 * @brief Check if Power Voltage Detector is enabled
352 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
353 * @retval State of bit (1 or 0).
354 */
LL_PWR_IsEnabledPVD(void)355 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
356 {
357 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
358 }
359 #endif /* PWR_PVD_SUPPORT */
360
361 /**
362 * @brief Enable the WakeUp PINx functionality
363 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
364 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
365 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n
366 * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n
367 * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n
368 * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n
369 * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n
370 * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin
371 * @param WakeUpPin This parameter can be one of the following values:
372 * @arg @ref LL_PWR_WAKEUP_PIN1
373 * @arg @ref LL_PWR_WAKEUP_PIN2
374 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
375 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
376 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
377 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
378 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
379 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
380 *
381 * (*) not available on all devices
382 * @retval None
383 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)384 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
385 {
386 SET_BIT(PWR->CSR, WakeUpPin);
387 }
388
389 /**
390 * @brief Disable the WakeUp PINx functionality
391 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
392 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
393 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n
394 * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n
395 * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n
396 * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n
397 * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n
398 * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin
399 * @param WakeUpPin This parameter can be one of the following values:
400 * @arg @ref LL_PWR_WAKEUP_PIN1
401 * @arg @ref LL_PWR_WAKEUP_PIN2
402 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
403 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
404 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
405 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
406 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
407 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
408 *
409 * (*) not available on all devices
410 * @retval None
411 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)412 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
413 {
414 CLEAR_BIT(PWR->CSR, WakeUpPin);
415 }
416
417 /**
418 * @brief Check if the WakeUp PINx functionality is enabled
419 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
420 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
421 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n
422 * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n
423 * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n
424 * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n
425 * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n
426 * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin
427 * @param WakeUpPin This parameter can be one of the following values:
428 * @arg @ref LL_PWR_WAKEUP_PIN1
429 * @arg @ref LL_PWR_WAKEUP_PIN2
430 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
431 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
432 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
433 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
434 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
435 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
436 *
437 * (*) not available on all devices
438 * @retval State of bit (1 or 0).
439 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)440 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
441 {
442 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
443 }
444
445
446 /**
447 * @}
448 */
449
450 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
451 * @{
452 */
453
454 /**
455 * @brief Get Wake-up Flag
456 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
457 * @retval State of bit (1 or 0).
458 */
LL_PWR_IsActiveFlag_WU(void)459 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
460 {
461 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
462 }
463
464 /**
465 * @brief Get Standby Flag
466 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
467 * @retval State of bit (1 or 0).
468 */
LL_PWR_IsActiveFlag_SB(void)469 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
470 {
471 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
472 }
473
474 #if defined(PWR_PVD_SUPPORT)
475 /**
476 * @brief Indicate whether VDD voltage is below the selected PVD threshold
477 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
478 * @retval State of bit (1 or 0).
479 */
LL_PWR_IsActiveFlag_PVDO(void)480 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
481 {
482 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
483 }
484 #endif /* PWR_PVD_SUPPORT */
485
486 #if defined(PWR_CSR_VREFINTRDYF)
487 /**
488 * @brief Get Internal Reference VrefInt Flag
489 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
490 * @retval State of bit (1 or 0).
491 */
LL_PWR_IsActiveFlag_VREFINTRDY(void)492 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
493 {
494 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
495 }
496 #endif /* PWR_CSR_VREFINTRDYF */
497 /**
498 * @brief Clear Standby Flag
499 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
500 * @retval None
501 */
LL_PWR_ClearFlag_SB(void)502 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
503 {
504 SET_BIT(PWR->CR, PWR_CR_CSBF);
505 }
506
507 /**
508 * @brief Clear Wake-up Flags
509 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
510 * @retval None
511 */
LL_PWR_ClearFlag_WU(void)512 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
513 {
514 SET_BIT(PWR->CR, PWR_CR_CWUF);
515 }
516
517 /**
518 * @}
519 */
520
521 #if defined(USE_FULL_LL_DRIVER)
522 /** @defgroup PWR_LL_EF_Init De-initialization function
523 * @{
524 */
525 ErrorStatus LL_PWR_DeInit(void);
526 /**
527 * @}
528 */
529 #endif /* USE_FULL_LL_DRIVER */
530
531 /**
532 * @}
533 */
534
535 /**
536 * @}
537 */
538
539 #endif /* defined(PWR) */
540
541 /**
542 * @}
543 */
544
545 #ifdef __cplusplus
546 }
547 #endif
548
549 #endif /* __STM32F0xx_LL_PWR_H */
550
