1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_DMA_H
21 #define __STM32F0xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
46 static const uint8_t CHANNEL_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
53 #if defined(DMA1_Channel6)
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 #endif /*DMA1_Channel6*/
56 #if defined(DMA1_Channel7)
57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
58 #endif /*DMA1_Channel7*/
59 };
60 /**
61 * @}
62 */
63
64 /* Private constants ---------------------------------------------------------*/
65 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
66 * @{
67 */
68 /* Define used to get CSELR register offset */
69 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
70
71 /* Defines used for the bit position in the register and perform offsets */
72 #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
73 /**
74 * @}
75 */
76
77 /* Private macros ------------------------------------------------------------*/
78 #if defined(USE_FULL_LL_DRIVER)
79 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
80 * @{
81 */
82 /**
83 * @}
84 */
85 #endif /*USE_FULL_LL_DRIVER*/
86
87 /* Exported types ------------------------------------------------------------*/
88 #if defined(USE_FULL_LL_DRIVER)
89 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
90 * @{
91 */
92 typedef struct
93 {
94 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
95 or as Source base address in case of memory to memory transfer direction.
96
97 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
98
99 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
100 or as Destination base address in case of memory to memory transfer direction.
101
102 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
103
104 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
105 from memory to memory or from peripheral to memory.
106 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
107
108 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
109
110 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
111 This parameter can be a value of @ref DMA_LL_EC_MODE
112 @note: The circular buffer mode cannot be used if the memory to memory
113 data transfer direction is configured on the selected Channel
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
116
117 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
118 is incremented or not.
119 This parameter can be a value of @ref DMA_LL_EC_PERIPH
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
122
123 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
124 is incremented or not.
125 This parameter can be a value of @ref DMA_LL_EC_MEMORY
126
127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
128
129 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
130 in case of memory to memory transfer direction.
131 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
132
133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
134
135 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
136 in case of memory to memory transfer direction.
137 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
138
139 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
140
141 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
142 The data unit is equal to the source buffer configuration set in PeripheralSize
143 or MemorySize parameters depending in the transfer direction.
144 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
145
146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
147 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
148
149 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
150 This parameter can be a value of @ref DMA_LL_EC_REQUEST
151
152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
153 #endif
154
155 uint32_t Priority; /*!< Specifies the channel priority level.
156 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
157
158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
159
160 } LL_DMA_InitTypeDef;
161 /**
162 * @}
163 */
164 #endif /*USE_FULL_LL_DRIVER*/
165
166 /* Exported constants --------------------------------------------------------*/
167 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
168 * @{
169 */
170 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
171 * @brief Flags defines which can be used with LL_DMA_WriteReg function
172 * @{
173 */
174 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
175 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
176 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
177 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
178 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
179 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
180 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
181 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
182 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
183 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
184 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
185 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
186 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
187 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
188 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
189 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
190 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
191 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
192 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
193 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
194 #if defined(DMA1_Channel6)
195 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
196 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
197 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
198 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
199 #endif
200 #if defined(DMA1_Channel7)
201 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
202 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
203 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
204 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
205 #endif
206 /**
207 * @}
208 */
209
210 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
211 * @brief Flags defines which can be used with LL_DMA_ReadReg function
212 * @{
213 */
214 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
215 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
216 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
217 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
218 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
219 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
220 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
221 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
222 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
223 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
224 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
225 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
226 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
227 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
228 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
229 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
230 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
231 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
232 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
233 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
234 #if defined(DMA1_Channel6)
235 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
236 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
237 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
238 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
239 #endif
240 #if defined(DMA1_Channel7)
241 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
242 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
243 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
244 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
245 #endif
246 /**
247 * @}
248 */
249
250 /** @defgroup DMA_LL_EC_IT IT Defines
251 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
252 * @{
253 */
254 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
255 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
256 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
257 /**
258 * @}
259 */
260
261 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
262 * @{
263 */
264 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
265 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
266 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
267 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
268 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
269 #if defined(DMA1_Channel6)
270 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
271 #endif
272 #if defined(DMA1_Channel7)
273 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
274 #endif
275 #if defined(USE_FULL_LL_DRIVER)
276 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
277 #endif /*USE_FULL_LL_DRIVER*/
278 /**
279 * @}
280 */
281
282 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
283 * @{
284 */
285 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
286 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
287 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
288 /**
289 * @}
290 */
291
292 /** @defgroup DMA_LL_EC_MODE Transfer mode
293 * @{
294 */
295 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
296 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
297 /**
298 * @}
299 */
300
301 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
302 * @{
303 */
304 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
305 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
306 /**
307 * @}
308 */
309
310 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
311 * @{
312 */
313 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
314 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
315 /**
316 * @}
317 */
318
319 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
320 * @{
321 */
322 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
323 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
324 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
325 /**
326 * @}
327 */
328
329 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
330 * @{
331 */
332 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
333 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
334 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
335 /**
336 * @}
337 */
338
339 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
340 * @{
341 */
342 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
343 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
344 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
345 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
346 /**
347 * @}
348 */
349
350 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
351 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
352 * @{
353 */
354 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
355 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
356 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
357 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
358 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
359 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
360 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
361 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
362 #define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */
363 #define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */
364 #define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */
365 #define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */
366 #define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */
367 #define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */
368 #define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */
369 #define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */
370 /**
371 * @}
372 */
373 #endif
374
375 /**
376 * @}
377 */
378
379 /* Exported macro ------------------------------------------------------------*/
380 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
381 * @{
382 */
383
384 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
385 * @{
386 */
387 /**
388 * @brief Write a value in DMA register
389 * @param __INSTANCE__ DMA Instance
390 * @param __REG__ Register to be written
391 * @param __VALUE__ Value to be written in the register
392 * @retval None
393 */
394 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
395
396 /**
397 * @brief Read a value in DMA register
398 * @param __INSTANCE__ DMA Instance
399 * @param __REG__ Register to be read
400 * @retval Register value
401 */
402 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
403 /**
404 * @}
405 */
406
407 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
408 * @{
409 */
410 /**
411 * @brief Convert DMAx_Channely into DMAx
412 * @param __CHANNEL_INSTANCE__ DMAx_Channely
413 * @retval DMAx
414 */
415 #if defined(DMA2)
416 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
417 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
418 #else
419 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
420 #endif
421
422 /**
423 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
424 * @param __CHANNEL_INSTANCE__ DMAx_Channely
425 * @retval LL_DMA_CHANNEL_y
426 */
427 #if defined (DMA2)
428 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
429 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
430 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
442 LL_DMA_CHANNEL_7)
443 #else
444 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
445 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
446 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
447 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
453 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
454 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
456 LL_DMA_CHANNEL_7)
457 #endif
458 #else
459 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
460 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
461 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
462 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
463 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
464 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
465 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
466 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
467 LL_DMA_CHANNEL_7)
468 #elif defined (DMA1_Channel6)
469 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
470 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
471 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
472 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
473 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
474 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
475 LL_DMA_CHANNEL_6)
476 #else
477 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
478 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
479 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
480 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
481 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
482 LL_DMA_CHANNEL_5)
483 #endif /* DMA1_Channel6 && DMA1_Channel7 */
484 #endif
485
486 /**
487 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
488 * @param __DMA_INSTANCE__ DMAx
489 * @param __CHANNEL__ LL_DMA_CHANNEL_y
490 * @retval DMAx_Channely
491 */
492 #if defined (DMA2)
493 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
494 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
495 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
496 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
497 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
498 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
499 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
500 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
501 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
502 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
503 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
504 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
505 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
506 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
507 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
508 DMA2_Channel7)
509 #else
510 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
511 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
512 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
513 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
514 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
515 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
516 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
517 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
518 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
519 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
520 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
521 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
522 DMA1_Channel7)
523 #endif
524 #else
525 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
526 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
527 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
528 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
529 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
530 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
531 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
532 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
533 DMA1_Channel7)
534 #elif defined (DMA1_Channel6)
535 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
536 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
537 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
538 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
539 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
540 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
541 DMA1_Channel6)
542 #else
543 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
544 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
545 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
546 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
547 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
548 DMA1_Channel5)
549 #endif /* DMA1_Channel6 && DMA1_Channel7 */
550 #endif
551
552 /**
553 * @}
554 */
555
556 /**
557 * @}
558 */
559
560 /* Exported functions --------------------------------------------------------*/
561 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
562 * @{
563 */
564
565 /** @defgroup DMA_LL_EF_Configuration Configuration
566 * @{
567 */
568 /**
569 * @brief Enable DMA channel.
570 * @rmtoll CCR EN LL_DMA_EnableChannel
571 * @param DMAx DMAx Instance
572 * @param Channel This parameter can be one of the following values:
573 * @arg @ref LL_DMA_CHANNEL_1
574 * @arg @ref LL_DMA_CHANNEL_2
575 * @arg @ref LL_DMA_CHANNEL_3
576 * @arg @ref LL_DMA_CHANNEL_4
577 * @arg @ref LL_DMA_CHANNEL_5
578 * @arg @ref LL_DMA_CHANNEL_6
579 * @arg @ref LL_DMA_CHANNEL_7
580 * @retval None
581 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)582 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
583 {
584 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
585 }
586
587 /**
588 * @brief Disable DMA channel.
589 * @rmtoll CCR EN LL_DMA_DisableChannel
590 * @param DMAx DMAx Instance
591 * @param Channel This parameter can be one of the following values:
592 * @arg @ref LL_DMA_CHANNEL_1
593 * @arg @ref LL_DMA_CHANNEL_2
594 * @arg @ref LL_DMA_CHANNEL_3
595 * @arg @ref LL_DMA_CHANNEL_4
596 * @arg @ref LL_DMA_CHANNEL_5
597 * @arg @ref LL_DMA_CHANNEL_6
598 * @arg @ref LL_DMA_CHANNEL_7
599 * @retval None
600 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)601 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
602 {
603 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
604 }
605
606 /**
607 * @brief Check if DMA channel is enabled or disabled.
608 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
609 * @param DMAx DMAx Instance
610 * @param Channel This parameter can be one of the following values:
611 * @arg @ref LL_DMA_CHANNEL_1
612 * @arg @ref LL_DMA_CHANNEL_2
613 * @arg @ref LL_DMA_CHANNEL_3
614 * @arg @ref LL_DMA_CHANNEL_4
615 * @arg @ref LL_DMA_CHANNEL_5
616 * @arg @ref LL_DMA_CHANNEL_6
617 * @arg @ref LL_DMA_CHANNEL_7
618 * @retval State of bit (1 or 0).
619 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)620 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
621 {
622 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
623 DMA_CCR_EN) == (DMA_CCR_EN));
624 }
625
626 /**
627 * @brief Configure all parameters link to DMA transfer.
628 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
629 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
630 * CCR CIRC LL_DMA_ConfigTransfer\n
631 * CCR PINC LL_DMA_ConfigTransfer\n
632 * CCR MINC LL_DMA_ConfigTransfer\n
633 * CCR PSIZE LL_DMA_ConfigTransfer\n
634 * CCR MSIZE LL_DMA_ConfigTransfer\n
635 * CCR PL LL_DMA_ConfigTransfer
636 * @param DMAx DMAx Instance
637 * @param Channel This parameter can be one of the following values:
638 * @arg @ref LL_DMA_CHANNEL_1
639 * @arg @ref LL_DMA_CHANNEL_2
640 * @arg @ref LL_DMA_CHANNEL_3
641 * @arg @ref LL_DMA_CHANNEL_4
642 * @arg @ref LL_DMA_CHANNEL_5
643 * @arg @ref LL_DMA_CHANNEL_6
644 * @arg @ref LL_DMA_CHANNEL_7
645 * @param Configuration This parameter must be a combination of all the following values:
646 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
647 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
648 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
649 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
650 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
651 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
652 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
653 * @retval None
654 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)655 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
656 {
657 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
658 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
659 Configuration);
660 }
661
662 /**
663 * @brief Set Data transfer direction (read from peripheral or from memory).
664 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
665 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
666 * @param DMAx DMAx Instance
667 * @param Channel This parameter can be one of the following values:
668 * @arg @ref LL_DMA_CHANNEL_1
669 * @arg @ref LL_DMA_CHANNEL_2
670 * @arg @ref LL_DMA_CHANNEL_3
671 * @arg @ref LL_DMA_CHANNEL_4
672 * @arg @ref LL_DMA_CHANNEL_5
673 * @arg @ref LL_DMA_CHANNEL_6
674 * @arg @ref LL_DMA_CHANNEL_7
675 * @param Direction This parameter can be one of the following values:
676 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
677 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
678 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
679 * @retval None
680 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)681 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
682 {
683 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
684 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
685 }
686
687 /**
688 * @brief Get Data transfer direction (read from peripheral or from memory).
689 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
690 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
691 * @param DMAx DMAx Instance
692 * @param Channel This parameter can be one of the following values:
693 * @arg @ref LL_DMA_CHANNEL_1
694 * @arg @ref LL_DMA_CHANNEL_2
695 * @arg @ref LL_DMA_CHANNEL_3
696 * @arg @ref LL_DMA_CHANNEL_4
697 * @arg @ref LL_DMA_CHANNEL_5
698 * @arg @ref LL_DMA_CHANNEL_6
699 * @arg @ref LL_DMA_CHANNEL_7
700 * @retval Returned value can be one of the following values:
701 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
702 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
703 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
704 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)705 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
706 {
707 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
708 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
709 }
710
711 /**
712 * @brief Set DMA mode circular or normal.
713 * @note The circular buffer mode cannot be used if the memory-to-memory
714 * data transfer is configured on the selected Channel.
715 * @rmtoll CCR CIRC LL_DMA_SetMode
716 * @param DMAx DMAx Instance
717 * @param Channel This parameter can be one of the following values:
718 * @arg @ref LL_DMA_CHANNEL_1
719 * @arg @ref LL_DMA_CHANNEL_2
720 * @arg @ref LL_DMA_CHANNEL_3
721 * @arg @ref LL_DMA_CHANNEL_4
722 * @arg @ref LL_DMA_CHANNEL_5
723 * @arg @ref LL_DMA_CHANNEL_6
724 * @arg @ref LL_DMA_CHANNEL_7
725 * @param Mode This parameter can be one of the following values:
726 * @arg @ref LL_DMA_MODE_NORMAL
727 * @arg @ref LL_DMA_MODE_CIRCULAR
728 * @retval None
729 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)730 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
731 {
732 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
733 Mode);
734 }
735
736 /**
737 * @brief Get DMA mode circular or normal.
738 * @rmtoll CCR CIRC LL_DMA_GetMode
739 * @param DMAx DMAx Instance
740 * @param Channel This parameter can be one of the following values:
741 * @arg @ref LL_DMA_CHANNEL_1
742 * @arg @ref LL_DMA_CHANNEL_2
743 * @arg @ref LL_DMA_CHANNEL_3
744 * @arg @ref LL_DMA_CHANNEL_4
745 * @arg @ref LL_DMA_CHANNEL_5
746 * @arg @ref LL_DMA_CHANNEL_6
747 * @arg @ref LL_DMA_CHANNEL_7
748 * @retval Returned value can be one of the following values:
749 * @arg @ref LL_DMA_MODE_NORMAL
750 * @arg @ref LL_DMA_MODE_CIRCULAR
751 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)752 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
753 {
754 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
755 DMA_CCR_CIRC));
756 }
757
758 /**
759 * @brief Set Peripheral increment mode.
760 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
761 * @param DMAx DMAx Instance
762 * @param Channel This parameter can be one of the following values:
763 * @arg @ref LL_DMA_CHANNEL_1
764 * @arg @ref LL_DMA_CHANNEL_2
765 * @arg @ref LL_DMA_CHANNEL_3
766 * @arg @ref LL_DMA_CHANNEL_4
767 * @arg @ref LL_DMA_CHANNEL_5
768 * @arg @ref LL_DMA_CHANNEL_6
769 * @arg @ref LL_DMA_CHANNEL_7
770 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
771 * @arg @ref LL_DMA_PERIPH_INCREMENT
772 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
773 * @retval None
774 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)775 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
776 {
777 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
778 PeriphOrM2MSrcIncMode);
779 }
780
781 /**
782 * @brief Get Peripheral increment mode.
783 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
784 * @param DMAx DMAx Instance
785 * @param Channel This parameter can be one of the following values:
786 * @arg @ref LL_DMA_CHANNEL_1
787 * @arg @ref LL_DMA_CHANNEL_2
788 * @arg @ref LL_DMA_CHANNEL_3
789 * @arg @ref LL_DMA_CHANNEL_4
790 * @arg @ref LL_DMA_CHANNEL_5
791 * @arg @ref LL_DMA_CHANNEL_6
792 * @arg @ref LL_DMA_CHANNEL_7
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_DMA_PERIPH_INCREMENT
795 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
796 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)797 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
798 {
799 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
800 DMA_CCR_PINC));
801 }
802
803 /**
804 * @brief Set Memory increment mode.
805 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
806 * @param DMAx DMAx Instance
807 * @param Channel This parameter can be one of the following values:
808 * @arg @ref LL_DMA_CHANNEL_1
809 * @arg @ref LL_DMA_CHANNEL_2
810 * @arg @ref LL_DMA_CHANNEL_3
811 * @arg @ref LL_DMA_CHANNEL_4
812 * @arg @ref LL_DMA_CHANNEL_5
813 * @arg @ref LL_DMA_CHANNEL_6
814 * @arg @ref LL_DMA_CHANNEL_7
815 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
816 * @arg @ref LL_DMA_MEMORY_INCREMENT
817 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
818 * @retval None
819 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)820 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
821 {
822 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
823 MemoryOrM2MDstIncMode);
824 }
825
826 /**
827 * @brief Get Memory increment mode.
828 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
829 * @param DMAx DMAx Instance
830 * @param Channel This parameter can be one of the following values:
831 * @arg @ref LL_DMA_CHANNEL_1
832 * @arg @ref LL_DMA_CHANNEL_2
833 * @arg @ref LL_DMA_CHANNEL_3
834 * @arg @ref LL_DMA_CHANNEL_4
835 * @arg @ref LL_DMA_CHANNEL_5
836 * @arg @ref LL_DMA_CHANNEL_6
837 * @arg @ref LL_DMA_CHANNEL_7
838 * @retval Returned value can be one of the following values:
839 * @arg @ref LL_DMA_MEMORY_INCREMENT
840 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
841 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)842 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
843 {
844 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
845 DMA_CCR_MINC));
846 }
847
848 /**
849 * @brief Set Peripheral size.
850 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
851 * @param DMAx DMAx Instance
852 * @param Channel This parameter can be one of the following values:
853 * @arg @ref LL_DMA_CHANNEL_1
854 * @arg @ref LL_DMA_CHANNEL_2
855 * @arg @ref LL_DMA_CHANNEL_3
856 * @arg @ref LL_DMA_CHANNEL_4
857 * @arg @ref LL_DMA_CHANNEL_5
858 * @arg @ref LL_DMA_CHANNEL_6
859 * @arg @ref LL_DMA_CHANNEL_7
860 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
861 * @arg @ref LL_DMA_PDATAALIGN_BYTE
862 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
863 * @arg @ref LL_DMA_PDATAALIGN_WORD
864 * @retval None
865 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)866 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
867 {
868 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
869 PeriphOrM2MSrcDataSize);
870 }
871
872 /**
873 * @brief Get Peripheral size.
874 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
875 * @param DMAx DMAx Instance
876 * @param Channel This parameter can be one of the following values:
877 * @arg @ref LL_DMA_CHANNEL_1
878 * @arg @ref LL_DMA_CHANNEL_2
879 * @arg @ref LL_DMA_CHANNEL_3
880 * @arg @ref LL_DMA_CHANNEL_4
881 * @arg @ref LL_DMA_CHANNEL_5
882 * @arg @ref LL_DMA_CHANNEL_6
883 * @arg @ref LL_DMA_CHANNEL_7
884 * @retval Returned value can be one of the following values:
885 * @arg @ref LL_DMA_PDATAALIGN_BYTE
886 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
887 * @arg @ref LL_DMA_PDATAALIGN_WORD
888 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)889 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
890 {
891 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
892 DMA_CCR_PSIZE));
893 }
894
895 /**
896 * @brief Set Memory size.
897 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
898 * @param DMAx DMAx Instance
899 * @param Channel This parameter can be one of the following values:
900 * @arg @ref LL_DMA_CHANNEL_1
901 * @arg @ref LL_DMA_CHANNEL_2
902 * @arg @ref LL_DMA_CHANNEL_3
903 * @arg @ref LL_DMA_CHANNEL_4
904 * @arg @ref LL_DMA_CHANNEL_5
905 * @arg @ref LL_DMA_CHANNEL_6
906 * @arg @ref LL_DMA_CHANNEL_7
907 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
908 * @arg @ref LL_DMA_MDATAALIGN_BYTE
909 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
910 * @arg @ref LL_DMA_MDATAALIGN_WORD
911 * @retval None
912 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)913 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
914 {
915 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
916 MemoryOrM2MDstDataSize);
917 }
918
919 /**
920 * @brief Get Memory size.
921 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
922 * @param DMAx DMAx Instance
923 * @param Channel This parameter can be one of the following values:
924 * @arg @ref LL_DMA_CHANNEL_1
925 * @arg @ref LL_DMA_CHANNEL_2
926 * @arg @ref LL_DMA_CHANNEL_3
927 * @arg @ref LL_DMA_CHANNEL_4
928 * @arg @ref LL_DMA_CHANNEL_5
929 * @arg @ref LL_DMA_CHANNEL_6
930 * @arg @ref LL_DMA_CHANNEL_7
931 * @retval Returned value can be one of the following values:
932 * @arg @ref LL_DMA_MDATAALIGN_BYTE
933 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
934 * @arg @ref LL_DMA_MDATAALIGN_WORD
935 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)936 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
937 {
938 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
939 DMA_CCR_MSIZE));
940 }
941
942 /**
943 * @brief Set Channel priority level.
944 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
945 * @param DMAx DMAx Instance
946 * @param Channel This parameter can be one of the following values:
947 * @arg @ref LL_DMA_CHANNEL_1
948 * @arg @ref LL_DMA_CHANNEL_2
949 * @arg @ref LL_DMA_CHANNEL_3
950 * @arg @ref LL_DMA_CHANNEL_4
951 * @arg @ref LL_DMA_CHANNEL_5
952 * @arg @ref LL_DMA_CHANNEL_6
953 * @arg @ref LL_DMA_CHANNEL_7
954 * @param Priority This parameter can be one of the following values:
955 * @arg @ref LL_DMA_PRIORITY_LOW
956 * @arg @ref LL_DMA_PRIORITY_MEDIUM
957 * @arg @ref LL_DMA_PRIORITY_HIGH
958 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
959 * @retval None
960 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)961 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
962 {
963 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
964 Priority);
965 }
966
967 /**
968 * @brief Get Channel priority level.
969 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
970 * @param DMAx DMAx Instance
971 * @param Channel This parameter can be one of the following values:
972 * @arg @ref LL_DMA_CHANNEL_1
973 * @arg @ref LL_DMA_CHANNEL_2
974 * @arg @ref LL_DMA_CHANNEL_3
975 * @arg @ref LL_DMA_CHANNEL_4
976 * @arg @ref LL_DMA_CHANNEL_5
977 * @arg @ref LL_DMA_CHANNEL_6
978 * @arg @ref LL_DMA_CHANNEL_7
979 * @retval Returned value can be one of the following values:
980 * @arg @ref LL_DMA_PRIORITY_LOW
981 * @arg @ref LL_DMA_PRIORITY_MEDIUM
982 * @arg @ref LL_DMA_PRIORITY_HIGH
983 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
984 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)985 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
986 {
987 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
988 DMA_CCR_PL));
989 }
990
991 /**
992 * @brief Set Number of data to transfer.
993 * @note This action has no effect if
994 * channel is enabled.
995 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
996 * @param DMAx DMAx Instance
997 * @param Channel This parameter can be one of the following values:
998 * @arg @ref LL_DMA_CHANNEL_1
999 * @arg @ref LL_DMA_CHANNEL_2
1000 * @arg @ref LL_DMA_CHANNEL_3
1001 * @arg @ref LL_DMA_CHANNEL_4
1002 * @arg @ref LL_DMA_CHANNEL_5
1003 * @arg @ref LL_DMA_CHANNEL_6
1004 * @arg @ref LL_DMA_CHANNEL_7
1005 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
1006 * @retval None
1007 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)1008 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
1009 {
1010 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
1011 DMA_CNDTR_NDT, NbData);
1012 }
1013
1014 /**
1015 * @brief Get Number of data to transfer.
1016 * @note Once the channel is enabled, the return value indicate the
1017 * remaining bytes to be transmitted.
1018 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1019 * @param DMAx DMAx Instance
1020 * @param Channel This parameter can be one of the following values:
1021 * @arg @ref LL_DMA_CHANNEL_1
1022 * @arg @ref LL_DMA_CHANNEL_2
1023 * @arg @ref LL_DMA_CHANNEL_3
1024 * @arg @ref LL_DMA_CHANNEL_4
1025 * @arg @ref LL_DMA_CHANNEL_5
1026 * @arg @ref LL_DMA_CHANNEL_6
1027 * @arg @ref LL_DMA_CHANNEL_7
1028 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1029 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1030 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1031 {
1032 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
1033 DMA_CNDTR_NDT));
1034 }
1035
1036 /**
1037 * @brief Configure the Source and Destination addresses.
1038 * @note This API must not be called when the DMA channel is enabled.
1039 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
1040 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1041 * CMAR MA LL_DMA_ConfigAddresses
1042 * @param DMAx DMAx Instance
1043 * @param Channel This parameter can be one of the following values:
1044 * @arg @ref LL_DMA_CHANNEL_1
1045 * @arg @ref LL_DMA_CHANNEL_2
1046 * @arg @ref LL_DMA_CHANNEL_3
1047 * @arg @ref LL_DMA_CHANNEL_4
1048 * @arg @ref LL_DMA_CHANNEL_5
1049 * @arg @ref LL_DMA_CHANNEL_6
1050 * @arg @ref LL_DMA_CHANNEL_7
1051 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1052 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1053 * @param Direction This parameter can be one of the following values:
1054 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1055 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1056 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1057 * @retval None
1058 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1059 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1060 uint32_t DstAddress, uint32_t Direction)
1061 {
1062 /* Direction Memory to Periph */
1063 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1064 {
1065 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
1066 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
1067 }
1068 /* Direction Periph to Memory and Memory to Memory */
1069 else
1070 {
1071 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
1072 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
1073 }
1074 }
1075
1076 /**
1077 * @brief Set the Memory address.
1078 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1079 * @note This API must not be called when the DMA channel is enabled.
1080 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1081 * @param DMAx DMAx Instance
1082 * @param Channel This parameter can be one of the following values:
1083 * @arg @ref LL_DMA_CHANNEL_1
1084 * @arg @ref LL_DMA_CHANNEL_2
1085 * @arg @ref LL_DMA_CHANNEL_3
1086 * @arg @ref LL_DMA_CHANNEL_4
1087 * @arg @ref LL_DMA_CHANNEL_5
1088 * @arg @ref LL_DMA_CHANNEL_6
1089 * @arg @ref LL_DMA_CHANNEL_7
1090 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1091 * @retval None
1092 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1093 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1094 {
1095 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1096 }
1097
1098 /**
1099 * @brief Set the Peripheral address.
1100 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1101 * @note This API must not be called when the DMA channel is enabled.
1102 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1103 * @param DMAx DMAx Instance
1104 * @param Channel This parameter can be one of the following values:
1105 * @arg @ref LL_DMA_CHANNEL_1
1106 * @arg @ref LL_DMA_CHANNEL_2
1107 * @arg @ref LL_DMA_CHANNEL_3
1108 * @arg @ref LL_DMA_CHANNEL_4
1109 * @arg @ref LL_DMA_CHANNEL_5
1110 * @arg @ref LL_DMA_CHANNEL_6
1111 * @arg @ref LL_DMA_CHANNEL_7
1112 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1113 * @retval None
1114 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1115 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1116 {
1117 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1118 }
1119
1120 /**
1121 * @brief Get Memory address.
1122 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1123 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1124 * @param DMAx DMAx Instance
1125 * @param Channel This parameter can be one of the following values:
1126 * @arg @ref LL_DMA_CHANNEL_1
1127 * @arg @ref LL_DMA_CHANNEL_2
1128 * @arg @ref LL_DMA_CHANNEL_3
1129 * @arg @ref LL_DMA_CHANNEL_4
1130 * @arg @ref LL_DMA_CHANNEL_5
1131 * @arg @ref LL_DMA_CHANNEL_6
1132 * @arg @ref LL_DMA_CHANNEL_7
1133 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1134 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1135 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1136 {
1137 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1138 }
1139
1140 /**
1141 * @brief Get Peripheral address.
1142 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1143 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1144 * @param DMAx DMAx Instance
1145 * @param Channel This parameter can be one of the following values:
1146 * @arg @ref LL_DMA_CHANNEL_1
1147 * @arg @ref LL_DMA_CHANNEL_2
1148 * @arg @ref LL_DMA_CHANNEL_3
1149 * @arg @ref LL_DMA_CHANNEL_4
1150 * @arg @ref LL_DMA_CHANNEL_5
1151 * @arg @ref LL_DMA_CHANNEL_6
1152 * @arg @ref LL_DMA_CHANNEL_7
1153 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1154 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1155 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1156 {
1157 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1158 }
1159
1160 /**
1161 * @brief Set the Memory to Memory Source address.
1162 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1163 * @note This API must not be called when the DMA channel is enabled.
1164 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1165 * @param DMAx DMAx Instance
1166 * @param Channel This parameter can be one of the following values:
1167 * @arg @ref LL_DMA_CHANNEL_1
1168 * @arg @ref LL_DMA_CHANNEL_2
1169 * @arg @ref LL_DMA_CHANNEL_3
1170 * @arg @ref LL_DMA_CHANNEL_4
1171 * @arg @ref LL_DMA_CHANNEL_5
1172 * @arg @ref LL_DMA_CHANNEL_6
1173 * @arg @ref LL_DMA_CHANNEL_7
1174 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1175 * @retval None
1176 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1177 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1178 {
1179 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1180 }
1181
1182 /**
1183 * @brief Set the Memory to Memory Destination address.
1184 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1185 * @note This API must not be called when the DMA channel is enabled.
1186 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1187 * @param DMAx DMAx Instance
1188 * @param Channel This parameter can be one of the following values:
1189 * @arg @ref LL_DMA_CHANNEL_1
1190 * @arg @ref LL_DMA_CHANNEL_2
1191 * @arg @ref LL_DMA_CHANNEL_3
1192 * @arg @ref LL_DMA_CHANNEL_4
1193 * @arg @ref LL_DMA_CHANNEL_5
1194 * @arg @ref LL_DMA_CHANNEL_6
1195 * @arg @ref LL_DMA_CHANNEL_7
1196 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1197 * @retval None
1198 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1199 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1200 {
1201 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1202 }
1203
1204 /**
1205 * @brief Get the Memory to Memory Source address.
1206 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1207 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1208 * @param DMAx DMAx Instance
1209 * @param Channel This parameter can be one of the following values:
1210 * @arg @ref LL_DMA_CHANNEL_1
1211 * @arg @ref LL_DMA_CHANNEL_2
1212 * @arg @ref LL_DMA_CHANNEL_3
1213 * @arg @ref LL_DMA_CHANNEL_4
1214 * @arg @ref LL_DMA_CHANNEL_5
1215 * @arg @ref LL_DMA_CHANNEL_6
1216 * @arg @ref LL_DMA_CHANNEL_7
1217 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1218 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1219 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1220 {
1221 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1222 }
1223
1224 /**
1225 * @brief Get the Memory to Memory Destination address.
1226 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1227 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1228 * @param DMAx DMAx Instance
1229 * @param Channel This parameter can be one of the following values:
1230 * @arg @ref LL_DMA_CHANNEL_1
1231 * @arg @ref LL_DMA_CHANNEL_2
1232 * @arg @ref LL_DMA_CHANNEL_3
1233 * @arg @ref LL_DMA_CHANNEL_4
1234 * @arg @ref LL_DMA_CHANNEL_5
1235 * @arg @ref LL_DMA_CHANNEL_6
1236 * @arg @ref LL_DMA_CHANNEL_7
1237 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1238 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1239 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1240 {
1241 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1242 }
1243
1244 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
1245 /**
1246 * @brief Set DMA request for DMA instance on Channel x.
1247 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1248 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1249 * CSELR C2S LL_DMA_SetPeriphRequest\n
1250 * CSELR C3S LL_DMA_SetPeriphRequest\n
1251 * CSELR C4S LL_DMA_SetPeriphRequest\n
1252 * CSELR C5S LL_DMA_SetPeriphRequest\n
1253 * CSELR C6S LL_DMA_SetPeriphRequest\n
1254 * CSELR C7S LL_DMA_SetPeriphRequest
1255 * @param DMAx DMAx Instance
1256 * @param Channel This parameter can be one of the following values:
1257 * @arg @ref LL_DMA_CHANNEL_1
1258 * @arg @ref LL_DMA_CHANNEL_2
1259 * @arg @ref LL_DMA_CHANNEL_3
1260 * @arg @ref LL_DMA_CHANNEL_4
1261 * @arg @ref LL_DMA_CHANNEL_5
1262 * @arg @ref LL_DMA_CHANNEL_6
1263 * @arg @ref LL_DMA_CHANNEL_7
1264 * @param PeriphRequest This parameter can be one of the following values:
1265 * @arg @ref LL_DMA_REQUEST_0
1266 * @arg @ref LL_DMA_REQUEST_1
1267 * @arg @ref LL_DMA_REQUEST_2
1268 * @arg @ref LL_DMA_REQUEST_3
1269 * @arg @ref LL_DMA_REQUEST_4
1270 * @arg @ref LL_DMA_REQUEST_5
1271 * @arg @ref LL_DMA_REQUEST_6
1272 * @arg @ref LL_DMA_REQUEST_7
1273 * @arg @ref LL_DMA_REQUEST_8
1274 * @arg @ref LL_DMA_REQUEST_9
1275 * @arg @ref LL_DMA_REQUEST_10
1276 * @arg @ref LL_DMA_REQUEST_11
1277 * @arg @ref LL_DMA_REQUEST_12
1278 * @arg @ref LL_DMA_REQUEST_13
1279 * @arg @ref LL_DMA_REQUEST_14
1280 * @arg @ref LL_DMA_REQUEST_15
1281 * @retval None
1282 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphRequest)1283 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
1284 {
1285 MODIFY_REG(DMAx->CSELR,
1286 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
1287 }
1288
1289 /**
1290 * @brief Get DMA request for DMA instance on Channel x.
1291 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1292 * CSELR C2S LL_DMA_GetPeriphRequest\n
1293 * CSELR C3S LL_DMA_GetPeriphRequest\n
1294 * CSELR C4S LL_DMA_GetPeriphRequest\n
1295 * CSELR C5S LL_DMA_GetPeriphRequest\n
1296 * CSELR C6S LL_DMA_GetPeriphRequest\n
1297 * CSELR C7S LL_DMA_GetPeriphRequest
1298 * @param DMAx DMAx Instance
1299 * @param Channel This parameter can be one of the following values:
1300 * @arg @ref LL_DMA_CHANNEL_1
1301 * @arg @ref LL_DMA_CHANNEL_2
1302 * @arg @ref LL_DMA_CHANNEL_3
1303 * @arg @ref LL_DMA_CHANNEL_4
1304 * @arg @ref LL_DMA_CHANNEL_5
1305 * @arg @ref LL_DMA_CHANNEL_6
1306 * @arg @ref LL_DMA_CHANNEL_7
1307 * @retval Returned value can be one of the following values:
1308 * @arg @ref LL_DMA_REQUEST_0
1309 * @arg @ref LL_DMA_REQUEST_1
1310 * @arg @ref LL_DMA_REQUEST_2
1311 * @arg @ref LL_DMA_REQUEST_3
1312 * @arg @ref LL_DMA_REQUEST_4
1313 * @arg @ref LL_DMA_REQUEST_5
1314 * @arg @ref LL_DMA_REQUEST_6
1315 * @arg @ref LL_DMA_REQUEST_7
1316 * @arg @ref LL_DMA_REQUEST_8
1317 * @arg @ref LL_DMA_REQUEST_9
1318 * @arg @ref LL_DMA_REQUEST_10
1319 * @arg @ref LL_DMA_REQUEST_11
1320 * @arg @ref LL_DMA_REQUEST_12
1321 * @arg @ref LL_DMA_REQUEST_13
1322 * @arg @ref LL_DMA_REQUEST_14
1323 * @arg @ref LL_DMA_REQUEST_15
1324 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1325 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1326 {
1327 return (READ_BIT(DMAx->CSELR,
1328 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
1329 }
1330 #endif
1331
1332 /**
1333 * @}
1334 */
1335
1336 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1337 * @{
1338 */
1339
1340 /**
1341 * @brief Get Channel 1 global interrupt flag.
1342 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1343 * @param DMAx DMAx Instance
1344 * @retval State of bit (1 or 0).
1345 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1346 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1347 {
1348 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1349 }
1350
1351 /**
1352 * @brief Get Channel 2 global interrupt flag.
1353 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1354 * @param DMAx DMAx Instance
1355 * @retval State of bit (1 or 0).
1356 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1357 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1358 {
1359 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1360 }
1361
1362 /**
1363 * @brief Get Channel 3 global interrupt flag.
1364 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1365 * @param DMAx DMAx Instance
1366 * @retval State of bit (1 or 0).
1367 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1368 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1369 {
1370 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1371 }
1372
1373 /**
1374 * @brief Get Channel 4 global interrupt flag.
1375 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1376 * @param DMAx DMAx Instance
1377 * @retval State of bit (1 or 0).
1378 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1379 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1380 {
1381 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1382 }
1383
1384 /**
1385 * @brief Get Channel 5 global interrupt flag.
1386 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1387 * @param DMAx DMAx Instance
1388 * @retval State of bit (1 or 0).
1389 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1390 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1391 {
1392 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1393 }
1394
1395 #if defined(DMA1_Channel6)
1396 /**
1397 * @brief Get Channel 6 global interrupt flag.
1398 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1399 * @param DMAx DMAx Instance
1400 * @retval State of bit (1 or 0).
1401 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1402 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1403 {
1404 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1405 }
1406 #endif
1407
1408 #if defined(DMA1_Channel7)
1409 /**
1410 * @brief Get Channel 7 global interrupt flag.
1411 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1412 * @param DMAx DMAx Instance
1413 * @retval State of bit (1 or 0).
1414 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1415 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1416 {
1417 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1418 }
1419 #endif
1420
1421 /**
1422 * @brief Get Channel 1 transfer complete flag.
1423 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1424 * @param DMAx DMAx Instance
1425 * @retval State of bit (1 or 0).
1426 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1427 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1428 {
1429 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1430 }
1431
1432 /**
1433 * @brief Get Channel 2 transfer complete flag.
1434 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1435 * @param DMAx DMAx Instance
1436 * @retval State of bit (1 or 0).
1437 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1438 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1439 {
1440 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1441 }
1442
1443 /**
1444 * @brief Get Channel 3 transfer complete flag.
1445 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1446 * @param DMAx DMAx Instance
1447 * @retval State of bit (1 or 0).
1448 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1449 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1450 {
1451 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1452 }
1453
1454 /**
1455 * @brief Get Channel 4 transfer complete flag.
1456 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1457 * @param DMAx DMAx Instance
1458 * @retval State of bit (1 or 0).
1459 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1460 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1461 {
1462 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1463 }
1464
1465 /**
1466 * @brief Get Channel 5 transfer complete flag.
1467 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1468 * @param DMAx DMAx Instance
1469 * @retval State of bit (1 or 0).
1470 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1471 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1472 {
1473 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1474 }
1475
1476 #if defined(DMA1_Channel6)
1477 /**
1478 * @brief Get Channel 6 transfer complete flag.
1479 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1480 * @param DMAx DMAx Instance
1481 * @retval State of bit (1 or 0).
1482 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1483 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1484 {
1485 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1486 }
1487 #endif
1488
1489 #if defined(DMA1_Channel7)
1490 /**
1491 * @brief Get Channel 7 transfer complete flag.
1492 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1493 * @param DMAx DMAx Instance
1494 * @retval State of bit (1 or 0).
1495 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1496 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1497 {
1498 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1499 }
1500 #endif
1501
1502 /**
1503 * @brief Get Channel 1 half transfer flag.
1504 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1505 * @param DMAx DMAx Instance
1506 * @retval State of bit (1 or 0).
1507 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1508 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1509 {
1510 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1511 }
1512
1513 /**
1514 * @brief Get Channel 2 half transfer flag.
1515 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1516 * @param DMAx DMAx Instance
1517 * @retval State of bit (1 or 0).
1518 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1519 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1520 {
1521 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1522 }
1523
1524 /**
1525 * @brief Get Channel 3 half transfer flag.
1526 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1527 * @param DMAx DMAx Instance
1528 * @retval State of bit (1 or 0).
1529 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1530 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1531 {
1532 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1533 }
1534
1535 /**
1536 * @brief Get Channel 4 half transfer flag.
1537 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1538 * @param DMAx DMAx Instance
1539 * @retval State of bit (1 or 0).
1540 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1541 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1542 {
1543 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1544 }
1545
1546 /**
1547 * @brief Get Channel 5 half transfer flag.
1548 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1549 * @param DMAx DMAx Instance
1550 * @retval State of bit (1 or 0).
1551 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1552 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1553 {
1554 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1555 }
1556
1557 #if defined(DMA1_Channel6)
1558 /**
1559 * @brief Get Channel 6 half transfer flag.
1560 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1561 * @param DMAx DMAx Instance
1562 * @retval State of bit (1 or 0).
1563 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1564 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1565 {
1566 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1567 }
1568 #endif
1569
1570 #if defined(DMA1_Channel7)
1571 /**
1572 * @brief Get Channel 7 half transfer flag.
1573 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1574 * @param DMAx DMAx Instance
1575 * @retval State of bit (1 or 0).
1576 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1577 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1578 {
1579 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1580 }
1581 #endif
1582
1583 /**
1584 * @brief Get Channel 1 transfer error flag.
1585 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1586 * @param DMAx DMAx Instance
1587 * @retval State of bit (1 or 0).
1588 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1590 {
1591 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1592 }
1593
1594 /**
1595 * @brief Get Channel 2 transfer error flag.
1596 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1597 * @param DMAx DMAx Instance
1598 * @retval State of bit (1 or 0).
1599 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1600 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1601 {
1602 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1603 }
1604
1605 /**
1606 * @brief Get Channel 3 transfer error flag.
1607 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1608 * @param DMAx DMAx Instance
1609 * @retval State of bit (1 or 0).
1610 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1611 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1612 {
1613 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1614 }
1615
1616 /**
1617 * @brief Get Channel 4 transfer error flag.
1618 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1619 * @param DMAx DMAx Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1622 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1623 {
1624 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1625 }
1626
1627 /**
1628 * @brief Get Channel 5 transfer error flag.
1629 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1630 * @param DMAx DMAx Instance
1631 * @retval State of bit (1 or 0).
1632 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1633 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1634 {
1635 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1636 }
1637
1638 #if defined(DMA1_Channel6)
1639 /**
1640 * @brief Get Channel 6 transfer error flag.
1641 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1642 * @param DMAx DMAx Instance
1643 * @retval State of bit (1 or 0).
1644 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1645 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1646 {
1647 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1648 }
1649 #endif
1650
1651 #if defined(DMA1_Channel7)
1652 /**
1653 * @brief Get Channel 7 transfer error flag.
1654 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1655 * @param DMAx DMAx Instance
1656 * @retval State of bit (1 or 0).
1657 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1658 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1659 {
1660 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1661 }
1662 #endif
1663
1664 /**
1665 * @brief Clear Channel 1 global interrupt flag.
1666 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1667 Instead clear specific flags transfer complete, half transfer & transfer
1668 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1669 LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
1670 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1671 * @param DMAx DMAx Instance
1672 * @retval None
1673 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1674 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1675 {
1676 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1677 }
1678
1679 /**
1680 * @brief Clear Channel 2 global interrupt flag.
1681 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1682 Instead clear specific flags transfer complete, half transfer & transfer
1683 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1684 LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
1685 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1686 * @param DMAx DMAx Instance
1687 * @retval None
1688 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1689 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1690 {
1691 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1692 }
1693
1694 /**
1695 * @brief Clear Channel 3 global interrupt flag.
1696 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1697 Instead clear specific flags transfer complete, half transfer & transfer
1698 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1699 LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
1700 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1701 * @param DMAx DMAx Instance
1702 * @retval None
1703 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1704 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1705 {
1706 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1707 }
1708
1709 /**
1710 * @brief Clear Channel 4 global interrupt flag.
1711 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1712 Instead clear specific flags transfer complete, half transfer & transfer
1713 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1714 LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
1715 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1716 * @param DMAx DMAx Instance
1717 * @retval None
1718 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1719 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1720 {
1721 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1722 }
1723
1724 /**
1725 * @brief Clear Channel 5 global interrupt flag.
1726 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1727 Instead clear specific flags transfer complete, half transfer & transfer
1728 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1729 LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
1730 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1731 * @param DMAx DMAx Instance
1732 * @retval None
1733 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1734 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1735 {
1736 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1737 }
1738
1739 #if defined(DMA1_Channel6)
1740 /**
1741 * @brief Clear Channel 6 global interrupt flag.
1742 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1743 Instead clear specific flags transfer complete, half transfer & transfer
1744 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1745 LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
1746 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1747 * @param DMAx DMAx Instance
1748 * @retval None
1749 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1750 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1751 {
1752 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1753 }
1754 #endif
1755
1756 #if defined(DMA1_Channel7)
1757 /**
1758 * @brief Clear Channel 7 global interrupt flag.
1759 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1760 Instead clear specific flags transfer complete, half transfer & transfer
1761 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1762 LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
1763 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1764 * @param DMAx DMAx Instance
1765 * @retval None
1766 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1767 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1768 {
1769 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1770 }
1771 #endif
1772
1773 /**
1774 * @brief Clear Channel 1 transfer complete flag.
1775 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1776 * @param DMAx DMAx Instance
1777 * @retval None
1778 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1779 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1780 {
1781 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1782 }
1783
1784 /**
1785 * @brief Clear Channel 2 transfer complete flag.
1786 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1787 * @param DMAx DMAx Instance
1788 * @retval None
1789 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1790 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1791 {
1792 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1793 }
1794
1795 /**
1796 * @brief Clear Channel 3 transfer complete flag.
1797 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1798 * @param DMAx DMAx Instance
1799 * @retval None
1800 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1801 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1802 {
1803 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1804 }
1805
1806 /**
1807 * @brief Clear Channel 4 transfer complete flag.
1808 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1809 * @param DMAx DMAx Instance
1810 * @retval None
1811 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1812 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1813 {
1814 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1815 }
1816
1817 /**
1818 * @brief Clear Channel 5 transfer complete flag.
1819 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1820 * @param DMAx DMAx Instance
1821 * @retval None
1822 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1823 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1824 {
1825 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1826 }
1827
1828 #if defined(DMA1_Channel6)
1829 /**
1830 * @brief Clear Channel 6 transfer complete flag.
1831 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1832 * @param DMAx DMAx Instance
1833 * @retval None
1834 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1835 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1836 {
1837 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1838 }
1839 #endif
1840
1841 #if defined(DMA1_Channel7)
1842 /**
1843 * @brief Clear Channel 7 transfer complete flag.
1844 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1845 * @param DMAx DMAx Instance
1846 * @retval None
1847 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1848 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1849 {
1850 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1851 }
1852 #endif
1853
1854 /**
1855 * @brief Clear Channel 1 half transfer flag.
1856 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1857 * @param DMAx DMAx Instance
1858 * @retval None
1859 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1860 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1861 {
1862 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1863 }
1864
1865 /**
1866 * @brief Clear Channel 2 half transfer flag.
1867 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1868 * @param DMAx DMAx Instance
1869 * @retval None
1870 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1871 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1872 {
1873 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1874 }
1875
1876 /**
1877 * @brief Clear Channel 3 half transfer flag.
1878 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1879 * @param DMAx DMAx Instance
1880 * @retval None
1881 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1882 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1883 {
1884 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1885 }
1886
1887 /**
1888 * @brief Clear Channel 4 half transfer flag.
1889 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1890 * @param DMAx DMAx Instance
1891 * @retval None
1892 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1893 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1894 {
1895 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1896 }
1897
1898 /**
1899 * @brief Clear Channel 5 half transfer flag.
1900 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1901 * @param DMAx DMAx Instance
1902 * @retval None
1903 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1904 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1905 {
1906 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1907 }
1908
1909 #if defined(DMA1_Channel6)
1910 /**
1911 * @brief Clear Channel 6 half transfer flag.
1912 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1913 * @param DMAx DMAx Instance
1914 * @retval None
1915 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1916 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1917 {
1918 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1919 }
1920 #endif
1921
1922 #if defined(DMA1_Channel7)
1923 /**
1924 * @brief Clear Channel 7 half transfer flag.
1925 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1926 * @param DMAx DMAx Instance
1927 * @retval None
1928 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1929 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1930 {
1931 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1932 }
1933 #endif
1934
1935 /**
1936 * @brief Clear Channel 1 transfer error flag.
1937 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1938 * @param DMAx DMAx Instance
1939 * @retval None
1940 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1941 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1942 {
1943 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1944 }
1945
1946 /**
1947 * @brief Clear Channel 2 transfer error flag.
1948 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1949 * @param DMAx DMAx Instance
1950 * @retval None
1951 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1952 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1953 {
1954 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1955 }
1956
1957 /**
1958 * @brief Clear Channel 3 transfer error flag.
1959 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1960 * @param DMAx DMAx Instance
1961 * @retval None
1962 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1963 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1964 {
1965 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1966 }
1967
1968 /**
1969 * @brief Clear Channel 4 transfer error flag.
1970 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1971 * @param DMAx DMAx Instance
1972 * @retval None
1973 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1974 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1975 {
1976 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1977 }
1978
1979 /**
1980 * @brief Clear Channel 5 transfer error flag.
1981 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1982 * @param DMAx DMAx Instance
1983 * @retval None
1984 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1985 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1986 {
1987 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1988 }
1989
1990 #if defined(DMA1_Channel6)
1991 /**
1992 * @brief Clear Channel 6 transfer error flag.
1993 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1994 * @param DMAx DMAx Instance
1995 * @retval None
1996 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1997 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1998 {
1999 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2000 }
2001 #endif
2002
2003 #if defined(DMA1_Channel7)
2004 /**
2005 * @brief Clear Channel 7 transfer error flag.
2006 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2007 * @param DMAx DMAx Instance
2008 * @retval None
2009 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2010 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2011 {
2012 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2013 }
2014 #endif
2015
2016 /**
2017 * @}
2018 */
2019
2020 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2021 * @{
2022 */
2023 /**
2024 * @brief Enable Transfer complete interrupt.
2025 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2026 * @param DMAx DMAx Instance
2027 * @param Channel This parameter can be one of the following values:
2028 * @arg @ref LL_DMA_CHANNEL_1
2029 * @arg @ref LL_DMA_CHANNEL_2
2030 * @arg @ref LL_DMA_CHANNEL_3
2031 * @arg @ref LL_DMA_CHANNEL_4
2032 * @arg @ref LL_DMA_CHANNEL_5
2033 * @arg @ref LL_DMA_CHANNEL_6
2034 * @arg @ref LL_DMA_CHANNEL_7
2035 * @retval None
2036 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2037 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2038 {
2039 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
2040 }
2041
2042 /**
2043 * @brief Enable Half transfer interrupt.
2044 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2045 * @param DMAx DMAx Instance
2046 * @param Channel This parameter can be one of the following values:
2047 * @arg @ref LL_DMA_CHANNEL_1
2048 * @arg @ref LL_DMA_CHANNEL_2
2049 * @arg @ref LL_DMA_CHANNEL_3
2050 * @arg @ref LL_DMA_CHANNEL_4
2051 * @arg @ref LL_DMA_CHANNEL_5
2052 * @arg @ref LL_DMA_CHANNEL_6
2053 * @arg @ref LL_DMA_CHANNEL_7
2054 * @retval None
2055 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2056 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2057 {
2058 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
2059 }
2060
2061 /**
2062 * @brief Enable Transfer error interrupt.
2063 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2064 * @param DMAx DMAx Instance
2065 * @param Channel This parameter can be one of the following values:
2066 * @arg @ref LL_DMA_CHANNEL_1
2067 * @arg @ref LL_DMA_CHANNEL_2
2068 * @arg @ref LL_DMA_CHANNEL_3
2069 * @arg @ref LL_DMA_CHANNEL_4
2070 * @arg @ref LL_DMA_CHANNEL_5
2071 * @arg @ref LL_DMA_CHANNEL_6
2072 * @arg @ref LL_DMA_CHANNEL_7
2073 * @retval None
2074 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2075 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2076 {
2077 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
2078 }
2079
2080 /**
2081 * @brief Disable Transfer complete interrupt.
2082 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2083 * @param DMAx DMAx Instance
2084 * @param Channel This parameter can be one of the following values:
2085 * @arg @ref LL_DMA_CHANNEL_1
2086 * @arg @ref LL_DMA_CHANNEL_2
2087 * @arg @ref LL_DMA_CHANNEL_3
2088 * @arg @ref LL_DMA_CHANNEL_4
2089 * @arg @ref LL_DMA_CHANNEL_5
2090 * @arg @ref LL_DMA_CHANNEL_6
2091 * @arg @ref LL_DMA_CHANNEL_7
2092 * @retval None
2093 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2094 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2095 {
2096 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
2097 }
2098
2099 /**
2100 * @brief Disable Half transfer interrupt.
2101 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2102 * @param DMAx DMAx Instance
2103 * @param Channel This parameter can be one of the following values:
2104 * @arg @ref LL_DMA_CHANNEL_1
2105 * @arg @ref LL_DMA_CHANNEL_2
2106 * @arg @ref LL_DMA_CHANNEL_3
2107 * @arg @ref LL_DMA_CHANNEL_4
2108 * @arg @ref LL_DMA_CHANNEL_5
2109 * @arg @ref LL_DMA_CHANNEL_6
2110 * @arg @ref LL_DMA_CHANNEL_7
2111 * @retval None
2112 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2113 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2114 {
2115 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
2116 }
2117
2118 /**
2119 * @brief Disable Transfer error interrupt.
2120 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2121 * @param DMAx DMAx Instance
2122 * @param Channel This parameter can be one of the following values:
2123 * @arg @ref LL_DMA_CHANNEL_1
2124 * @arg @ref LL_DMA_CHANNEL_2
2125 * @arg @ref LL_DMA_CHANNEL_3
2126 * @arg @ref LL_DMA_CHANNEL_4
2127 * @arg @ref LL_DMA_CHANNEL_5
2128 * @arg @ref LL_DMA_CHANNEL_6
2129 * @arg @ref LL_DMA_CHANNEL_7
2130 * @retval None
2131 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2132 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2133 {
2134 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
2135 }
2136
2137 /**
2138 * @brief Check if Transfer complete Interrupt is enabled.
2139 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2140 * @param DMAx DMAx Instance
2141 * @param Channel This parameter can be one of the following values:
2142 * @arg @ref LL_DMA_CHANNEL_1
2143 * @arg @ref LL_DMA_CHANNEL_2
2144 * @arg @ref LL_DMA_CHANNEL_3
2145 * @arg @ref LL_DMA_CHANNEL_4
2146 * @arg @ref LL_DMA_CHANNEL_5
2147 * @arg @ref LL_DMA_CHANNEL_6
2148 * @arg @ref LL_DMA_CHANNEL_7
2149 * @retval State of bit (1 or 0).
2150 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2151 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2152 {
2153 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2154 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
2155 }
2156
2157 /**
2158 * @brief Check if Half transfer Interrupt is enabled.
2159 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2160 * @param DMAx DMAx Instance
2161 * @param Channel This parameter can be one of the following values:
2162 * @arg @ref LL_DMA_CHANNEL_1
2163 * @arg @ref LL_DMA_CHANNEL_2
2164 * @arg @ref LL_DMA_CHANNEL_3
2165 * @arg @ref LL_DMA_CHANNEL_4
2166 * @arg @ref LL_DMA_CHANNEL_5
2167 * @arg @ref LL_DMA_CHANNEL_6
2168 * @arg @ref LL_DMA_CHANNEL_7
2169 * @retval State of bit (1 or 0).
2170 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2171 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2172 {
2173 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2174 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
2175 }
2176
2177 /**
2178 * @brief Check if Transfer error Interrupt is enabled.
2179 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2180 * @param DMAx DMAx Instance
2181 * @param Channel This parameter can be one of the following values:
2182 * @arg @ref LL_DMA_CHANNEL_1
2183 * @arg @ref LL_DMA_CHANNEL_2
2184 * @arg @ref LL_DMA_CHANNEL_3
2185 * @arg @ref LL_DMA_CHANNEL_4
2186 * @arg @ref LL_DMA_CHANNEL_5
2187 * @arg @ref LL_DMA_CHANNEL_6
2188 * @arg @ref LL_DMA_CHANNEL_7
2189 * @retval State of bit (1 or 0).
2190 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2191 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2192 {
2193 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2194 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
2195 }
2196
2197 /**
2198 * @}
2199 */
2200
2201 #if defined(USE_FULL_LL_DRIVER)
2202 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2203 * @{
2204 */
2205
2206 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2207 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2208 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2209
2210 /**
2211 * @}
2212 */
2213 #endif /* USE_FULL_LL_DRIVER */
2214
2215 /**
2216 * @}
2217 */
2218
2219 /**
2220 * @}
2221 */
2222
2223 #endif /* DMA1 || DMA2 */
2224
2225 /**
2226 * @}
2227 */
2228
2229 #ifdef __cplusplus
2230 }
2231 #endif
2232
2233 #endif /* __STM32F0xx_LL_DMA_H */
2234
2235
